An example method includes the following operations: receiving information about tests performed on a device, where the tests are associated with one or more parameters; performing an optimization process that includes varying the one or more parameters to optimize one or more criteria associated with the tests, where the optimization process includes an artificial intelligence process or a machine learning process; and outputting information that is based on which of the one or more parameters optimizes the one or more criteria.
An example test system includes a plenum including an air inlet and a rack including slots to hold devices under test. The rack is adjacent to the plenum. The slots are arranged on the rack in a matrix such that part of each device held in a slot borders the plenum and is in fluid communication with the air inlet. One or more blowers are configured to force temperature-conditioned air into the air inlet of the plenum to thereby increase air pressure in the plenum and force the temperature-conditioned air over the devices and out of the plenum.
An example test system includes a plenum including an air inlet and a rack including slots to hold devices under test. The rack is adjacent to the plenum. The slots are arranged on the rack in a matrix such that part of each device held in a slot borders the plenum and is in fluid communication with the air inlet. One or more blowers are configured to force temperature-conditioned air into the air inlet of the plenum to thereby increase air pressure in the plenum and force the temperature-conditioned air over the devices and out of the plenum.
An example system includes a first memory that includes primary storage; a second memory that includes secondary storage; and a control system for predicting paths through a test program that will be taken during a planned execution of the test program, and for causing test data associated with the test program to be stored in the first memory or the second memory based on the paths predicted.
G01R 31/319 - Matériel de test, c.-à-d. circuits de traitement de signaux de sortie
G06F 11/22 - Détection ou localisation du matériel d'ordinateur défectueux en effectuant des tests pendant les opérations d'attente ou pendant les temps morts, p. ex. essais de mise en route
G06F 11/36 - Prévention d'erreurs par analyse, par débogage ou par test de logiciel
5.
CONTROLLING STORAGE OF TEST DATA BASED ON PRIOR TEST PROGRAM EXECUTION
An example system includes a first memory that includes primary storage; a second memory that includes secondary storage; and a control system for predicting paths through a test program that will be taken during a planned execution of the test program, and for causing test data associated with the test program to be stored in the first memory or the second memory based on the paths predicted.
An example system is for testing a device under test (DUT) that includes a first core and a second core. The system includes channels in parallel for connecting to a number of pins on the DUT. The channels are for sending test data to the DUT and for receiving measurement data from the DUT based on the test data. The measurement data includes time-division-multiplexed (TDM) data comprised of successive data packets received from the DUT over the channels as part of a bitstream. Each data packet includes a first number of bits from the first core and a second number of bits from the second core. Circuitry associated with the channels is configured to compare the measurement data with expected data, and to determine pass/fail status for the first core and for the second core based on the comparison.
An example system is for testing a device under test (DUT) that includes a first core and a second core. The system includes channels in parallel for connecting to a number of pins on the DUT. The channels are for sending test data to the DUT and for receiving measurement 5 data from the DUT based on the test data. The measurement data includes time-division-multiplexed (TDM) data comprised of successive data packets received from the DUT over the channels as part of a bitstream. Each data packet includes a first number of bits from the first core and a second number of bits from the second core. Circuitry associated with the channels is configured to compare 10 the measurement data with expected data, and to determine pass/fail status for the first core and for the second core based on the comparison.
An example cable assembly includes a coaxial cable. A layer encases at least part of the coaxial cable. A memory on, or in contact with, the layer, the memory is configured to store calibration data for the coaxial cable.
H01B 11/18 - Câbles coaxiauxCâbles analogues ayant plusieurs conducteurs intérieurs dans un conducteur extérieur commun
H01B 7/18 - Protection contre les dommages provoqués par des facteurs extérieurs, p. ex. gaines ou armatures par l'usure, la contrainte mécanique ou la pression
H01B 3/30 - Isolateurs ou corps isolants caractérisés par le matériau isolantEmploi de matériaux spécifiés pour leurs propriétés isolantes ou diélectriques composés principalement de substances organiques matières plastiquesIsolateurs ou corps isolants caractérisés par le matériau isolantEmploi de matériaux spécifiés pour leurs propriétés isolantes ou diélectriques composés principalement de substances organiques résinesIsolateurs ou corps isolants caractérisés par le matériau isolantEmploi de matériaux spécifiés pour leurs propriétés isolantes ou diélectriques composés principalement de substances organiques cires
G11B 33/12 - Disposition des éléments de structure dans les appareils, p. ex. d'alimentation, des modules
An example cable assembly includes a coaxial cable. A layer encases at least part of the coaxial cable. A memory on, or in contact with, the layer, the memory is configured to store calibration data for the coaxial cable.
H01R 24/54 - Pièces intermédiaires, p. ex. adaptateurs, répartiteurs ou coudes
H01R 24/48 - Dispositifs de couplage en deux pièces, ou l'une des pièces qui coopèrent dans ces dispositifs, caractérisés par leur structure générale ayant des contacts disposés concentriquement ou coaxialement spécialement adaptés à la haute fréquence comprenant des moyens d'adaptation d'impédance ou des composants électriques, p. ex. des filtres ou des interrupteurs comprenant des dispositifs de protection, p. ex. de protection contre les surtensions
H01R 24/50 - Dispositifs de couplage en deux pièces, ou l'une des pièces qui coopèrent dans ces dispositifs, caractérisés par leur structure générale ayant des contacts disposés concentriquement ou coaxialement spécialement adaptés à la haute fréquence montés sur une PCB [carte de circuits imprimés]
09 - Appareils et instruments scientifiques et électriques
Produits et services
Semiconductor testing apparatus; computer component testing
and calibrating equipment; computer hardware for testing and
analyzing computer hardware, memory and logic devices,
semiconductors and chips; recorded computer software for
testing and analyzing computer hardware, memory and logic
devices, semiconductors and chips.
An example test system includes a test instrument configured to test a device under test (DUT). The test instrument is configured to interact with the DUT using first commands having a first syntax. The test system also includes one or more processing devices configured (i) to receive a definitions file, where the definitions file includes information defining a second syntax that is used by a third party to communicate with the DUT, (ii) to receive second commands having the second syntax, (iii) to convert the second commands into the first commands having the first syntax based on the definitions file, and (iv) to send the first commands to the test instrument to enable the test instrument to interact with the DUT.
An example system for testing a device under test (DUT) includes one or more processing devices configured to receive first data from the DUT over a communication channel, and to analyze the first data to identify an error associated with the communication channel; and a power supply controller configured to receive second data based on a power disturbance from the DUT, and to compare the first data and the second data to determine if there is a correlation between the power disturbance and the error.
G06F 11/22 - Détection ou localisation du matériel d'ordinateur défectueux en effectuant des tests pendant les opérations d'attente ou pendant les temps morts, p. ex. essais de mise en route
G06F 11/273 - Matériel de test, c.-à-d. circuits de traitement de signaux de sortie
09 - Appareils et instruments scientifiques et électriques
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Semiconductor testing apparatus; downloadable computer
software development tools; downloadable and recorded
computer software for testing and analyzing computer
hardware, semiconductors and chips, circuit boards, memory
and logic devices, and data networks. Design and development of computer software for others;
providing temporary use of non-downloadable cloud-based
software for testing and analyzing computer hardware,
semiconductors and chips, circuit boards, memory and logic
devices, and data networks.
14.
DETERMINING A CORRELATION BETWEEN POWER DISTURBANCES AND DATA ERORS IN A TEST SYSTEM
An example system for testing a device under test (DUT) includes one or more processing devices configured to receive first data from the DUT over a communication channel, and to analyze the first data to identify an error associated with the communication channel; and a power supply controller configured to receive second data based on a power disturbance from the DUT, and to compare the first data and the second data to determine if there is a correlation between the power disturbance and the error.
09 - Appareils et instruments scientifiques et électriques
Produits et services
Semiconductor testing apparatus; Computer component testing and calibrating equipment; computer hardware for testing and analyzing computer hardware, memory and logic devices, semiconductors and chips; recorded computer software for testing and analyzing computer hardware, memory and logic devices, semiconductors and chips
09 - Appareils et instruments scientifiques et électriques
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
(1) Semiconductor testing apparatus; downloadable computer software development tools; downloadable and recorded computer software for testing and analyzing computer hardware, semiconductors and chips, circuit boards, memory and logic devices, and data networks. (1) Design and development of computer software for others; providing temporary use of non-downloadable cloud-based software for testing and analyzing computer hardware, semiconductors and chips, circuit boards, memory and logic devices, and data networks.
09 - Appareils et instruments scientifiques et électriques
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Semiconductor testing apparatus; downloadable computer software development tools; downloadable and recorded computer software for testing and analyzing computer hardware, semiconductors and chips, circuit boards, memory and logic devices, and data networks Design and development of computer software for others; providing temporary use of non-downloadable cloud-based software for testing and analyzing computer hardware, semiconductors and chips, circuit boards, memory and logic devices, and data networks
09 - Appareils et instruments scientifiques et électriques
Produits et services
Semiconductor testing apparatus; computer component testing
and calibrating equipment; computer hardware for testing and
analyzing computer hardware, memory and logic devices,
semiconductors and chips; recorded computer software for
testing and analyzing computer hardware, memory and logic
devices, semiconductors and chips.
19.
Method for reduction of SIC MOSFET gate voltage glitches
Aspects of the present disclosure are directed to a circuit and methods of operating the same to provide an off-state circuit path with a programmable impedance in combination with a negative gate-to-source voltage Vgs for power transistors in an inverter configuration to prevent gate voltage glitches. Gate voltage glitch may occur due to Miller current generation across the gate path of a power transistor in the off state during rapid voltage transient dV/dt when the other, complementary power transistor is switched on or off. According to one aspect, using a negative gate-to-source voltage to turn-off a power transistor may mitigate gate voltage spikes caused by a large voltage transient when the complimentary power transistor is turned on, thus preventing parasitic turn-on of the power transistor. According to another aspect, an off-state circuit path with a programmable impedance is provided that is controllable to be in a low impedance state prior to a complementary power transistor is being turned on, such that the gate voltage glitches of the power transistor is prevented by the low impedance off-state circuit path.
G01R 31/26 - Test de dispositifs individuels à semi-conducteurs
H02M 1/088 - Circuits spécialement adaptés à la production d'une tension de commande pour les dispositifs à semi-conducteurs incorporés dans des convertisseurs statiques pour la commande simultanée de dispositifs à semi-conducteurs connectés en série ou en parallèle
H02M 7/537 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant alternatif sans possibilité de réversibilité par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs, p. ex. onduleurs à impulsions à un seul commutateur
20.
METHOD FOR REDUCTION OF SIC MOSFET GATE VOLTAGE GLITCHES
Aspects of the present disclosure are directed to a circuit and methods of operating the same to provide an off-state circuit path with a programmable impedance in combination with a negative gate-to- source voltage Vgs for power transistors in an inverter configuration to prevent gate voltage glitches. Gate voltage glitch may occur due to Miller current generation across the gate path of a power transistor in the off state during rapid voltage transient dV/dt when the other, complementary power transistor is switched on or off. According to one aspect, using a negative gate-to-source voltage to turn-off a power transistor may mitigate gate voltage spikes caused by a large voltage transient when the complimentary power transistor is turned on, thus preventing parasitic tum-on of the power transistor. According to another aspect, an off-state circuit path with a programmable impedance is provided that is controllable to be in a low impedance state prior to a complementary power transistor is being turned on, such that the gate voltage glitches of the power transistor is prevented by the low impedance off-state circuit path.
An example method of flattening a circuit board assembly includes attaching the circuit board assembly to a structure having dimensions that partly enclose a space, where attachment of the circuit board assembly to the structure creates an air-tight seal over the space, and where the structure has at least one port in fluid communication with the space. The method also includes applying vacuum pressure to the space via the at least one port, where the vacuum pressure forces at least part of the circuit board assembly toward the space, and dispensing thermal interface material selectively onto parts of the circuit board assembly while the vacuum pressure is applied.
An example method of flattening a circuit board assembly includes attaching the circuit board assembly to a structure having dimensions that partly enclose a space, where attachment of the circuit board assembly to the structure creates an air-tight seal over the space, and where the structure has at least one port in fluid communication with the space. The method also includes applying vacuum pressure to the space via the at least one port, where the vacuum pressure forces at least part of the circuit board assembly toward the space, and dispensing thermal interface material selectively onto parts of the circuit board assembly while the vacuum pressure is applied.
09 - Appareils et instruments scientifiques et électriques
Produits et services
Semiconductor testing apparatus; Computer component testing and calibrating equipment; Computer hardware for testing and analyzing computer hardware, memory and logic devices, semiconductors and chips; Recorded computer software for testing and analyzing computer hardware, memory and logic devices, semiconductors and chips
An example system includes a first circuit board having first conductive traces, where a first conductive trace is for conducting an alternating current (AC) digital signal having an edge; a second circuit board having second conductive traces, where a second conductive trace is within a predefined distance of the first conductive trace to produce a contactless coupling with the first conductive trace, and where the contactless coupling enables electrical energy on the first conductive trace to manifest on the second conductive trace as a transient response that is based on the edge; and circuitry to reconstruct the edge based on the transient response from the second conductive trace.
An example probe for a test system includes a conductor to carry direct current (DC) signals between a DC testing resource and a signal trace on the test system, where the signal trace is for carrying the DC signals and alternating current (AC) signals to and from a device under test; and an inductor connected in series with the conductor. A mechanism is included in the probe for enabling the conductor to move toward the signal trace or a pin electrically connected to the signal trace to create an electrical connection between the conductor and the signal trace to enable the testing resource to transmit the DC signals to the signal trace, and to move away from the signal trace or the pin so that no electrical connection is created between the conductor and the signal trace when the DC signals are not to be transmitted to the signal trace.
An example probe for a test system includes a conductor to carry direct current (DC) signals between a DC testing resource and a signal trace on the test system, where the signal trace is for carrying the DC signals and alternating current (AC) signals to and from a device under test; and an inductor connected in series with the conductor. A mechanism is included in the probe for enabling the conductor to move toward the signal trace or a pin electrically connected to the signal trace to create an electrical connection between the conductor and the signal trace to enable the testing resource to transmit the DC signals to the signal trace, and to move away from the signal trace or the pin so that no electrical connection is created between the conductor and the signal trace when the DC signals are not to be transmitted to the signal trace.
An example system includes first memory, second memory having a greater areal density than the first memory, and a logic circuit configured to move some test data from the second memory to the first memory while at least one of (i) reading other test data from the first memory or (ii) processing the other test data. The logic circuit is configured to process the other test data prior to output along a test channel. The test channel leads to a device under test (OUT) to be tested.
An example system includes first memory, second memory having a greater areal density than the first memory, and a logic circuit configured to move some test data from the second memory to the first memory while at least one of (i) reading other test data from the first memory or (ii) processing the other test data. The logic circuit is configured to process the other test data prior to output along a test channel. The test channel leads to a device under test (DUT) to be tested.
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 11/263 - Génération de signaux d'entrée de test, p. ex. vecteurs, formes ou séquences de test
G06F 12/06 - Adressage d'un bloc physique de transfert, p. ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
Example techniques may be implemented as a method, a system or more nontransitory machine-readable media storing instructions that are executable by one or more processing devices. Operations performed by the example techniques include obtaining data representing results of tests executed by one or more test instruments on an initial set of devices under test (DUTs) in a test system; and using the data to train a machine learning model. The machine learning model is for predicting which of the tests will produce failing results for a different set of DUTs. DUTs in the different set have one or more features in common with DUTs in the initial set.
Example techniques may be implemented as a method, a system or more non-transitory machine-readable media storing instructions that are executable by one or more processing devices, Operations performed by the example techniques include obtaining data representing results of tests executed by one or more test instruments on an initial set of devices under test (DUTs) in a test system; and using the data to train a machine learning model. The machine learning model is for predicting which of the tests will produce failing results for a different set of DUTs. DUTs in the different set have one or more features in common with DUTs in the initial set.
G06F 11/22 - Détection ou localisation du matériel d'ordinateur défectueux en effectuant des tests pendant les opérations d'attente ou pendant les temps morts, p. ex. essais de mise en route
09 - Appareils et instruments scientifiques et électriques
Produits et services
Semiconductor testing apparatus; computer component testing
and calibrating equipment; computer hardware for testing and
analyzing computer hardware, memory and logic devices,
semiconductors and chips; recorded computer software for
testing and analyzing computer hardware, memory and logic
devices, semiconductors and chips.
An example test socket for a test system includes a receptacle to make electrical and mechanical connections to a device under test (OUT) and a lid to cover the OUT in the receptacle. The lid is controllable to open automatically to enable receipt of the OUT in the receptacle and, following receipt of the OUT, to close automatically to cover the OUT in the receptacle. Closing the lid applies force to the OUT to complete the electrical and mechanical connections between the test socket and the OUT.
An example test socket for a test system includes a receptacle to make electrical and mechanical connections to a device under test (DUT) and a lid to cover the DUT in the receptacle. The lid is controllable to open automatically to enable receipt of the DUT in the receptacle and, following receipt of the DUT, to close automatically to cover the DUT in the receptacle. Closing the lid applies force to the DUT to complete the electrical and mechanical connections between the test socket and the DUT.
G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
G01R 1/04 - BoîtiersOrganes de supportAgencements des bornes
34.
Waveguide connector for connecting first and second waveguides, where the connector includes a male part, a female part and a self-alignment feature and a test system formed therefrom
An example waveguide connector is for making a blind-mate electrical connection between a first waveguide and a second waveguide. The waveguide connector includes a male part connected to the first waveguide, where the first waveguide includes a first conductive channel, and a female part connected to the second waveguide, where the second waveguide includes a second conductive channel. The female part includes a receptacle into which the male part slides to create the blind-mate electrical connection between the first conductive channel and the second conductive channel. A self-alignment feature is on at least one of the male part or the female part. The self-alignment feature is configured to guide the male part into the receptacle while correcting for misalignment of the male part and the female part.
An example waveguide connector is for making a blind-mate electrical connection between a first waveguide and a second waveguide. The waveguide connector includes a male part connected to the first waveguide, where the first waveguide includes a first conductive channel, and a female part connected to the second waveguide, where the second waveguide includes a second conductive channel. The female part includes a receptacle into which the male part slides to create the blind-mate electrical connection between the first conductive channel and the second conductive channel. A self-alignment feature is on at least one of the male part or the female part. The self-alignment feature is configured to guide the male part into the receptacle while correcting for misalignment of the male part and the female part.
09 - Appareils et instruments scientifiques et électriques
Produits et services
Semiconductor testing apparatus; Computer component testing and calibrating equipment; computer hardware for testing and analyzing computer hardware, memory and logic devices, semiconductors and chips; recorded computer software for testing and analyzing computer hardware, memory and logic devices, semiconductors and chips
An example front-end module includes a channel to connect to a device under test (DUT). The front-end module includes a transmission line between the DUT and the front-end module that is configured for bidirectional transmission of oscillating signals including test signals and response signals, and in-phase and quadrature (IQ) circuitry configured to modulate a test signal for transmission over the transmission line to the DUT and to demodulate a response received over the transmission line from the DUT. The front-end module include at least four taps into the transmission line to obtain direct current (DC) voltage values based on the oscillating signals. Scattering (s) parameters of the channel are based on the DC voltage values. The front-end module includes at least six ports.
An example contact head includes coaxial contacts configured for transmission of radio frequency (RF) signals or digital signals between a test system and a device under test (DUT). Each of the coaxial contacts is configured to target a specific impedance. Each of the coaxial contacts includes a coaxial structure having an open-curve shape. The coaxial structure includes a spring material that bends in response to applied force and that returns to the open-curve shape absent the applied force. The coaxial structure includes a center conductor terminating in a contact pin and a return conductor separated by a dielectric from the center conductor. At least part of the center conductor and the return conductor include an electrically-conductive material. Flexible contacts on the coaxial contact include the electrically-conductive material.
An example printed circuit board (PCB) includes a substrate having layers of a dielectric material, where the layers of dielectric material include a first layer and a second layer; a conductive trace that is between the first layer and the second layer and that is parallel to the first layer and the second layer along at least part of a length of the conductive trace; and a conductive via that extends at least part-way through the layers of dielectric material and that connects electrically to the conductive trace, where the conductive via is configured also to connect electrically to a signal input to receive or to transmit a signal that has a center frequency span.
An example apparatus is for contacting a device to change a temperature of the device. The apparatus includes a plate configured to contact the device and a channel within the plate configured to enable flow of fluid between an input port and an output port. The plate includes a thermally conductive material to conduct heat between the device and the fluid. The channel includes multiple islands arranged in series. An island among the multiple islands is arranged to receive the fluid at a first side. The island is for splitting the fluid into a first flow and a second flow and for causing the first flow and the second flow to merge at a second side of the island that is downstream of the first side of the island.
An example apparatus is for contacting a device to change a temperature of the device. The apparatus includes a plate configured to contact the device and a channel within the plate configured to enable flow of fluid between an input port and an output port. The plate includes a thermally conductive material to conduct heat between the device and the fluid. The channel includes multiple islands arranged in series. An island among the multiple islands is arranged to receive the fluid at a first side. The island is for splitting the fluid into a first flow and a second flow and for causing the first flow and the second flow to merge at a second side of the island that is downstream of the first side of the island.
F28D 1/047 - Appareils échangeurs de chaleur comportant des ensembles de canalisations fixes pour une seule des sources de potentiel calorifique, les deux sources étant en contact chacune avec un côté de la paroi de la canalisation, dans lesquels l'autre source de potentiel calorifique est une grande masse de fluide, p. ex. radiateurs domestiques ou de moteur de voiture avec des canalisations d'échange de chaleur immergées dans la masse du fluide avec canalisations tubulaires les canalisations étant courbées, p. ex. en serpentin ou en zigzag
An example front-end module includes a channel to connect to a device under test (DUT). The front-end module includes a transmission line between the DUT and the front-end module that is configured for bidirectional transmission of oscillating signals including test signals and response signals, and in-phase and quadrature (IQ) circuitry configured to modulate a test signal for transmission over the transmission line to the DUT and to demodulate a response received over the transmission line from the DUT. The front-end module include at least four taps into the transmission line to obtain direct current (DC) voltage values based on the oscillating signals. Scattering (s) parameters of the channel are based on the DC voltage values. The front-end module includes at least six ports.
An example printed circuit board (PCB) includes a substrate having layers of a dielectric material, where the layers of dielectric material include a first layer and a second layer; a conductive trace that is between the first layer and the second layer and that is parallel to the first layer and the second layer along at least part of a length of the conductive trace; and a conductive via that extends at least part-way through the layers of dielectric material and that connects electrically to the conductive trace, where the conductive via is configured also to connect electrically to a signal input to receive or to transmit a signal that has a center frequency span.
G01R 31/00 - Dispositions pour tester les propriétés électriquesDispositions pour la localisation des pannes électriquesDispositions pour tests électriques caractérisées par ce qui est testé, non prévues ailleurs
G01R 1/04 - BoîtiersOrganes de supportAgencements des bornes
G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
An example test head manipulator includes a tower having a base and a track, where the track is vertical relative to the base, and arms to enable support for the test head. The arms are connected to the track to move the test head vertically relative to the tower, and the arms are configured to control rotation of the test head. Each of the arms includes a cam that is rotatable, and at least one plunger in contact with the cam and that is configured to contact the test head. Rotation of the cam is controllable to move the at least one plunger to offset an uncontrolled rotation the test head.
An example test head manipulator includes a tower having a base and a track, where the track is vertical relative to the base, and arms to enable support for the test head. The arms are connected to the track to move the test head vertically relative to the tower, and the arms are configured to control rotation of the test head. Each of the arms includes a cam that is rotatable, and at least one plunger in contact with the cam and that is configured to contact the test head. Rotation of the cam is controllable to move the at least one plunger to offset an uncontrolled rotation the test head.
G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
G01R 31/00 - Dispositions pour tester les propriétés électriquesDispositions pour la localisation des pannes électriquesDispositions pour tests électriques caractérisées par ce qui est testé, non prévues ailleurs
B25J 9/04 - Manipulateurs à commande programmée caractérisés par le mouvement des bras, p. ex. du type à coordonnées cartésiennes par rotation d'au moins un bras en excluant le mouvement de la tête elle-même, p. ex. du type à coordonnées cylindriques ou polaires
G01N 29/265 - Dispositions pour l'orientation ou le balayage en déplaçant le capteur par rapport à un matériau fixe
An interposer for a test system includes coaxial cables, each of which is configured to transport a first portion of current originating from a current source, and printed circuit boards (PCBs), each of which is connected to a set of the coaxial cables in order to receive the first portion of the current from each coaxial cable in the set and to transport a second portion of the current. A spring leaf assembly includes spring leaves, each of which is connected to a PCB in order to transport a third portion of the current obtained from the PCB to a device interface board (DIB) that connects to devices under test (DUTs) to be tested by the test system. The coaxial cables on each PCB are arranged in parallel, the PCBs are arranged in parallel, and the spring leaves on each PCB are arranged in parallel.
An example test system includes a test head, and a device interface board (DIB) configured to connect to the test head. The DIB is for holding devices under test (DUTs). The DIB includes electrical conductors for transmitting electrical signals between the DUTs and the test head. Servers are programmed to function as test instruments. The servers are external to, and remote from, the test head and are configured to communicate signals over fiber optic cables with the test head. The signals include serial signals.
An example polarity inverter includes multiple contactors, each of which includes switches that are controllable to configure a current path. Each of the multiple contactors includes contacts, which are interleaved such that first contacts to receive voltage having a first polarity alternate with second contacts to receive voltage having a second polarity, where the first polarity and the second polarity are different. The polarity inverter also includes a first conductive plate to connect electrically to each of the first contacts, and a second conductive plate to connect electrically to each of the second contacts. The first conductive plate and the second conductive plate are in parallel. A dielectric material is between the first conductive plate and the second conductive plate.
G01R 31/26 - Test de dispositifs individuels à semi-conducteurs
G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
H01H 9/00 - Détails de dispositifs de commutation non couverts par
H01H 9/22 - Mécanismes d'interverrouillage, verrouillage ou accrochage pour interverrouillage entre enveloppe, capot ou volet de protection et le mécanisme actionnant les contacts
H01H 1/58 - Connexions électriques avec ou entre contactsBornes
49.
Automatic test equipement having fiber optic connections to remote servers
An example test system includes a test head, and a device interface board (DIB) configured to connect to the test head. The DIB is for holding devices under test (DUTs). The DIB includes electrical conductors for transmitting electrical signals between the DUTs and the test head. Servers are programmed to function as test instruments. The servers are external to, and remote from, the test head and are configured to communicate signals over fiber optic cables with the test head. The signals include serial signals.
An interposer for a test system includes coaxial cables, each of which is configured to transport a first portion of current originating from a current source, and printed circuit boards (PCBs), each of which is connected to a set of the coaxial cables in order to receive the first portion of the current from each coaxial cable in the set and to transport a second portion of the current. A spring leaf assembly includes spring leaves, each of which is connected to a PCB in order to transport a third portion of the current obtained from the PCB to a device interface board (DIB) that connects to devices under test (DUTs) to be tested by the test system. The coaxial cables on each PCB are arranged in parallel, the PCBs are arranged in parallel, and the spring leaves on each PCB are arranged in parallel.
H01R 13/6587 - Matériau de blindage entourant individuellement des contacts espacés les uns des autres ou interposé entre ces derniers pour séparer des modules de connecteurs multibroches pour montage sur des cartes de circuits imprimés
H01R 12/51 - Connexions fixes pour circuits imprimés rigides ou structures similaires
H01R 13/24 - Contacts pour coopération par aboutage élastiquesContacts pour coopération par aboutage montés élastiquement
An example polarity inverter includes multiple contactors, each of which includes switches that are controllable to configure a current path. Each of the multiple contactors includes contacts, which are interleaved such that first contacts to receive voltage having a first polarity alternate with second contacts to receive voltage having a second polarity, where the first polarity and the second polarity are different. The polarity inverter also includes a first conductive plate to connect electrically to each of the first contacts, and a second conductive plate to connect electrically to each of the second contacts. The first conductive plate and the second conductive plate are in parallel. A dielectric material is between the first conductive plate and the second conductive plate.
An example test system includes a test socket for testing a DUT, a lid for the test socket, and an actuator configured to force the lid onto the test socket and to remove the lid from the test socket. The actuator includes an upper arm to move the lid, an attachment mechanism connected to the upper arm to contact the lid, where the attachment mechanism is configured to allow the lid to float relative to the test socket to enable alignment between the lid and the test socket, and a lower arm to anchor the actuator to a board containing the test socket. The actuator is configured to move the upper arm linearly towards and away from the test socket and to rotate the upper arm towards and away from the test socket.
An example test system includes packs. The packs include test sockets for testing devices under test (DUTs) and at least some test electronics for performing tests on the DUTs in the test sockets. Different packs are configured to have different configurations. The different configurations include at least different numbers of test sockets arranged at different pitches.
An example test system includes test sites that include sockets for testing devices under test (DUTs), pickers for picking DUTs from the sockets or placing the DUTs in the sockets, and a gantry on which the pickers are mounted. The gantry is configured to move the pickers relative to the test sites to position the pickers for picking the DUTs from the sockets or placing the DUTs into the sockets. The test system also includes one or more LASER range finders mounted on the gantry for movement over the DUTs in the sockets and in conjunction with movement of the pickers. A LASER range finder among the one or more LASER rangefinders mounted on the gantry is configured to detect a distance to a DUT placed into a socket.
An example test system includes packs. The packs include test sockets for testing devices under test (DUTs) and at least some test electronics for performing tests on the DUTs in the test sockets. Different packs are configured to have different configurations. The different configurations include at least different numbers of test sockets arranged at different pitches.
An example test system includes a test socket for testing a DUT, a lid for the test socket, and an actuator configured to force the lid onto the test socket and to remove the lid from the test socket. The actuator includes an upper arm to move the lid, an attachment mechanism connected to the upper arm to contact the lid, where the attachment mechanism is configured to allow the lid to float relative to the test socket to enable alignment between the lid and the test socket, and a lower arm to anchor the actuator to a board containing the test socket. The actuator is configured to move the upper arm linearly towards and away from the test socket and to rotate the upper arm towards and away from the test socket.
An example test system includes test sites for testing devices under test (DUTs), where the test sites include a test site configured to hold a DUT for testing. The test system includes a thermal control system to control a temperature of the DUT separately from control over temperatures of other DUTs in other test sites. The thermal control system includes a thermoelectric cooler (TEC) and a structure that is thermally conductive. The TEC is in thermal communication with the DUT to control the temperature of the DUT by transferring heat between the DUT and the structure.
G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
F25B 21/04 - Machines, installations ou systèmes utilisant des effets électriques ou magnétiques utilisant l'effet PeltierMachines, installations ou systèmes utilisant des effets électriques ou magnétiques utilisant l'effet Nernst-Ettinghausen réversibles
G01R 1/04 - BoîtiersOrganes de supportAgencements des bornes
An example test system includes test sites comprising test sockets for testing devices under test (DUTs) and pickers for picking DUTs from the test sockets or placing the DUTs into the test sockets. Each picker may include a picker head for holding a DUT. The test system also includes a gantry on which the pickers are mounted. The gantry may be configured to move the pickers relative to the test sites to position the pickers for picking the DUTs from the test sockets or placing the DUTs into the test sockets. The test sockets are arranged in at least one array that is accessible to the pickers on the gantry.
An example test system includes test sites that include sockets for testing devices under test (DUTs), pickers for picking DUTs from the sockets or placing the DUTs in the sockets, and a gantry on which the pickers are mounted. The gantry is configured to move the pickers relative to the test sites to position the pickers for picking the DUTs from the sockets or placing the DUTs into the sockets. The test system also includes one or more LASER range finders mounted on the gantry for movement over the DUTs in the sockets and in conjunction with movement of the pickers. A LASER range finder among the one or more LASER rangefinders mounted on the gantry is configured to detect a distance to a DUT placed into a socket.
An example test system includes test sites comprising test sockets for testing devices under test (DUTs) and pickers for picking DUTs from the test sockets or placing the DUTs into the test sockets. Each picker may include a picker head for holding a DUT. The test system also includes a gantry on which the pickers are mounted. The gantry may be configured to move the pickers relative to the test sites to position the pickers for picking the DUTs from the test sockets or placing the DUTs into the test sockets. The test sockets are arranged in at least one array that is accessible to the pickers on the gantry.
An example test system includes test sites for testing devices under test (DUTs), where the test sites include a test site configured to hold a DUT for testing. The test system includes a thermal control system to control a temperature of the DUT separately from control over temperatures of other DUTs in other test sites. The thermal control system includes a thermoelectric cooler (TEC) and a structure that is thermally conductive. The TEC is in thermal communication with the DUT to control the temperature of the DUT by transferring heat between the DUT and the structure.
G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
G01R 31/00 - Dispositions pour tester les propriétés électriquesDispositions pour la localisation des pannes électriquesDispositions pour tests électriques caractérisées par ce qui est testé, non prévues ailleurs
62.
APPARATUS AND METHOD FOR OPERATING SOURCE SYNCHRONOUS DEVICES
Circuitry and methods of operating the same to strobe a DQ signal with a gated DQS signal are described. Some aspects are directed to a gating scheme to selectively pass a received strobe signal such as a DQS strobe signal based on a state of a drive enable (DE) signal in a drive circuit in the ATE, such that edges generated by the drive circuit are prevented from mistakenly strobing a received data signal such as a DQ signal.
Circuitry and methods of operating the same to strobe a DQ signal with a gated DQS signal are described. Some aspects are directed to a gating scheme to selectively pass a received strobe signal such as a DQS strobe signal based on a state of a drive enable (DE) signal in a drive circuit in the ATE, such that edges generated by the drive circuit are prevented from mistakenly strobing a received data signal such as a DQ signal.
G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
Example systems for determining a configuration of a test system execute operations that include receiving first parameters specifying at least part of an operation of a test system; receiving second parameters specifying at least part of a first configuration of the test system; determining a second configuration of the test system based, at least in part, on the first parameters and the second parameters, with the second configuration being determined to impact a cost of test of the test system; generating, by one or more processing devices, data for a graphical user interface representing information about the second configuration and the cost of test; and outputting the data for the graphical user interface for rendering on a display device.
G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
G06Q 10/06 - Ressources, gestion de tâches, des ressources humaines ou de projetsPlanification d’entreprise ou d’organisationModélisation d’entreprise ou d’organisation
An example includes the following operations: identifying parameters associated with a test program, where the parameters are based on at least one of a device under test (DUT) to be tested by the test program or a type of test to be performed on the DUT by the test program; assigning weights to the parameters; generating a numerical value for the test program based on the parameters, the weights, and equations that are based on the parameters and the weights, where the numerical value is indicative of a complexity of the test program; and using the numerical value to obtain information about effort needed to develop future test programs.
An example test system includes a device interface board (DIB) having one or more signal transmission paths and an interface for connecting to one or more other components of the test system. Test circuitry is configured to inject test signals into the one or more signal transmission paths and to measure transmitted versions of the test signals at the interface to obtain measurement signals. One or more processing devices are configured to generate calibration factors based on differences between the injected test signals and the measurement signals, and to store the calibration factors in computer memory. The calibration factors are for correcting for effects on the test signals of the one or more signal transmission paths.
An example test system includes a device interface board (DIB) having one or more signal transmission paths and an interface for connecting to one or more other components of the test system. Test circuitry is configured to inject test signals into the one or more signal transmission paths and to measure transmitted versions of the test signals at the interface to obtain measurement signals. One or more processing devices are configured to generate calibration factors based on differences between the injected test signals and the measurement signals, and to store the calibration factors in computer memory. The calibration factors are for correcting for effects on the test signals of the one or more signal transmission paths.
Example circuitry includes a first circuit to provide a low signal; a second circuit to provide a high signal, where the high signal has a greater voltage magnitude than the low signal; and a differential amplifier configured to receive the low signal from the first circuit and the high signal from the second circuit. The differential amplifier is for producing an output voltage that is based on the high signal and the low signal. The example circuitry includes a first measurement circuit to measure the output voltage; a second measurement circuit to measure the low signal at the first circuit; and processing logic to determine a differential measurement based on the output voltage measured by the first measurement circuit, the low signal measured by the second measurement circuit, and calibration values obtained for the circuitry.
G01R 35/00 - Test ou étalonnage des appareils couverts par les autres groupes de la présente sous-classe
G01R 19/25 - Dispositions pour procéder aux mesures de courant ou de tension ou pour en indiquer l'existence ou le signe utilisant une méthode de mesure numérique
G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
Example circuitry includes a first circuit to provide a low signal; a second circuit to provide a high signal, where the high signal has a greater voltage magnitude than the low signal; and a differential amplifier configured to receive the low signal from the first circuit and the high signal from the second circuit. The differential amplifier is for producing an output voltage that is based on the high signal and the low signal. The example circuitry includes a first measurement circuit to measure the output voltage; a second measurement circuit to measure the low signal at the first circuit; and processing logic to determine a differential measurement based on the output voltage measured by the first measurement circuit, the low signal measured by the second measurement circuit, and calibration values obtained for the circuitry.
An example apparatus includes a block configured to connect mechanically to a circuit board. The circuit board includes a first conductive path running to a first electrical contact on the circuit board and a second conductive path running to a second electrical contact on the circuit board. The first electrical contact and the second electrical contact are arranged in an area of the circuit board. The block includes a component having a surface that is configured to cover at least part of the area. A conductive layer is attached to at least part of the surface. The conductive layer is for creating a short circuit between the first electrical contact and the second electrical contact following connection of the block to the circuit board.
A probe card in an automated test equipment (ATE) and methods for operating the same for testing electronic devices. The probe card may be a portion of a vertical-type probe card assembly in which pads on a circuit board are contacted by probe pins. The probe card has a pad geometry that compensates for misalignment with corresponding probe pins due to manufacturing error or a mismatch of coefficient of thermal expansion, enabling reliable operation of the ATE over a wide range of test temperatures. The pad array may have a plurality of elongated pads, each of uniquely designed size, tilt angle, and/or center location, with the characteristics of each pad being dependent on a distance between each pad and a centroid of the pad array, such that a probe pin to pad location errors can be mitigated.
A probe card in an automated test equipment (ATE) is disclosed. The probe card may be a portion of a vertical-type probe card assembly in which pads on a circuit board are contacted by probe pins, with vertical vias in the circuit board interconnecting various conductive elements. Disclosed herein is a probe card having ground vias in a coaxial arrangement around a signal via that provide electromagnetic shielding to a signal via to reduce crosstalk between adjacent signal vias.
G01R 3/00 - Appareils ou procédés spécialement adaptés à la fabrication des appareils de mesure
G01R 31/01 - Passage successif d'articles similaires aux tests, p. ex. tests "tout ou rien" d'une production de sérieTest d'objets en certains points lorsqu'ils passent à travers un poste de test
Probe pin arrangements in a vertical-type probe card assembly for an automated test equipment (ATE) are disclosed. In some embodiments, one or more additional conductive regions are provided in between adjacent probe pins. The additional conductive regions may reduce spacing between probe pins connected to adjacent probe card pads, and may in turn reduce mutual inductance between the two probe cards pads, and provide improved impedance matching. In one embodiment, the additional conductive region is a short probe pin. In another embodiment, the additional conductive region is a protrusion on a vertical probe pin.
G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
G01R 31/01 - Passage successif d'articles similaires aux tests, p. ex. tests "tout ou rien" d'une production de sérieTest d'objets en certains points lorsqu'ils passent à travers un poste de test
75.
TRANSPOSED VIA ARRANGEMENT IN PROBE CARD FOR AUTOMATED TEST EQUIPMENT
A probe card in an automated test equipment (ATE) is disclosed. The probe card may be a portion of a vertical-type probe card assembly in which pads on a circuit board are contacted by probe pins, with vertical vias in the circuit board interconnecting various conductive elements. Disclosed herein is a transposed via arrangement within a circuit board for a probe card, where adjacent vias are offset towards each other such that the inductance between the adjacent vias may be reduced to provide a desirable impedance during high frequency signal and/or power transmission.
G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
G01R 3/00 - Appareils ou procédés spécialement adaptés à la fabrication des appareils de mesure
G01R 1/04 - BoîtiersOrganes de supportAgencements des bornes
G01R 31/01 - Passage successif d'articles similaires aux tests, p. ex. tests "tout ou rien" d'une production de sérieTest d'objets en certains points lorsqu'ils passent à travers un poste de test
An example optical receiving device includes a photodiode to receive an optical signal, where the photodiode is configured to conduct a current that is based on an optical power of the optical signal, and a radio frequency (RF) gain circuitry to generate one or more analog electrical signals based on the current and based on gain provided by the RF gain circuitry. A power detector is configured to receive an analog electrical signal of the one or more analog electrical signals, to detect alternating current (AC) power of the optical signal based on the analog electrical signal, and to output a signal representing the AC power based on the detecting.
H04B 10/69 - Dispositions électriques dans le récepteur
H03G 3/30 - Commande automatique dans des amplificateurs comportant des dispositifs semi-conducteurs
G01R 15/24 - Adaptations fournissant une isolation en tension ou en courant, p. ex. adaptations pour les réseaux à haute tension ou à courant fort utilisant des dispositifs modulateurs de lumière
G01R 19/18 - Dispositions pour procéder aux mesures de courant ou de tension ou pour en indiquer l'existence ou le signe utilisant la conversion d'un courant continu en courant alternatif, p. ex. à l'aide de vibreurs
G01R 19/25 - Dispositions pour procéder aux mesures de courant ou de tension ou pour en indiquer l'existence ou le signe utilisant une méthode de mesure numérique
An example optical receiving device includes a photodiode to receive an optical signal, where the photodiode is configured to conduct a current that is based on an optical power of the optical signal, and a radio frequency (RF) gain circuitry to generate one or more analog electrical signals based on the current and based on gain provided by the RF gain circuitry. A power detector is configured to receive an analog electrical signal of the one or more analog electrical signals, to detect alternating current (AC) power of the optical signal based on the analog electrical signal, and to output a signal representing the AC power based on the detecting.
An example method determines an error vector magnitude using automatic test equipment (ATE). The method includes demodulating data received at a first receiver to produce first symbol error vectors, where each first symbol error vector represents a difference between a predefined point on a constellation diagram and a first measured point on the constellation diagram generated based on at least part of the data received by the first receiver; demodulating the data received at a second receiver to produce second symbol error vectors, where each second symbol error vector represents a difference between the predefined point on the constellation diagram and a second measured point on the constellation diagram generated based on at least part of the data received by the second receiver; and determining the error vector magnitude for the data based on the first symbol error vectors and the second symbol error vectors.
Embodiments of the present disclosure are directed towards robotic systems and methods. The robot may include an end effector, a tool flange of the robot, and a joint. The end effector may include a contacting part configured to contact a workpiece. The joint may be positioned between, and connected to, the tool flange and the end effector. The joint may include a variable angle between the tool flange and the end effector.
An example method of stabilizing a voltage at a device under test (DUT) includes identifying one or more characteristics of a deviation in a first voltage to appear at the DUT. The deviation may result from a digital signal and a concomitant transient current in the DUT. The digital signal may be part of a test flow to be sent over one or more test channels of automatic test equipment (ATE) to the DUT. The one or more characteristics may be identified prior to sending the test flow to the DUT. The method also includes generating a second voltage to apply to the DUT. The second voltage may be based on the one or more characteristics and being shaped to reduce the deviation.
An example method of stabilizing a voltage at a device under test (DUT) includes identifying one or more characteristics of a deviation in a first voltage to appear at the DUT. The deviation may result from a digital signal and a concomitant transient current in the DUT. The digital signal may be part of a test flow to be sent over one or more test channels of automatic test equipment (ATE) to the DUT. The one or more characteristics may be identified prior to sending the test flow to the DUT. The method also includes generating a second voltage to apply to the DUT. The second voltage may be based on the one or more characteristics and being shaped to reduce the deviation.
G01R 31/00 - Dispositions pour tester les propriétés électriquesDispositions pour la localisation des pannes électriquesDispositions pour tests électriques caractérisées par ce qui est testé, non prévues ailleurs
G01R 19/10 - Mesure d'une somme, d'une différence, ou d'un rapport
G01R 31/01 - Passage successif d'articles similaires aux tests, p. ex. tests "tout ou rien" d'une production de sérieTest d'objets en certains points lorsqu'ils passent à travers un poste de test
An example apparatus includes a cover to shield, at least partly, a conductive trace on a surface of a circuit board from electromagnetic interference. The cover includes a conductive surface that faces the conductive trace. The cover at least partly encloses a volume over the conductive trace. The volume is for holding air over the conductive trace. One or more contacts electrically connect the conductive surface of the cover to electrical ground on the circuit board.
H05K 9/00 - Blindage d'appareils ou de composants contre les champs électriques ou magnétiques
G01R 31/00 - Dispositions pour tester les propriétés électriquesDispositions pour la localisation des pannes électriquesDispositions pour tests électriques caractérisées par ce qui est testé, non prévues ailleurs
G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
An example apparatus includes a cover to shield, at least partly, a conductive trace on a surface of a circuit board from electromagnetic interference. The cover includes a conductive surface that faces the conductive trace. The cover at least partly encloses a volume over the conductive trace. The volume is for holding air over the conductive trace. One or more contacts electrically connect the conductive surface of the cover to electrical ground on the circuit board.
An example test system includes an output stage to source at least one of voltage or current to a channel of a test instrument; a tracking circuit to detect a channel voltage following the output stage and to control a supply voltage to the output stage based on the channel voltage; and a controller to determine a power dissipation of the output stage based on the supply voltage and the channel voltage, and to control the output stage based on the power dissipation in the output stage.
G01R 22/06 - Dispositions pour la mesure de l'intégrale dans le temps d'une puissance électrique ou d'un courant, p. ex. compteurs d'électricité par des méthodes électroniques
G01R 21/06 - Dispositions pour procéder aux mesures de la puissance ou du facteur de puissance par mesure du courant et de la tension
G01R 19/165 - Indication de ce qu'un courant ou une tension est, soit supérieur ou inférieur à une valeur prédéterminée, soit à l'intérieur ou à l'extérieur d'une plage de valeurs prédéterminée
G01R 35/00 - Test ou étalonnage des appareils couverts par les autres groupes de la présente sous-classe
86.
Controlling power dissipation in an output stage of a test channel
An example test system includes an output stage to source at least one of voltage or current to a channel of a test instrument; a tracking circuit to detect a channel voltage following the output stage and to control a supply voltage to the output stage based on the channel voltage; and a controller to determine a power dissipation of the output stage based on the supply voltage and the channel voltage, and to control the output stage based on the power dissipation in the output stage.
G01R 31/00 - Dispositions pour tester les propriétés électriquesDispositions pour la localisation des pannes électriquesDispositions pour tests électriques caractérisées par ce qui est testé, non prévues ailleurs
G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
87.
SYSTEM AND METHOD FOR ROBOTIC BIN PICKING USING ADVANCED SCANNING TECHNIQUES
A method and system for programming picking and placing of a workpiece is provided. Embodiments may include associating a workpiece with an end effector that is attached to a robot and scanning the workpiece while the workpiece is associated with the end effector. Embodiments may also include determining a pose of the workpiece relative to the robot, based upon, at least in part, the scanning.
A method and system for programming picking and placing of a workpiece is provided. Embodiments may include associating a workpiece with an end effector that is attached to a robot and scanning the workpiece while the workpiece is associated with the end effector. Embodiments may also include determining a pose of the workpiece relative to the robot, based upon, at least in part, the scanning.
The systems determine the parasitic capacitance of a signal path. That parasitic capacitance is then used to determine a leakage characteristic of the signal path, such as leakage current or leakage resistance. The capability of ATE channels to force current accurately, and to measure time intervals at prescribed voltages, can be used to multiply the accuracy of the force current function. Using these resources, small leakage currents—for example, on the order of 10 nA or less—can be measured.
G01R 31/50 - Test d’appareils, de lignes, de câbles ou de composants électriques pour y déceler la présence de courts-circuits, de continuité, de fuites de courant ou de connexions incorrectes de lignes
90.
Using vibrations to position devices in a test system
An example test system includes a tray to hold devices, where the devices include devices to be tested or devices that have been tested; a motor that is controllable to cause vibrations; and a component that couples the motor to the tray to cause the tray to vibrate in response to the vibrations of the motor.
An example test system includes a tray to hold devices, where the devices include devices to be tested or devices that have been tested; a motor that is controllable to cause vibrations; and a component that couples the motor to the tray to cause the tray to vibrate in response to the vibrations of the motor.
An example method measures a leakage characteristic of a signal path. The example method includes forcing a current onto the signal path; determining a parasitic capacitance of the signal path based on a rate of change of a voltage on the signal path resulting from the current; forcing a voltage onto the signal path for a period of time; and following the period of time, determining the leakage characteristic based on the parasitic capacitance and a rate of change in voltage on the signal path from the forced voltage.
An example test system includes a circuit to sample a signal that is repetitive in cycles to obtain data; a processor configured to generate an eye diagram based on the data, where the eye diagram represents parametric information about the signal; and a functional test circuit to receive the signal and to perform one or more functional tests on the signal. The test systems is configured to receive the signal from a unit under test and to allow the signal to pass to the functional test circuit inline without changing at least part of the signal.
Example automatic test equipment (ATE) includes a first test instrument to receive a waveform from a device under test, where the waveform is based on test signals sent from the ATE to the DUT; circuitry to generate digital pulses based on the waveform; and a second test instrument to receive the digital pulses over at least two digital pins and to process the digital pulses to test the DUT.
Example automatic test equipment (ATE) includes a first test instrument to receive a waveform from a device under test, where the waveform is based on test signals sent from the ATE to the DUT; circuitry to generate digital pulses based on the waveform; and a second test instrument to receive the digital pulses over at least two digital pins and to process the digital pulses to test the DUT.
Aspects of the present application are directed to an automated test equipment (ATE) and methods for operating the same for testing high-power electronic components. The inventor has recognized and appreciated an ATE that provides both high-power alternating-current (AC) and direct-current (DC) testing in a single test system can lead to high throughput testing for high- power components with reduced system hardware complexity and cost. Aspects of the present application provide a synchronized inductor switch module and both a high-precision digitizer and a high-speed digitizer for capturing DC and AC characteristics of a high-power transistor.
Aspects of the present application are directed to an automated test equipment (ATE) and methods for operating the same for testing high-power electronic components. The inventor has recognized and appreciated an ATE that provides both high-power alternating-current (AC) and direct-current (DC) testing in a single test system can lead to high throughput testing for high-power components with reduced system hardware complexity and cost. Aspects of the present application provide a synchronized inductor switch module and both a high-precision digitizer and a high-speed digitizer for capturing DC and AC characteristics of a high-power transistor.
G01R 31/3167 - Tests de circuits analogiques et numériques combinés
H03K 5/131 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés contrôlées numériquement
G01R 31/3183 - Génération de signaux d'entrée de test, p. ex. vecteurs, formes ou séquences de test
Circuitry and methods of operating the same to delay a signal by a precise and variable amount. One embodiment is directed to a high speed delay line used in automated test equipment. The inventors have recognized and appreciated that an input signal having high data rate may be split into parallel split signals having lower data rates that are delayed in respective parallel delay paths before being combined to generate a delayed signal. One advantage of delaying a signal in such a fashion is to provide high delay line timing accuracy at high data speeds, while using a compact circuit design using circuitry components of lower bandwidth with reduced power consumption, for example by using complementary metal- oxide- semiconductor (CMOS). A further advantage is that a high speed delay line may be constructed from multiple lower data rate parallel delay lines that are modular, simplifying circuit design.
G01R 31/3193 - Matériel de test, c.-à-d. circuits de traitement de signaux de sortie avec une comparaison entre la réponse effective et la réponse connue en l'absence d'erreur
G01R 31/3183 - Génération de signaux d'entrée de test, p. ex. vecteurs, formes ou séquences de test
Disclosed herein are voltage driver circuits and methods of operating the same to provide a variable output voltage that is suitable for use in ATE to provide a large number of test signals with accurate voltage levels at high data rates using components that consume relatively low power. According to an aspect, a change in output current in a voltage driver related to changing output voltage may be offset by a stabilization current generated by a correction driver for the voltage driver, such that supply currents drawn from the supply voltages can remain substantially stable. The correction driver may be connected to one or more supply voltages, and programmed to output a stabilization current that offsets changes in supply currents arising from changing of the programmed output of the voltage driver circuit. Such a driver may enable a test system to more precisely test semiconductor devices.
Circuitry and methods of operating the same to delay a signal by a precise and variable amount. One embodiment is directed to a high speed delay line used in automated test equipment. The inventors have recognized and appreciated that an input signal having high data rate may be split into parallel split signals having lower data rates that are delayed in respective parallel delay paths before being combined to generate a delayed signal. One advantage of delaying a signal in such a fashion is to provide high delay line timing accuracy at high data speeds, while using a compact circuit design using circuitry components of lower bandwidth with reduced power consumption, for example by using complementary metal-oxide-semiconductor (CMOS). A further advantage is that a high speed delay line may be constructed from multiple lower data rate parallel delay lines that are modular, simplifying circuit design.
H03K 5/15 - Dispositions dans lesquelles des impulsions sont délivrées à plusieurs sorties à des instants différents, c.-à-d. distributeurs d'impulsions
G01R 35/00 - Test ou étalonnage des appareils couverts par les autres groupes de la présente sous-classe
G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
H03K 5/00 - Transformation d'impulsions non couvertes par l'un des autres groupes principaux de la présente sous-classe
H03K 19/21 - Circuits OU EXCLUSIF, c.-à-d. donnant un signal de sortie si un signal n'existe qu'à une seule entréeCircuits à COÏNCIDENCES, c.-à-d. ne donnant un signal de sortie que si tous les signaux d'entrée sont identiques
