Proposed is a test board for a burn-in test. According to a specific embodiment of the present technology, in a basic-type test board that supplies a test signal of a PGB to sockets of sub-boards, each sub-board is arranged in a single-row single-layer structure on one interface board or FTB, so the height of the test board can be lowered compared to a conventional test board, thereby enabling smooth airflow, and a plurality of semiconductor devices can be tested in a uniform environment, thereby improving the durability of the test board. Furthermore, each sub-board is connected in parallel to the interface board or FTB, so a test signal can be simultaneously supplied to sockets of each sub-board through each sub-connector, thereby enabling high-speed processing. Moreover, each sub-board can be configured in various types and sizes, so the productivity of a test board circuit board can be increased.
The present invention relates to an automatic coupler for supplying utilities, the coupler comprising: a first coupling member (110) provided in one from among a utility supply end and a utility reception end; a first valve body (120) which is provided in the first coupling member (110), and which has an elastically-supported first check ball (121) such that a flow path is opened and closed by the first check ball (121); a second coupling member (210) provided in the other from among the utility supply end and the utility reception end, and coupled to the first coupling member (110); and a second valve body (220) which is provided in the second coupling member (210), and which has an elastically-supported second check ball (221) such that a flow path is opened and closed by the second check ball (221), wherein the second valve body (220) includes: a main body part (222); a first floating body part (223) elastically supported with respect to the main body part (222); and a second floating body part (224) which is elastically supported with respect to the first floating body part (223) so that a portion thereof protrudes to the outside of the first floating body part (223), and which elastically supports the second check ball (221) so that a portion of the second check ball (221) protrudes to the outside of the first floating body part (223).
F16L 37/33 - Accouplements du type à action rapide avec moyens pour couper l'écoulement du fluide avec un obturateur dans chaque extrémité de tuyau avec deux clapets dont l'un au moins est ouvert automatiquement au moment de l'accouplement les clapets étant du type à bille
F16K 15/04 - Soupapes, clapets ou valves de retenue à corps de soupapes rigides guidés en forme de sphère
F16K 27/02 - Structures des logementsMatériaux utilisés à cet effet des soupapes de levage
The present invention relates to an electric connector for utility supply, comprising: a first coupling member (110) provided on one of a utility supply end and a utility receiving end; a first terminal portion (120) provided on the first coupling member (110); a second coupling member (210) provided on the other of the utility supply end and the utility receiving end and coupled to the first coupling member (110); and a second terminal portion (220) provided on the second coupling member (210) so as to elastically contact the first terminal portion (120).
H01R 13/514 - SoclesBoîtiers formés comme un bloc ou un assemblage modulaire, c.-à-d. composés de parties coopérantes pourvues de pièces de contact ou maintenant entre elles des pièces de contact
H01R 13/631 - Moyens additionnels pour faciliter l'engagement ou la séparation des pièces de couplage, p. ex. moyens pour aligner ou guider, leviers, pression de gaz pour l'engagement uniquement
H01R 13/24 - Contacts pour coopération par aboutage élastiquesContacts pour coopération par aboutage montés élastiquement
H01R 13/66 - Association structurelle avec des composants électriques incorporés
G01R 1/04 - BoîtiersOrganes de supportAgencements des bornes
Proposed is an automatic coupler for supplying a utility. The automatic coupler includes a first coupling member provided on any one of a utility supplying end or a utility receiving end, and a first valve body provided in the first coupling member and provided with a first check ball elastically supported, a second coupling member provided on the other one of the utility supplying end or the utility receiving end and coupled to the first coupling member, and a second valve body provided in the second coupling member and provided with a second check ball elastically supported. The second valve body includes a main body, a first floating body, and a second floating body elastically supported to the first floating body, the second floating body elastically supporting the second check ball.
F16L 37/33 - Accouplements du type à action rapide avec moyens pour couper l'écoulement du fluide avec un obturateur dans chaque extrémité de tuyau avec deux clapets dont l'un au moins est ouvert automatiquement au moment de l'accouplement les clapets étant du type à bille
F16L 29/04 - Raccords comportant des moyens pour couper le courant de fluide comportant un obturateur dans chacune des deux extrémités de tuyau, les obturateurs s'ouvrant automatiquement lors de l'accouplement
F16L 37/23 - Accouplements du type à action rapide dans lesquels l'assemblage est maintenu par des billes, rouleaux ou ressorts hélicoïdaux sous pression radiale entre parties au moyen de billes
Proposed is an electrical connector for supplying a utility. The electrical connector includes a first coupling member provided on any one of a utility supplying end or a utility receiving end, a first terminal provided on the first coupling member, a second coupling member provided on other one of the utility supplying end or the utility receiving end and configured to be coupled to the first coupling member, and a second terminal provided on the second coupling member and configured to be elastically in contact with the first terminal.
H01R 13/15 - Broches, lames ou alvéoles ayant un ressort indépendant pour produire ou améliorer la pression de contact
H01R 13/405 - Fixation d'une manière non démontable, p. ex. par moulage, rivetage
H01R 13/629 - Moyens additionnels pour faciliter l'engagement ou la séparation des pièces de couplage, p. ex. moyens pour aligner ou guider, leviers, pression de gaz
6.
CARTRIDGE MODULE AND MULTI-WAFER TEST APPARATUS USING SAME
The present invention relates to a cartridge module capable of maintaining its own position through the modularization of a probe card and a wafer, and to a multi-wafer test apparatus capable of testing multiple wafers in a single test by using the cartridge module. The multi-wafer test apparatus according to the present invention includes: at least two chambers (120) connected to a tester (110) and each provided with a test head (121) for electrically connecting the tester (110) to a probe card; a cartridge module (200) including a first body part (210) provided with a probe card (211), and a second body part (220) provided with a wafer chuck (221), on which a wafer (10) is to be seated, and detachably assembled with the first body part (210); a wafer loading part (130) configured to perform unclamping of the first body part (210) and the second body part (220) to detach the first body part (210) from the second body part (220) to load a wafer (10) onto the second body part (220), and to perform a clamping operation to assemble the first body part (210) and the second body part (220); and a transfer part (150) configured to transfer the cartridge module (200) between the wafer loading unit (130) and the chambers (120).
Proposed is a cartridge module that modularizes a probe card and a wafer to maintain positions thereof, and a multi wafer burn-in test device capable of inspecting multiple wafers in one test using the same. The device includes at least two chambers (120), each of which has a test head (121) that electrically connects a probe card and a tester (110) to test a loaded wafer, a cartridge module (200) including a first body (210) provided with the probe card (211), and a second body (220) provided with a wafer chuck (221) on which a wafer (10) is seated, the first body (210) and the second body (220) being detachably assembled with each other, a wafer loading unit (130) for loading the wafer (10) into the second body (220), and a transfer unit (150) configured to transfer and deliver the cartridge module (200).
The present invention relates to a probe card holder capable of maintaining a self-position by fixing a probe card and a wafer together as one unit for inspecting a wafer, the probe card holder comprising: a first body part (110) having a probe card (111) in the center and a guide hole (112) vertically penetrating around the probe card (111); a second body part (120) having a wafer chuck (121) on which a wafer is mounted in the center and a magnet holder (122) corresponding to the guide hole (112); a weight ring (130) having a magnet chuck (131) inserted into the guide hole (112) to be fixed to the magnet holder (122) by a magnetic force, and assembled with the second body part (120) at an upper portion of the first body part (110); and a clamping part (140) provided between the first body part (110) and the weight ring (130) to fix a gap between the first body part (110) and the weight ring (130).
Proposed is a probe card holder for wafer testing including a first body part (110) provided with a probe card (111) and through guide holes (112) vertically formed around the probe card (111), a second body part (120) provided with a wafer chuck (121) on which a wafer is seated and a magnet holder (122) corresponding to the guide hole (112), a weight ring (130) provided with a magnet chuck (131) that is inserted into the guide hole (112) and fixed with the magnet holder (122) by magnetic force, and assembled with the second body part (120) at a top of the first body part (110), and a clamping part (140) provided between the first body part (110) and the weight ring (130) to hold spacing between the first body part (110) and the weight ring (130).
The present invention relates to a surface treatment method for a perovskite thin film and, more specifically, to: a surface treatment method for a perovskite thin film, capable of improving durability and efficiency and ensuring light stability by removing surplus ions present in a perovskite thin film; and to a solar cell manufactured by comprising same.
H10K 30/40 - Dispositifs organiques sensibles au rayonnement infrarouge, à la lumière, au rayonnement électromagnétique de plus courte longueur d'onde ou au rayonnement corpusculaire comprenant une structure p-i-n, ayant p. ex. un absorbeur pérovskite entre des couches de transport de charge de type p et de type n
The present invention relates to a perovskite solar cell module and a manufacturing method for same. The perovskite solar cell module comprises a plurality of perovskite solar cells disposed on a substrate, each of the perovskite solar cells comprising: a first electrode, a first charge transport layer on the first electrode, an optical active layer formed of a perovskite crystal structure, and a second charge transport layer, which are laminated in this order; and a second electrode laminated on the second charge transport layer, wherein the second electrode included in each of the cells can be electrically connected in series to the first electrode of the closest perovskite solar cell and enhance the photoelectric conversion efficiency of the perovskite solar cell module.
The present invention relates to a perovskite solar cell module and a manufacturing method for same. The perovskite solar cell module comprises a plurality of perovskite solar cells disposed on a substrate, each of the perovskite solar cells comprising: a first electrode, a first charge transport layer on the first electrode, an optical active layer formed of a perovskite crystal structure, and a second charge transport layer, which are laminated in this order; and a second electrode laminated on the second charge transport layer, wherein the second electrode included in each of the cells can be electrically connected in series to the first electrode of the closest perovskite solar cell and enhance the photoelectric conversion efficiency of the perovskite solar cell module.
H01L 51/44 - Dispositifs à l'état solide qui utilisent des matériaux organiques comme partie active, ou qui utilisent comme partie active une combinaison de matériaux organiques et d'autres matériaux; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de tels dispositifs ou de leurs parties constitutives spécialement adaptés, soit comme convertisseurs de l'énergie dudit rayonnement en énergie électrique, soit comme dispositifs de commande de l'énergie électrique par ledit rayonnement - Détails des dispositifs
H01L 51/42 - Dispositifs à l'état solide qui utilisent des matériaux organiques comme partie active, ou qui utilisent comme partie active une combinaison de matériaux organiques et d'autres matériaux; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de tels dispositifs ou de leurs parties constitutives spécialement adaptés, soit comme convertisseurs de l'énergie dudit rayonnement en énergie électrique, soit comme dispositifs de commande de l'énergie électrique par ledit rayonnement
H01L 51/00 - Dispositifs à l'état solide qui utilisent des matériaux organiques comme partie active, ou qui utilisent comme partie active une combinaison de matériaux organiques et d'autres matériaux; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de tels dispositifs ou de leurs parties constitutives
KOREA RESEARCH INSTITUTE OF CHEMICAL TECHNOLOGY (République de Corée)
UNITEST INC (République de Corée)
Inventeur(s)
Jeon, Nam Joong
Shin, Seong Sik
Park, Helen Hejin
Song, Seulki
Moon, Chan Su
Kim, Geun Jin
Huh, Jaesuk
Abrégé
33 (A is a monovalent organic cation; M is a divalent metal ion; and X is a halogen anion including I-and Br-); and a tin ion as an anion segregation inhibitor. The perovskite light absorption layer according to the present invention can stably maintain wide bandgap characteristics since the anion segregation by light is prevented in the perovskite light absorption layer.
H01L 51/42 - Dispositifs à l'état solide qui utilisent des matériaux organiques comme partie active, ou qui utilisent comme partie active une combinaison de matériaux organiques et d'autres matériaux; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de tels dispositifs ou de leurs parties constitutives spécialement adaptés, soit comme convertisseurs de l'énergie dudit rayonnement en énergie électrique, soit comme dispositifs de commande de l'énergie électrique par ledit rayonnement
H01L 31/055 - Dispositifs à semi-conducteurs sensibles aux rayons infrarouges, à la lumière, au rayonnement électromagnétique d'ondes plus courtes, ou au rayonnement corpusculaire, et spécialement adaptés, soit comme convertisseurs de l'énergie dudit rayonnement e; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives; Leurs détails adaptés comme dispositifs de conversion photovoltaïque [PV] Éléments optiques directement associés ou intégrés à la cellule PV, p.ex. moyens réflecteurs ou concentrateurs de lumière où la lumière est absorbée et réémise avec une longueur d’onde différente par l’élément optique directement associé ou intégré à la cellule PV, p.ex. en utilisant un matériau luminescent, des concentrateurs fluorescents ou des dispositions de convers
H01L 31/0745 - Dispositifs à semi-conducteurs sensibles aux rayons infrarouges, à la lumière, au rayonnement électromagnétique d'ondes plus courtes, ou au rayonnement corpusculaire, et spécialement adaptés, soit comme convertisseurs de l'énergie dudit rayonnement e; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives; Leurs détails adaptés comme dispositifs de conversion photovoltaïque [PV] caractérisés par au moins une barrière de potentiel ou une barrière de surface les barrières de potentiel étant uniquement du type PN à hétérojonction comprenant uniquement une hétérojonction AIVBIV, p.ex. cellules solaires Si/Ge, SiGe/Si ou Si/SiC
H01L 31/0725 - Cellules solaires à jonctions multiples ou dites "tandem"
H01L 51/00 - Dispositifs à l'état solide qui utilisent des matériaux organiques comme partie active, ou qui utilisent comme partie active une combinaison de matériaux organiques et d'autres matériaux; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de tels dispositifs ou de leurs parties constitutives
14.
Sealed plasma melting furnace for treating low- and intermediate-level radioactive waste
The present invention relates to a sealed plasma melting furnace for treating low- and intermediate-level radioactive waste, which allows the secondary pollutants to be minimized. The sealed plasma melting furnace includes: a waste supply chamber communicatively provided with a hopper; a pyrolysis chamber channel communicatively coupled with the waste supply chamber; a pyrolysis chamber having a burner mounted thereon; a melting chamber channel guiding the waste transferred from the pyrolysis chamber communicatively provided therewith to fall down; a melting chamber provided with a furnace interior portion accommodating a molten substance on a bottom surface thereof; a processed molten substance discharge channel discharging the processed molten substance generated in the melting chamber; a secondary combustion chamber channel inducing and exhausting an off-gas flow generated in the melting chamber; and a secondary combustion chamber inducing complete combustion of the off-gas input from the secondary combustion chamber channel.
B09B 3/00 - Destruction de déchets solides ou transformation de déchets solides en quelque chose d'utile ou d'inoffensif
F23G 5/027 - Procédés ou appareils, p. ex. incinérateurs, spécialement adaptés à la combustion de déchets ou de combustibles pauvres comportant un traitement préalable par pyrolyse ou par gazéification
F27B 17/00 - Fours d'un genre non couvert par l'un des groupes
F23G 5/16 - Procédés ou appareils, p. ex. incinérateurs, spécialement adaptés à la combustion de déchets ou de combustibles pauvres comportant un chauffage supplémentaire comportant une combustion secondaire dans une chambre de combustion séparée
F23G 5/08 - Procédés ou appareils, p. ex. incinérateurs, spécialement adaptés à la combustion de déchets ou de combustibles pauvres comportant un chauffage supplémentaire
F23G 5/44 - Procédés ou appareils, p. ex. incinérateurs, spécialement adaptés à la combustion de déchets ou de combustibles pauvres Parties constitutivesAccessoires
F23G 5/00 - Procédés ou appareils, p. ex. incinérateurs, spécialement adaptés à la combustion de déchets ou de combustibles pauvres
G21F 9/14 - Traitements par incinérationTraitements par calcination, p. ex. dessiccation
An apparatus for measuring round-trip time of a test signal using a programmable logic device comprises a pattern generator generating a test signal and measuring a round-trip time of the test signal, a programmable logic device of which internal circuits are configured to transmit the test signal in a predetermined manner, and bidirectional bus lines connecting the pattern generator and the programmable logic device. The round-trip time of the test signal is measured by a time difference between a starting time at which the pattern generator outputs the test signal and an arrival time at which the test signal is fed back to the pattern generator.
G11C 29/56 - Équipements externes pour test de mémoires statiques, p. ex. équipement de test automatique [ATE]Interfaces correspondantes
H03K 19/177 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle
16.
SEALED PLASMA MELTING FURNACE FOR TREATING MEDIUM- AND LOW-LEVEL RADIOACTIVE WASTE
The present invention relates to a sealed plasma melting furnace (10) for treating medium- and low-level radioactive wastes, which is capable of batch-processing the medium- and low-level radioactive wastes regardless of the types thereof according to the characteristics of each waste in a sealed state to thus minimize secondary pollutants. The sealed plasma melting furnace comprises: a waste supply chamber (100), provided with a hopper (110) on one side thereof in communication therewith, in which waste introduced from the hopper (110) is stacked in a vertical direction; a pyrolysis chamber channel (210) provided on one side of the waste supply chamber (100) and communicated with the waste supply chamber (100); a pyrolysis chamber (200) provided on one side of the pyrolysis chamber channel (210) and having a burner mounted thereon; a melting chamber channel (310), provided on one side of the pyrolysis chamber (200), which guides the waste conveyed from the pyrolysis chamber (200) communicating therewith and has a nozzle (311) for injecting liquid waste on one side thereof; a melting chamber (300), provided on one side of the melting chamber channel (310), which has a plasma torch (320) mounted on one side thereof and has a furnace inside for accommodating a molten material formed at a bottom surface thereof; a molten processed product discharging channel (350), provided at a lower portion of the melting chamber (300), for discharging the molten processed product generated in the melting chamber; a secondary combustion chamber channel (410), provided on one side of the pyrolysis chamber (200), for inducing and exhausting a flow of an exhaust gas generated in the melting chamber (300); and a secondary combustion chamber (400), provided on one side of the secondary combustion chamber channel (410), for inducing a complete combustion of the exhaust gas introduced from the secondary combustion chamber channel (410) communicating therewith.
F23G 5/027 - Procédés ou appareils, p. ex. incinérateurs, spécialement adaptés à la combustion de déchets ou de combustibles pauvres comportant un traitement préalable par pyrolyse ou par gazéification
F23G 5/44 - Procédés ou appareils, p. ex. incinérateurs, spécialement adaptés à la combustion de déchets ou de combustibles pauvres Parties constitutivesAccessoires
F27D 99/00 - Matière non prévue dans les autres groupes de la présente sous-classe
F27B 17/00 - Fours d'un genre non couvert par l'un des groupes
A burn-in test system may include a burn-in test chamber, a heating chamber and a cooling chamber. The burn-in test chamber may receive an object thereon. The burn-in test chamber may perform a burn-in test at a burn-in test temperature. The heating chamber may be positioned at a first sidewall of the burn-in test chamber, and may preheat the object. The cooling chamber may be positioned at a second sidewall of the burn-in test chamber, and may cool the object.
G01R 31/10 - Localisation de défauts dans les câbles, les lignes de transmission ou les réseaux en augmentant la destruction à l'endroit du dérangement, p. ex. combustion au moyen d'un générateur d'impulsions appliquant un programme spécial
G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
18.
Test board unit and apparatus for testing a semiconductor chip including the same
A test board unit may include a test board, a thermal tank and a heat-dissipating plate. The test board may be configured to provide a semiconductor chip with a test current. The thermal tank may be configured to dissipate heat generated in the semiconductor chip. The heat-dissipating plate may be coupled between the test board and the thermal tank and may be configured to transfer the heat from the semiconductor chip to the thermal tank.
Disclosed is a detection system for detecting fail block using logic block address and data buffer address in a storage tester, which is capable of comparing data read from SSD test without expected data buffer. The system comprises a device driver for controlling HBA; a request processor for reading the request to Root Complex and transmitting the result to a data engine; and the data engine for generating data to be transmitted to SSD and comparing the read data.
G11C 29/56 - Équipements externes pour test de mémoires statiques, p. ex. équipement de test automatique [ATE]Interfaces correspondantes
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. circuits de commande E/S de données, mémoires tampon de données E/S
G11C 13/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
G06F 11/273 - Matériel de test, c.-à-d. circuits de traitement de signaux de sortie
G11C 29/12 - Dispositions intégrées pour les tests, p. ex. auto-test intégré [BIST]
G06F 12/06 - Adressage d'un bloc physique de transfert, p. ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
G11C 29/04 - Détection ou localisation d'éléments d'emmagasinage défectueux
A non-mounted storage test device based on FPGA includes a processor unit for performing enumeration and configuration for device, creating a scenario for test and performing test; a device driver unit for managing storage device; a data engine unit for generating pattern data for test and performing test; a system memory interface unit for receiving data for test and storing test result; a monitoring unit for monitoring packet; a DMA driver/address translation unit for performing DMA operation and transmitting Memory Read Request to Root Complex; a message input/output unit for transmitting to the data engine unit and the device driver unit; a switch unit for constituting DUT unit; a storage-in DUT unit as device under test which is storage for direct interface to PCIe including HBA; and a memory unit for storing data for test and record generated between tasks.
Disclosed is a storage tester capable of individual control for a plurality of storages, which comprises a host terminal for receiving user's control signal for storage test; a communication interface unit transmitting data among the host terminal, an embedded processor and a data engine unit; a data engine unit for generating pattern data and command data and reading the data from the storage; a sequence control module for controlling respectively a plurality of SATA/SAS/PCIe interface units; and SATA/SAS/PCIe interface unit for connecting to the storage through one among SATA, SAS, PCIe interface according to the signal for interface selection generated from the embedded processor and controlling a plurality of storages according to control of the sequence control module by the embedded processor in order to test respectively connected storage.
An apparatus and method for correcting an output signal of an FPGA-based memory test device includes a clock generator for outputting clock signals having different phases; and a pattern generator for outputting an address signal, a data signal and a clock signal in response to the clock signals input from the clock generator, and correcting a timing of each of the output signals using flip flops for timing measurement. Wherein the address signal, the data signal and the clock signal, through a pattern generator, are implemented with a programmable logic such as FPGA, thereby shortening the correcting time without the use of an external delay device, and increasing accuracy of output timing of the signal for memory testing, ultimately enhancing performance (accuracy) of a memory tester.
H03K 19/173 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants
G06F 7/38 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale
H03K 19/003 - Modifications pour accroître la fiabilité
H03K 19/177 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle
23.
System for simultaneously determining memory test result
A system for test plural memories simultaneously includes a pattern generation part which generates a pattern signal for testing and transmits the signal to the memories, a delay part which receives data through a first data line from a first memory device that is disposed in a closest position from the delay part and a second data line from a second memory device that is disposed in a farthest position from the delay part, and a determination part which determines the result of testing by comparing the data from the first memory device and the second memory device. The delay part output the first data and the second data to the determination part simultaneously.
An apparatus and method for acquiring data of fast fail memory includes a pattern generator for generating a pattern to be recorded to a device under test (DUT) and receiving DUT data from the DUT; a data transmitter for sending the DUT data and the pattern generated so as to correspond thereto to a failure analyzer from the pattern generator; and a failure analyzer for analyzing the DUT data and the pattern generated so as to correspond to the DUT data, which are received from the data transmitter, thus producing failure analysis information. The data transmitter (FIFO) able to advance the failure analysis time allows failure analysis to be performed before completion of testing, thereby shortening the total failure analysis time and overcoming hardware limitations for failure analysis.
G11C 29/38 - Dispositifs de vérification de réponse
G11C 29/12 - Dispositions intégrées pour les tests, p. ex. auto-test intégré [BIST]
G11C 29/56 - Équipements externes pour test de mémoires statiques, p. ex. équipement de test automatique [ATE]Interfaces correspondantes
G06F 11/22 - Détection ou localisation du matériel d'ordinateur défectueux en effectuant des tests pendant les opérations d'attente ou pendant les temps morts, p. ex. essais de mise en route
G11C 29/54 - Dispositions pour concevoir les circuits de test, p. ex. outils de conception pour le test [DFT]
Disclosed is a device under test (DUT) tester using a redriver. The DUT tester more effectively tests the DUT, which is a predetermined semiconductor device, by applying an electrical signal to the DUT and measuring the electrical signal. The DUT tester includes a DUT test unit, a printed circuit board (PCB) provided therein with connectors for the connection with the DUT test unit, one DUT or more horizontally arranged on the PCB, and redrivers horizontally provided under the PCB and one-to-one matched with one DUT or more to compensate for the distortion of the signal integrity of test signals caused according to the variation of the transmission distance.
G01R 31/00 - Dispositions pour tester les propriétés électriquesDispositions pour la localisation des pannes électriquesDispositions pour tests électriques caractérisées par ce qui est testé, non prévues ailleurs
G01R 31/319 - Matériel de test, c.-à-d. circuits de traitement de signaux de sortie
Disclosed is a solid state drive tester which reduces the size of the tester and easily changes a function without changing hardware (H/W) by implementing a plurality of devices for testing an SSD as one chip using a Field Programmable Gate Array (FPGA). The solid state drive tester includes: a host terminal receiving a test condition for testing a storage from a user; and a test control unit generating a test pattern corresponding to the test condition, adaptively selecting an interface according to an interface type of the storage to be tested to test the storage using the test pattern, and storing fail data generated during the test in an internal memory. The test control unit is implemented by an FPGA to reduce the size of the tester and easily change a function without hardware.
G11C 29/00 - Vérification du fonctionnement correct des mémoiresTest de mémoires lors d'opération en mode de veille ou hors-ligne
G11C 29/10 - Algorithmes de test, p. ex. algorithmes par balayage de mémoire [MScan]Configurations de test, p. ex. configurations en damier
G06F 11/22 - Détection ou localisation du matériel d'ordinateur défectueux en effectuant des tests pendant les opérations d'attente ou pendant les temps morts, p. ex. essais de mise en route
G11C 29/56 - Équipements externes pour test de mémoires statiques, p. ex. équipement de test automatique [ATE]Interfaces correspondantes
G11C 29/04 - Détection ou localisation d'éléments d'emmagasinage défectueux
Disclosed is a solid state drive tester which divides the functions of generating and comparing test pattern data and Frame Information Structure (FIS) data with each other into each other to implement the functions as separate logics, so that entire test time is decreased by reducing load of a processor. The solid state drive tester includes a host terminal for receiving a test condition for testing a storage from a user, and a test control unit creating a test pattern corresponding to the test condition, and adaptively selecting an interface according to an interface type of the storage to be tested to test the storage using the test pattern, wherein the test control unit is divided into a control module for controlling the test of the storage and a test execution module for practically executing the test in hardware to test a plurality of storages in real time.
G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
G11C 29/10 - Algorithmes de test, p. ex. algorithmes par balayage de mémoire [MScan]Configurations de test, p. ex. configurations en damier
G06F 11/22 - Détection ou localisation du matériel d'ordinateur défectueux en effectuant des tests pendant les opérations d'attente ou pendant les temps morts, p. ex. essais de mise en route
G06F 13/38 - Transfert d'informations, p. ex. sur un bus
Disclosed is a storage interface apparatus for a solid state drive (SSD) tester which allows a plurality of interfaces to share a single protocol in parts where the protocol is commonly used in a multiple interface for interfacing a storage. The storage interface apparatus for the solid state driver tester includes: a host terminal for receiving a test condition for testing a storage from a user; and a test control unit for generating a test pattern corresponding to the test condition to test the storage. The test control unit includes a storage interface unit for interfacing the storage, and the storage interface unit includes a plurality of interfaces that share a protocol in parts where the protocol is commonly used.
G11C 11/4093 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. mémoires tampon de données
G11C 29/10 - Algorithmes de test, p. ex. algorithmes par balayage de mémoire [MScan]Configurations de test, p. ex. configurations en damier
G06F 11/22 - Détection ou localisation du matériel d'ordinateur défectueux en effectuant des tests pendant les opérations d'attente ou pendant les temps morts, p. ex. essais de mise en route
29.
Failure detection apparatus for solid state drive tester
A failure detection apparatus for a solid state driver tester is provided. The failure detection apparatus includes a host terminal for receiving a test condition for testing a storage from a user and a test control unit for creating a test pattern according to the test condition or creating a test pattern at random, and adaptively selects an interface according to a type of the storage to be tested to test the storage with the test pattern. The test control unit includes a plurality of buffer memories for storing readout data of the storage, stores the readout data in the buffer memories in an interleaving manner, and endows comparison of the created test pattern and the readout data stored in the buffer memories with continuity to test the storage in real time.
G11C 29/00 - Vérification du fonctionnement correct des mémoiresTest de mémoires lors d'opération en mode de veille ou hors-ligne
G11C 29/10 - Algorithmes de test, p. ex. algorithmes par balayage de mémoire [MScan]Configurations de test, p. ex. configurations en damier
G06F 11/22 - Détection ou localisation du matériel d'ordinateur défectueux en effectuant des tests pendant les opérations d'attente ou pendant les temps morts, p. ex. essais de mise en route
30.
Error generating apparatus for solid state drive tester
Disclosed is an error generating apparatus of a solid state drive tester. The error processing operation of the storage is tested by inserting errors into a specific instruction to be transmitted to the storage, and detecting the results of the error processing operation of the storage when testing the storage. The error generating apparatus includes a host terminal for receiving a test condition for a test of a storage from a user, and a test control unit for generating a test pattern according to the test condition or generating a test pattern randomly, generating error data used to test an error characteristic of the storage, and testing the storage based on the test pattern and a normal instruction or an error instruction which is formed by inserting the error data into the normal instruction.
G11C 29/10 - Algorithmes de test, p. ex. algorithmes par balayage de mémoire [MScan]Configurations de test, p. ex. configurations en damier
G06F 11/22 - Détection ou localisation du matériel d'ordinateur défectueux en effectuant des tests pendant les opérations d'attente ou pendant les temps morts, p. ex. essais de mise en route
G11C 29/54 - Dispositions pour concevoir les circuits de test, p. ex. outils de conception pour le test [DFT]
G11C 29/56 - Équipements externes pour test de mémoires statiques, p. ex. équipement de test automatique [ATE]Interfaces correspondantes
G11C 29/04 - Détection ou localisation d'éléments d'emmagasinage défectueux
Disclosed is a lighting device for a street lamp, of which a structure is improved such that the diffusion degree of light may be effectively controlled by improving the directivity of a luminous element. To this end, the lighting device for a street lamp includes: a base member which is formed at an upper side of a street lamp body which is arranged above a ground surface; at least one luminous element or a plurality of luminous element units, which are arranged on the bottom surface of the base member so that the luminous element units are arranged adjacently; and a plurality of reflection units, which are arranged mutually isolated from each other by a predetermined distance on the bottom surface of the base member to diffuse light radiated from the luminous element in multiple directions. The reflection unit includes: a first reflection section which is arranged to be isolated from any one luminous element unit among the luminous element units by a predetermined distance, and formed to surround only one part of the luminous element unit such that at least one part of light radiated from the luminous element unit is reflected by the reflection units which are adjacently positioned in a first direction; and a second reflection section which is formed to be slanted at a certain angle from the base member to diffuse light in multiple directions by being reflected by the reflection units which are adjacently positioned in a second direction, opposite to the first direction.
A method for calibrating a semiconductor device tester is disclosed. In accordance with method of the present invention, a timing is calibrated using a programmable delay device and calibration boards so as to remove a timing difference between channels and compensate a linearity of the programmable delay device for an adjustment of a timing by building and using a database of the round trip delay actually generated during the test.
G01R 31/02 - Essai des appareils, des lignes ou des composants électriques pour y déceler la présence de courts-circuits, de discontinuités, de fuites ou de connexions incorrectes de lignes
G01R 31/00 - Dispositions pour tester les propriétés électriquesDispositions pour la localisation des pannes électriquesDispositions pour tests électriques caractérisées par ce qui est testé, non prévues ailleurs
G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
A sequential semiconductor device tester, and in particular to a sequential semiconductor device tester is disclosed. In accordance with the sequential semiconductor device tester, a function of generating a test pattern data for a test of a semiconductor device and a function of carrying out the test are separated to sequentially test the semiconductor device, to maintain a signal integrity and to improve an efficiency of the test by carrying out a test under an application environment or an ATE test according to the test selection command.
A sequential semiconductor device tester, and in particular to a sequential semiconductor device tester is disclosed. In accordance with the sequential semiconductor device tester, a function of generating a test pattern data for a test of a semiconductor device and a function of carrying out the test are separated to sequentially test the semiconductor device, to maintain a signal integrity and to improve an efficiency of the test by carrying out a test under an application environment or an ATE test according to the test pattern data.
A tester for testing a semiconductor device is disclosed. The tester for testing the semiconductor device employs a data selector for converting a logical test pattern data transmitted from a pattern generator into a physical test pattern data and an expected data based on the logical test pattern data, thereby generating various timings based on a time delay instead of using a plurality of clocks to improve a test efficiency and reduce a manufacturing cost.
A tester for testing a semiconductor device is disclosed. In accordance with the tester of the present invention, the tester is configured to have different drive signal path and input/output signal path wherein the drive signal path has a fly-by structure, i.e. a daisy chain structure and the input/output signal path has a star-stub structure such that more DUTs may be tested simultaneously and an integrity of the signals is secured.
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