According to some embodiments, a sensor includes an analog-to-digital converter (ADC) configured to sample a load current signal to generate load current data and a processor configured to perform a Fast Fourier Transform of the load current data to generate a frequency distribution comprising bins, sort the bins based on magnitude to generated sorted bins, determine a signal metric for a first subset of the sorted bins, determine a noise metric for a second subset of the sorted bins, and identify a fault condition based on the signal metric and the noise metric.
G01R 19/252 - Dispositions pour procéder aux mesures de courant ou de tension ou pour en indiquer l'existence ou le signe utilisant une méthode de mesure numérique utilisant des convertisseurs analogiques/numériques du type à conversion de la tension ou du courant en fréquence et mesure de cette fréquence
G01R 19/25 - Dispositions pour procéder aux mesures de courant ou de tension ou pour en indiquer l'existence ou le signe utilisant une méthode de mesure numérique
G01R 31/52 - Test pour déceler la présence de courts-circuits, de fuites de courant ou de défauts à la terre
A system on a chip includes a plurality of tiles, a non-volatile memory, and a repair system. The repair system includes a cache and control logic. The control logic is configured to receive a repair data write request and a respective repair address and corresponding repair data for a respective tile of the plurality of tiles from a respective repair controller and store the corresponding repair data in the cache in a redundancy encoded and compressed format; write the contents of the cache to the non-volatile memory; and receive a repair data read request and the respective repair address for the respective tile from the respective repair controller, read the corresponding redundancy encoded and compressed repair data from the cache, decompress the repair data, decode the corresponding repair data with error detection and correction logic, and output the corresponding repair data to the respective repair controller.
INDACINREFREFDACININ, and the SAR sets or clears a current bit represented by the capacitance driven. The reference buffer includes adaptive power tuning to dynamically tune a drive-strength of the reference buffer based on the current bit.
H03M 1/08 - Compensation ou prévention continue de l'influence indésirable de paramètres physiques du bruit
H03M 1/38 - Valeur analogique comparée à des valeurs de référence uniquement séquentiellement, p. ex. du type à approximations successives
H03M 1/46 - Valeur analogique comparée à des valeurs de référence uniquement séquentiellement, p. ex. du type à approximations successives avec convertisseur numérique/analogique pour fournir des valeurs de référence au convertisseur
H03M 1/68 - Convertisseurs numériques/analogiques à conversions de sensibilités différentes, c.-à-d. qu'une conversion se rapportant aux bits les plus significatifs et une autre aux bits les moins significatifs
H03M 1/06 - Compensation ou prévention continue de l'influence indésirable de paramètres physiques
H03M 1/14 - Conversion par étapes, avec pour chaque étape la mise en jeu de moyens de conversion identiques ou différents et délivrant plus d'un bit
H03M 1/28 - Convertisseurs analogiques/numériques du type à lecture de dessin utilisant un lecteur et un disque ou un ruban en mouvement relatif à codage non pondéré
H03M 1/34 - Valeur analogique comparée à des valeurs de référence
A semiconductor device and methods of fabrication the same are disclosed. In one embodiment, the semiconductor device may include a non-volatile memory (NVM) cell including a memory gate stack and a select gate stack separated by an inter-gate dielectric disposed in a memory region of a substrate, a low voltage field-effect transistor (LVFET) including a first high-K metal-gate (HKMG) stack disposed in a peripheral region of the substrate, and a high voltage field-effect transistor (HVFET) including a second HKMG stack disposed in the peripheral region, in which top surfaces of the memory gate stack and the select gate stack of the NVM cell, the LVFET, and the HVFET have an approximately same elevation from the substrate or are substantially co-planar. Other embodiments are also disclosed within.
H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
H01L 21/265 - Bombardement par des radiations ondulatoires ou corpusculaires par des radiations d'énergie élevée produisant une implantation d'ions
H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
H01L 21/285 - Dépôt de matériaux conducteurs ou isolants pour les électrodes à partir d'un gaz ou d'une vapeur, p. ex. condensation
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
H01L 29/51 - Matériaux isolants associés à ces électrodes
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/792 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à isolant de grille à emmagasinage de charges, p.ex. transistor de mémoire MNOS
H10B 41/30 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire
H10B 41/49 - Fabrication simultanée de périphérie et de cellules de mémoire comprenant différents types de transistors périphériques
H10B 43/30 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
5.
SYSTEMS, METHODS, AND DEVICES FOR LOW-POWER AUDIO SIGNAL DETECTION
Systems, methods, and devices detect wake signals included in audio signals. Methods include receiving a dataset including raw audio data, the raw audio data comprising a plurality of audio samples and associated metadata, and generating, using one or more processing elements, an augmented dataset based on the raw audio data, the augmented dataset comprising a plurality of annotations identifying types of raw audio data. Methods further include generating, using the one or more processing elements, a feature dataset by extracting features from the augmented dataset based, at least in part, on the plurality of annotations, and generating, using the one or more processing elements, a wake signal detection model based, at least in part, on the feature dataset, the wake signal detection model being a machine learning model trained based on the feature dataset.
G10L 15/22 - Procédures utilisées pendant le processus de reconnaissance de la parole, p. ex. dialogue homme-machine
G10L 19/00 - Techniques d'analyse ou de synthèse de la parole ou des signaux audio pour la réduction de la redondance, p. ex. dans les vocodeursCodage ou décodage de la parole ou des signaux audio utilisant les modèles source-filtre ou l’analyse psychoacoustique
G10L 15/02 - Extraction de caractéristiques pour la reconnaissance de la paroleSélection d'unités de reconnaissance
G10L 15/06 - Création de gabarits de référenceEntraînement des systèmes de reconnaissance de la parole, p. ex. adaptation aux caractéristiques de la voix du locuteur
G10L 25/18 - Techniques d'analyse de la parole ou de la voix qui ne se limitent pas à un seul des groupes caractérisées par le type de paramètres extraits les paramètres extraits étant l’information spectrale de chaque sous-bande
Systems, methods, and devices enhance integration of components of a wireless environment. Methods include determining, using a processing device, a plurality of contextual parameters identifying a plurality of settings associated with an application executed on a central wireless device and a plurality of wireless devices included in an operational environment of the central wireless device. Methods also include determining, using the processing device, a plurality of wireless device parameters and wireless connection parameters for the plurality of wireless devices based on the contextual parameters. Methods further include generating, using the processing device, instructions for each of the plurality of wireless devices based, at least in part, on the plurality of contextual parameters and a native format and wireless protocol of each of the plurality of wireless devices.
H04L 69/18 - Gestionnaires multi-protocoles, p. ex. dispositifs uniques capables de gérer plusieurs protocoles
H04L 69/08 - Protocoles d’interopérabilitéConversion de protocole
H04W 36/00 - Dispositions pour le transfert ou la resélection
H04B 1/38 - Émetteurs-récepteurs, c.-à-d. dispositifs dans lesquels l'émetteur et le récepteur forment un ensemble structural et dans lesquels au moins une partie est utilisée pour des fonctions d'émission et de réception
Techniques are described to improve the security of frame synchronization detection between wireless devices in high accuracy positioning (HAP) applications using personal area networks (PANs). A receiver may detect whether a frame synchronization pattern has been manipulated by comparing the sampled data of the received frame synchronization pattern with a reference waveform predicted as the frame synchronization pattern. The receiver may reuse the data in the correlation buffer at the moment a correlator finds a peak and declares that the synchronization pattern is found. The correlator may also provide fractional timing information associated with the correlation peak for the receiver to create a delayed reference phase differential pattern. The receiver may subtract the data in the correlation buffer by the delayed reference differential data and look for absolute deviations in the output of such subtraction that exceed a predetermined threshold. Specific patterns or signatures of error may also be analyzed.
A multi-port USB Power Delivery Type-C (USB-C/PD) power converter for switching clock phase shifts is described herein. The multi-port USB-C/PD power converter includes a first PD port, a second PD port, and a power controller coupled to the first and second PD ports. The power controller includes a first phased clock generator to generate a first phase-shifted clock signal by shifting a clock signal by a first phase with respect to a reference clock signal, and a second phased clock generator to generate a second phase-shifted clock signal to generate a second phased-shifted clock signal by shifting the clock signal by a second phase with respect to the reference clock signal. The first PD port and the second PD port output power in response to a first control signal based on the first phase-shifted clock signal and a second control signal based on the second phase-shifted clock signal, respectively.
A system includes a first USB Type-C Power Delivery (USB-C/PD) port and a control circuit operatively coupled to the first USB-C/PD port. The control circuit is configured to determine whether a short circuit condition has occurred. The control circuit is also configured to turn off a ground isolation switch when short circuit condition occurs. The control circuit is further configured to determine a whether a voltage on a configuration channel line (CC line) is greater than a first threshold voltage. The control circuit is further configured to determine whether the voltage on the CC line is less than a second threshold voltage. The control circuit is further configured to turn on the ground isolation switch when the voltage on the CC line is less than the second threshold voltage. The control circuit may perform one or more error recovery operations after turning on the ground isolation switch.
An IC controller for USB Type-C device includes an error amplifier (EA), which includes an EA output coupled to a PWM comparator of a buck-boost converter; a first transconductance amplifier to adjust a current at the EA output, the first transconductance amplifier operating in a constant voltage mode; and a second transconductance amplifier to adjust the current at the EA output, the second transconductance amplifier operating in a constant current mode. A first set of programmable registers is to store a first set of increasingly higher transconductance values. A second set of programmable registers is to store a second set of increasingly higher transconductance values. Control logic is to: cause the first transconductance amplifier to operate while sequentially using transconductance values stored in the first set of programmable registers; and cause the second transconductance amplifier to operate while sequentially using transconductance values stored in the second set of programmable registers.
G06F 13/00 - Interconnexion ou transfert d'information ou d'autres signaux entre mémoires, dispositifs d'entrée/sortie ou unités de traitement
G06F 3/00 - Dispositions d'entrée pour le transfert de données destinées à être traitées sous une forme maniable par le calculateurDispositions de sortie pour le transfert de données de l'unité de traitement à l'unité de sortie, p. ex. dispositions d'interface
H02M 3/335 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu avec transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrodes de commande pour produire le courant alternatif intermédiaire utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
G06F 1/32 - Moyens destinés à économiser de l'énergie
H02M 3/156 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation
11.
DEVICES, SYSTEMS AND METHODS FOR ACCESSING RANDOM ACCESS RESOURCE UNITS OF A WIRELESS CHANNEL
A method can include wireless device operations, including receiving a trigger communication that identifies available random access resource units (RA RUs), the RA RUs being portions of transmission channel for a wireless system. In response to a back-off value and a number of available RA RUs, selecting or not selecting one RA RU as a transmission RA RU. In response to not selecting a transmission RA RU, monitoring for wireless responses following the trigger communication to determine unselected RA RUs, designating one unselected RA RUs as an alternate RA RU; and transmitting uplink data on the alternate RA RU. The unselected RA RUs comprise any RA RUs that remain after other wireless devices have selected RA RUs in response to the trigger communication. Corresponding devices and systems are also disclosed.
The embodiments described herein are directed to systems and devices for electronically measuring the absolute position of one or more moving targets e.g., along the length of a metal beam using mutual capacitive sensing. The beam may be made of metal and may have a limited inset area to fit a position detection sensor device along its length. The moving targets may have no active elements and the position of multiple targets may be detected simultaneously along the beam. The systems and devices described herein do not utilize electronic position feedback and instead rely on an integrated ruler and minimize the total number of sensors required to support recalibration, thereby minimizing scan time (more sensors results in a linear increase in scan time).
G06F 3/044 - Numériseurs, p. ex. pour des écrans ou des pavés tactiles, caractérisés par les moyens de transduction par des moyens capacitifs
G01R 27/26 - Mesure de l'inductance ou de la capacitanceMesure du facteur de qualité, p. ex. en utilisant la méthode par résonanceMesure de facteur de pertesMesure des constantes diélectriques
G01D 5/24 - Moyens mécaniques pour le transfert de la grandeur de sortie d'un organe sensibleMoyens pour convertir la grandeur de sortie d'un organe sensible en une autre variable, lorsque la forme ou la nature de l'organe sensible n'imposent pas un moyen de conversion déterminéTransducteurs non spécialement adaptés à une variable particulière utilisant des moyens électriques ou magnétiques influençant la valeur d'un courant ou d'une tension en faisant varier la capacité
An apparatus includes a global baseliner circuit coupled with sensing channels of a sensing device. The global baseliner circuit has a signal generator to generate a rectified sinusoidal signal and a square wave having a frequency matching that of an excitation sinusoidal signal, and is to use the square wave to modulate the excitation sinusoidal signal provided at an output of the global baseliner circuit. A channel baseliner circuit is coupled between the global baseliner circuit and a sensing channel and that includes a switched capacitor coupled between the output of the global baseliner circuit and the sensing channel; a sigma-delta modulator coupled with the signal generator and to generate, from the rectified sinusoidal signal, a density-modulated bit stream; and a pair of AND gates to use the density-modulated bit stream and non-overlapping clock signals to generate outputs including density-modulated clock signals sent to switches of the switched capacitor.
G06F 3/01 - Dispositions d'entrée ou dispositions d'entrée et de sortie combinées pour l'interaction entre l'utilisateur et le calculateur
G06F 3/03 - Dispositions pour convertir sous forme codée la position ou le déplacement d'un élément
G06F 3/041 - Numériseurs, p. ex. pour des écrans ou des pavés tactiles, caractérisés par les moyens de transduction
G06F 3/044 - Numériseurs, p. ex. pour des écrans ou des pavés tactiles, caractérisés par les moyens de transduction par des moyens capacitifs
G06F 3/0488 - Techniques d’interaction fondées sur les interfaces utilisateur graphiques [GUI] utilisant des caractéristiques spécifiques fournies par le périphérique d’entrée, p. ex. des fonctions commandées par la rotation d’une souris à deux capteurs, ou par la nature du périphérique d’entrée, p. ex. des gestes en fonction de la pression exercée enregistrée par une tablette numérique utilisant un écran tactile ou une tablette numérique, p. ex. entrée de commandes par des tracés gestuels
14.
Method of forming high-voltage transistor with thin gate poly
A semiconductor device and method of fabricating the same are disclosed. The method includes depositing a polysilicon gate layer over a gate dielectric formed over a surface of a substrate in a peripheral region, forming a dielectric layer over the polysilicon gate layer and depositing a height-enhancing (HE) film over the dielectric layer. The HE film, the dielectric layer, the polysilicon gate layer and the gate dielectric are then patterned for a high-voltage Field Effect Transistor (HVFET) gate to be formed in the peripheral region. A high energy implant is performed to form at least one lightly doped region in a source or drain region in the substrate adjacent to the HVFET gate. The HE film is then removed, and a low voltage (LV) logic FET formed on the substrate in the peripheral region. In one embodiment, the LV logic FET is a high-k metal-gate logic FET.
H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
H01L 21/265 - Bombardement par des radiations ondulatoires ou corpusculaires par des radiations d'énergie élevée produisant une implantation d'ions
H01L 21/285 - Dépôt de matériaux conducteurs ou isolants pour les électrodes à partir d'un gaz ou d'une vapeur, p. ex. condensation
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/792 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à isolant de grille à emmagasinage de charges, p.ex. transistor de mémoire MNOS
H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
H10B 41/30 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire
H10B 41/49 - Fabrication simultanée de périphérie et de cellules de mémoire comprenant différents types de transistors périphériques
H10B 43/30 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
Systems, methods, and devices seamlessly playback data files using one or more wireless connections. Methods include establishing a first wireless connection between a source device and a sink device, the first wireless connection using a first transmission protocol and transmitting audio data via the first wireless connection. Methods further include determining a switch should be initiated based on one or more signal quality metrics, the one or more signal quality metrics representing, at least in part, an estimate of a quality of the first wireless connection. Methods also include switching to a second wireless connection between the source device and the sink device, the second wireless connection using a second transmission protocol, and the second wireless connection using data packets encapsulated for transmission in accordance with the second transmission protocol.
Described herein are devices, methods, and systems that detect the presence of faults such as shorts and/or opens within a touch sensitive display panel. In one embodiment, a touch screen controller is disclosed, the touch screen controller comprising one or more receive channels, where each receive channel is configured to scan a corresponding group of sensors of a plurality of sensors. The touch screen controller may also comprise a plurality of multiplexers, each multiplexer configured to selectively couple a respective sensor of the plurality of sensors to a corresponding receive channel or a reference voltage. The touch screen controller may further comprise a processing device configured to detect one or more shorts based on DC current sensing. The touch screen controller may also detect one or more opens based on AC current sensing of each of the one or more receive channels.
A non-volatile memory (NVM) integrated circuit device includes an NVM array of memory cells partitioned into a first physical region to store a first firmware stack and a second physical region to store a second firmware stack. The NVM integrated circuit device also includes a processing device that enables a host microcontroller to execute in place the first firmware stack stored within a first set of logical addresses that is mapped to the first physical region. The processing device tracks accesses, by the host microcontroller, to the first set of logical addresses. The processing device, in response to detecting one of a certain number or a certain type of the accesses by the host microcontroller, initiates a recovery operation including to remap the first set of logical addresses to the second physical region.
A non-volatile memory (NVM) integrated circuit device includes an NVM array of memory cells partitioned into a first physical region to store a first firmware stack and a second physical region to store a second firmware stack. The NVM integrated circuit device also includes a processing device that enables a host microcontroller to execute in place the first firmware stack stored within a first set of logical addresses that is mapped to the first physical region. The processing device tracks accesses, by the host microcontroller, to the first set of logical addresses. The processing device, in response to detecting one of a certain number or a certain type of the accesses by the host microcontroller, initiates a recovery operation including to remap the first set of logical addresses to the second physical region.
G06F 12/00 - Accès à, adressage ou affectation dans des systèmes ou des architectures de mémoires
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
G06F 21/78 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du stockage de données
Disclosed are methods and systems for operating a dual-band capable STA of a WiFi network in a real-time simultaneous dual band (RSDB) configuration in which a 2.4 GHz base-channel link to the WiFi network through the AP may operate in parallel with 5 GHz off-channel links to one or more peer STAs of the WiFi network through tunneled direct link setup (TDLS). The STA may connect to the AP and may establish a TDLS link with a peer STA over the base- channel. If the peer STA is capable of RSDB configuration using the off-channel TDLS link, the STA and the peer STA may switch the TDLS link from the base-channel to the off-channel. The base-channel AP link and the off-channel TDLS link are maintained in parallel, eliminating the need to toggle between the channels of the two links, reducing packet latency, eliminating discontinuity of data transfer, and increasing data throughput.
A semiconductor device that has a semiconductor-oxide-nitride-oxide-semiconductor (SONOS) based non-volatile memory (NVM) array including NVM cells arranged in rows and columns, in which NVM transistors of the NVM cells are configured to store N x analog values corresponding to the N x levels of their drain current (ID) or threshold voltage (VT) levels, digital-to-analog (DAC) function that receives and converts digital signals from external devices, column multiplexor (mux) function that is configured to select and combine the analog value read from the NVM cells, and analog-to-digital (ADC) function that is configured to convert analog results of the column mux function to digital values and output the digital values.
G11C 16/14 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement
G11C 16/16 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement pour effacer des blocs, p. ex. des réseaux, des mots, des groupes
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
21.
SILICON-OXIDE-NITRIDE-OXIDE-SILICON MULTI-LEVEL NON-VOLATILE MEMORY DEVICE AND METHODS OF FABRICATION THEREOF
A semiconductor device that has a silicon-oxide-nitride-oxide-silicon (SONOS) based non-volatile memory (NVM) array including charge-trapping memory cells arranged in rows and columns and configured to store one of N x analog values. Each charge-trapping memory cells may include a memory transistor including an angled lightly doped drain (LDD) implant extends at least partly under an oxide-nitride-oxide (ONO) layer of the memory transistor. The ONO layer disposed within the memory transistor and over an adjacent isolation structure has the same elevation substantially.
H01L 27/11526 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec grilles flottantes caractérisées par la région de circuit périphérique
H01L 27/115 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs
H01L 27/11563 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM
H01L 27/1157 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par la région noyau de mémoire avec transistors de sélection de cellules, p.ex. NON-ET
H01L 27/11597 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs les électrodes de grille comprenant une couche utilisée pour ses propriétés de mémoire ferro-électrique, p.ex. semi-conducteur métal-ferro-électrique [MFS] ou semi-conducteur d’isolation métal-ferro-électrique-métal [MFMIS] caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur
22.
Silicon-oxide-nitride-oxide-silicon multi-level non-volatile memory device and methods of fabrication thereof
A semiconductor device that has a silicon-oxide-nitride-oxide-silicon (SONOS) based non-volatile memory (NVM) array including charge-trapping memory cells arranged in rows and columns and configured to store one of N×analog values. Each charge-trapping memory cells may include a memory transistor including an angled lightly doped drain (LDD) implant extends at least partly under an oxide-nitride-oxide (ONO) layer of the memory transistor. The ONO layer disposed within the memory transistor and over an adjacent isolation structure has the same elevation substantially.
G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p. ex. de tension, de courant, de phase, de fréquence
G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
G11C 16/08 - Circuits d'adressageDécodeursCircuits de commande de lignes de mots
G11C 16/16 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement pour effacer des blocs, p. ex. des réseaux, des mots, des groupes
G11C 16/24 - Circuits de commande de lignes de bits
G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
H01L 27/11524 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec grilles flottantes caractérisées par la région noyau de mémoire avec transistors de sélection de cellules, p.ex. NON-ET
H01L 27/11529 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec grilles flottantes caractérisées par la région de circuit périphérique de régions de mémoire comprenant des transistors de sélection de cellules, p.ex. NON-ET
H01L 27/1157 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par la région noyau de mémoire avec transistors de sélection de cellules, p.ex. NON-ET
H01L 27/11573 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par la région de circuit périphérique
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/792 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à isolant de grille à emmagasinage de charges, p.ex. transistor de mémoire MNOS
23.
Silicon-oxide-nitride-oxide-silicon based multi level non-volatile memory device and methods of operation thereof
T) levels, digital-to-analog (DAC) function that receives and converts digital signals from external devices, column multiplexor (mux) function that is configured to select and combine the analog value read from the NVM cells, and analog-to-digital (ADC) function that is configured to convert analog results of the column mux function to digital values and output the digital values.
G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p. ex. de tension, de courant, de phase, de fréquence
G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
G11C 16/08 - Circuits d'adressageDécodeursCircuits de commande de lignes de mots
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 16/24 - Circuits de commande de lignes de bits
G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
G11C 16/16 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement pour effacer des blocs, p. ex. des réseaux, des mots, des groupes
Disclosed are systems and methods for diagnosing the health of a plurality of memory cells in a memory array. Diagnostics are initiated from a remote server via an encrypted channel on the memory device embedded in an end-use system. The memory device includes a plurality of memory cells in a memory array. At the remote server, encrypted diagnostics data is received in response to execution of a diagnostics program by the memory device on the plurality of memory cells. The diagnostics data pertains to the health of the memory cells. The encrypted diagnostics data is decrypted into decrypted diagnostics data and the decrypted diagnostics data is analyzed to determine the health of the memory cells. Failure mitigation is performed for the memory device if the analyzing indicates unhealthy memory cells.
H04L 29/06 - Commande de la communication; Traitement de la communication caractérisés par un protocole
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
H04L 9/30 - Clé publique, c.-à-d. l'algorithme de chiffrement étant impossible à inverser par ordinateur et les clés de chiffrement des utilisateurs n'exigeant pas le secret
25.
TECHNIQUES FOR REMOVING NON-LINEAR ECHO IN ACOUSTIC ECHO CANCELLERS
Techniques for non-linear acoustic echo cancellation are described herein. In an embodiment, a system comprises a loudspeaker, a microphone array, a spatial filtering logic with a spatial filter, an acoustic echo canceller (AEC) logic and an adder logic block. The spatial filtering logic is configured to generate a spatially-filtered signal by applying the spatial filter using a reference signal sent to the loudspeaker and a multi-channel microphone signal from the microphone array. The generated spatially-filtered signal carries both linear echo and non-linear echo that are included in the multi-channel microphone signal. The AEC logic is configured to apply a linear adaptive filter using the spatially-filtered signal to generate a cancellation signal that estimates both the linear echo and the non-linear echo of the multi-channel microphone signal. The adder logic block is configured to generate an output signal based on the cancellation signal.
H04M 9/08 - Systèmes téléphoniques à haut-parleur à double sens comportant des moyens pour conditionner le signal, p. ex. pour supprimer les échos dans l'une ou les deux directions du trafic
26.
DETECTION OF VARIATION IN LOAD IMPEDANCE OF WIRELESS COMMUNICATIONS DEVICES
Systems, methods, and devices detect variations in load impedances of wireless communications devices. Methods include determining a first distortion measurement of a transceiver based on a first comparison of a digital loopback path and a radio frequency (RF) loopback path, and determining a second distortion measurement of the transceiver based on a second comparison of the digital loopback path and the RF loopback path. Methods also include implementing, using a processor, a third comparison of the first distortion measurement and the second distortion measurement, and determining if there is a change in a load of the transceiver based on the third comparison.
Disclosed are methods and systems for tailoring the transmit power of a wireless device to the parameters of the device such as the process split, voltage, and temperature. The device may identify one or more parameters of the device such as identifying the process split, or sensing the operating voltage or temperature. The device may determine an updated transmit power based on the known parameter values identified and any unknown parameter values. The updated transmit power is determined to be a maximum transmit power that meets one or more target transmit metrics, such as EVM and spectral mask, when the device transmits based on the known parameter values and across a range of variations of the unknown parameter values. The device may adjust its transmit power based on the updated transmit power periodically.
H04W 52/22 - Commande de puissance d'émission [TPC Transmission power control] le TPC étant effectué selon des paramètres spécifiques tenant compte des informations ou des instructions antérieures
H04W 52/24 - Commande de puissance d'émission [TPC Transmission power control] le TPC étant effectué selon des paramètres spécifiques utilisant le rapport signal sur parasite [SIR Signal to Interference Ratio] ou d'autres paramètres de trajet sans fil
H04W 52/50 - Commande de puissance d'émission [TPC Transmission power control] le TPC étant effectué dans des situations particulières au moment de déclencher une communication dans un environnement à accès multiple
H04W 52/36 - Commande de puissance d'émission [TPC Transmission power control] utilisant les limitations de la quantité totale de puissance d'émission disponible avec une plage ou un ensemble discrets de valeurs, p. ex. incrément, variation graduelle ou décalages
28.
POWER SAVING TECHNIQUE IN DETACH CONDITION FOR USB-POWER DELIVERY WITH INTEGRATED SYNCHRONOUS RECITIFIER CONTROLLER
A secondary-side controller for an AC-DC converter that has a single synchronous rectifier sensing (SR_SNS) terminal, coupled to a synchronous rectifier (SR) of the AC-DC converter, and a voltage divider circuit coupled to the single SR_SNS terminal configured to provide signals to a sensing circuit. The voltage divider includes an active diode, an internal resistive element, and a switch, in which the active diode is configured to control the switch to enable or disable the internal resistive element based on a comparison result of a voltage at the single SR_SNS terminal and a reference voltage.
H02M 7/217 - Transformation d'une puissance d'entrée en courant alternatif en une puissance de sortie en courant continu sans possibilité de réversibilité par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
29.
Method and apparatus for data transmission via capacitance sensing device
A system made up of a first device which includes a communication interface and a processing device and a second device which includes a touch sensor assembly and a controller, where the controller uses the touch sensor assembly to communicate with the processing device through a capacitor that is jointly formed by the touch sensor assembly and a conductive portion of the communications interface.
H04B 5/00 - Systèmes de transmission en champ proche, p. ex. systèmes à transmission capacitive ou inductive
G06F 3/041 - Numériseurs, p. ex. pour des écrans ou des pavés tactiles, caractérisés par les moyens de transduction
G06F 3/044 - Numériseurs, p. ex. pour des écrans ou des pavés tactiles, caractérisés par les moyens de transduction par des moyens capacitifs
H04M 1/724 - Interfaces utilisateur spécialement adaptées aux téléphones sans fil ou mobiles
G06Q 20/36 - Architectures, schémas ou protocoles de paiement caractérisés par l'emploi de dispositifs spécifiques utilisant des portefeuilles électroniques ou coffres-forts électroniques
30.
A POWER-EFFICIENT SYNC-RECTIFIER GATE DRIVER ARCHITECTURE
A synchronous switching scheme with adaptive slew control in order to adiabatically charge and discharge a capacitor to recycle charge and generate a boosted voltage on the gate of the synchronous rectifier field effect transistor (FET) is described. In one embodiment, an apparatus includes a synchronous rectifier FET coupled to a transformer, and a secondary-side controller coupled to the synchronous rectifier FET. The secondary-side controller includes a synchronous rectifier gate driver (SRGD) coupled to a gate of the synchronous rectifier FET. The SRGD is to drive the synchronous rectifier FET using the capacitor and an adaptive slew rate, and to adiabatically charge and discharge the capacitor.
H02M 7/04 - Transformation d'une puissance d'entrée en courant alternatif en une puissance de sortie en courant continu sans possibilité de réversibilité par convertisseurs statiques
H02M 7/02 - Transformation d'une puissance d'entrée en courant alternatif en une puissance de sortie en courant continu sans possibilité de réversibilité
H02M 7/00 - Transformation d'une puissance d'entrée en courant alternatif en une puissance de sortie en courant continuTransformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant alternatif
H02J 7/02 - Circuits pour la charge ou la dépolarisation des batteries ou pour alimenter des charges par des batteries pour la charge des batteries par réseaux à courant alternatif au moyen de convertisseurs
H02J 7/00 - Circuits pour la charge ou la dépolarisation des batteries ou pour alimenter des charges par des batteries
H02M 1/10 - Dispositions comprenant des moyens de conversion, pour permettre l'alimentation à volonté d'une charge par des sources de puissance de nature différente, p. ex. à courant alternatif ou à courant continu
H02M 1/00 - Détails d'appareils pour transformation
G06F 1/26 - Alimentation en énergie électrique, p. ex. régulation à cet effet
31.
AVOIDING FALSE NSN DETECTION IN FLYBACK CONVERTERS
Techniques for avoiding false negative sense (NSN) detection in a flyback AC-DC converter are described herein. In an example embodiment, a secondary side controller of the AC-DC converter comprises a frequency detector, a negative sense detector, and control logic. The frequency detector is configured to determine a frequency of an input signal from the drain node of a synchronous rectifier (SR) circuit on the secondary side of the AC-DC converter. The negative sense detector is configured to determine a negative voltage of the input signal. The control logic is configured to: enable the negative sense detector, when the frequency of the input signal rises above a frequency threshold value; and turn on the SR circuit to transfer power to the secondary side of the AC-DC converter, when the negative voltage of the input signal falls below a voltage threshold value.
H02H 7/125 - Circuits de protection de sécurité spécialement adaptés aux machines ou aux appareils électriques de types particuliers ou pour la protection sectionnelle de systèmes de câble ou de ligne, et effectuant une commutation automatique dans le cas d'un changement indésirable des conditions normales de travail pour convertisseursCircuits de protection de sécurité spécialement adaptés aux machines ou aux appareils électriques de types particuliers ou pour la protection sectionnelle de systèmes de câble ou de ligne, et effectuant une commutation automatique dans le cas d'un changement indésirable des conditions normales de travail pour redresseurs pour convertisseurs ou redresseurs statiques pour redresseurs
H02M 7/02 - Transformation d'une puissance d'entrée en courant alternatif en une puissance de sortie en courant continu sans possibilité de réversibilité
H02M 7/04 - Transformation d'une puissance d'entrée en courant alternatif en une puissance de sortie en courant continu sans possibilité de réversibilité par convertisseurs statiques
32.
NAND memory cell string having a stacked select gate structure and process for forming same
A memory string is disclosed including a plurality of core cells serially connected between a source select gate and a drain select gate along a channel. Each core cell includes a wordline separated from the channel by a stack of layers including a charge trapping layer. At least one of the source and drain select gates is a stacked select gate with a plurality of components, including a first component adjacent to the plurality of core cells and a second component separated from the core cells by the first component. The first component includes a wordline separated from the channel by a stack of layers including a charge trapping layer, and a distance between the wordline of the first component and the wordline of a first core cell in the plurality of core cells is substantially the same as distances between each wordline in the plurality of word core cells.
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
G11C 16/14 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement
H01L 27/1157 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par la région noyau de mémoire avec transistors de sélection de cellules, p.ex. NON-ET
H01L 29/51 - Matériaux isolants associés à ces électrodes
H01L 29/04 - Corps semi-conducteurs caractérisés par leur structure cristalline, p.ex. polycristalline, cubique ou à orientation particulière des plans cristallins
H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée
H01L 27/11582 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. canaux en forme de U
G11C 16/16 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement pour effacer des blocs, p. ex. des réseaux, des mots, des groupes
H01L 23/528 - Configuration de la structure d'interconnexion
33.
SYSTEM LEVEL SIMULATION AND EVALUATION OF CAPACITIVE AND INDUCTIVE SENSING-BASED SOLUTIONS
Information associated with a plurality of components of a capacitance sensing system is received. Performance of the capacitance sensing system is simulated based on the information associated with the plurality of components of the capacitance sensing system. A set of configuration parameters for a capacitance sensing controller is generated without user intervention based on the simulated performance of the capacitance sensing system.
G06F 30/367 - Vérification de la conception, p. ex. par simulation, programme de simulation avec emphase de circuit intégré [SPICE], méthodes directes ou de relaxation
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
An example device detects a pattern of medium reservations by a first wireless device by detecting that the first wireless device has indicated a reservation duration that meets or exceeds a threshold duration value. Responsive to detecting the pattern of medium reservations, the device provides a mitigation operation to prevent a second wireless device from yielding the medium to the first wireless device.
An example system and method operate a wireless device in a first mode with power to operate a communication resource of the wireless device at a first level. While operating the wireless device in the first mode, the system and method evaluates an attribute in a first portion of sensor data. Responsive to the evaluation of the attribute, the system and method transitions to the wireless device to operate in a second mode with power to operate the communication resource at a second level. The system and method use the communication resource to communicate packets via a wireless connection.
H04B 1/403 - Circuits utilisant le même oscillateur pour générer à la fois la fréquence de l’émetteur et la fréquence de l’oscillateur local du récepteur
G10L 15/22 - Procédures utilisées pendant le processus de reconnaissance de la parole, p. ex. dialogue homme-machine
G06F 1/3206 - Surveillance d’événements, de dispositifs ou de paramètres initiant un changement de mode d’alimentation
Disclosed are methods and systems for a WLAN device operating on DFS channels to calibrate the PRI as well as delays between partial pulses of received radar pulses that are impaired due to channel and filtering effects. The calibrated PRI may approximate the PRI of the transmitted pulses. The calibrated delay between the partial pulses estimates the interval between two partial pulses that originally belong to the same transmitted pulse. Using the calibrated PRI and the calibrated delay between partial pulses, the WLAN device may reconstruct the original pulses from received impaired pulses even when the impaired pulses are delayed and partial pulses of the original pulses. The WLAN device may use the calibrated results to correct the shortened PW and varying PRI of the impaired pulses to restore the partial pulses to their full PW with a relatively uniform PRI, increasing the probability of detecting the radar signals.
Controlling an active clamp field effect transistor (FET) in a secondary-controlled active clamp converter is described. In one embodiment, an apparatus includes a primary-side FET coupled to a transformer, a secondary-side FET coupled to the transformer, and an active clamp FET disposed on a primary side of the transformer. A secondary-side controller is configured to control the active clamp FET across a galvanic isolation barrier.
H02M 3/335 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu avec transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrodes de commande pour produire le courant alternatif intermédiaire utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
H02M 1/08 - Circuits spécialement adaptés à la production d'une tension de commande pour les dispositifs à semi-conducteurs incorporés dans des convertisseurs statiques
H02J 7/00 - Circuits pour la charge ou la dépolarisation des batteries ou pour alimenter des charges par des batteries
38.
CONTROLLED GATE-SOURCE VOLTAGE N-CHANNEL FIELD EFFECT TRANSISTOR (NFET) GATE DRIVER
Controlling gate-source voltage with a gate driver in a secondary-side controller in a secondary-controlled converter is described. In one embodiment, an apparatus includes a provider field effect transistor (FET) coupled to a transformer and the secondary-side controller coupled to the transformer. The gate driver is integrated on the secondary-side controller and is configured to control the gate-source voltage and slew rate of the secondary-side FET.
H02M 7/217 - Transformation d'une puissance d'entrée en courant alternatif en une puissance de sortie en courant continu sans possibilité de réversibilité par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
H02M 3/07 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des résistances ou des capacités, p. ex. diviseur de tension utilisant des capacités chargées et déchargées alternativement par des dispositifs à semi-conducteurs avec électrode de commande
H02M 7/04 - Transformation d'une puissance d'entrée en courant alternatif en une puissance de sortie en courant continu sans possibilité de réversibilité par convertisseurs statiques
G06F 13/38 - Transfert d'informations, p. ex. sur un bus
G06F 13/42 - Protocole de transfert pour bus, p. ex. liaisonSynchronisation
H02J 7/00 - Circuits pour la charge ou la dépolarisation des batteries ou pour alimenter des charges par des batteries
39.
DETECTING THE ANGLE OF A TOUCH SCREEN MOUNTED PASSIVE DIAL
A touch screen display and corresponding devices and methods are disclosed, the touch screen display comprising a touchscreen having a plurality of capacitive sensors and a passive dial having one or more conductive elements, the passive dial mounted within an active area of the touchscreen such that the one or more conductive elements are proximate to the face of the touchscreen and move in conjunction with a rotation of the passive dial. The touch screen display may further include a touchscreen controller to detect an angle of the passive dial using conventional capacitive sensing techniques.
G06F 3/044 - Numériseurs, p. ex. pour des écrans ou des pavés tactiles, caractérisés par les moyens de transduction par des moyens capacitifs
G06F 3/045 - Numériseurs, p. ex. pour des écrans ou des pavés tactiles, caractérisés par les moyens de transduction utilisant des éléments résistifs, p. ex. une seule surface uniforme ou deux surfaces parallèles mises en contact
G06F 3/041 - Numériseurs, p. ex. pour des écrans ou des pavés tactiles, caractérisés par les moyens de transduction
G06F 3/046 - Numériseurs, p. ex. pour des écrans ou des pavés tactiles, caractérisés par les moyens de transduction par des moyens électromagnétiques
G06F 3/0362 - Dispositifs de pointage déplacés ou positionnés par l'utilisateurLeurs accessoires avec détection des translations ou des rotations unidimensionnelles [1D] d’une partie agissante du dispositif de pointage, p. ex. molettes de défilement, curseurs, boutons, rouleaux ou bandes
40.
Methods for error detection and correction and corresponding systems and devices for the same
A method can include, in response to receiving a read request at a memory controller, sending a read command and address values on a command address bus in synchronism with a clock. In response to the read command, receiving an uninterrupted burst of read data values on at least one parallel data bus, the burst of read data values having double date rate with respect to the clock, and receiving error correction code (ECC) values for the read data values in response to the same read command, the ECC values not being included in the burst of read data values being output on non-ECC input/outputs (I/Os); wherein the non-ECC I/Os are I/Os not assigned to ECC data according to a preexisting standards organization. Corresponding systems and devices are disclosed.
H03M 13/00 - Codage, décodage ou conversion de code pour détecter ou corriger des erreursHypothèses de base sur la théorie du codageLimites de codageMéthodes d'évaluation de la probabilité d'erreurModèles de canauxSimulation ou test des codes
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
G06F 13/42 - Protocole de transfert pour bus, p. ex. liaisonSynchronisation
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
A device can include a plurality of processing sources; a multiplexer (MUX) configured to assign read requests from the processing sources to predetermined time division multiplexer (TDM) command slots. A memory controller can generate nonvolatile memory (NVM) command and address data from read requests received from the MUX during the TDM command slots assigned to the read requests on a unidirectional command-address bus. The address data can include at least a bank address. The device can also receive read data on a unidirectional parallel data bus in synchronism with rising and falling edges of a received data clock. The read data can be received in TDM read slots having a predetermined order. A demultiplexer can provide the read data of each TDM read slot to one of the processing sources based on the TDM read slot position in the predetermined order. Related methods and systems are also disclosed.
A nonvolatile memory device can include a serial port having at least one serial clock input, and at least one serial data input/output (I/O) configured to receive command, address and write data in synchronism with the at least one serial clock input. At least one parallel port can include a plurality of command address inputs configured to receive command and address data in groups of parallel bits and a plurality of unidirectional data outputs configured to output read data in parallel on rising and falling edges of a data clock signal. Each of a plurality of banks can include nonvolatile memory cells and be configurable for access by the serial port or the parallel port. When a bank is configured for access by the serial port, the bank is not accessible by the at least one parallel port. Related methods and systems are also disclosed.
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. circuits de commande E/S de données, mémoires tampon de données E/S
G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
43.
METHODS FOR ERROR DETECTION AND CORRECTION AND CORRESPONDING SYSTEMS AND DEVICES FOR THE SAME
A method can include, in response to receiving a read request at a memory controller, sending a read command and address values on a command address bus in synchronism with a clock. In response to the read command, receiving an uninterrupted burst of read data values on at least one parallel data bus, the burst of read data values having double date rate with respect to the clock, and receiving error correction code (ECC) values for the read data values in response to the same read command, the ECC values not being included in the burst of read data values being output on non-ECC input/outputs (I/Os); wherein the non-ECC I/Os are I/Os not assigned to ECC data according to a preexisting standards organization. Corresponding systems and devices are disclosed.
A device can include a plurality of processing sources; a multiplexer (MUX) configured to assign read requests from the processing sources to predetermined time division multiplexer (TDM) command slots. A memory controller can generate nonvolatile memory (NVM) command and address data from read requests received from the MUX during the TDM command slots assigned to the read requests on a unidirectional command-address bus. The address data can include at least a bank address. The device can also receive read data on a unidirectional parallel data bus in synchronism with rising and falling edges of a received data clock. The read data can be received in TDM read slots having a predetermined order. A demultiplexer can provide the read data of each TDM read slot to one of the processing sources based on the TDM read slot position in the predetermined order. Related methods and systems are also disclosed.
A method can include, in an access point (AP) configured to control data transfers for associated stations (STAs) in time intervals, storing a unique identifier and quality-of-service (QoS) requirement for each STA of a first set in a nonvolatile memory of the AP. In response to a STA associating with the AP, if the associating STA is in the first set, allocating time for the STA in the time intervals to meet the QoS requirement of the STA without receiving transmitted QoS data from the STA, and if the associating STA is not in the first set, establishing a QoS for the STA having a lower priority than any associated STAs of the first set. Corresponding systems and devices are also disclosed.
An example method for estimating the angle-of-arrival (AoA) and other parameters of radio frequency (RF) signals that are received by an antenna array comprises: receiving a plurality of radio frequency (RF) signal power measurements by a plurality of antenna elements at a plurality of RF channels; computing, by applying a machine learning model to the plurality of RF signal power measurements, an estimated RF signal parameter value; and outputting the RF signal parameter value.
An example method of estimating the angular resolution of antenna array comprises: receiving a plurality of values of magnitude and phase of a radio frequency (RF) signal for each antenna element of a plurality of antenna elements comprised by an antenna array; performing, by a machine learning model, a feature extraction operation to transform the plurality of values of magnitude and phase into a plurality of data points in a reduced-dimension space; clustering, by the machine learning model, the plurality of data points into a plurality of clusters; and computing, based on the clustered data points, an angular resolution value for the antenna array.
G01S 11/04 - Systèmes pour déterminer la distance ou la vitesse sans utiliser la réflexion ou la reradiation utilisant les ondes radioélectriques utilisant des mesures d'angle
H04B 17/391 - Modélisation du canal de propagation
A wireless communication device and method for operating the same for mitigating interference in a wireless communication network are provided. Generally, the method includes sensing with the wireless communication device pulses of electromagnetic radiation recurring within a band of frequencies used by the device for communication of signals, identifying the pulses as interference, and determining a number of frequencies of the interference within the band of frequencies used by the wireless communication device. Next, a sensitivity of the wireless communication device is reduced upon sensing one of the pulses and repeated at a frequency corresponding to the frequency of the interference. Thus, a spectrum of electromagnetic radiation around the wireless communication device is perceived by the device as free of interference, enabling it to transmit and/or receive more often. Other embodiments are also disclosed.
A system includes a transceiver configured to receive frequency dependent channel estimates or beamforming feedback in a multi-carrier, multi-antenna communication system, and a multi-layer perceptron feed forward neural network component, coupled with the transceiver, configured to estimate parameters of multipath reflections using representations of the channel estimates or beamforming feedback, and to generate transmission correction factors for the transceiver.
H04B 7/0456 - Sélection de matrices de pré-codage ou de livres de codes, p. ex. utilisant des matrices pour pondérer des antennes
H04B 1/712 - Pondération des doigts pour combiner, p. ex. la commande d'amplitude ou la rotation de phase à l'aide d'une boucle interne
H04B 7/06 - Systèmes de diversitéSystèmes à plusieurs antennes, c.-à-d. émission ou réception utilisant plusieurs antennes utilisant plusieurs antennes indépendantes espacées à la station d'émission
G01S 5/02 - Localisation par coordination de plusieurs déterminations de direction ou de ligne de positionLocalisation par coordination de plusieurs déterminations de distance utilisant les ondes radioélectriques
G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
G06N 3/04 - Architecture, p. ex. topologie d'interconnexion
Communicating information stored at a secondary controller to a primary controller in a secondary-controlled flyback converter is described. In one embodiment, a method includes storing, by a secondary-side controller of a power converter, calibration information associated with a primary-side controller of the power converter. The power converter is a secondary-controlled alternating current to direct current (AC-DC) flyback converter comprising a galvanic isolation barrier. The method further includes sending, by the secondary-side controller, the calibration information to the primary-side controller across the galvanic isolation barrier in response to power-up of the power converter.
H02M 3/156 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation
H02M 3/158 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation comprenant plusieurs dispositifs à semi-conducteurs comme dispositifs de commande finale pour une charge unique
H02M 3/335 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu avec transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrodes de commande pour produire le courant alternatif intermédiaire utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
51.
COMMUNICATING FAULT INDICATIONS BETWEEN PRIMARY AND SECONDARY CONTROLLERS IN A SECONDARY-CONTROLLED FLYBACK CONVERTERS
Communicating fault indications between primary and secondary controller in a secondary-controlled flyback converter is described. In one embodiment, an apparatus includes a primary-side field effect transistor (FET) coupled to a flyback transformer coupled to the primary-side FET, and a primary-side controller coupled to the flyback transformer. The primary-side controller is configured to receive a signal from a secondary-side controller across a galvanic isolation barrier, apply a pulse signal to the primary-side FET in response to the signal to turn-on and turn-off the primary-side FET, communicate information to the secondary-side controller across the flyback transformer by varying a first pulse width of the pulse signal to a second pulse width and applying the pulse signal with the second pulse width to the primary-side FET.
H02M 1/08 - Circuits spécialement adaptés à la production d'une tension de commande pour les dispositifs à semi-conducteurs incorporés dans des convertisseurs statiques
H02M 3/335 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu avec transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrodes de commande pour produire le courant alternatif intermédiaire utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
H02H 1/00 - Détails de circuits de protection de sécurité
G01R 31/42 - Tests d'alimentation d'alimentations en courant alternatif
52.
STACKABLE FULLY MOLDED SEMICONDUCTOR STRUCTURE WITH VERTICAL INTERCONNECTS
A method of making a semiconductor device may include providing a carrier and forming a first photoresist over the carrier with first openings through the first photoresist. A non-planar conductive seed layer may be formed over the first photoresist and conformally extend into the first openings through the first photoresist. A second photoresist may be formed over the first photoresist and over the non-planar conductive seed layer. The second photoresist layer may be patterned to form second openings through the second photoresist that extend to the non-planar conductive seed layer. Conductive posts may be plated over the non-planar conductive seed layer and within the second openings. The second photoresist may be removed while leaving in place the first photoresist. A semiconductor die may be coupled to the carrier. The semiconductor die, the conductive posts, and the first photoresist may be encapsulated with mold compound.
H01L 21/60 - Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement
An apparatus is provided. The apparatus comprises a controller configured to operate in an access point (AP) mode. The apparatus also includes a processing device. The processing device is configured to transmit a signal to one or more stations (STAs) to prevent the one or more STAs from using a frequency band. The frequency band is shared by the one or more STAs and a radio. The processing device is also configured to detect that the frequency band is available for use by at least one STA of the one or more STAs to transmit uplink signals to the controller without interfering with the radio; and in response, transmit a trigger frame to the at least one STA to schedule the at least one STA to transmit the uplink signals to the controller using the frequency band.
A method can include selecting a channel from a network operating according to a first protocol (e.g., an IEEE 802.11ax channel). Designating at least one portion of the channel as a shared resource unit (RU) and another portion as a dedicated RU. When an associated device is communicating according to a different protocol (e.g., a Bluetooth standard), allocating frequencies of the shared RU for use by the associated device and allocating the dedicated RUs for use by the network operating according to the first protocol.
H04W 84/12 - Réseaux locaux sans fil [WLAN Wireless Local Area Network]
H04B 1/713 - Techniques d'étalement de spectre utilisant des sauts de fréquence
H04W 28/16 - Gestion centrale des ressourcesNégociation de ressources ou de paramètres de communication, p. ex. négociation de la bande passante ou de la qualité de service [QoS Quality of Service]
55.
METHOD FOR IOT DEVICE TO STAGGER TX AND SAVE POWER
Disclosed are methods and systems for delaying packet transmissions over a wireless communication channel until a more favorable channel condition is detected. A device may measure a channel metric when it receives periodic beacon signals. The device may compare the channel metric against a programmed metric threshold. If the channel metric is less than the metric threshold, the device may delay the transmission of a packet until a later transmission window or transmit opportunity (TXOP) when the channel metric rises above the metric threshold, indicating the presence of a more favorable condition for transmission, or until a preconfigured timeout period elapses before the more favorable condition is found.
Embodiments can include a method in which a transmission duration for data frames to a plurality of different receiving devices is determined by a transmitting device. The transmission duration can include at least interframe spacings that separate the data frames from one another. The transmitting device can transmit a control message over a medium to reserve the medium for the transmission duration. The data frames can then be sequentially transmitted by the transmitting device to the plurality of receiving devices during the transmission duration. The transmitting device can operate according to a contention based protocol. Related devices and systems are also disclosed.
A device can include a plurality of regions, each region including a plurality of nonvolatile memory cells: a permission store configured to store a set of permission values, including at least one permission value for each region in a nonvolatile fashion; and access control circuits configured to control access to each region according to the permission value for the region, including one or more of requiring authentication to access the region, encrypting data read from the region, and decrypting data for storage in the region. Related methods and systems are also disclosed.
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
Systems, methods, and devices schedule requests associated with wireless communications devices. Methods include receiving a plurality of requests from a plurality of wireless communications devices that is compatible with an (802.11) transmission protocol, where each request of the plurality of requests includes a proposed service period and proposed service interval. Methods further include generating, using a processing device, a plurality of quantization factors by quantizing the proposed service interval included in each of the plurality of requests, determining, using the processing device, a common service interval based, at least in part, on the plurality of quantization factors and a basic service unit, and generating, using the processing device, an allocation pattern to allocate the proposed service periods within the common service interval.
Implementations disclosed describe systems and methods to optimize delivery of channel state information in wireless networks. In one implementation, a beamformee device may comprise a plurality of antennas, to receive radio frequency signals, a radio circuit coupled to the plurality of antennas, the radio circuit to generate strength indicators of the received radio frequency signals, and a processor to determine, based on the strength indicators, a first set of feedback parameters characterizing signal transmission received by each of the plurality of antennas, generate a sparse set of feedback parameters from the first set of feedback parameters, generate a second set of feedback parameters with elements of the sparse set that exceed a threshold value, and cause the radio circuit to transmit the second set of feedback parameters.
H04B 7/04 - Systèmes de diversitéSystèmes à plusieurs antennes, c.-à-d. émission ou réception utilisant plusieurs antennes utilisant plusieurs antennes indépendantes espacées
H04B 7/06 - Systèmes de diversitéSystèmes à plusieurs antennes, c.-à-d. émission ou réception utilisant plusieurs antennes utilisant plusieurs antennes indépendantes espacées à la station d'émission
H04L 5/00 - Dispositions destinées à permettre l'usage multiple de la voie de transmission
60.
ENHANCEMENT OF RANGE AND THROUGHPUT FOR MULTI-ANTENNA WIRELESS COMMUNICATIONS DEVICES
Systems, methods, and devices select antennas to enhance the range and throughput of wireless communications devices. Methods include identifying a plurality of combinations of antennas based on a plurality of available antennas for a wireless communications device, and generating, using a processing device included in a multiple-input-multiple-output (MIMO) device, a plurality of quality metrics including at least one quality metric for each of the identified combinations of antennas, where each of the at least one quality metrics represents a signal quality of a signal associated with each of the plurality of antennas, and wherein the signal is a spatial stream. Methods further include selecting at least two antennas from the plurality of combinations of antennas based, at least in part, on the plurality of quality metrics, where the at least two antennas are selected for use by the wireless communications device during a transmitting or receiving operation.
Maintaining a fixed frequency in a resonant circuit of an inductive sensor circuit is described. In one embodiment, an apparatus includes an inductance-todigital converter (LDC). The LDC includes a digital filter to measure an inductance change of a sensor and convert the inductance change to a digital value. The LDC further includes a digital control loop to maintain a fixed frequency in the sensor. The sensor forms an oscillator in the digital control loop. An output of the digital control loop is representative of the inductance change of the sensor.
G01D 5/20 - Moyens mécaniques pour le transfert de la grandeur de sortie d'un organe sensibleMoyens pour convertir la grandeur de sortie d'un organe sensible en une autre variable, lorsque la forme ou la nature de l'organe sensible n'imposent pas un moyen de conversion déterminéTransducteurs non spécialement adaptés à une variable particulière utilisant des moyens électriques ou magnétiques influençant la valeur d'un courant ou d'une tension en faisant varier l'inductance, p. ex. une armature mobile
G01R 27/28 - Mesure de l'atténuation, du gain, du déphasage ou des caractéristiques qui en dérivent dans des réseaux électriques quadripoles, c.-à-d. des réseaux à double entréeMesure d'une réponse transitoire
62.
APPARATUS, SYSTEMS, AND METHODS FOR SELECTING A WIRELESS DEVICE ANTENNA FOR COMMUNICATION
Example systems and methods of a wireless device use a signal attribute detector to determine a signal attribute value associated with a first frame received via a first antenna. Media access control (MAC) logic can detect that the first frame indicates an acknowledgement (ACK) of a second frame transmitted by the wireless device. Responsive to the detection of the ACK by the MAC logic, an antenna evaluator uses the signal attribute value to select one of the first antenna and the second antenna to transmit or receive a third frame
H04B 7/06 - Systèmes de diversitéSystèmes à plusieurs antennes, c.-à-d. émission ou réception utilisant plusieurs antennes utilisant plusieurs antennes indépendantes espacées à la station d'émission
H04B 7/08 - Systèmes de diversitéSystèmes à plusieurs antennes, c.-à-d. émission ou réception utilisant plusieurs antennes utilisant plusieurs antennes indépendantes espacées à la station de réception
H04L 5/00 - Dispositions destinées à permettre l'usage multiple de la voie de transmission
H04L 1/18 - Systèmes de répétition automatique, p. ex. systèmes Van Duuren
63.
DEVICES, SYSTEMS, AND METHODS FOR PREDICTING COMMUNICATION CHANNEL CONDITIONS
An example device tracks geographical location of the wireless device and time associated with the wireless device. The device may access channel map data comprising a predicted channel condition value for each of a plurality of Wi-Fi channels within each of a plurality of geographical locations during a plurality of time periods of day. The device can use the channel map data to select one of the plurality of Wi-Fi channels for communication based on a geographical location of the wireless device and a time of day associated with the wireless device.
H04W 72/02 - Sélection de ressources sans fil par un utilisateur ou un terminal
H04W 4/029 - Services de gestion ou de suivi basés sur la localisation
H04W 4/40 - Services spécialement adaptés à des environnements, à des situations ou à des fins spécifiques pour les véhicules, p. ex. communication véhicule-piétons
H04W 24/04 - Configurations pour maintenir l'état de fonctionnement
H04W 24/10 - Planification des comptes-rendus de mesures
H04W 64/00 - Localisation d'utilisateurs ou de terminaux pour la gestion du réseau, p. ex. gestion de la mobilité
H04L 5/00 - Dispositions destinées à permettre l'usage multiple de la voie de transmission
64.
METHODS, SYSTEMS AND DEVICES FOR VARYING WIRELESS TRANSMIT POWER BASED ON PATH LOSS INFORMATION
A method can include at a first station in a wireless network, receiving path loss (PL) transmissions from at least a second station, dynamically changing power for transmissions from the first station to the second station based on the received PL information, determining PL values for transmissions received at the first station from other stations, and sending PL transmissions from the first station that include the determined PL values for at least one other station. The PL transmissions are configured to be received by stations of the same wireless network and stations of a different wireless network. Corresponding devices and systems are also disclosed.
According to embodiments, methods, devices and systems can include monitoring all of a first channel for a first monitoring period. After the first monitoring period, monitoring at least one narrow band for at least a first narrow band signal. In response to detecting the first narrow band signal, establishing a network connection over the narrow band, wherein the at least one narrow band has a frequency range less than one half that of the first channel.
Embodiments can include methods, devices and systems which can transmitting a preamble across a first channel according to a first communication protocol; sequentially transmitting signal values in a plurality of narrow bands; monitoring the narrow bands for response communications; and upon detecting response communications on at least one of the narrow bands, establishing communications across at least one of the narrow bands. Each narrow band can be a different portion of the first channel.
According to embodiments, methods, devices and systems can include generating packet data for a narrow band packet. Transmitting first preamble data across a first channel followed by the narrow band packet with a second preamble across at least one resource unit (RU). The RU can have a smaller bandwidth than the first channel and occupy a portion of the first channel. The first preamble can be configured to enable detection of a packet transmitted in the first channel, and the second preamble is configured to enable detection of a packet transmitted in the RU without the first preamble.
H04L 27/26 - Systèmes utilisant des codes à fréquences multiples
H04W 4/80 - Services utilisant la communication de courte portée, p. ex. la communication en champ proche, l'identification par radiofréquence ou la communication à faible consommation d’énergie
68.
SYSTEMS AND METHODS FOR ADJUSTING RECEIVE SENSITIVITY USING COLLOCATED COMMUNICATION CIRCUITRY
Example systems and methods of a wireless device use first communication circuitry of the wireless device to determine a first signal level associated with a first radio frequency signal and use second communication circuitry of the wireless device to determine a second signal level associated with a second radio frequency signal. Systems and methods generate a sensitivity adjustment value based on the first signal level and the second signal level, and use the sensitivity adjustment value to process a combined signal comprising the first radio frequency signal and the second radio frequency signal.
H04B 1/10 - Dispositifs associés au récepteur pour limiter ou supprimer le bruit et les interférences
H04B 1/00 - Détails des systèmes de transmission, non couverts par l'un des groupes Détails des systèmes de transmission non caractérisés par le milieu utilisé pour la transmission
69.
GENERAL-PURPOSE ANALOG SWITCH WITH A CONTROLLED DIFFERENTIAL EQUALIZATION VOLTAGE-SLOPE LIMIT
A differential-slope-limiting-switch and method are provided. Generally, the switch includes a first transistor having a first source-drain (SD) and well coupled to a first port of the switch, a gate, and a second SD, and a second transistor having a first SD and well coupled to a second port, a gate, and a second SD coupled to the second SD of the first transistor. A selector-circuit couples the gate of the first transistor to a first current-source when a signal to close the switch is received, and to the first port when it is not received. A second selector-circuit couples the gate of the second transistor to a second current-source when the signal is received, or to the second port. First and second feedback-capacitors couple each gate to the port on opposite sides of the switch and with the current-sources limit a slope of voltage transitions across the closed switch.
H03K 5/08 - Mise en forme d'impulsions par limitation, par application d'un seuil, par découpage, c.-à-d. par application combinée d'une limitation et d'un seuil
H04L 25/06 - Moyens pour rétablir le niveau à courant continuCorrection de distorsion de polarisation
70.
GPS-ASSISTED COLLABORATIVE AND SIGNALING-AIDED WLAN DFS OPERATION
Disclosed are methods and systems for a WLAN device to select an operating dynamic frequency selection (DFS) channel that minimizes the probability of radar interference by using aiding information. The aiding information may be a crowd-sourced database of geo-tagged radar zones including one or more DFS channels used within the geo-tagged radar zones that are detected by a plurality of WLAN devices. The WLAN device may query the crowd-sourced database for a geo-tagged radar zone that is nearby to determine if a radar operates on an overlapping DFS channel so it may switch to a different channel. In one aspect, the aiding information may be periodic special action frames broadcast by a WLAN beaconing device over the operating channel of the WLAN device. The special action frames may carry information on one or more channels used by a near-by radar and recommended alternative channels to use by the WLAN device.
Disclosed are apparatus and methods for programming a plurality of nonvolatile memory (NVM) devices. Each NVM device self-generates and stores a unique encryption key. Each NVM device concurrently receives an image from a multiple-device programming system to which all the NVM devices are communicatively coupled. Each NVM device encrypts the received image using such NVM device's unique encryption key to produce a unique encrypted image for each NVM device. Each NVM device stores its unique encrypted image within a nonvolatile memory of such NVM device. The unique encryption key can then be securely transferred to a host device for decrypting the image accessed from one of the NVM devices.
Disclosed are apparatus and methods for programming a plurality of nonvolatile memory (NVM) devices. Each NVM device self-generates and stores a unique encryption key. Each NVM device concurrently receives an image from a multiple-device programming system to which all the NVM devices are communicatively coupled. Each NVM device encrypts the received image using such NVM device's unique encryption key to produce a unique encrypted image for each NVM device. Each NVM device stores its unique encrypted image within a nonvolatile memory of such NVM device. The unique encryption key can then be securely transferred to a host device for decrypting the image accessed from one of the NVM devices.
H04L 29/06 - Commande de la communication; Traitement de la communication caractérisés par un protocole
H04L 9/14 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité utilisant plusieurs clés ou algorithmes
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
A method, apparatus, and system for providing temporary access point (AP) functionality to an intermediary device to provide wireless network credentials to a wireless device (STA) to be connected to a wireless network including an AP is described. The intermediary device may mimic the AP to provide wireless network credentials to the wireless device and discontinue an onboarding session to allow the wireless device to access the AP directly.
Techniques for guided placement of a wireless device are described herein. In an example embodiment, a wi-fi wireless device comprises a radio frequency (RF) transceiver coupled to a baseband processor. The RF transceiver is configured to receive an RF signal transmitted over a wireless channel and to convert the RF signal to a modulated digital signal. The baseband processor is configured to receive the modulated digital signal from the RF transceiver, extract a wireless packet from the modulated digital signal, and compute an Exponential Effective SNR Mapping (EESM) value based on the preamble of the wireless packet, where the computed EESM value indicates the quality of the wireless channel at the current location of the wireless device. The baseband processor is further configured to provide a quality indicator based on the EESM value for the current location of the wireless device.
H04W 40/00 - Acheminement ou recherche d'itinéraire pour la communication
H04W 40/02 - Sélection d'itinéraire ou de voie de communication, p. ex. routage basé sur l'énergie disponible ou le chemin le plus court
H04W 40/12 - Sélection d'itinéraire ou de voie de communication, p. ex. routage basé sur l'énergie disponible ou le chemin le plus court sur la base de la qualité d'émission ou de la qualité des canaux
H04W 40/20 - Sélection d'itinéraire ou de voie de communication, p. ex. routage basé sur l'énergie disponible ou le chemin le plus court sur la base de la position ou de la localisation géographique
H04W 64/00 - Localisation d'utilisateurs ou de terminaux pour la gestion du réseau, p. ex. gestion de la mobilité
75.
POWER MANAGEMENT AND DATA BANDWIDTH IMPROVEMENTS FOR PASSIVE ENTRY, PASSIVE START (PEPS)
A passive entry, passive start (PEPS) application is described, wherein a number of sensors are configured with wireless communication protocol information for wireless communication between a master device and a BLE hub. The sensors eavesdrop signals from the master device to the BLE hub while not in operative communication with the master device. Eavesdropped signals are processed to determine and calculate position-related information, such as phase and magnitude of the wireless signals received at multiple antennas of the sensors, angle-of-arrival (AoA), and distance or position of the master device relative to the sensors, individually or as a system. Power management techniques for a PEPS system are also described.
B60R 25/00 - Équipements ou systèmes pour empêcher ou signaler l’usage non autorisé ou le vol de véhicules
B60R 25/20 - Moyens pour enclencher ou arrêter le système antivol
B60R 25/24 - Moyens pour enclencher ou arrêter le système antivol par des éléments d’identification électroniques comportant un code non mémorisé par l’utilisateur
G01S 1/00 - Radiophares ou systèmes de balisage émettant des signaux ayant une ou des caractéristiques pouvant être détectées par des récepteurs non directionnels et définissant des directions, situations ou lignes de position déterminées par rapport aux émetteurs de radiophareRécepteurs travaillant avec ces systèmes
G07C 9/00 - Enregistrement de l’entrée ou de la sortie d'une entité isolée
76.
DEVICES, SYSTEMS AND METHODS FOR POWER OPTIMIZATION USING TRANSMISSION SLOT AVAILABILITY MASK
A method can include at a combination device, receiving or generating a slot availability mask (SAM) information compatible with a Bluetooth and/or Bluetooth Low Energy (BT) standard; by operation of BT compatible circuits of the combination device, determining a schedule of BT compatible data transfers in response to at least the SAM information; and by operation of circuits compatible with at least one IEEE 802.11 wireless standard (WLAN circuits), determining a schedule of WLAN compatible data transfers in response to at least the SAM information. Related systems and methods are also disclosed.
H04W 4/80 - Services utilisant la communication de courte portée, p. ex. la communication en champ proche, l'identification par radiofréquence ou la communication à faible consommation d’énergie
A system includes an apparatus and a station. The apparatus includes a first access point (AP) function configured to operate on a first channel of a first frequency band and a second AP function configured to operate on a second channel of a second frequency band. The apparatus also includes a processing device. In response to detecting that the second channel is unavailable for use by the second AP function, the processing device is configured to transition the second AP function to operate on a third channel of the first frequency band. The station can be used in an automotive application and is configured to communicate with the first AP function in the first frequency band, or communicate with the second AP function in the first frequency band or the second frequency band.
An example method of operating a device includes using a switching circuitry to a first subset of antennas from an antenna cluster, using the first subset of antennas to receive a first Bluetooth signal, generating a first directional value of the first Bluetooth signal, using a processing element to evaluate at least one antenna of the antenna cluster based at least partly on the first directional value, selecting a second subset of antennas based on evaluation, using the second subset of antennas to receive a second Bluetooth signal, and generating a second directional value of the second Bluetooth signal. Other embodiments of the device and operations thereof are also disclosed.
H04W 48/16 - ExplorationTraitement d'informations sur les restrictions d'accès ou les accès
H04W 64/00 - Localisation d'utilisateurs ou de terminaux pour la gestion du réseau, p. ex. gestion de la mobilité
G01S 5/14 - Localisation par coordination de plusieurs déterminations de direction ou de ligne de positionLocalisation par coordination de plusieurs déterminations de distance utilisant les ondes radioélectriques déterminant des distances absolues à partir de plusieurs points espacés d'emplacement connu
H04W 4/02 - Services utilisant des informations de localisation
79.
NAND memory cell string having a stacked select gate structure and process for for forming same
A memory string is disclosed including a plurality of core cells serially connected between a source select gate and a drain select gate along a channel. Each core cell includes a wordline separated from the channel by a stack of layers including a charge trapping layer. At least one of the source and drain select gates is a stacked select gate with a plurality of components, including a first component adjacent to the plurality of core cells and a second component separated from the core cells by the first component. The first component includes a wordline separated from the channel by a stack of layers including a charge trapping layer, and a distance between the wordline of the first component and the wordline of a first core cell in the plurality of core cells is substantially the same as distances between each wordline in the plurality of word core cells.
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
G11C 16/14 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement
H01L 27/1157 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par la région noyau de mémoire avec transistors de sélection de cellules, p.ex. NON-ET
H01L 27/11582 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par des agencements tridimensionnels, p.ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p.ex. avec des canaux inclinés les canaux comprenant des parties verticales, p.ex. canaux en forme de U
H01L 29/51 - Matériaux isolants associés à ces électrodes
H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée
H01L 23/528 - Configuration de la structure d'interconnexion
G11C 16/16 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement pour effacer des blocs, p. ex. des réseaux, des mots, des groupes
H01L 29/04 - Corps semi-conducteurs caractérisés par leur structure cristalline, p.ex. polycristalline, cubique ou à orientation particulière des plans cristallins
80.
TIMESTAMP BASED ONBOARDING PROCESS FOR WIRELESS DEVICES
A method, apparatus, and system for provisioning a device onto a network using a non-secure communication channel between the device and a provisioner is described. The provisioner receives a timestamp-based on-time password (TOTP), and a universal resource identifier (URI) from the device and provides the TOTP and an out-of-band (OOB) UUID to a remote server over a secure communication channel identified by the URI. The device is then provisioned onto a network based on comparisons of the UUID and the TOTP.
H04W 4/80 - Services utilisant la communication de courte portée, p. ex. la communication en champ proche, l'identification par radiofréquence ou la communication à faible consommation d’énergie
A universal serial bus (USB) apparatus that has a USB hub, a first switching unit including first end coupled to a USB peripheral port of a first device, a second switching unit including a second end coupled to the USB hub and the first switching unit and a first end configured to be coupled to a first USB device, and control circuitry operable to provide control signals to the first and second switching units, in which the first control signals cause the first and second switching units to provide connectivity between the USB peripheral port of the first device and the first USB device when the first USB device is operating as a USB host and the second control signals to provide connectivity between the USB host port to the first USB device via the USB hub when the first USB device is operating as a USB peripheral.
An apparatus including non-volatile memory to store a forensic key and data, the data received from a host computing system. A processing device is coupled to the non-volatile memory and is to: allow writing the data, by the host computing system, to a region of the non-volatile memory; in response to a lock signal received from the host computing system, assert a lock on the region of the non-volatile memory, the lock to cause a restriction on access to the region of the non-volatile memory by an external device; and provide unrestricted access, by the external device, to the region of the non-volatile memory in response to verification of the forensic key received from the external device.
An apparatus including non-volatile memory to store a forensic key and data, the data received from a host computing system. A processing device is coupled to the non-volatile memory and is to: allow writing the data, by the host computing system, to a region of the non-volatile memory; in response to a lock signal received from the host computing system, assert a lock on the region of the non-volatile memory, the lock to cause a restriction on access to the region of the non-volatile memory by an external device; and provide unrestricted access, by the external device, to the region of the non-volatile memory in response to verification of the forensic key received from the external device.
A method can include monitoring a transmission medium for packets of a first protocol type with first communication circuits while the medium is controlled by second communication circuits. Requesting access to the medium in response to the first communication circuits detecting a packet of the first protocol type. Upon being granted access to the medium, executing a data transmission operation. Yielding the medium back to the second communication circuits in response the first communication circuits completing the data transmission operation. Related devices and systems are also disclosed.
A method can include, by operation of first communication circuits, determining a quality of a plurality of communication frequencies according to wireless communications of a first protocol type; recording a quality of the communication frequencies; selecting communication frequencies for use by second communication circuits based on the quality of the communication frequencies; and wirelessly transmitting and receiving data with the second communication circuits according to a second protocol different than the first protocol; wherein the first and second communication circuits are collocated on the same device. Related devices and systems are also disclosed.
A method can include receiving a timing signal that is part of a first communication protocol; by operation of a master device operating according to a second communication protocol, determining event timing windows for a plurality of slave devices of the master device; and by operation of the master device, transmitting control packets to the slave devices, adjusting clock values in the slave devices to sequentially order the event timing windows within an event group window; wherein the event window is timed according to the timing signal. Related devices and systems are also disclosed.
H04W 4/80 - Services utilisant la communication de courte portée, p. ex. la communication en champ proche, l'identification par radiofréquence ou la communication à faible consommation d’énergie
Implementations disclosed describe a method and a multi-band hardware support to optimize performance of wireless networks having multi-band connectivity by steering devices connecting to the network to preferred frequency ranges. The method may comprise receiving, a first probe request from a client device at a first access point of the wireless network, establishing a first association between the first access point and the client device, the first access point operating at a first frequency range of the wireless network, receiving a second probe request from the client device at a second access point, the second access point operating at a second frequency range of the wireless network, sending a transition request over the first access point to instruct the client device to transition to the second access point, and establishing a second association between the second access point and the client device.
Disclosed herein are systems and techniques for adaptive capacitor charge voltage management, particularly for lithium-ion capacitors and hybrid capacitors. The techniques adapt the capacitor charge voltage and hence the capacitor stored energy based on capacitor operating temperature and one or more of the capacitance and the equivalent series resistance (ESR) of the capacitor.
G11C 14/00 - Mémoires numériques caractérisées par des dispositions de cellules ayant des propriétés de mémoire volatile et non volatile pour sauvegarder l'information en cas de défaillance de l'alimentation
89.
METHODS, SYSTEMS AND DEVICES FOR COMMUNICATING BETWEEN DEVICES WITHIN A CHANNEL HOPPING SYSTEM
A method can include, by operation of a first device, generating sequence information for a plurality of sequential transmission windows, the sequence information including at least a channel identification (ID) corresponding to a base frequency for each window; generating payload data for a packet and wirelessly transmitting the packet in one of the windows, the payload data including sequence information for a window later in the sequence than the window in which the packet is transmitted. By operation of an application executed on a second device, a target packet can be composed that includes inverse whitened data; wherein the whitening of the inverse whitened data by the second device results in a substantially sinusoidal signal when the target packet is transmitted. The first device can determine a direction of the second device by processing the substantially sinusoidal signal. Devices for executing such a method are also disclosed.
H04W 4/029 - Services de gestion ou de suivi basés sur la localisation
H04W 4/80 - Services utilisant la communication de courte portée, p. ex. la communication en champ proche, l'identification par radiofréquence ou la communication à faible consommation d’énergie
H04B 1/713 - Techniques d'étalement de spectre utilisant des sauts de fréquence
H04L 27/10 - Systèmes à courant porteur à modulation de fréquence, p. ex. utilisant une manipulation à décalage de fréquence
90.
SYSTEMS, METHODS, AND DEVICES FOR FAST WAKEUP OF DC-DC CONVERTERS INCLUDING FEEDBACK REGULATION LOOPS
Systems, methods, and devices implement direct current (DC)-DC converters having fast wake up times and low ripple effects. Methods include determining a DC-DC converter is to be transitioned from an operational mode to a low power mode, and storing a voltage at an input of a comparator coupled to an input of a charge pump, the voltage being stored in a feedback capacitor of a feedback regulation loop. The methods further include uncoupling a voltage trimming circuit from the input of the comparator, and maintaining, at least in part, the stored voltage at the feedback capacitor during the low power mode.
H02M 3/07 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des résistances ou des capacités, p. ex. diviseur de tension utilisant des capacités chargées et déchargées alternativement par des dispositifs à semi-conducteurs avec électrode de commande
H02M 3/02 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif
H02M 3/04 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques
H02M 3/06 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des résistances ou des capacités, p. ex. diviseur de tension
Implementations disclosed describe a programmable analog subsystem (PASS) having a plurality of reconfigurable analog circuits. The PASS may be coupled to an input/output device to receive an input signal and to an interface to communicate data with a central processing unit. In a first PASS configuration, with the plurality of reconfigurable analog circuits having a first configuration setting, the PASS may process the input signal through the plurality of reconfigurable analog circuits to generate a first output value based on the input signal. Responsive to the first output value, the PASS may reconfigure the plurality of reconfigurable analog circuits into a second PASS configuration having a second configuration setting, such that the second configuration setting is different than the first configuration setting.
H03K 19/173 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants
G06G 7/06 - Dispositifs de programmation, p. ex. panneau de connexion pour l'interconnexion des unités fonctionnelles du calculateurProgrammation numérique
G05B 19/02 - Systèmes de commande à programme électriques
G05B 19/042 - Commande à programme autre que la commande numérique, c.-à-d. dans des automatismes à séquence ou dans des automates à logique utilisant des processeurs numériques
G05B 19/045 - Commande à programme autre que la commande numérique, c.-à-d. dans des automatismes à séquence ou dans des automates à logique utilisant des machines à états logiques composées uniquement d'une mémoire ou d'un dispositif logique programmable contenant la logique de la machine commandée et dans lesquelles l'état de ses sorties dépend de l'état de ses entrées, ou d'une partie des états de sa propre sortie, p. ex. contrôleurs de décision binaire, automates finis
G06F 13/10 - Commande par programme pour dispositifs périphériques
92.
Semiconductor device and method of manufacturing the same
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 21/683 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/29 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par le matériau
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
93.
TRAFFIC COEXISTENCE FOR COLLOCATED TRANSCEIVERS INCLUDING BLUETOOTH TRANSCEIVERS
Systems, methods, and devices enable coexistence of traffic for collocated transceivers. Methods may include generating, using a processing device, a medium access schedule for at least a first transceiver based on a transmission parameter of a second transceiver, the second transceiver being collocated with the first transceiver and sharing a transmission medium with the first transceiver, and the medium access schedule comprising a QuietIE schedule. Methods may also include identifying a plurality of wireless devices communicatively coupled to the first transceiver. Methods may further include transmitting the QuietIE schedule to the plurality of wireless devices, the QuietIE schedule identifying a plurality of quiet periods and a plurality of available periods to the plurality of wireless devices.
H04W 4/80 - Services utilisant la communication de courte portée, p. ex. la communication en champ proche, l'identification par radiofréquence ou la communication à faible consommation d’énergie
94.
SYSTEM AND METHODS FOR ARBITRATING COMMUNICATIONS BY COLLOCATED COMMUNICATION CIRCUITRY
An example system and method, during operation of first communication circuitry in a first operating mode comprising first power consumption, uses the first communication circuitry to perform packet arbitration for wireless communications by the first communication circuitry, second communication circuitry, and third communication circuitry. During operation of the first communication circuitry in a second operating mode comprising second power consumption, the example system and method uses the second communication circuitry to perform packet arbitration for wireless communications by the second communication circuitry and a third communication circuitry.
A method includes receiving an absence schedule and storing the absence schedule in a memory. The absence schedule indicates a plurality of absence periods during which a group owner device in a wireless network will be unavailable for receiving transmissions in a frequency band. The method further includes controlling a primary radio transceiver of a wireless device based on the absence schedule, receiving a first request from a secondary radio transceiver of the wireless device to transmit a first wireless message in the frequency band, and granting the first request in response to determining based on the stored absence schedule that a transmission time of the first wireless message is within one of the plurality of absence periods.
H04W 4/80 - Services utilisant la communication de courte portée, p. ex. la communication en champ proche, l'identification par radiofréquence ou la communication à faible consommation d’énergie
96.
BEAMFORMER AND ACOUSTIC ECHO CANCELLER (AEC) SYSTEM
Techniques for acoustic echo cancellation are described herein. In an example embodiment, a system comprises a speaker, a microphone array with multiple microphones, a beamformer (BF) logic and an acoustic echo canceller (AEC) logic. The speaker is configured to receive a reference signal. The BF logic is configured to receive audio signals from the multiple microphones and to generate a beamformed signal. The AEC logic is configured to receive the beamformed signal and the reference signal. The AEC logic is also configured to compute a vector of bias coefficients multiple times per time frame, to compute a background filter coefficient based on the vector of bias coefficients, to apply a background filter to the reference signal and the beamformed signal based on the background filter coefficient, to generate a background cancellation signal, and to generate an output signal based at least on the background cancellation signal.
G10K 11/16 - Procédés ou dispositifs de protection contre le bruit ou les autres ondes acoustiques ou pour amortir ceux-ci, en général
G10K 11/178 - Procédés ou dispositifs de protection contre le bruit ou les autres ondes acoustiques ou pour amortir ceux-ci, en général utilisant des effets d'interférenceMasquage du son par régénération électro-acoustique en opposition de phase des ondes acoustiques originales
G10L 19/06 - Détermination ou codage des caractéristiques spectrales, p. ex. des coefficients de prédiction à court terme
G10L 19/08 - Détermination ou codage de la fonction d'excitationDétermination ou codage des paramètres de prédiction à long terme
G10L 19/09 - Prédiction à long terme, c.-à-d. en éliminant les redondances périodiques, p. ex. en utilisant un répertoire adaptatif ou un prédicateur de hauteur tonale
G10L 21/0216 - Filtration du bruit caractérisée par le procédé d’estimation du bruit
G10L 21/0264 - Filtration du bruit caractérisée par le type de mesure du paramètre, p. ex. techniques de corrélation, techniques de passage par zéro ou techniques prédictives
H04M 9/08 - Systèmes téléphoniques à haut-parleur à double sens comportant des moyens pour conditionner le signal, p. ex. pour supprimer les échos dans l'une ou les deux directions du trafic
97.
SECURED COMMUNICATION FROM WITHIN NON-VOLATILE MEMORY DEVICE
An apparatus includes a non-volatile memory (NVM) device coupled to a host, the NVM device including a processing device to: receive a communication packet from a server via the host computing system that is coupled to the NVM device and communicatively coupled to the server, the communication packet comprising clear text data that requests to initiate secure communications; perform a secure handshake with the server, via communication through the host computing system, using a secure protocol that generates a session key; receive data, via the host computing system, from the server within a secure protocol packet, wherein the data is inaccessible to the host computing system; authenticate the data using secure protocol metadata of the secure protocol packet; optionally decrypt, using the session key, the data to generate plaintext data; and store the plaintext data in NVM storage elements of the NVM device.
A power supply architecture for USB Type-C controllers is described herein. In an example embodiment, an integrated circuit (IC) controller comprises a power rail, a VDDD terminal, a VCONN terminal, and a VBUS terminal. The VDDD terminal, the VCONN terminal, and the VBUS terminal are coupled to the power rail, where a VCONN switch is coupled between the VCONN terminal and the power rail, and a VBUS regulator is coupled between the VBUS terminal and the power rail. The power rail is coupled to internal circuits of the IC controller and is configured to provide operating power to the internal circuits from any one of the VCONN terminal and the VBUS terminal.
An electronic device includes a first switch configured to connect a first sideband use (SBU) terminal of a Universal Serial Bus Type-C (USB-C) controller to a first SBU terminal of a USB-C receptacle. The electronic device also includes a second switch configured to connect a second sideband use (SBU) terminal of the USB-C controller to a second SBU terminal of the USB-C receptacle. The electronic device further includes a voltage protection circuit configured to deactivate one or more of the first switch and the second switch when a voltage exceeding a predetermined threshold is detected. The voltage protection circuit includes a first set of diodes coupled to the first SBU terminal of the USB-C controller and a second set of diodes coupled to the second SBU terminal of the USB-C controller.
H01R 13/66 - Association structurelle avec des composants électriques incorporés
H01R 24/60 - Contacts espacés le long de la paroi latérale plane transversalement par rapport à l'axe longitudinal d’engagement
G06F 13/42 - Protocole de transfert pour bus, p. ex. liaisonSynchronisation
H02H 3/20 - Circuits de protection de sécurité pour déconnexion automatique due directement à un changement indésirable des conditions électriques normales de travail avec ou sans reconnexion sensibles à un excès de tension
100.
DYNAMIC VCONN SWAPPING IN DUAL-POWERED TYPE-C CABLE APPLICATIONS
A semiconductor device for a USB Type-C cable includes a first terminal to couple to a first VCONN line from a first end of the cable, a second terminal to couple to a second VCONN line from the second end of the cable, a charge pump, and a switch circuit coupled to the first terminal and the second terminal. The switch circuit includes a first drain-extended n-type field effect transistor (DENFET) coupled between the first terminal and an internal power supply of the semiconductor device; a first pump switch coupled between the charge pump and a gate of the first DENFET; a second DENFET coupled between the second terminal and the internal power supply; and a second pump switch coupled between the charge pump and a gate of the second DENFET.
H02M 3/07 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des résistances ou des capacités, p. ex. diviseur de tension utilisant des capacités chargées et déchargées alternativement par des dispositifs à semi-conducteurs avec électrode de commande
G06F 13/38 - Transfert d'informations, p. ex. sur un bus
