Abrégé

The present invention provides a monocrystalline silicon wafer and method of forming the wafer. The monocrystalline silicon wafer includes an upper surface and a first region located within a predefined distance from the upper surface, and the first region is free of self-interstitial defects. Semiconductor devices fabricated from such a monocrystalline silicon wafer free of self-interstitial defects will exhibit improved performance because of less leakage and a higher breakdown voltage. The method includes a thermal process for eliminating concentrated self-interstitial defects in the monocrystalline silicon wafer. The thermal process includes rapid thermal processing and/or prolonged thermal processing. That is, a monocrystalline silicon wafer free of self-interstitial defects can be obtained by performing the thermal process on the wafer, resulting in improved performance of semiconductor devices fabricated from the wafer.

Classes IPC  ?

• H10P 90/00 -
• H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
• H10D 62/83 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe IV, p. ex. Si dopé B ou Ge non dopé
• H10P 70/00 -

Abrégé

A silicon crystal, a silicon crystal defect treatment method, and a defect characterization method. The silicon crystal defect treatment method includes: providing a silicon crystal with self-interstitial defects; and executing a rapid heat treatment process on the silicon crystal, so as to at least eliminate self-interstitial defects within a preset distance from a surface of the silicon crystal. By means of executing a rapid heat treatment process on a silicon crystal, self-interstitial defects in the silicon crystal can be quickly and effectively reduced or even completely eliminated.

Classes IPC  ?

• C30B 33/02 - Traitement thermique
• C30B 29/06 - Silicium
• C30B 33/10 - Gravure dans des solutions ou des bains fondus

Abrégé

The present invention pertains to the field of semiconductors, and provides a method for determining whether a crystal orientation of a <111> ingot is in an optimal rotation angle region, and a method and a system for processing a <111> ingot. The method for processing a <111> ingot comprises: providing a <111> ingot, and acquiring an initial X crystal orientation deviation and an initial Y crystal orientation deviation of a crystal orientation of the ingot; determining whether the crystal orientation of the ingot is in an optimal rotation angle region; if the crystal orientation of the ingot is in the optimal rotation angle region, processing the ingot; and if the crystal orientation of the ingot is not in the optimal rotation angle region, adjusting an X-axis crystal orientation and a Y-axis crystal orientation of the ingot, such that the crystal orientation of the ingot falls within the optimal rotation angle region, and then processing the ingot. In the present invention, the crystal orientation of the ingot is rotated from a random rotation angle into an optimal rotation-angle range, thereby reducing the warp value of silicon wafers after slicing and maintaining the stability of the warp value.

Classes IPC  ?

• B24B 1/00 - Procédés de meulage ou de polissageUtilisation d'équipements auxiliaires en relation avec ces procédés
• B24B 7/16 - Machines ou dispositifs conçus pour une seule opération particulière pour meuler des faces d'extrémités de pièces, p. ex. de calibres, de rouleaux, d'écrous ou de segments de piston
• B24B 49/12 - Appareillage de mesure ou de calibrage pour la commande du mouvement d'avance de l'outil de meulage ou de la pièce à meulerAgencements de l'appareillage d'indication ou de mesure, p. ex. pour indiquer le début de l'opération de meulage impliquant des dispositifs optiques
• G06F 17/15 - Calcul de fonction de corrélation

Abrégé

A method for measuring BMDs in heavily doped P-type silicon wafers, a method and system for acquiring optimal heat treatment conditions for BMD growth in silicon wafers, and a computer-readable medium, relating to the field of semiconductors. The method for measuring BMDs in the heavily doped P-type silicon wafers comprises: providing a plurality of heavily doped P-type silicon wafers, and subjecting the silicon wafers to two-stage heat treatment under an oxygen-containing atmosphere, comprising: performing heat treatment at a first set temperature for a first set time, then heating to a second set temperature at a set heating rate, and performing heat treatment at the second set temperature for a second set time to grow BMDs in the silicon wafers; cleaning the silicon wafers in which the BMDs are grown; and measuring the silicon wafers to acquire the density and size of the BMDs of the silicon wafers. Relatively accurate quantification of the maximum BMD density that can be formed in silicon wafers is performed, so as to evaluate the characteristics of the heavily doped P-type silicon wafers, thereby providing guidance for subsequent processing steps.

Classes IPC  ?

• H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
• G01N 21/47 - Dispersion, c.-à-d. réflexion diffuse

Abrégé

A monocrystalline silicon ingot product, a monocrystalline growth device and a monocrystalline growth method. The monocrystalline growth device comprises a furnace, a crucible, a heater, an insulating support, a support rod, a short-circuit connecting block and a first driving apparatus, wherein the heater is divided into a heating region and a short-circuit region by the short-circuit connecting block. During crystal growth, the insulating support is driven by means of the first driving apparatus as the crucible moves upwards, such that the short-circuit connecting block slowly rises, so as to control the length of the heating region of the heater, thereby enhancing the ability to regulate and control the temperature gradient distribution of a growth interface, improving the uniformity of V/G at the growth interface, and promoting the growth of a high-quality monocrystalline silicon ingot product. In addition, the heating area of the heater is adjusted by means of regulating the length of the heating region of the heater, and thus an application process window of the heater is expanded, one heater can be applied to the production of a plurality of monocrystalline silicon ingot products having different oxygen contents; moreover, by means of the monocrystalline silicon growth method, the production of a monocrystalline silicon ingot product having a low oxygen content of 3 nppma to 20 nppma is realized.

Classes IPC  ?

• C30B 15/00 - Croissance des monocristaux par tirage hors d'un bain fondu, p. ex. méthode de Czochralski
• C30B 15/14 - Chauffage du bain fondu ou du matériau cristallisé
• C30B 15/20 - Commande ou régulation
• C30B 29/06 - Silicium

Abrégé

The present invention provides a crystal growing apparatus and a RF-SOI substrate for growing a crystal. The crystal growing apparatus may comprise: a crucible, a first superconducting coil and a second superconducting coil, a controller and a pulling-up mechanism. The first superconducting coil and the second superconducting coil, distributed outside the crucible, are opposite to each other to generate a magnetic field in the crucible. The controller controls the first superconducting coil generating the first current and controlling the second superconducting coil generating the second current, wherein a value of the first current is not equal to a value of the second current. The pulling-up mechanism pulls up to grow a single crystal in the magnetic field in the crucible, which is asymmetric magnetic field, based on the first current and the second current.

Classes IPC  ?

• C30B 30/04 - Production de monocristaux ou de matériaux polycristallins homogènes de structure déterminée, caractérisée par l'action de champs électriques ou magnétiques, de l'énergie ondulatoire ou d'autres conditions physiques spécifiques en utilisant des champs magnétiques
• C30B 15/20 - Commande ou régulation
• C30B 29/06 - Silicium
• H01F 6/06 - Bobines, p. ex. dispositions pour l'enroulement, l'isolation, les enveloppes ou les bornes des bobines
• H10D 86/00 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre

Abrégé

A support device for a crystal bar cutting machine, comprising: one or more support members (121, 221) for carrying a crystal bar; and a driving assembly for driving the one or more support members (121, 221) to ascend and descend, so that the height of each support member (121, 221) among the one or more support members (121, 221) matches the diameter of the portion of the crystal bar carried by each of the one or more support members (121, 221). In the device, a crystal bar does not displace after being cut off, and the cut-off crystal segments do not collide with adjacent crystal segments, so that the generation of edge breakage and cracks is avoided, thereby improving the product yield. The present invention also relates to a crystal bar cutting machine.

Classes IPC  ?

• B28D 7/04 - Accessoires spécialement conçus pour leur utilisation avec les machines ou les dispositifs des autres groupes de la présente sous-classe pour supporter ou maintenir les pièces travaillées
• B28D 5/04 - Travail mécanique des pierres fines, pierres précieuses, cristaux, p. ex. des matériaux pour semi-conducteursAppareillages ou dispositifs à cet effet par outils autres que ceux du type rotatif, p. ex. par des outils animés d'un mouvement alternatif

Abrégé

The present invention relates to the field of semiconductors, and provides a standard sheet and a manufacturing method therefor, a semiconductor material defect correction method, and a measurement device correction method. The semiconductor material defect correction method comprises: providing a standard sheet, and acquiring scattering signal intensities corresponding to standard particles of each size, so as to establish a functional relationship between the scattering signal intensities and the particle sizes; acquiring a scattering signal intensity of a defect particle of a semiconductor material, and acquiring a corrected size of the defect particle on the basis of the functional relationship; and acquiring a target size of the defect particle of the semiconductor material. In the present invention, a standard sheet having standard particles is manufactured, a functional relationship between scattering signal intensities and particle sizes is then established, and finally, a scattering signal intensity of a defect particle of a semiconductor material is acquired, and a corrected size of the defect particle is acquired on the basis of the functional relationship. Thus, the target size is compared with the corrected size for correction, thereby improving the accuracy of defect detection.

Classes IPC  ?

• G01N 21/93 - Étalons de détectionCalibrage

Abrégé

A grinding carrier assembly, a grinding apparatus, and a grinding method. The grinding carrier assembly (200) comprises a first carrier (210) and second carriers (220), wherein the first carrier (210) is provided with a first accommodating groove (211); and a plurality of second carriers (220) are detachably arranged in the first accommodating groove (211), and are arranged at equal intervals around the axis of the first accommodating groove (211), each of the second carriers (220) is provided with a second accommodating groove (221), and the second accommodating grooves (221) accommodate target objects. The grinding carrier assembly (200) is applied to the grinding apparatus. The grinding apparatus comprises a base, wherein the base is provided with a grinding region (101). A plurality of grinding carrier assemblies (200) are arranged at equal intervals around the axis of the grinding region (101), and the grinding carrier assemblies (200) can revolve around the axis of the grinding region (101). The number of the second carriers of the grinding carrier assembly is adjusted on the basis of the number of target objects to be ground, thereby improving the adaptability of the grinding apparatus, and reducing the adverse effect of disc deviation on the grinding quality.

Classes IPC  ?

• B24B 7/22 - Machines ou dispositifs pour meuler les surfaces planes des pièces, y compris ceux pour le polissage des surfaces planes en verreAccessoires à cet effet caractérisés par le fait qu'ils sont spécialement étudiés en fonction des propriétés de la matière des objets non métalliques à meuler pour meuler de la matière inorganique, p. ex. de la pierre, des céramiques, de la porcelaine
• B24B 41/00 - Éléments constitutifs des machines ou dispositifs à meuler, tels que bâtis, bancs, chariots ou poupées
• B24B 41/06 - Supports de pièces, p. ex. lunettes réglables
• B24B 1/00 - Procédés de meulage ou de polissageUtilisation d'équipements auxiliaires en relation avec ces procédés

Abrégé

The present invention provides characterization and evaluation methods for wafer warpage topography, and characterization and evaluation methods for ingot wire-cut topography. The characterization method for wafer warpage topography comprises: acquiring raw data of wafer warpage topography after ingot wire-cut; on the basis of the overall warpage topography of a wafer in the raw data, selecting warpage data of the wafer within first to third radius ranges in each of a plurality of radial directions, and respectively extracting graphic features of the warpage data within the first to third radius ranges to obtain corresponding first information codes, wherein the second radius range is located between the first radius range and the third radius range in the radial direction and located in the central area of the wafer; and sequentially combining the first information codes of the wafer within the first to third radius ranges in the same radial direction to obtain second information codes in corresponding radial directions, and sequentially combining the second information codes of the wafer in at least two radial directions to obtain third information codes of the wafer. The present invention can be used to visually represent warpage topography after ingot wire-cut and facilitate the identification and determination of the warpage topography of a wafer.

Classes IPC  ?

• B28D 5/00 - Travail mécanique des pierres fines, pierres précieuses, cristaux, p. ex. des matériaux pour semi-conducteursAppareillages ou dispositifs à cet effet
• G01B 21/20 - Dispositions pour la mesure ou leurs détails, où la technique de mesure n'est pas couverte par les autres groupes de la présente sous-classe, est non spécifiée ou est non significative pour mesurer des contours ou des courbes, p. ex. pour déterminer un profil
• G01B 11/24 - Dispositions pour la mesure caractérisées par l'utilisation de techniques optiques pour mesurer des contours ou des courbes
• B28D 5/04 - Travail mécanique des pierres fines, pierres précieuses, cristaux, p. ex. des matériaux pour semi-conducteursAppareillages ou dispositifs à cet effet par outils autres que ceux du type rotatif, p. ex. par des outils animés d'un mouvement alternatif

Abrégé

Provided in the present invention are a quartz support member, a semiconductor process chamber and a semiconductor process method. The quartz support member comprises a lens structure having a central lens and an annular lens, and a support structure, wherein the lens structure is placed on the support structure. In the present invention, by means of providing a wafer base on the quartz support member containing the lens structure, the lens structure containing the central lens and the annular lens is arranged to refract heating light, adjust annular uneven radiation heat distribution caused by a heating light tube, a reflective gold plate and a cavity structure, optimize the adjustment accuracy of heating uniformity, and improve the thickness of an epitaxial layer and the uniformity of resistivity obtained after a heating process. In addition, by means of providing the lens structure and the support structure as an integrally formed structure, floating dust particles introduced by the quartz support member are reduced, and the product yield is improved. Finally, by means of a support block and a quartz block which are adjustable in terms of stacking sequence, the height of the lens structure can be flexibly adjusted, thereby further improving the adjustment accuracy of the heating uniformity.

Classes IPC  ?

• H05B 3/00 - Chauffage par résistance ohmique
• H05B 3/02 - Chauffage par résistance ohmique Détails
• H01L 21/67 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants

Abrégé

A heater for a single crystal furnace and the single crystal furnace. The heater comprises: a plurality of heater units, the plurality of heater units being connected to form a cylindrical heating body; and a plurality of electrode pins, two adjacent heater units being physically connected by means of one electrode pin, and two ends of each heater unit being respectively and electrically connected to two electrode pins. The number of the electrode pins is an integer multiple of three, and the integer is greater than or equal to two; and the plurality of electrode pins are respectively and electrically connected to a three-phase alternating current of an alternating current power supply. By electrically connecting the electrode pins to the alternating current power supply, and assembling the plurality of heater units to form the heating body, the power efficiency of the power supply is improved, the operating current is reduced, and the stability of molten silicon is enhanced.

Classes IPC  ?

• C30B 15/14 - Chauffage du bain fondu ou du matériau cristallisé
• C30B 29/06 - Silicium

Abrégé

A silicon crystal, a silicon crystal defect treatment method, and a defect characterization method. The silicon crystal defect treatment method comprises: providing a silicon crystal, wherein the silicon crystal includes self-interstitial defects; and executing a rapid heat treatment process on the silicon crystal, so as to at least eliminate self-interstitial defects within a preset distance from a surface of the silicon crystal. By means of executing a rapid heat treatment process on a silicon crystal, self-interstitial defects in the silicon crystal can be quickly and effectively reduced or even completely eliminated.

Classes IPC  ?

• C30B 33/02 - Traitement thermique
• C30B 29/06 - Silicium
• C30B 33/10 - Gravure dans des solutions ou des bains fondus
• H01L 21/324 - Traitement thermique pour modifier les propriétés des corps semi-conducteurs, p. ex. recuit, frittage
• H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée
• G01N 21/95 - Recherche de la présence de criques, de défauts ou de souillures caractérisée par le matériau ou la forme de l'objet à analyser

Abrégé

The present invention provides a monocrystalline silicon wafer and a forming method therefor. The monocrystalline silicon wafer has an upper surface and a first area within a predetermined distance from the upper surface, and there is no self-interstitial defect in the first area. For a semiconductor device manufactured from the monocrystalline silicon wafer without a self-interstitial defect, the leakage current of the device is reduced and the breakdown voltage is increased, thereby improving the performance of the semiconductor device. Furthermore, the forming method for the monocrystalline silicon wafer eliminates the self-interstitial defect in the monocrystalline silicon wafer by means of a heat treatment process, and the heat treatment process comprises a rapid heat treatment process and/or a long-time heat treatment process. In other words, the monocrystalline silicon wafer without a self-interstitial defect can be obtained by means of the heat treatment process, improving the performance of the semiconductor device.

Classes IPC  ?

• C30B 33/02 - Traitement thermique
• C30B 29/06 - Silicium
• C30B 33/00 - Post-traitement des monocristaux ou des matériaux polycristallins homogènes de structure déterminée
• H01L 29/30 - Corps semi-conducteurs ayant des surfaces polies ou rugueuses
• H01L 21/324 - Traitement thermique pour modifier les propriétés des corps semi-conducteurs, p. ex. recuit, frittage

Abrégé

The present application provides a method and an apparatus for measuring ingot diameter, and a device for growing the ingot. The method comprises controlling a first calibration light source and a second calibration light source to emit light; obtaining coordinates of the calibration light sources; obtaining a diameter measurement coefficient based on the coordinates; obtaining diameter coordinates of two ends of the ingot diameter; and obtaining a measured value of the diameter based on the diameter coordinates and the diameter measurement coefficient. Accordingly, the measurement error of the ingot diameter can be reduced, and the accuracy of ingot diameter control during the growth process can be improved, thereby the production efficiency of Czochralski silicon ingot can be increased.

Classes IPC  ?

• C30B 15/26 - Stabilisation, ou commande de la forme, de la zone fondue au voisinage du cristal tiréCommande de la section du cristal en utilisant des détecteurs de télévisionStabilisation, ou commande de la forme, de la zone fondue au voisinage du cristal tiréCommande de la section du cristal en utilisant des détecteurs photographiques ou à rayons X
• C30B 29/06 - Silicium
• C30B 35/00 - Appareillages non prévus ailleurs, spécialement adaptés à la croissance, à la production ou au post-traitement de monocristaux ou de matériaux polycristallins homogènes de structure déterminée

Abrégé

Provided in the present invention is a magnetic control apparatus, comprising: a coil assembly, the coil assembly being sleeved on the outer side of a monocrystalline silicon device, and the coil assembly being movable in the axial direction of the monocrystalline silicon device. The coil assembly comprises a plurality of main coils, the plurality of main coils being arranged in the circumferential direction of the monocrystalline silicon device, and the component intensity of a magnetic field generated by the main coils in the radial direction of the monocrystalline silicon device being greater than the component intensity of same in the axial direction of the monocrystalline silicon device. By means of the configuration, the component intensity of said magnetic field in the radial direction of the monocrystalline silicon device is greater than the component intensity of same in the axial direction of the monocrystalline silicon device, so that the radial component intensity of the magnetic field is improved, thus effectively suppressing natural convection at the edge of a melt and flexibly controlling the content of impurities such as oxygen and carbon in crystals and radial uniformity. In addition, the coil assembly can move in the axial direction of the monocrystalline silicon device, thereby further improving the practicability and flexibility of the magnetic control apparatus.

Classes IPC  ?

• C30B 15/20 - Commande ou régulation
• H01F 7/06 - Électro-aimantsActionneurs comportant des électro-aimants

Abrégé

The present application provides a structure of HR-SOI embedded with a charge capture layer and manufacture thereof. The process for manufacturing a structure of HR-SOI embedded with a charge capture layer comprises: providing a first substrate, wherein the first substrate has a first surface to be subjected to a roughness treatment to form an uneven morphology on the first surface; forming a surface treatment layer, wherein the surface treatment layer has an uneven surface morphology; and forming a polysilicon layer on the surface treatment layer. By the roughness treatment to the first substrate, the first surface and the surface treatment layer both have uneven surface morphology, such that the formed polysilicon layer has stable orientation evolution and grain size, and an increased grain boundary density. Thereby a highly efficient charge trapping polysilicon film can be obtained.

Classes IPC  ?

• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
• H01L 21/762 - Régions diélectriques
• H01L 21/763 - Régions polycristallines semi-conductrices

Abrégé

The present application provides a structure of HR-SOI embedded with a charge capture layer and manufacture thereof. The process for manufacturing a structure of HR-SOI embedded with a charge capture layer comprises: providing a first substrate, wherein the first substrate has a first surface, and a pinning layer is formed on the first surface by a deposition process, and homogenizing the pinning layer surface by dry etching to adjust a thickness uniformity of the pinning layer. Accordingly, the thickness uniformity of the obtained polysilicon film is able to reach a good state.

Classes IPC  ?

• H01L 21/762 - Régions diélectriques
• H01L 21/3065 - Gravure par plasmaGravure au moyen d'ions réactifs
• H01L 21/324 - Traitement thermique pour modifier les propriétés des corps semi-conducteurs, p. ex. recuit, frittage
• H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant

Abrégé

The present invention provides a crystal growing method, an apparatus and a RF-SOI substrate for growing a crystal. The crystal growing method may comprise: controlling a first superconducting coil to generate a first current, and controlling a second superconducting coil to generate a second current, wherein a value of the first current is not equal to a value of the second current, the first superconducting coil and the second superconducting coil are superconducting coils positioned oppositely outside a crucible to generate a magnetic field in the crucible; and pulling upwards to grow a monocrystalline in an asymmetric magnetic field generated by the first current and the second current in the crucible.

Classes IPC  ?

• C30B 30/04 - Production de monocristaux ou de matériaux polycristallins homogènes de structure déterminée, caractérisée par l'action de champs électriques ou magnétiques, de l'énergie ondulatoire ou d'autres conditions physiques spécifiques en utilisant des champs magnétiques
• C30B 15/20 - Commande ou régulation
• C30B 29/06 - Silicium
• H01F 6/06 - Bobines, p. ex. dispositions pour l'enroulement, l'isolation, les enveloppes ou les bornes des bobines

Abrégé

The present invention discloses a method, apparatus, system and computer storage medium of controlling crystal growth. The method may comprise: obtaining a target piecewise curve of a heater power at different crystal lengths, a segment dividing point being positioned at an intersection point of adjacent segments of the target piecewise curve; based on the crystal lengths, interpolation calculating a value of the heater power at a length as a control value of the heater power; based on the control value of the heater power at different crystal lengths, obtaining a target control curve of the heater power, the target control curve of the heater power being smooth at the segment dividing point.

Classes IPC  ?

• C30B 15/20 - Commande ou régulation

Abrégé

The present application provides an epitaxy susceptor, an epitaxy growth apparatus and a manufacturing method of semiconductor device. The epitaxy susceptor comprises a pocket, wherein the pocket comprises plural lift-pin holes for setting lift-pins, and each lift-pin hole is surrounded by at least one auxiliary through hole penetrating the pocket. By setting plural auxiliary through holes with various diameters and/or various distributions surrounding the lift-pin holes in the pocket of the epitaxy susceptor, the physical properties near the lift-pin hole can be similar with that of auxiliary through holes, such that the abnormal thickness of the epitaxial film of the wafer at the site corresponding the lift-pin hole can be eliminated or reduced.

Classes IPC  ?

• C30B 25/12 - Porte-substrat ou supports
• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives

Abrégé

The present invention provides a method for determining the type of defects in a monocrystalline silicon wafer, which includes the steps of: using LST to measure particles in an as-grown silicon wafer and thereby obtaining a first measurement, and determining a V-rich region based on the first measurement and a first preset density value; and subjecting the silicon wafer to a thermal treatment, again using LST to measure particles in the silicon wafer and thereby obtaining a second measurement, and determining a Pv region, an I-rich region and a Pi region based on the second measurement, a second preset density value and a third preset density value. As a result, a particle density can be utilized as a basis for accurately and efficiently determining a region of interest of a monocrystalline silicon wafer as one of a V-rich region, a Pv region, a Pi region and an I-rich region.

Classes IPC  ?

• G01N 21/95 - Recherche de la présence de criques, de défauts ou de souillures caractérisée par le matériau ou la forme de l'objet à analyser
• G01N 21/49 - Dispersion, c.-à-d. réflexion diffuse dans un corps ou dans un fluide

Abrégé

A SOI wafer is disclosed. The SOI wafer may be characterized by surface roughness of a top silicon layer of the SOI wafer is less than 4 Å, thickness uniformity of the top silicon layer is within ±1%, and a total number of particles on a surface of the top silicon layer of the SOI wafer, measured with setting of 37 nm of SPx detection threshold, is less than 100.

Classes IPC  ?

• H01L 21/324 - Traitement thermique pour modifier les propriétés des corps semi-conducteurs, p. ex. recuit, frittage
• H01L 21/762 - Régions diélectriques

Abrégé

The present application provides a method for detecting temperature of thermal chamber comprising: conducting a thermal treatment at a predicted temperature to a selected silicon wafer within a thermal chamber, wherein the predicted temperature comprises plural temperature points set in order; obtaining a haze value corresponding to the predicted temperature; obtaining a linear relationship I between the temperature and the haze; polishing and washing the silicon wafer; conducting a thermal treatment at a predicted temperature to the polished silicon wafer within the thermal chamber; obtaining a linear relationship II between the temperature and the haze; calculating a difference of the haze at same temperature point between the two thermal treatments, and obtaining an actual temperature difference of the thermal chamber based on the difference of the haze. The present application increases efficiency and accuracy of temperature detection of the thermal chamber, reduce fluctuations caused by silicon wafer thickness and resistivity, increase utilization of silicon wafer, and reduce cost.

Classes IPC  ?

• H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
• G01K 3/10 - Thermomètres donnant une indication autre que la valeur instantanée de la température fournissant des différences de valeursThermomètres donnant une indication autre que la valeur instantanée de la température fournissant des valeurs différenciées par rapport au temps, p. ex. réagissant uniquement à une variation rapide de température
• G01K 11/00 - Mesure de la température basée sur les variations physiques ou chimiques, n'entrant pas dans les groupes , , ou

Abrégé

The present invention provides standard wafers, a method of making the same and a calibration method. The method of making a standard wafer comprise providing a silicon substrate having a first conductive type; forming a reverse epitaxy layer having a second conductive type; forming a target epitaxy layer having the first conductive type; measuring a measurement of a resistivity of the target epitaxy layer with four point probing, the measurement being utilized as a standard resistivity of the standard wafer. In the present invention, the method of making a standard wafer is low-cost and convenient because the standard wafer is made with electrical isolation formed with the reverse epitaxy layer positioned between the silicon substrate and the target epitaxy layer formed after forming the reverse epitaxy layer facilitates in presenting a resistivity of the target epitaxy layer greater than 50 ohm/cm at first and then utilizing the four point probing to measure the resistivity of the target epitaxy layer as the resistivity of the standard wafer.

Classes IPC  ?

• H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives

Abrégé

The present invention provides a method of growing a single-crystal silicon, comprising: loading a batch of polysilicon material in a crucible of a furnace, heating the crucible to melt the polysilicon material into a mass of silicon melt, confirming a liquid surface of the mass of silicon melt, applying a superconducting magnetic field to the mass of silicon melt with a magnetic field generator and adjusting a position of the magnetic field generator to position a maximum point of the superconducting magnetic field within a predetermined range under the liquid surface, and dipping a seed crystal into the silicon melt, and pulling the seed crystal during rotation of the seed crystal to crystallize the single crystal under the seed crystal until forming an ingot of single-crystal silicon. Oxygen content in the ingot is controlled through positioning the maximum point of the superconducting magnetic field under the liquid surface. According to the present invention, it is needless to change heat field, cost is low and success rate to pull the single crystal is high.

Classes IPC  ?

• C30B 15/20 - Commande ou régulation
• C30B 29/06 - Silicium
• C30B 30/04 - Production de monocristaux ou de matériaux polycristallins homogènes de structure déterminée, caractérisée par l'action de champs électriques ou magnétiques, de l'énergie ondulatoire ou d'autres conditions physiques spécifiques en utilisant des champs magnétiques

Abrégé

The present application provides a semiconductor substrate and a preparation process thereof. In the present application, the polysilicon layer includes the first polysilicon layer and the second polysilicon layer formed separately to generate the less stress, the more random grain orientation and the smaller grain size, maintain the high grain boundary density, and enhance the charge capture. By the combination of different deposition temperature and the combination of two cooling steps after each isothermal annealing treatment, the rate of contraction between the first polysilicon layer and the second polysilicon layer and the initial semiconductor substrate is decreased, and the thermal mismatch of semiconductor substrate is reduced. The stretch between the polysilicon layer and the initial semiconductor substrate can be reduced to prevent the warpage of the semiconductor substrate. Thereby, the stress generated during the growth process of the polysilicon layer can be further reduced.

Classes IPC  ?

• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives

Abrégé

A SOI wafer and a method of final processing the same is disclosed. Rapid thermal annealing comprises a first heating process in an atmosphere of a mixture of argon gas and hydrogen gas, volume of the hydrogen gas being less than 10% of whole volume of the mixture, and a first annealing process in an atmosphere of argon gas and optionally hydrogen gas, volume of the hydrogen gas being no greater than 10% of whole volume of the mixture. Long-time thermal annealing comprises a second heating process in an atmosphere of a mixture of argon gas and hydrogen gas, volume of the hydrogen gas being less than 10% of whole volume of the mixture, and a second annealing process in an atmosphere of argon gas and optionally hydrogen gas, volume of the hydrogen gas being no greater than 10% of whole volume of the mixture.

Classes IPC  ?

• H01L 21/324 - Traitement thermique pour modifier les propriétés des corps semi-conducteurs, p. ex. recuit, frittage
• H01L 21/762 - Régions diélectriques

Abrégé

The present application provides a method of surface treatment of a SOI wafer comprising: providing a SOI wafer comprising a substrate, atop silicon layer and an insulating buried layer, wherein the insulating buried layer is located between the back substrate and the top silicon layer, and the top silicon layer has a surface roughness of larger than 10 Å; removing a native oxide layer from a surface of the top silicon layer by conducting a first isothermal annealing process at a first target temperature, wherein the first isothermal annealing process is under atmosphere of a mixture of argon and hydrogen; and planarizing the surface of the top silicon layer by conducting a second isothermal annealing process at a second target temperature, wherein the second target temperature is higher than the first target temperature, and the second isothermal annealing process is under atmosphere of argon. The present method can optimize the atmosphere for batch annealing to achieve better planarization than the conventional technologies. Specifically, the obtained top silicon layer of the SOI wafer has a surface roughness of less than 4 Å.

Classes IPC  ?

• H01L 21/324 - Traitement thermique pour modifier les propriétés des corps semi-conducteurs, p. ex. recuit, frittage
• C30B 29/06 - Silicium
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices

Abrégé

A SOI structured semiconductor silicon wafer and a method of making the same is disclosed, comprising: loading a semiconductor silicon wafer in a first batch vertical furnace, and conducting a long-time thermal treatment; conducting a sacrificial oxidation process in a second batch vertical furnace after the long-time thermal treatment; conducting a rapid thermal annealing treatment after the second step ; wherein during the long-time thermal treatment, the semiconductor silicon wafer is kept in a protection atmosphere of pure , heated-up until meet a target temperature after changing the atmosphere of pure argon into a mixture gas of 1-n % Ar and n % H2, and then annealed in the atmosphere of a mixture of 1-n % Ar and n % hydrogen gas or pure Ar, and n is a value no greater than 10.

Classes IPC  ?

• H01L 21/324 - Traitement thermique pour modifier les propriétés des corps semi-conducteurs, p. ex. recuit, frittage
• H01L 21/762 - Régions diélectriques

Abrégé

−cm to rapidly and accurately determine conductivity type of the silicon wafer. Advantages of the method of the present application include accurate test results, easy operation, simple device requirement, and reduced cost.

Classes IPC  ?

• H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
• G01N 27/12 - Recherche ou analyse des matériaux par l'emploi de moyens électriques, électrochimiques ou magnétiques en recherchant l'impédance en recherchant la résistance d'un corps solide dépendant de l'absorption d'un fluideRecherche ou analyse des matériaux par l'emploi de moyens électriques, électrochimiques ou magnétiques en recherchant l'impédance en recherchant la résistance d'un corps solide dépendant de la réaction avec un fluide
• G01N 33/00 - Recherche ou analyse des matériaux par des méthodes spécifiques non couvertes par les groupes
• H01L 21/322 - Traitement des corps semi-conducteurs en utilisant des procédés ou des appareils non couverts par les groupes pour modifier leurs propriétés internes, p. ex. pour produire des défectuosités internes

Abrégé

The invention provides a measuring method of resistivity of a wafer, comprising: choosing a wafer to be measured, conducting a thermal treatment for the wafer to remove a thermal doner in the wafer, conducting an oxidation process for the wafer to form an oxidized surface on the wafer, and measuring resistivity of the wafer. In the method, firstly, the wafer is oxidized to get the oxidized surface, so as to restrict surface variation when placing the wafer in a later process. Therefore, the resistivity measurement of the wafer surface only slightly varies.

Classes IPC  ?

• H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
• G01R 27/02 - Mesure de résistances, de réactances, d'impédances réelles ou complexes, ou autres caractéristiques bipolaires qui en dérivent, p. ex. constante de temps

Abrégé

The invention provides a method of detecting crystallographic defects, comprising: sampling wafer of an ingot in complying with a predetermined wafer sampling frequency; identifying crystallographic defects of the wafer to show the crystallographic defects of the wafer; characterizing observation of the crystallographic defects of the wafer and extracting a value characterizing the crystallographic defects; through a result of characterizing the crystallographic defects, obtaining a radial distribution of density of the wafer and categorizing the crystallographic defects; and obtaining an isogram of the crystallographic defects of the wafer to show a crystallographic defect distribution of the whole ingot according to the value characterizing the crystallographic defects and categories of the crystallographic defects. It is no need to break the ingot to obtain the crystallographic defect distribution of the whole ingot, through which the technology for growing the ingot may be effectively adjusted to obtain the ingot with required characteristics of defect.

Classes IPC  ?

• G01N 21/95 - Recherche de la présence de criques, de défauts ou de souillures caractérisée par le matériau ou la forme de l'objet à analyser
• C30B 15/20 - Commande ou régulation
• C30B 29/06 - Silicium
• G01N 33/00 - Recherche ou analyse des matériaux par des méthodes spécifiques non couvertes par les groupes

Abrégé

The present application provides a method for characterizing defects in silicon crystal comprising the following steps: etching a surface of the silicon crystal to remove a predicted thickness of the silicon crystal; conducting a LLS scanning to a surface of the etched silicon crystal to obtain a LLS map of the surface, a LSE size of defects, and defect bulk density; based on at least one of the LLS map of the surface, the LSE size of defects and the defect bulk density, determining a type of defect existing in the silicon crystal and/or a defect zone of each type of defect on the surface. By applying the method, the characterizing period and the characterizing cost can be reduced, plural defects such as vacancy, oxygen precipitate and dislocation can be characterized simultaneously, the characterizing accuracy can be enhanced, and the defect type and the defect zone can be determined with high reliability. In addition, the method can be applied to all crystal defect types, is easy to operate, and is an environmentally friendly method for determination of grown-in defects.

Classes IPC  ?

• C30B 29/06 - Silicium
• G01N 21/956 - Inspection de motifs sur la surface d'objets
• G01N 21/88 - Recherche de la présence de criques, de défauts ou de souillures

Abrégé

A semiconductor crystal growth method and device are provided. The method comprises: obtaining an initial position of a graphite crucible when used in a semiconductor crystal growth process for the first time; obtaining a current production batch of the graphite crucible which characterizes a number of times of growth processes performed by the graphite crucible so far; and loading polysilicon raw materials into a quartz crucible sleeved in the graphite crucible based on the current production batch, wherein a total weight of the materials is called a charging amount, and the charging amount is adjusted based on the current production batch to keep an initial position of a silicon melt liquid surface in the quartz crucible stable while keeping the initial position of the graphite crucible unchanged. The present invention ensures the stability of each parameter in the crystal pulling process, and enhances the crystal pulling speed and quality.

Classes IPC  ?

• C30B 15/14 - Chauffage du bain fondu ou du matériau cristallisé
• C30B 15/10 - Creusets ou récipients pour soutenir le bain fondu
• C30B 15/20 - Commande ou régulation
• C30B 29/06 - Silicium

Abrégé

The present application provides a detection method of metal impurity in wafer. The method comprises conducting a medium temperature thermal treatment for a first predicted time period to the wafer, cooling the wafer and conducting a low temperature thermal treatment for a second predicted time period, cooling the wafer to ambient temperature; providing a liquid of vapor phase decomposition on the wafer to collect metal impurities; atomizing the liquid containing the collected metal impurities, conducting an inductively coupled plasma mass spectrometry analysis and obtaining concentrations of the metal impurities. The present application applies the combination of various thermal treatment without an interrupt of cooling to ambient temperature to contemplate diffusions of various metal impurities to the wafer surface. Accordingly, the detection of metal impurities can be conducted with reduced time cost and enhanced efficiency.

Classes IPC  ?

• H01L 21/225 - Diffusion des impuretés, p. ex. des matériaux de dopage, des matériaux pour électrodes, à l'intérieur ou hors du corps semi-conducteur, ou entre les régions semi-conductricesRedistribution des impuretés, p. ex. sans introduction ou sans élimination de matériau dopant supplémentaire en utilisant la diffusion dans ou hors d'un solide, à partir d'une ou en phase solide, p. ex. une couche d'oxyde dopée
• H01J 49/00 - Spectromètres pour particules ou tubes séparateurs de particules
• H01J 49/10 - Sources d'ionsCanons à ions
• H01L 21/66 - Test ou mesure durant la fabrication ou le traitement

Abrégé

The present invention provides a method of making a silicon on insulator (SOI) structure, comprising steps of: providing a bonded structure, the bonded structure comprises a first substrate, a second substrate and an insulating buried layer, the insulating buried layer is positioned between the first substrate and the second substrate; peeling off a layer of removing region of the first substrate from the bonded structure to obtain a SOI structure; and processing the SOI structure with isothermal annealing technology at a pressure which is lower than atmospheric pressure.

Classes IPC  ?

• H01L 21/762 - Régions diélectriques
• H01L 21/322 - Traitement des corps semi-conducteurs en utilisant des procédés ou des appareils non couverts par les groupes pour modifier leurs propriétés internes, p. ex. pour produire des défectuosités internes

Abrégé

A method of making a silicon on insulator structure comprises: providing a bonded structure, the bonded structure comprises the first substrate, the second substrate and the insulating buried layer, the insulating buried layer is positioned between the first substrate and the second substrate; peeling off a layer of removing region of the first substrate from the bonded structure to obtain a first film; at a first temperature, performing a first etching to etch the first film to remove a first thickness of the first film; at a second temperature, performing a second etching to etch the first film to planarize the first film and remove a second thickness of the first film, the first temperature being lower than the second temperature, the first thickness being greater than the second thickness, and a sum of the first thickness and the second thickness being a total etching thickness of the first film.

Classes IPC  ?

• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
• H01L 21/306 - Traitement chimique ou électrique, p. ex. gravure électrolytique
• H01L 21/762 - Régions diélectriques

Abrégé

The present invention provides a method for calculating the liquid-solid interface morphology during growth of the ingot. The method comprises providing a wafer, selecting plural sampling locations on the wafer and detecting electrical resistivity at the plural sampling locations, calculating height differences between the sampling locations based on the detected electrical resistivity, and illustrating the morphology of the liquid-solid interface based on the calculated height differences. The method of the invention has advantages including easy operation and low cost.

Classes IPC  ?

• C30B 15/22 - Stabilisation, ou commande de la forme, de la zone fondue au voisinage du cristal tiréCommande de la section du cristal
• G01N 27/04 - Recherche ou analyse des matériaux par l'emploi de moyens électriques, électrochimiques ou magnétiques en recherchant l'impédance en recherchant la résistance

Abrégé

The present invention provides a method and an apparatus of monocrystal growth. The method comprises providing an apparatus comprising a crucible, a first lifting device for lifting the crucible, a deflector tube and a second lifting device for lifting the deflector tube; setting a theoretical distance between the deflector tube and the melt surface, determining a theoretical ratio of the crucible lifting rate relative to the monocrystal lifting rate based on sizes of the crucible and the monocrystal, and starting to grow the monocrystal. During the growth, the position of one or more of the crucible, the deflector tube and the monocrystal is adjusted, the actual distance between the deflector tube and the melt surface is real-time detected, the deviation value between the theoretical and the actual distances is calculated, a variation of the ratio is obtained by the deviation value, and the theoretical ratio is adjusted based on the variation. Based on the variation of the ratio of the crucible lifting rate relative to the monocrystal lifting rate, the speeds of the lifting devices are adjusted to maintain the process lifting rate during the crystal growth without change. The process lifting rate is the lifting rate of the monocrystal ingot relative to the melt surface. The present invention can facilitate to produce the monocrystal with high quality.

Classes IPC  ?

• C30B 15/20 - Commande ou régulation
• C30B 15/14 - Chauffage du bain fondu ou du matériau cristallisé

Abrégé

A seeding method for crystal growth comprising: a first seeding step: rotating a crucible with a first rotation speed to grow the crystal to a first length; a second seeding step: gradually increasing the rotation speed of the crucible from the first rotation speed to a second rotation speed, and growing the crystal to a second length; a third seeding step: rotating the crucible with the second rotation speed to growing the crystal to a predicted length. By separating the seeding stage to three steps and gradually increasing the rotation speed in the second step of the crucible, the silicon melt convection is enhanced and the temperature at center of the silicon melt is kept to be not lower than the starting temperature of the seeding. Thereby, the removal of dislocation within the seed crystal can be increased, and the growth problems such as broken or polycrystallization can be prevented.

Classes IPC  ?

• C30B 15/20 - Commande ou régulation
• C30B 15/30 - Mécanismes pour faire tourner ou pour déplacer soit le bain fondu, soit le cristal
• C30B 15/10 - Creusets ou récipients pour soutenir le bain fondu

Abrégé

The present application provides a method for detecting temperature of thermal chamber comprising: conducting a thermal treatment at a predicted temperature to a selected silicon wafer within a thermal chamber, wherein the predicted temperature comprises plural temperature points set in order; obtaining a haze value corresponding to the predicted temperature; obtaining a linear relationship I between the temperature and the haze; polishing and washing the silicon wafer; conducting a thermal treatment at a predicted temperature to the polished silicon wafer within the thermal chamber; obtaining a linear relationship II between the temperature and the haze; calculating a difference of the haze at same temperature point between the two thermal treatments, and obtaining an actual temperature difference of the thermal chamber based on the difference of the haze. The present application increases efficiency and accuracy of temperature detection of the thermal chamber, reduce fluctuations caused by silicon wafer thickness and resistivity, increase utilization of silicon wafer, and reduce cost.

Classes IPC  ?

• H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
• G01K 3/10 - Thermomètres donnant une indication autre que la valeur instantanée de la température fournissant des différences de valeursThermomètres donnant une indication autre que la valeur instantanée de la température fournissant des valeurs différenciées par rapport au temps, p. ex. réagissant uniquement à une variation rapide de température
• G01K 11/00 - Mesure de la température basée sur les variations physiques ou chimiques, n'entrant pas dans les groupes , , ou

Abrégé

The present invention provides a semiconductor crystal growth device, comprising: a furnace body; a crucible disposed inside the furnace body for containing a silicon melt; a pulling unit disposed at a top portion of the furnace body for pulling out a silicon ingot from the silicon melt; and a heat shield unit including a flow tube that is barrel-shaped and disposed around the silicon ingot for rectifying argon gas input from the top portion of the furnace body and adjusting thermal field distribution between the silicon ingot and the silicon melt liquid surface, wherein, the heat shield unit further includes an adjustment unit disposed at a lower end inside the flow tube for adjusting a minimum distance between the heat shield unit and the silicon ingot. According to the present invention, by providing the adjustment unit at the lower end inside the flow tube, it is possible to adjust the distance between the silicon ingot and the adjacent heat shield unit and thereby boost the crystal growth speed and quality, without changing the shape and position of the flow tube.

Classes IPC  ?

• C30B 15/14 - Chauffage du bain fondu ou du matériau cristallisé
• C30B 15/00 - Croissance des monocristaux par tirage hors d'un bain fondu, p. ex. méthode de Czochralski
• C30B 29/06 - Silicium

Abrégé

The present invention provides a polishing pad, a polishing apparatus and a polishing method for a silicon wafer. The polishing pad comprises a polishing surface in contact with the silicon wafer. The polishing surface is provided with at least one groove. When polishing the silicon wafer, the edge of the silicon wafer is at least partially suspended above the groove. The polishing pad, polishing apparatus and silicon wafer polishing method according to the present invention can reduce the polishing rate at the edge of the silicon wafer while keeping the polishing rate of the entire wafer basically unchanged, thereby improving the flatness of the edge thickness of the silicon wafer as well as improving the production yield.

Classes IPC  ?

• B24B 37/04 - Machines ou dispositifs de rodageAccessoires conçus pour travailler les surfaces planes
• H01L 21/306 - Traitement chimique ou électrique, p. ex. gravure électrolytique
• B24B 37/26 - Tampons de rodage pour travailler les surfaces planes caractérisés par la forme ou le profil de la surface du tampon de rodage, p. ex. rainurée

Abrégé

The present application provides an apparatus and a method for ingot growth. The apparatus for ingot growth comprises a growth furnace, a crucible, a heater, a lifting mechanism, an infrared detector, a dividing disc, a sensor and a control device. The crucible is located within the growth furnace. The lifting mechanism comprises a lifting wire and a driving device, wherein the lifting wire connects to the top of the ingot via one terminal and to the driving device via another terminal. The bottom of the ingot puts inside the crucible, and the ingot has plural crystal lines thereon. The infrared detector is located outside the growth furnace. The dividing disc is above the growth furnace, connects to the lifting mechanism, and rotates with the ingot synchronously under the driving of the lifting mechanism, and an orthographic projection of bisector of the dividing disc is between two adjacent crystal lines. The sensor is located on the periphery of the dividing disc. The control device connects to the infrared detector and the sensor in order to control the infrared detector to detect the ingot diameter while the sensor senses the bisector of the dividing disc. The present application is able to increase ingot quality and enhance product yield.

Classes IPC  ?

• C30B 15/30 - Mécanismes pour faire tourner ou pour déplacer soit le bain fondu, soit le cristal
• C30B 15/14 - Chauffage du bain fondu ou du matériau cristallisé
• C30B 15/20 - Commande ou régulation
• C30B 29/06 - Silicium

Abrégé

Disclosed a heat shield structure for a single crystal production furnace, which is provided above a melt crucible of a single crystal production furnace and comprises an outer housing and a heat insulation plate disposed within the outer housing. A bottom outer surface of the outer housing faces an interior of the melt crucible, and an angle formed between a plane in which the heat insulation plate is located and a plane in which a bottom of the outer housing is located is an acute angle and faces an outer surface of single crystal silicon. The heat shield design is changed, a heat absorbing plate is additionally provided for transferring heat absorbed to the single crystal silicon, a heat channel is formed in the heat shield, so that a pulling rate is controlled, which improves radial mass uniformity of the single crystal silicon.

Classes IPC  ?

• C30B 15/14 - Chauffage du bain fondu ou du matériau cristallisé
• C30B 15/10 - Creusets ou récipients pour soutenir le bain fondu
• C30B 29/06 - Silicium

Abrégé

The invention provides a method for positioning a wafer and a semiconductor manufacturing apparatus, which are applied to thin film processes. The method includes: Step S1: Obtain the state distribution of the first surface of the first wafer after the thin film process is performed on the first wafer, wherein the first surface is the surface opposite to a surface that the thin film formed thereon in the thin film process; Step S2: Determine whether the first wafer is located at the ideal positioning center according to the state distribution of the first surface, when the first wafer is not located at the ideal positioning center, according to the state distribution of the first surface adjusts the positioning position of the second wafer to be subjected to the thin film process, so that the second wafer is positioned at the ideal positioning center during the thin film process. According to the present invention, the wafer is positioned at the ideal positioning center during the thin film process, thereby improving the quality of the thin film layer and the entire wafer (epitaxial wafer) after the thin film process, and improving the effect of the thin film process.

Classes IPC  ?

• G06T 7/77 - Détermination de la position ou de l'orientation des objets ou des caméras utilisant des procédés statistiques
• H01L 21/67 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants
• H01L 21/68 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le positionnement, l'orientation ou l'alignement
• H01L 21/66 - Test ou mesure durant la fabrication ou le traitement

Abrégé

The invention provides a semiconductor crystal growth device comprising a furnace body; a crucible; a pulling device; a horizontal magnetic field applying device; and a deflector, being barrel-shaped and disposed above the silicon melt in the furnace body in a vertical direction, and the pulling device pulls the silicon ingot through the deflector in the vertical direction; wherein the bottom of the deflector has different thermal reflection coefficients at different positions, and the thermal reflection coefficient of the bottom of the deflector in the direction of the horizontal magnetic field is smaller than that in the direction perpendicular to the horizontal magnetic field. According to the semiconductor crystal growth device of the present invention, the temperature distribution inside the melt silicon and quality of the semiconductor crystal are improved.

Classes IPC  ?

• C30B 15/22 - Stabilisation, ou commande de la forme, de la zone fondue au voisinage du cristal tiréCommande de la section du cristal
• C30B 29/06 - Silicium
• C30B 15/10 - Creusets ou récipients pour soutenir le bain fondu

Abrégé

The present invention provides a semiconductor crystal growth method and apparatus. The semiconductor crystal growth method comprises: obtaining an initial position CP0 of a graphite crucible when being used in a semiconductor crystal growth process for the first time; obtaining the current production batch N of the graphite crucible, wherein the current production bath N represents the number of times that the graphite crucible currently is used in the semiconductor crystal growth process; and according to the current production batch N, filling a polysilicon raw material in a quartz crucible embedded in the graphite crucible, wherein the total weight of the polysilicon raw material is a loading amount W(N), and the loading amount W(N) is adjusted according to the current production batch N, so that the initial position of a silicon melt liquid level in the quartz crucible remains stable while the initial position CP0 of the graphite crucible remains unchanged. Therefore, the present invention ensures the stability of each parameter in a crystal pulling process, enhances a crystal pulling speed, and improves the quality of crystal pulling.

Classes IPC  ?

• C30B 15/22 - Stabilisation, ou commande de la forme, de la zone fondue au voisinage du cristal tiréCommande de la section du cristal
• C30B 29/06 - Silicium

Abrégé

Disclosed is a semiconductor crystal growth device comprising: a furnace (1), a crucible (11), the crucible (11) is disposed inside the furnace (1) and configured to contain a silicon melt (13); a drawing unit (14), the drawing unit (14) is disposed at a top portion of the furnace (1) and configured to draw a silicon ingot (10) out of the silicon melt (13); and a heat shield unit. The heat shield unit comprises a draft tube (16), the draft tube (16) is barrel-like and disposed peripherally around the silicon ingot (10), and is configured to regulate a flow of an argon gas drawn from a top portion of the furnace (1) and to adjust a thermal field distribution between the silicon ingot (10) and a liquid surface of the silicon melt (13). The heat shield unit also comprises an adjustment unit (17) disposed at an inner side of a lower end of the draft tube (16) and configured to adjust a minimum distance (Drc) between the heat shield unit and the silicon ingot (10). The disposition of the adjustment unit (17) at an inner side of a lower end of the draft tube (16) enables increased crystal growth speed and quality by adjusting the distance (Drc) between the silicon ingot (10) and the adjacent heat shield unit, without altering a shape and a position of the draft tube (16).

Classes IPC  ?

• C30B 15/20 - Commande ou régulation
• C30B 29/06 - Silicium

Abrégé

A complementary metal-oxide-semiconductor field-effect transistor comprises a semiconductor substrate, N-type and P-type field-effect transistors positioned in the semiconductor substrate. Each of the field-effect transistors includes a germanium nanowire, a III-V compound layer surrounding the germanium nanowire, a potential barrier layer mounted on the III-V compound layer, a gate dielectric layer, a gate, a source region and a drain region mounted on two sides of the gate. The field-effect transistor can produce two-dimensional electron gases and two-dimensional electron hole gases, and enhance the carrier mobility of the complementary metal-oxide-semiconductor field-effect transistor.

Classes IPC  ?

• H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
• H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/786 - Transistors à couche mince
• H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives

Abrégé

The present invention relates to a method for preparing vacuum tube flash memory structure, to form a vacuum channel in the flash memory, and using oxide-nitride-oxide (ONO) composite materials as gate dielectric layer, wherein the nitride layer serves as a charge-trap layer to provide a blocking insulating between the gate electrode and the vacuum channel. The present structure exhibits superior program and erase speed as well as the retention time. It also provide with excellent gate controllability and negligible gate leakage current due to adoption ONO as the gate dielectric layer.

Classes IPC  ?

• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
• H01L 21/324 - Traitement thermique pour modifier les propriétés des corps semi-conducteurs, p. ex. recuit, frittage
• H01L 27/11568 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par la région noyau de mémoire
• H01L 29/792 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à isolant de grille à emmagasinage de charges, p.ex. transistor de mémoire MNOS

Abrégé

The present invention relates to a thermal processing method for wafer. A wafer is placed in an environment filled with a gas mixture comprising oxygen gas and deuterium gas, and a rapid thermal processing process is performed on a surface of the wafer. As a result, a denuded zone is formed on the surface of the wafer, deuterium atoms, which may be released to improve characteristics at an interface of semiconductor devices in a later fabrication process, are held in the wafer, and bulk micro-defects are formed far from the semiconductor devices.

Classes IPC  ?

• H01L 21/322 - Traitement des corps semi-conducteurs en utilisant des procédés ou des appareils non couverts par les groupes pour modifier leurs propriétés internes, p. ex. pour produire des défectuosités internes

Abrégé

This invention application provides a method for manufacturing a SOI substrate, and the method comprising: providing a first semiconductor substrate; growing a first insulating layer on a top surface of the first semiconductor substrate for forming a first wafer; irradiating the first semiconductor substrate via a ion beam for forming a doping layer to a pre-determined depth from a top surface of the first insulating layer; providing a second substrate; growing a second insulating layer on a top surface of the second semiconductor substrate for forming a second wafer; bonding the first wafer with the second wafer; annealing the first wafer and second wafer at a deuterium atmosphere; separating a part of the first wafer from the second wafer; and forming a deuterium doped layer on the second wafer.

Classes IPC  ?

• H01L 21/762 - Régions diélectriques
• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
• H01L 29/34 - Corps semi-conducteurs ayant des surfaces polies ou rugueuses les défectuosités étant sur la surface

Abrégé

This invention provides a method for growing monocrystalline silicon by applying Czochralski method comprising forming a melt of silicon-containing materials in a crucible and pulling the melt for monocrystalline silicon growth, which is characterized by, the silicon-containing materials comprising a deuterium-implanted nitride-deposited silicon and a monocrystalline silicon, introducing a gas containing argon during formation of the melt, and, applying a magnetic field during the pulling step. This invention also provides a method for producing a wafer based on the above monocrystalline silicon.

Classes IPC  ?

• C30B 29/06 - Silicium
• C30B 15/00 - Croissance des monocristaux par tirage hors d'un bain fondu, p. ex. méthode de Czochralski
• C30B 15/20 - Commande ou régulation
• C30B 30/04 - Production de monocristaux ou de matériaux polycristallins homogènes de structure déterminée, caractérisée par l'action de champs électriques ou magnétiques, de l'énergie ondulatoire ou d'autres conditions physiques spécifiques en utilisant des champs magnétiques

Abrégé

The present invention relates to a method for preparing vacuum tube flash memory structure, to form a vacuum channel in the flash memory, and using oxide-nitride-oxide (ONO) composite materials as gate dielectric layer, wherein the nitride layer serves as a charge-trap layer to provide a blocking insulating between the gate electrode and the vacuum channel. The present structure exhibits superior program and erase speed as well as the retention time. It also provide with excellent gate controllability and negligible gate leakage current due to adoption ONO as the gate dielectric layer.

Classes IPC  ?

• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 27/11568 - Mémoires mortes programmables électriquement; Procédés de fabrication à étapes multiples de ces dispositifs avec isolateurs de grille à piégeage de charge, p.ex. MNOS ou NROM caractérisées par la région noyau de mémoire
• H01L 29/792 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à isolant de grille à emmagasinage de charges, p.ex. transistor de mémoire MNOS
• H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
• H01L 21/324 - Traitement thermique pour modifier les propriétés des corps semi-conducteurs, p. ex. recuit, frittage

Abrégé

The present invention relates to a thermal processing method for wafer. A wafer is placed in an environment filled with a non-oxygenated gas mixture comprising deuterium gas and at least one kind of low active gas, and a rapid heating processing process is performed on a surface of the wafer to heat the wafer to a predetermined high temperature. Then, the wafer is placed in an environment filled with an oxygenated gas mixture, and a rapid cooling processing process is performed on a surface of the wafer. As a result, a denuded zone is formed on the surface of the wafer, deuterium atoms, which may be released to improve characteristics at an interface of semiconductor devices in a later fabrication process, are held in the wafer, and bulk micro-defects are formed far from the semiconductor devices.

Classes IPC  ?

• H01L 21/322 - Traitement des corps semi-conducteurs en utilisant des procédés ou des appareils non couverts par les groupes pour modifier leurs propriétés internes, p. ex. pour produire des défectuosités internes
• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives

Abrégé

This invention provides a method for growing monocrystalline silicon by applying Czochralski method comprising forming a melt of silicon-containing materials in a crucible and pulling the melt for monocrystalline silicon growth, which is characterized by, introducing a gas containing argon during formation of the melt, and, applying a magnetic field during the pulling step. This invention also provides a method for producing a wafer based on the above monocrystalline silicon.

Classes IPC  ?

• B24B 7/22 - Machines ou dispositifs pour meuler les surfaces planes des pièces, y compris ceux pour le polissage des surfaces planes en verreAccessoires à cet effet caractérisés par le fait qu'ils sont spécialement étudiés en fonction des propriétés de la matière des objets non métalliques à meuler pour meuler de la matière inorganique, p. ex. de la pierre, des céramiques, de la porcelaine
• C30B 15/22 - Stabilisation, ou commande de la forme, de la zone fondue au voisinage du cristal tiréCommande de la section du cristal
• B24B 9/06 - Machines ou dispositifs pour meuler les bords ou les biseaux des pièces ou pour enlever des bavuresAccessoires à cet effet caractérisés par le fait qu'ils sont spécialement étudiés en fonction des propriétés de la matière propre aux objets à meuler de matière inorganique non métallique, p. ex. de la pierre, des céramiques, de la porcelaine
• C30B 15/04 - Croissance des monocristaux par tirage hors d'un bain fondu, p. ex. méthode de Czochralski en introduisant dans le matériau fondu le matériau à cristalliser ou les réactifs le formant in situ avec addition d'un matériau de dopage, p. ex. pour une jonction n–p
• C30B 15/20 - Commande ou régulation
• C30B 29/06 - Silicium
• C30B 30/04 - Production de monocristaux ou de matériaux polycristallins homogènes de structure déterminée, caractérisée par l'action de champs électriques ou magnétiques, de l'énergie ondulatoire ou d'autres conditions physiques spécifiques en utilisant des champs magnétiques
• C30B 33/00 - Post-traitement des monocristaux ou des matériaux polycristallins homogènes de structure déterminée

Abrégé

Present embodiments provide for a complementary nanowire semiconductor device and fabrication method thereof. The fabrication method comprises providing a substrate, wherein the substrate has a NMOS active region, a PMOS active region and a shallow trench isolation (STI) region; forming a plurality of first hexagonal epitaxial wires on the NMOS active region and the PMOS active region by selective epitaxially growing a germanium (Ge) crystal material; selectively etching the substrate to suspend the pluralities of first hexagonal epitaxial wires on the substrate; forming a plurality of second hexagonal epitaxial wires on the NMOS active region by selective epitaxially growing a III-V semiconductor crystal material surrounding the pluralities of first hexagonal epitaxial wires on the NMOS active region; depositing a dielectric material on the pluralities of first hexagonal epitaxial wires and the pluralities of second hexagonal epitaxial wires, wherein the dielectric material covers the pluralities of first hexagonal epitaxial wires and the pluralities of second hexagonal epitaxial wires; and depositing a conducting material on the dielectric material for forming a gate electrode surrounding the pluralities of first hexagonal epitaxial wires and the pluralities of second hexagonal epitaxial wires, wherein the pluralities of first hexagonal epitaxial wires are a plurality of first nanowires and the pluralities of second hexagonal epitaxial wires are a plurality of second nanowires.

Classes IPC  ?

• H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant
• H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
• H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/786 - Transistors à couche mince
• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives

Abrégé

Present embodiments provide for a FinFET and fabrication method thereof. The fabrication method includes two selective etching processes to form the channel. The FinFET includes a substrate, a shallow trench isolation (STI) layer, a buffer layer, a III-V group material, an oxide-isolation layer, a high-K dielectric layer and a conductor material. The STI is formed on the substrate with a trench. The buffer layer is formed on the substrate in the trench. The III-V group material is formed on the buffer layer in vertical stacked bowl shape. The oxide-isolation layer is formed between the substrate and the III-V group material. The high-K dielectric layer is formed on the STI layer and surrounding the III-V group material. The conductor material is formed surrounding the high-K dielectric layer.

Classes IPC  ?

• H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 29/51 - Matériaux isolants associés à ces électrodes
• H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes

Abrégé

Present embodiments provide for a complementary nanowire semiconductor device and fabrication method thereof. The fabrication method comprises providing a substrate, wherein the substrate has a NMOS active region, a PMOS active region and a shallow trench isolation (STI) region; forming a plurality of first hexagonal epitaxial wires on the NMOS active region and the PMOS active region by selective epitaxially growing a germanium (Ge) crystal material; selectively etching the substrate to suspend the pluralities of first hexagonal epitaxial wires on the substrate; forming a plurality of second hexagonal epitaxial wires on the NMOS active region by selective epitaxially growing a III-V semiconductor crystal material surrounding the pluralities of first hexagonal epitaxial wires on the NMOS active region; depositing a dielectric material on the pluralities of first hexagonal epitaxial wires and the pluralities of second hexagonal epitaxial wires, wherein the dielectric material covers the pluralities of first hexagonal epitaxial wires and the pluralities of second hexagonal epitaxial wires; and depositing a conducting material on the dielectric material for forming a gate electrode surrounding the pluralities of first hexagonal epitaxial wires and the pluralities of second hexagonal epitaxial wires, wherein the pluralities of first hexagonal epitaxial wires are a plurality of first nanowires and the pluralities of second hexagonal epitaxial wires are a plurality of second nanowires.

Classes IPC  ?

• H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant
• H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
• H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/786 - Transistors à couche mince

Abrégé

The present invention application provides a method for manufacturing a SOI substrate, and the method comprising: providing a first semiconductor substrate; growing a first insulating layer on a top surface of the first semiconductor substrate for forming a first wafer; implanting a deuterium and hydrogen co-doping layer at a certain pre-determined depth of the first wafer; providing a second substrate; growing a second insulating layer on a top surface of the second semiconductor substrate for forming a second wafer; bonding the first wafer with the second wafer; annealing the first wafer and second wafer; separating a part of the first wafer from the second wafer; and forming a deuterium and hydrogen co-doping semiconductor layer on the second wafer.

Classes IPC  ?

• H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant
• H01L 21/762 - Régions diélectriques
• H01L 21/265 - Bombardement par des radiations ondulatoires ou corpusculaires par des radiations d'énergie élevée produisant une implantation d'ions
• H01L 21/324 - Traitement thermique pour modifier les propriétés des corps semi-conducteurs, p. ex. recuit, frittage
• H01L 21/84 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant autre chose qu'un corps semi-conducteur, p.ex. étant un corps isolant
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/167 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée caractérisés en outre par le matériau de dopage
• H01L 29/207 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV caractérisés en outre par le matériau de dopage
• H01L 29/227 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIBVI caractérisés en outre par le matériau de dopage

Abrégé

The present invention provides a method of manufacturing nanowire semiconductor device. In the active region of the PMOS the first nanowire is formed with high hole mobility and in the active region of the NMOS the second nanowire is formed with high electron mobility to achieve the objective of improving the performance of nanowire semiconductor device.

Classes IPC  ?

• H01L 21/283 - Dépôt de matériaux conducteurs ou isolants pour les électrodes
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
• H01L 29/51 - Matériaux isolants associés à ces électrodes
• H01L 29/786 - Transistors à couche mince
• H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
• H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant
• H01L 21/84 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant autre chose qu'un corps semi-conducteur, p.ex. étant un corps isolant

Abrégé

The present invention provides a field effect transistor and the method for preparing such a filed effect transistor. The filed effect transistor comprises a semiconductor, germanium nanowires, a first III-V compound layer surrounding the germanium nanowires, a semiconductor barrier layer, a gate dielectric layer and a gate electrode sequentially formed surrounding the first III-V compound layer, and source/drain electrodes are respectively located at each side of the gate electrode and on the first III-V compound layer. According to the present invention, the band width of the barrier layer is greater than that of the first III-V compound layer, and the band curvatures of the barrier layer and the first III-V compound layer are different, therefore, a two-dimensional electron gas (2DEG) is formed in the first III-V compound layer near the barrier layer boundary. Since the 2DEG has higher mobility, the performance of the filed effect transistor improved. Besides, the performance of the filed effect transistor also improved due to the structure is a gate-all-around structure.

Classes IPC  ?

• H01L 27/118 - Circuits intégrés à tranche maîtresse
• H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/786 - Transistors à couche mince
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/51 - Matériaux isolants associés à ces électrodes
• H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
• H01L 29/66 - Types de dispositifs semi-conducteurs

Abrégé

The present invention discloses a method of forming a high voltage junctionless device with drift region. The drift region formed between the semiconductor channel and the dielectric layer enables the high voltage junctionless device to exhibit higher punch-through voltages and high mobility with better performance and reliability.

Classes IPC  ?

• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV

Abrégé

Present embodiments provide for a FinFET and fabrication method thereof. The fabrication method includes two selective etching processes to form the channel. The FinFET includes a substrate, a shallow trench isolation (STI) layer, a buffer layer, an III-V group material, a high-K dielectric layer and a conductor material. The STI is formed on the substrate with a trench. The buffer layer is formed on the substrate in the trench. The III-V group material is formed on the buffer layer in vertical stacked bowl shape. The high-K dielectric layer is formed on the STI layer and surrounding the III-V group material. The conductor material is formed surrounding the high-K dielectric layer as a gate electrode.

Classes IPC  ?

• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
• H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
• H01L 29/66 - Types de dispositifs semi-conducteurs

Abrégé

A vertical transistor and the fabrication method. The transistor comprises a first surface and a second surface that is opposite to the first surface. A drift region of the first doping type, this drift region is located between the first surface and the second surface; at least one source region of the first doping type and the source region being located between the drift region and the first surface, with a first dielectric layer located between adjacent source regions; at least one drain region with said first doping type and said drain region being located between said drift region and said second surface, a gate being provided between adjacent drain regions. Said gate includes a gate electrode and a gate dielectric layer disposed between said gate electrode and said drift region, and the second dielectric layer being positioned between said gate electrode and said second surface.

Classes IPC  ?

• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
• H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/51 - Matériaux isolants associés à ces électrodes
• H01L 29/66 - Types de dispositifs semi-conducteurs

Abrégé

A method for making III-V-on-insulator on large-area Si Substrate wafer by confined epitaxial lateral overgrowth (CELO) has been disclosed. This method, based on selective epitaxy, starting from defining an epitaxy seed window to the Si substrate in a thermal oxide, from which the III-V material will grow.

Classes IPC  ?

• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
• H01L 21/311 - Gravure des couches isolantes

Abrégé

A structure and a method of fabrication are disclosed of a high voltage junctionless field effect device. A channel layer and a barrier layer are formed sequentially underneath the gate structure. The width of energy band gap of the barrier layer is wider than that of the channel layer. Thus the two dimensional electron gas (2-DEG) generated in the interface between the channel layer and the barrier layer of this junctionless field effect device has higher electron mobility. The structure of the device of this disclosure has a higher breakdown voltage which is advantageous for a high voltage junctionless field device. The structure offers advantages in device performance and reliability.

Classes IPC  ?

• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
• H01L 27/108 - Structures de mémoires dynamiques à accès aléatoire
• H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant
• H01L 29/788 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée à grille flottante
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/24 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des matériaux semi-conducteurs inorganiques non couverts par les groupes , ,  ou
• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
• H01L 29/51 - Matériaux isolants associés à ces électrodes
• H01L 21/443 - Dépôt de matériaux conducteurs ou isolants pour les électrodes à partir d'un gaz ou d'une vapeur, p. ex. condensation
• H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
• H01L 21/4763 - Dépôt de couches non isolantes, p. ex. conductrices, résistives sur des couches isolantesPost-traitement de ces couches
• H01L 21/027 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée

Abrégé

Embodiments provide a quantum well device and the method for forming this device with high mobility and higher punch through voltages. For forming the quantum well device, a buffer layer can be formed on a patterned substrate of a quantum well device. A fin-like structure can be formed through an etching process performed to the buffer layer. A quantum well layer, a barrier layer, a cover layer and a dielectric layer can be successively deposited on the buffer layer and surface of the fin-like structure. A metal layer can then be formed on the surface of the said dielectric layer. Metal gate electrode and gate dielectric layer can be formed on the metal layer and dielectric layer. The cover layer, the barrier layer and the quantum well can then be etched to form recessed source and drain regions. Such a quantum well device can have better performance and reliability.

Classes IPC  ?

• H01L 21/336 - Transistors à effet de champ à grille isolée
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 21/3065 - Gravure par plasmaGravure au moyen d'ions réactifs
• H01L 21/311 - Gravure des couches isolantes
• H01L 21/3213 - Gravure physique ou chimique des couches, p. ex. pour produire une couche avec une configuration donnée à partir d'une couche étendue déposée au préalable
• H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/15 - Structures avec une variation de potentiel périodique ou quasi périodique, p.ex. puits quantiques multiples, superréseaux
• H01L 21/306 - Traitement chimique ou électrique, p. ex. gravure électrolytique
• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
• H01L 29/205 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV comprenant plusieurs composés dans différentes régions semi-conductrices
• H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
• H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
• H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
• H01L 29/207 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV caractérisés en outre par le matériau de dopage
• H01L 21/8234 - Technologie MIS
• H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter

Abrégé

The present invention provides a filed effect transistor and the method for preparing such a filed effect transistor. The filed effect transistor comprises a semiconductor, germanium nanowires, a first III-V compound layer surrounding the germanium nanowires, a semiconductor barrier layer, a gate dielectric layer and a gate electrode sequentially formed surrounding the first III-V compound layer, and source/drain electrodes are respectively located at each side of the gate electrode and on the first III-V compound layer. According to the present invention, the band width of the barrier layer is greater than that of the first III-V compound layer, and the band curvatures of the barrier layer and the first III-V compound layer are different, therefore, a two dimensional electron gas (2DEG) is formed in the first III-V compound layer near the barrier layer boundary. Since the 2DEG has higher mobility, the performance of the filed effect transistor improved. Besides, the performance of the filed effect transistor also improved due to the structure is a gate-all-around structure.

Classes IPC  ?

• H01L 27/118 - Circuits intégrés à tranche maîtresse
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée
• H01L 29/45 - Electrodes à contact ohmique
• H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
• H01L 29/786 - Transistors à couche mince
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
• H01L 21/265 - Bombardement par des radiations ondulatoires ou corpusculaires par des radiations d'énergie élevée produisant une implantation d'ions
• H01L 21/324 - Traitement thermique pour modifier les propriétés des corps semi-conducteurs, p. ex. recuit, frittage
• H01L 21/283 - Dépôt de matériaux conducteurs ou isolants pour les électrodes

Abrégé

A complementary metal-oxide-semiconductor field-effect transistor comprises a semiconductor substrate, N-type and P-Type field-effect transistors positioned in the semiconductor substrate. Each of the field-effect transistor includes a germanium nanowire, a III-V compound layer surrounding around the germanium nanowire, a potential barrier layer mounted on the III-V compound layer, a gate dielectric layer, a gate, a source region and a drain region mounted on two sides of the gate. The field-effect transistor can produce two-dimensional electron gases and two-dimensional electron hole gases, and enhance the carrier mobility of the complementary metal-oxide-semiconductor field-effect transistor.

Classes IPC  ?

• H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
• H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/786 - Transistors à couche mince
• H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives