Abrégé

Aspects of this disclosure relate to multi-turn magnetic sensing systems and related methods. A system can include a first multi-turn magnetic sensor and a second multi-turn magnetic sensor, in which domain walls propagate in an opposite direction in the second multi-turn magnetic sensor relative to the first multi-turn magnetic sensor in response to a magnetic field. A decoder can output a turn count that is based on states of the first and second multi-turn sensors. The first and second multi-turn sensors can have a reset state that corresponds to the turn count having a value between minimum and maximum values of a counting range relative to the reset state.

Classes IPC  ?

• G01D 5/14 - Moyens mécaniques pour le transfert de la grandeur de sortie d'un organe sensibleMoyens pour convertir la grandeur de sortie d'un organe sensible en une autre variable, lorsque la forme ou la nature de l'organe sensible n'imposent pas un moyen de conversion déterminéTransducteurs non spécialement adaptés à une variable particulière utilisant des moyens électriques ou magnétiques influençant la valeur d'un courant ou d'une tension

Abrégé

Example implementations include a method, apparatus and computer-readable medium for indicating reliability of an artificial intelligence (AI) model, comprising configuring an AI model to generate an output vector representing output values for a first period of time based on an input vector. The implementations further include receiving a plurality of output vectors from the AI model. The implementations further include generating a matrix comprising the plurality of output vectors ordered sequentially such that each output vector of the plurality of output vectors is placed in a unique row or column of the matrix. The implementations further include extracting and filtering values in a cross section of the matrix. The implementations further include calculating a variance of the filtered values. The implementations further include transmitting an indication that the plurality of output vectors is unreliable in response to determining that the variance is greater than a variance threshold.

Classes IPC  ?

• G06N 20/00 - Apprentissage automatique

Abrégé

A biosensor structure may include a well structure comprising a first well and a second well, wherein a geometry of the well structure impacts where a solution dispensed into the well structure is located. A biosensor structure may include an electrode configured to sense an analyte in the solution, the electrode disposed at a bottom of the well structure. A biosensor structure may include a membrane positioned on the electrode and on at least part of a bottom surface of the well structure.

Classes IPC  ?

• B01L 3/00 - Récipients ou ustensiles pour laboratoires, p. ex. verrerie de laboratoireCompte-gouttes

Abrégé

A biosensor structure may include a well structure having a bottom surface, a side surface, and an open top. A biosensor structure may include a first membrane having a top surface and a bottom surface. A biosensor structure may include an electrode configured to sense an analyte in a solution in the well structure, wherein the electrode is disposed on the bottom surface of the well structure, wherein the bottom surface of the membrane is disposed on the electrode and on the bottom surface of the well structure, and wherein at least one of bottom surface and the side surface comprises a textured feature.

Classes IPC  ?

• B01L 3/00 - Récipients ou ustensiles pour laboratoires, p. ex. verrerie de laboratoireCompte-gouttes
• G01N 27/414 - Transistors à effet de champ sensibles aux ions ou chimiques, c.-à-d. ISFETS ou CHEMFETS
• G01N 27/416 - Systèmes

Abrégé

The present disclosure provides a buffer amplifier arrangement that seeks to find a solution to varying load configurations, output modes, modulator modes etc on an output of the buffer and the corresponding varying currents or voltages that appear at transistor devices throughout the circuit. To address this issue a current source that supplies an output of the buffer is divided into a fixed current source which supplies the current for the transistors of the buffer, and a variable current source that provides current for the variable load. The variable current source is a programmable current source that can be varied based on the associated modulator mode bus.

Classes IPC  ?

• G05F 1/56 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final

Abrégé

Aspects of this disclosure relate to multi-turn magnetic sensing systems and methods with rollover counting. In response to a multi-turn magnetic sensor reaching a maximum value, the multi-turn magnetic sensor can be reset and an index value can be updated. A decoder can determine a turn count based on the index value and the state of the multi-turn magnetic sensor. The turn count can have a magnitude greater than a number of turns of the multi-turn magnetic sensor.

Classes IPC  ?

• G01D 5/245 - Moyens mécaniques pour le transfert de la grandeur de sortie d'un organe sensibleMoyens pour convertir la grandeur de sortie d'un organe sensible en une autre variable, lorsque la forme ou la nature de l'organe sensible n'imposent pas un moyen de conversion déterminéTransducteurs non spécialement adaptés à une variable particulière utilisant des moyens électriques ou magnétiques influençant les caractéristiques d'impulsionsMoyens mécaniques pour le transfert de la grandeur de sortie d'un organe sensibleMoyens pour convertir la grandeur de sortie d'un organe sensible en une autre variable, lorsque la forme ou la nature de l'organe sensible n'imposent pas un moyen de conversion déterminéTransducteurs non spécialement adaptés à une variable particulière utilisant des moyens électriques ou magnétiques produisant des impulsions ou des trains d'impulsions utilisant un nombre variable d'impulsions dans un train

Abrégé

Aspects of this disclosure relate to an antenna array. An antenna array may include a first circularly polarized dipole antenna that includes a first pair of conductive elements. The antenna array may include a second circularly polarized dipole antenna that includes a second pair conductive elements, the second pair of conductive elements being geometrically orthogonal to the first pair of conductive elements. The antenna array may include a beamformer integrated circuit configured to drive the second circularly polarized dipole antenna such that the second circularly polarized dipole antenna transmits a first radio frequency signal while the first circularly polarized dipole antenna receives a second radio frequency signal. The first radio frequency signal can have a different polarization and be in a different frequency band than the second radio frequency signal.

Classes IPC  ?

• H01Q 5/48 - Combinaisons de plusieurs antennes de type dipôle
• H01Q 25/00 - Antennes ou systèmes d'antennes fournissant au moins deux diagrammes de rayonnement

Abrégé

A new method and circuit arrangement for operating a stepper motor in a control loop. Load values associated with a mechanical load of a stepper motor in operation are filtered to generate stall detection values. A step value is determined based on the difference between two stall detection values. The step value is compared to a threshold, and the stepper motor is determined to be in a stall condition based on the comparison between the step value to the threshold. This arrangement enables improved detection of stepper motor stall conditions when the stepper motor is operated at low velocities.

Classes IPC  ?

• H02P 8/38 - Protection contre les défauts, p. ex. contre l'échauffement excessif ou le décrochageIndication des défauts le défaut consistant en un décrochage
• H02P 8/22 - Commande de la grandeur des pasÉchelonnement intermédiaire, p. ex. micro-échelonnement

Abrégé

Aspects of this disclosure relate to an antenna cell. An antenna cell may include a first circularly polarized dipole antenna that includes a first pair of differently fed conductive elements, the first circularly polarized dipole antenna being right hand circularly polarized. The antenna cell may include a second circularly polarized dipole antenna that includes a second pair of differently fed conductive elements, the second circularly polarized dipole antenna being left hand circularly polarized. The first circularly polarized dipole antenna and the second circularly polarized dipole antenna may be geometrically orthogonal and configured to radiate concurrently. The first circularly polarized dipole antenna may be positioned adjacent to the second circularly polarized dipole antenna.

Classes IPC  ?

• H01Q 21/26 - Antennes tourniquet ou similaires comportant des dispositions de trois éléments ou plus allongés disposés radialement et symétriquement dans un plan horizontal par rapport à un centre commun

Abrégé

Apparatuses including spark gap structures for electrical overstress (EOS) monitoring or protection, and associated methods, are disclosed. In an aspect, a vertical spark gap device includes a substrate having a horizontal main surface and a plurality of pairs of conductive layers over the horizontal main surface. Different ones of the pairs are separated by different vertical distances such that each pair serves as an arcing electrode pair and different ones of the arcing electrode pairs are configured to arc discharge at different voltages.

Classes IPC  ?

• H02H 9/06 - Circuits de protection de sécurité pour limiter l'excès de courant ou de tension sans déconnexion sensibles à un excès de tension utilisant des éclateurs à étincelles
• H01T 1/02 - Moyens d'extinction d'arc
• H01T 2/02 - Éclateurs comportant des moyens de déclenchement auxiliaires comportant une électrode de déclenchement ou un éclateur auxiliaire

Abrégé

Methods and devices for detecting a property of a fluid inside a cartridge is disclosed herein. An electronic reader can be configured to electrically connect to a cartridge and detect the property of the fluid inline. The electronic reader can measure a voltage of the fluid inside the cartridge to determine an impedance of the fluid at a first time point. The electronic reader can use the determined impedance of the fluid and an impedance of a calibration resistor to get a first impedance ratio at the first time point. The electronic reader can then compare the first impedance ratio with a second impedance ratio determined at a second time point to evaluate whether the fluid inside the cartridge is still effective for its intended purpose.

Classes IPC  ?

• G01N 27/02 - Recherche ou analyse des matériaux par l'emploi de moyens électriques, électrochimiques ou magnétiques en recherchant l'impédance

Abrégé

There is provided an inverter system comprising a DC input for connecting to a DC power source. The inverter system comprises a plurality of transistors that are controllable to convert a DC voltage to an AC voltage. The inverter system further comprises a DC link capacitor coupled to the DC input of the inverter system and a discharge controller configured to cause a discharge of energy from the DC link capacitor when the DC power source is disconnected from the DC input of the inverter system. The discharge controller is configured to cause the discharge of energy from the DC link capacitor by turning on at least a first transistor and a second transistor so as to cause a controlled shoot-through of the inverter system. At least one of the first transistor and the second transistor are controlled by the discharge controller to operate in a linear region of operation.

Classes IPC  ?

• H02M 1/32 - Moyens pour protéger les convertisseurs autrement que par mise hors circuit automatique
• H02J 7/00 - Circuits pour la charge ou la dépolarisation des batteries ou pour alimenter des charges par des batteries
• H02M 7/537 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant alternatif sans possibilité de réversibilité par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs, p. ex. onduleurs à impulsions à un seul commutateur

Abrégé

Semiconductor devices can include features to apply electrical stimulation to liquids in which material is present and to measure the response to the electrical stimulation.

Classes IPC  ?

• G01N 33/483 - Analyse physique de matériau biologique
• B01L 3/00 - Récipients ou ustensiles pour laboratoires, p. ex. verrerie de laboratoireCompte-gouttes
• H01L 21/311 - Gravure des couches isolantes

Abrégé

The present disclosure relates to a circuit for setting an amplifier supply voltage for an amplifier. The circuit comprises a switch circuit having a first transistor arranged to switchably couple a first supply voltage to a supply terminal of the amplifier and a second transistor arranged to switchably couple a second supply voltage to the supply terminal of the amplifier, wherein a magnitude of the first supply voltage is greater than a magnitude of the second supply voltage. The circuit further comprises a control circuit arranged to control the switch circuit to set an amplifier supply voltage at the supply terminal of the amplifier based on an output signal of the amplifier. The control circuit is configured to set the amplifier supply voltage to substantially equal the second supply voltage when a magnitude of a tracking voltage is less than the magnitude of the second supply voltage and set the amplifier supply voltage to track the amplifier output signal when the magnitude of the tracking voltage is greater than the magnitude of the second supply voltage.

Classes IPC  ?

• H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
• H03F 3/24 - Amplificateurs de puissance, p. ex. amplificateurs de classe B, amplificateur de classe C d'étages transmetteurs de sortie

Abrégé

A power management device includes a first input port configured to be electrically coupled to an energy source, a second input port configured to be electrically coupled to a capacitor, a first output port configured to be electrically coupled to a first load, and a direct-current-to-direct-current (DC-to-DC) converter. The DC-to-DC converter is configured to (a) charge the capacitor from energy of the energy source and (b) provide energy to the first output port at least partially using energy stored in the capacitor. The energy source includes, for example, a battery.

Classes IPC  ?

• H02J 7/34 - Fonctionnement en parallèle, dans des réseaux, de batteries avec d'autres sources à courant continu, p. ex. batterie tampon
• H02J 7/00 - Circuits pour la charge ou la dépolarisation des batteries ou pour alimenter des charges par des batteries

Abrégé

The present disclosure provides systems and methods for signal processing and detection for pacemaker pulses. Systems and methods can activate an analog-to-digital converter based on detecting a leading edge of a pacemaker pulse. Such use of the analog-to-digital converter may allow a system to operate at a lower power and with more specificity than certain other systems.

Classes IPC  ?

• A61N 1/37 - SurveillanceProtection

Abrégé

Semiconductor devices can include features to apply electrical stimulation to liquids in which material is present and to measure the response to the electrical stimulation.

Classes IPC  ?

• G01N 27/403 - Ensembles de cellules et d'électrodes
• G01N 27/416 - Systèmes

Abrégé

The present disclosure provides methods and systems for reducing interference by one or more bubbles in a sensing assembly. Bubble prevention arrangements can use surfaces located in a fluid channel to provide surfaces with higher affinity for bubbles relative to the other surfaces so that the surface retains one or more bubbles within a bubble collection region; and/or to divert at least a portion of any bubbles passing through an opening in the fluid channel. Additionally or alternatively, bubble prevention arrangements comprise an agitation device configured to agitate liquid within the fluid channel. Additionally or alternatively, bubble prevention arrangements are configured to displace one or more bubbles in a region on or adjacent the sensing surface so as to reduce interference of one or more bubbles on the sensing surface.

Classes IPC  ?

• G01N 27/416 - Systèmes

Abrégé

The present disclosure provides methods and systems for reducing interference by one or more bubbles in a sensing assembly by determining a first property of the solution and using the first property in a removal step.

Classes IPC  ?

• G01N 27/416 - Systèmes
• G01N 27/02 - Recherche ou analyse des matériaux par l'emploi de moyens électriques, électrochimiques ou magnétiques en recherchant l'impédance

Abrégé

Aspects of this disclosure relate to symbol based envelope tracking. A voltage modulator circuit can generate an output bias voltage that tracks a root mean square symbol power of a radio frequency signal. A digital predistortion system in a signal path that provides the radio frequency signal can adjust a digital predistortion based on a symbol based envelope tracking state.

Classes IPC  ?

• H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
• H03F 1/32 - Modifications des amplificateurs pour réduire la distorsion non linéaire
• H03F 3/24 - Amplificateurs de puissance, p. ex. amplificateurs de classe B, amplificateur de classe C d'étages transmetteurs de sortie

Abrégé

Aspects of this disclosure relate to symbol based envelope tracking. A voltage modulator circuit can generate an output bias voltage that tracks a root mean square symbol power of a radio frequency signal. A crest factor reduction circuit in a signal path that provides the radio frequency signal can adjust a crest factor reduction threshold such that the crest factor reduction threshold corresponds to the output bias voltage.

Classes IPC  ?

• H03F 3/213 - Amplificateurs de puissance, p. ex. amplificateurs de classe B, amplificateur de classe C comportant uniquement des dispositifs à semi-conducteurs dans des circuits intégrés
• H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire

Abrégé

A semiconductor fabrication control system and method of operation can include: detecting a status with a control board communicatively coupled to a semiconductor fabrication tool; collecting process information from the semiconductor fabrication tool with the control board based on the status changing or a predetermined time elapsing; storing the process information to a server with the control board communicatively coupled to the server by a network connection; and engaging an auto-stop mechanism of the semiconductor fabrication tool to prevent the semiconductor fabrication tool from running based on the process information being wrong.

Classes IPC  ?

• G05B 19/418 - Commande totale d'usine, c.-à-d. commande centralisée de plusieurs machines, p. ex. commande numérique directe ou distribuée [DNC], systèmes d'ateliers flexibles [FMS], systèmes de fabrication intégrés [IMS], productique [CIM]
• H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
• H01L 21/67 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants

Abrégé

This disclosure relates to electronic chip identifiers, ECIDs. In one example an electronic device is disclosed, which includes an identity unit configured to store an ECID that uniquely identifies the electronic chip, and a multi-purpose pin for use in outputting the ECID from the electronic device. The multi-purpose pin is also for a function of the electronic device that is unrelated to electronic chip identification. The identity unit is configured to output the ECID from the electronic device using the multi-purpose pin such that the electronic device can be uniquely identified using the multi-purpose pin.

Classes IPC  ?

• H03K 19/003 - Modifications pour accroître la fiabilité

Abrégé

This disclosure relates to electronic chip identifiers, ECIDs. In one example an electronic device is disclosed, which includes an identity unit configured to store an ECID that uniquely identifies the electronic chip, and a multi-purpose pin for use in outputting the ECID from the electronic device. The multi-purpose pin is also for a function of the electronic device that is unrelated to electronic chip identification. The identity unit is configured to output the ECID from the electronic device using the multi-purpose pin such that the electronic device can be uniquely identified using the multi-purpose pin.

Classes IPC  ?

• G06K 19/077 - Détails de structure, p. ex. montage de circuits dans le support
• G06K 19/08 - Supports d'enregistrement pour utilisation avec des machines et avec au moins une partie prévue pour supporter des marques numériques caractérisés par le genre de marque numérique, p. ex. forme, nature, code utilisant des marquages de différentes sortes sur le même support d'enregistrement, p. ex. un marquage étant lu optiquement et l'autre par des moyens magnétiques

Abrégé

Systems and methods for reference electrodes are disclosed. In one aspect, a measurement system includes a pseudo-reference electrode configured to provide a reference potential and a dependence electrode configured to generate a dependence potential when exposed to a sample. Both the reference potential and the dependence potential vary based on a property of the sample. An electrochemical sensor includes the pseudo-reference electrode and the dependence electrode.

Classes IPC  ?

• G01N 27/30 - Électrodes, p. ex. électrodes pour testsDemi-cellules
• G01N 27/416 - Systèmes

Abrégé

Systems and methods embodiments are described for low-power, low-area current reference generator circuits that deliver a stable current bias for applications such as wake-up circuits. The current reference generator circuit provides for a nearly temperature-independent small-area bias current generator that uses a single pair of BJTs to reliably output a nominal 150 nA bias current that, irrespective of variations in process, supply voltage, and temperature (PVT), and local device mismatch, remains in a range between 120 nA and 180 nA. Advantageously, the circuit, which may be powered from and supply that is operationally functional at as low as about 1.0 V, does not require a calibration procedure or the combination of traditional PTAT and CTAT circuitries.

Classes IPC  ?

• G05F 3/26 - Miroirs de courant

Abrégé

An adaptable, multistage, multi-rate digital predistortion system that can increase the accuracy of the distortion applied to a power amplifier input signal is disclosed. Further, the digital predistortion system can be implemented using a reduced circuit area by reducing a number of coefficients used by the models applied to generate the distortion compensation signal. Further, the system can implement an improved digital predistortion adaptation engine that improves an adjacent channel leakage ratio of the digital predistortion system. Moreover, the system can compensate for non-linear impairments due to analog/RF circuits and systems and improve at least the following metrics: Error vector magnitude (EVM), adjacent channel leakage ratio (ACLR), spectrum emission mask (SEM), and power consumption of the circuits and systems. An example of circuits and systems is radio frequency power amplifier (RF PA).

Classes IPC  ?

• H03F 1/32 - Modifications des amplificateurs pour réduire la distorsion non linéaire

Abrégé

Apparatuses including spark gap structures for electrical overstress (EOS) monitoring or protection, and associated methods, are disclosed. In an aspect, a spark gap device includes first and second conductive layers formed over a substrate, where the first and second conductive layers are electrically connected to first and second voltage nodes, respectively. The first conductive layer includes a plurality of arcing tips configured to form arcing electrode pairs with the second conductive layer to form an arc discharge in response to an EOS voltage between the first and second voltage nodes. The spark gap device further includes a series ballast resistor electrically connected between the arcing tips and the first voltage node, where the ballast resistor in formed in a metallization layer over the substrate and a resistance of the series ballast resistor is substantially higher than a resistance of the second conductive layer.

Classes IPC  ?

• H01T 4/10 - Limiteurs de surtension utilisant des éclateurs ayant un intervalle simple ou plusieurs intervalles disposés en parallèle

Abrégé

An apparatus is provided that is implemented to enable multiple tests of different types, such as a direct current (DC) test and/or a radio frequency (RF) test of a semiconductor device. The apparatus includes a microelectromechanical systems (MEMS) switch block coupled between the semiconductor device and automatic testing equipment (ATE). The apparatus is configured to enable/disable a DC path or an RF path to switch between a DC test and an RF test without reconfiguring the connections between the semiconductor device and the ATE. The DC path is used to perform a DC contact test for one or more pins of the semiconductor device. The RF path is used to perform an RF test for the semiconductor device.

Classes IPC  ?

• G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
• H01H 1/00 - Contacts

Abrégé

Apparatus and methods for RF signal limiters with diode-enhanced limiting are provided. In certain embodiments, an RF signal limiter includes a field-effect transistor (FET) stack electrically connected between an RF signal path and a limiting node, such as ground. The FET stack includes a first or topmost FET having a drain connected to the RF signal path. The gate of the topmost FET is biased through a first gate resistor. The RF signal limiter further includes a first forward enhancement diode having an anode connected to the RF signal path and a cathode connected to the gate of topmost FET.

Classes IPC  ?

• H03F 1/52 - Circuits pour la protection de ces amplificateurs
• H03F 3/19 - Amplificateurs à haute fréquence, p. ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs

Abrégé

Apparatuses including spark gap structures for electrical overstress (EOS) monitoring or protection, and associated methods, are disclosed. In an aspect, a vertical spark gap device includes a substrate having a horizontal main surface, a first conductive layer and a second conductive layer each extending over the substrate and substantially parallel to the horizontal main surface while being separated in a vertical direction crossing the horizontal main surface. One of the first and second conductive layers is electrically connected to a first voltage node and the other of the first and second conductive layers is electrically connected to a second voltage node. The first and second conductive layers serve as one or more arcing electrode pairs and have overlapping portions configured to generate one or more arc discharges extending generally in the vertical direction in response to an EOS voltage signal received between the first and second voltage nodes.

Classes IPC  ?

• B81B 7/02 - Systèmes à microstructure comportant des dispositifs électriques ou optiques distincts dont la fonction a une importance particulière, p. ex. systèmes micro-électromécaniques [SMEM, MEMS]
• H02H 9/06 - Circuits de protection de sécurité pour limiter l'excès de courant ou de tension sans déconnexion sensibles à un excès de tension utilisant des éclateurs à étincelles
• H02H 9/04 - Circuits de protection de sécurité pour limiter l'excès de courant ou de tension sans déconnexion sensibles à un excès de tension
• H01T 4/08 - Limiteurs de surtension utilisant des éclateurs associés structuralement avec un appareil protégé
• H01T 4/12 - Limiteurs de surtension utilisant des éclateurs ayant un intervalle simple ou plusieurs intervalles disposés en parallèle scellés hermétiquement
• H01L 23/60 - Protection contre les charges ou les décharges électrostatiques, p. ex. écrans Faraday
• H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
• H01H 59/00 - Relais électrostatiquesRelais à électro-adhésion
• H01H 1/00 - Contacts
• B60L 53/14 - Transfert d'énergie par conduction
• H02J 7/00 - Circuits pour la charge ou la dépolarisation des batteries ou pour alimenter des charges par des batteries
• H01L 23/62 - Protection contre l'excès de courant ou la surcharge, p. ex. fusibles, shunts

Abrégé

Apparatuses including spark gap structures for electrical overstress (EOS) monitoring or protection, and associated methods, are disclosed. In an aspect, a vertical spark gap device includes a substrate having a horizontal main surface, an enclosed volume formed over the horizontal main surface and filled with a medium; and one or more arcing electrode pairs separated by the enclosed volume. The electrodes of each arcing electrode pair are separated in a vertical direction, crossing the horizontal main surface, by a gap and serve as arcing electrodes configured to generate an arc discharge in response to an EOS signal received between a first voltage node and a second voltage node.

Classes IPC  ?

• H01T 4/12 - Limiteurs de surtension utilisant des éclateurs ayant un intervalle simple ou plusieurs intervalles disposés en parallèle scellés hermétiquement
• H01H 1/00 - Contacts
• H01L 23/60 - Protection contre les charges ou les décharges électrostatiques, p. ex. écrans Faraday
• H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
• H01T 4/08 - Limiteurs de surtension utilisant des éclateurs associés structuralement avec un appareil protégé
• H02H 9/04 - Circuits de protection de sécurité pour limiter l'excès de courant ou de tension sans déconnexion sensibles à un excès de tension
• H02H 9/06 - Circuits de protection de sécurité pour limiter l'excès de courant ou de tension sans déconnexion sensibles à un excès de tension utilisant des éclateurs à étincelles
• B81B 7/02 - Systèmes à microstructure comportant des dispositifs électriques ou optiques distincts dont la fonction a une importance particulière, p. ex. systèmes micro-électromécaniques [SMEM, MEMS]
• H01H 59/00 - Relais électrostatiquesRelais à électro-adhésion

Abrégé

Apparatuses including spark gap structures for electrical overstress (EOS) monitoring or protection, and associated methods, are disclosed. In an aspect, an EOS monitoring or protection device include a semiconductor substrate having a horizontal main surface, a PN junction formed by first and second oppositely doped semiconductor regions in the semiconductor substrate, first and second metal layers electrically connecting the first and second doped semiconductor regions to first and second voltage nodes, respectively, and a stack of layers formed on the horizontal main surface over the first doped semiconductor region. The stack of layers includes a dielectric layer between the horizontal main surface and an arcing electrode layer, wherein the arcing electrode layer and the first doped semiconductor region are configured to generate an arc discharge therebetween through the dielectric layer in response to an EOS voltage signal received between the first and second voltage nodes.

Classes IPC  ?

• B81B 7/02 - Systèmes à microstructure comportant des dispositifs électriques ou optiques distincts dont la fonction a une importance particulière, p. ex. systèmes micro-électromécaniques [SMEM, MEMS]
• H02H 9/06 - Circuits de protection de sécurité pour limiter l'excès de courant ou de tension sans déconnexion sensibles à un excès de tension utilisant des éclateurs à étincelles
• H02H 9/04 - Circuits de protection de sécurité pour limiter l'excès de courant ou de tension sans déconnexion sensibles à un excès de tension
• H01T 4/08 - Limiteurs de surtension utilisant des éclateurs associés structuralement avec un appareil protégé
• H01T 4/12 - Limiteurs de surtension utilisant des éclateurs ayant un intervalle simple ou plusieurs intervalles disposés en parallèle scellés hermétiquement
• H01L 23/60 - Protection contre les charges ou les décharges électrostatiques, p. ex. écrans Faraday
• H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
• H01H 59/00 - Relais électrostatiquesRelais à électro-adhésion
• H01H 1/00 - Contacts
• B60L 53/14 - Transfert d'énergie par conduction
• H02J 7/00 - Circuits pour la charge ou la dépolarisation des batteries ou pour alimenter des charges par des batteries
• H01L 23/62 - Protection contre l'excès de courant ou la surcharge, p. ex. fusibles, shunts

Abrégé

Apparatuses including spark gap structures for electrical overstress (EOS) monitoring or protection, and associated methods, are disclosed. In an aspect, an energy management system includes an electric charging system that transmits electric energy to an electric energy storage system to charge a secondary battery, where one or both of the energy management system and the electric charging system include one or more EOS protection or monitoring devices for monitoring and/or protecting the respective system(s) from an EOS signal during energy transfer from the electric charging system to the electric energy storage system. The EOS protection or monitor device includes a spark gap formed by a pair of arcing electrodes fabricated on a substrate and configured to generate an arc discharge in response to the EOS signal.

Classes IPC  ?

• H01T 4/08 - Limiteurs de surtension utilisant des éclateurs associés structuralement avec un appareil protégé
• B60L 53/14 - Transfert d'énergie par conduction
• H01T 4/12 - Limiteurs de surtension utilisant des éclateurs ayant un intervalle simple ou plusieurs intervalles disposés en parallèle scellés hermétiquement
• H01L 23/60 - Protection contre les charges ou les décharges électrostatiques, p. ex. écrans Faraday
• H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
• H02H 9/04 - Circuits de protection de sécurité pour limiter l'excès de courant ou de tension sans déconnexion sensibles à un excès de tension
• H02H 9/06 - Circuits de protection de sécurité pour limiter l'excès de courant ou de tension sans déconnexion sensibles à un excès de tension utilisant des éclateurs à étincelles
• H02J 7/00 - Circuits pour la charge ou la dépolarisation des batteries ou pour alimenter des charges par des batteries
• H01L 23/62 - Protection contre l'excès de courant ou la surcharge, p. ex. fusibles, shunts
• H01H 59/00 - Relais électrostatiquesRelais à électro-adhésion
• H01H 1/00 - Contacts

Abrégé

An apparatus is provided for pin count reduction in a chip for using across boards. The apparatus includes a circuit configured to bypass a respective scan pin on each of one or more scan chains subject to the pin count reduction while maintaining scan chain flows of patterns from a head flipflop through intermediate flipflops to a tail flipflop of each of the one or more scan chains subject to the pin count reduction, using scan chain elements of the one or more scan chains subject to the pin count reduction and scan chain elements of one or more scan chains not subject to the pin count reduction. The respective scan pin is any of a scan IN pin and a scan OUT pin.

Classes IPC  ?

• G01R 31/3185 - Reconfiguration pour les essais, p. ex. LSSD, découpage

Abrégé

There is provided a printed antenna including a first conductive layer patterned to form two or more metal regions of a radiating element; a second conductive layer patterned to form at least one metal region of the radiating element, wherein the first conductive layer and the second conductive layer are separated by a dielectric; and a plurality of vias connecting the two or more metal regions on the first conductive layer to the at least one metal region on the second conductive layer to form a coil. There is also provided a wireless battery management system including the printed antenna and a method of forming a printed antenna thereof.

Classes IPC  ?

• H01Q 9/04 - Antennes résonnantes

Abrégé

Aspects of this disclosure relate to generating a bias signal with magnetic field cancellation. A voltage modulator circuit can generate a bias voltage that tracks an envelope of a radio frequency signal. For example, the bias signal can track the envelope of the radio frequency signal that is amplified by a power amplifier on a symbol-by-symbol basis. The voltage modulator circuit includes one or more pairs of switches with magnetic field cancellation.

Classes IPC  ?

• H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
• H03F 3/24 - Amplificateurs de puissance, p. ex. amplificateurs de classe B, amplificateur de classe C d'étages transmetteurs de sortie
• H04B 1/16 - Circuits

Abrégé

Apparatuses including spark gap structures for electrical overstress (EOS) monitoring or protection, and associated methods, are disclosed. In an aspect, a spark gap array includes a sheet resistor and an array of arcing electrode pairs formed over a substrate. The array of arcing electrode pairs includes first arcing electrodes formed on the sheet resistor and a second arcing electrode arranged as a sheet formed over the first arcing electrodes and separated from the first arcing electrodes by an arcing gap. The first arcing electrodes and second arcing electrode are electrically connected to first and second voltage nodes, respectively, and the arcing electrode pairs are configured to generate arc discharges in response to an EOS voltage signal received between the first and second voltage nodes.

Classes IPC  ?

• H01T 4/06 - Dispositions pour le montage de plusieurs limiteurs de surtension
• H01T 4/12 - Limiteurs de surtension utilisant des éclateurs ayant un intervalle simple ou plusieurs intervalles disposés en parallèle scellés hermétiquement

Abrégé

Apparatuses including spark gap structures for electrical overstress (EOS) monitoring or protection, and associated methods, are disclosed. In an aspect, a vertical spark gap device includes a substrate having a horizontal main surface, a first conductive layer and a second conductive layer each extending over the substrate and substantially parallel to the horizontal main surface while being separated in a vertical direction crossing the horizontal main surface. One of the first and second conductive layers is electrically connected to a first voltage node and the other of the first and second conductive layers is electrically connected to a second voltage node. The first and second conductive layers serve as one or more arcing electrode pairs and have overlapping portions configured to generate one or more arc discharges extending generally in the vertical direction in response to an EOS voltage signal received between the first and second voltage nodes.

Classes IPC  ?

• H01T 4/12 - Limiteurs de surtension utilisant des éclateurs ayant un intervalle simple ou plusieurs intervalles disposés en parallèle scellés hermétiquement
• H01T 2/02 - Éclateurs comportant des moyens de déclenchement auxiliaires comportant une électrode de déclenchement ou un éclateur auxiliaire
• H05K 1/02 - Circuits imprimés Détails

Abrégé

Aspects of the present disclosure include a memory circuit including a timing circuit including a flip-flop configured to receive a clock signal having a first frequency and output an intermediate clock signal having a second frequency that is a fraction of the first frequency, a multiplexer configured to receive the clock signal and the intermediate clock signal, receive a selection signal indicating a selection of the clock signal or the intermediate clock signal, and output one of the clock signal or the intermediate clock signal based on the selection signal, and a memory controller configured to be read via a first interface synchronized to the clock signal at the first frequency, and programmed via a second interface synchronized to the intermediate clock signal at the second frequency.

Classes IPC  ?

• G11C 17/18 - Circuits auxiliaires, p. ex. pour l'écriture dans la mémoire
• G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. circuits de commande E/S de données, mémoires tampon de données E/S
• G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
• G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]

Abrégé

Apparatuses including spark gap structures for electrical overstress (EOS) monitoring or protection, and associated methods, are disclosed. In an aspect, a vertical spark gap device and a MEMS switch are formed on the substrate having a horizontal main surface. The MEMS switch includes a switch beam anchored at one end over the horizontal main surface and the vertical spark gap device includes one or more pairs of arcing electrodes fabricated on the substrate, where the arcing electrodes of each pair are vertically separated by an arcing gap and generate an arc discharge in response to an EOS signal received by the MEMS switch received between a first voltage node and a second voltage node. The MEMS switch and the vertical spark gap device have one or more corresponding structures that are co-fabricated such that the corresponding structures include the same material or have at least one common feature dimension.

Classes IPC  ?

• B81B 7/02 - Systèmes à microstructure comportant des dispositifs électriques ou optiques distincts dont la fonction a une importance particulière, p. ex. systèmes micro-électromécaniques [SMEM, MEMS]
• H02H 9/06 - Circuits de protection de sécurité pour limiter l'excès de courant ou de tension sans déconnexion sensibles à un excès de tension utilisant des éclateurs à étincelles
• H02H 9/04 - Circuits de protection de sécurité pour limiter l'excès de courant ou de tension sans déconnexion sensibles à un excès de tension
• H01T 4/08 - Limiteurs de surtension utilisant des éclateurs associés structuralement avec un appareil protégé
• H01T 4/12 - Limiteurs de surtension utilisant des éclateurs ayant un intervalle simple ou plusieurs intervalles disposés en parallèle scellés hermétiquement
• H01L 23/60 - Protection contre les charges ou les décharges électrostatiques, p. ex. écrans Faraday
• H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
• H01H 59/00 - Relais électrostatiquesRelais à électro-adhésion
• H01H 1/00 - Contacts
• B60L 53/14 - Transfert d'énergie par conduction
• H02J 7/00 - Circuits pour la charge ou la dépolarisation des batteries ou pour alimenter des charges par des batteries

Abrégé

Aspects of the disclosure relate to a device that includes a plurality of light sources comprising a first light source and a second light source configured to emit electromagnetic radiation. The device may be configured to determine to perform a first set of measurements on the subject within a time window, wherein the first set of measurements comprise a first measurement performed with the first light source using a first optimal voltage and a second measurement performed with the second light source using a second optimal voltage, wherein the first measurement and the second measurement are performed in a contiguous sequence within the time window, and wherein the first optimal voltage is different from the second optimal voltage. The device may be further configured to apply the first optimal voltage to the first light source and apply the second optimal voltage to the second light source.

Classes IPC  ?

• A61B 5/024 - Mesure du pouls ou des pulsations cardiaques

Abrégé

An electrochemical impedance spectroscopy (EIS) excitation system may include energy transfer circuitry, which may be configured to transfer energy from a first electrochemical device to a second electrochemical device. The EIS excitation system may also include a controller, which may be configured to control the energy transfer circuitry to generate an EIS excitation signal for the first electrochemical device. The controller may be configured to control the energy transfer circuitry to transfer energy in a first direction between the first electrochemical device and the second electrochemical device for a first portion of an EIS excitation signal cycle.

Classes IPC  ?

• G01N 27/02 - Recherche ou analyse des matériaux par l'emploi de moyens électriques, électrochimiques ou magnétiques en recherchant l'impédance

Abrégé

Aspects of the disclosure relate to a device that includes a plurality of light sources comprising a first light source and a second light source configured to emit electromagnetic radiation. The device may be configured to determine to perform a first set of measurements on the subject within a time window, wherein the first set of measurements comprise a first measurement performed with the first light source using a first optimal voltage and a second measurement performed with the second light source using a second optimal voltage, wherein the first measurement and the second measurement are performed in a contiguous sequence within the time window, and wherein the first optimal voltage is different from the second optimal voltage. The device may be further configured to apply the first optimal voltage to the first light source and apply the second optimal voltage to the second light source.

Classes IPC  ?

• A61B 5/024 - Mesure du pouls ou des pulsations cardiaques
• A61B 5/1455 - Mesure des caractéristiques du sang in vivo, p. ex. de la concentration des gaz dans le sang ou de la valeur du pH du sang en utilisant des capteurs optiques, p. ex. des oxymètres à photométrie spectrale

Abrégé

A system for reducing a voltage-dependent effect of a first capacitor caused by a first voltage may include the first capacitor, which may include a first physical spacing between a first capacitor terminal conductor of the first capacitor and a second capacitor terminal conductor of the first capacitor. The system may also include a second capacitor, which may include a second physical spacing between a first capacitor terminal conductor of the second capacitor and a second capacitor terminal conductor of the second capacitor, where the second physical spacing is different from the first physical spacing. The system may also include a compensation circuit, which may be arranged to receive and at least partially offset a voltage dependent signal contribution from each of the first and second capacitors for output to a signal-processing circuit.

Classes IPC  ?

• H03K 5/01 - Mise en forme d'impulsions

Abrégé

Various techniques for determining self-discharge rates of one or more battery cells, such as by determining a current leakage of the battery cell(s), are described. The techniques may improve the effective ADC linearity. An example of a technique may calculate the average time when each ADC digital code is observed, such as for a given battery cell or battery module, which allows the battery cell discharge rate to be estimated from the interval between the average time observed for neighboring, e.g., adjacent, digital codes. This approach allows the self-discharge rate of a battery cell to be calculated with high resolution even when the total cell voltage excursion is only a few least significant bits (LSBs).

Classes IPC  ?

• G01R 31/367 - Logiciels à cet effet, p. ex. pour le test des batteries en utilisant une modélisation ou des tables de correspondance
• G01R 31/36 - Dispositions pour le test, la mesure ou la surveillance de l’état électrique d’accumulateurs ou de batteries, p. ex. de la capacité ou de l’état de charge
• G01R 31/3828 - Dispositions pour la surveillance de variables des batteries ou des accumulateurs, p. ex. état de charge utilisant l’intégration du courant

Abrégé

An apparatus and methods for detecting seat occupancy of a vehicle including a plurality of seats, one or more microphones, and one or more loudspeakers are described. The apparatus in the vehicle includes a digital signal processor coupled to a memory and configured to: determine a first set of transfer functions between the one or more microphones and the one or more loudspeakers based on a first audio signal played from the one or more loudspeakers while passengers are occupying one or more of the plurality of seats. The digital signal processor is configured to apply at least the first set of transfer functions and a second set of transfer functions for the vehicle to a neural network trained on transfer functions for a type of the vehicle to predict a seat occupancy of each of the plurality of seats based on the transfer functions.

Classes IPC  ?

• B60N 2/00 - Sièges spécialement adaptés aux véhiculesAgencement ou montage des sièges dans les véhicules
• B60Q 5/00 - Agencement ou adaptation des dispositifs de signalisation acoustique

Abrégé

Aspects of the present disclosure include a memory circuit including a timing circuit including a flip-flop configured to receive a clock signal having a first frequency and output an intermediate clock signal having a second frequency that is a fraction of the first frequency, a multiplexer configured to receive the clock signal and the intermediate clock signal, receive a selection signal indicating a selection of the clock signal or the intermediate clock signal, and output one of the clock signal or the intermediate clock signal based on the selection signal, and a memory controller configured to be read via a first interface synchronized to the clock signal at the first frequency, and programmed via a second interface synchronized to the intermediate clock signal at the second frequency.

Classes IPC  ?

• G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
• G06F 1/08 - Générateurs d'horloge ayant une fréquence de base modifiable ou programmable
• G06F 13/42 - Protocole de transfert pour bus, p. ex. liaisonSynchronisation

Abrégé

A new method and circuit arrangement for operating an electric motor, such as a stepper motor, in a control loop for preventing motor stall, the electric motor comprising at least a first motor coil and a second motor coil, the method comprising: operating the electric motor at a velocity equal to the target velocity; receiving a load value associated with an electric motor load; and determining whether the load value is greater than a load value threshold. Based on a determination that the load value is greater than the load value threshold decreasing the velocity of the electric motor to a velocity less than the target velocity.

Classes IPC  ?

• H02P 8/36 - Protection contre les défauts, p. ex. contre l'échauffement excessif ou le décrochageIndication des défauts
• H02P 8/16 - Réduction de l'énergie dissipée ou de l'énergie d'alimentation

Abrégé

Reading, by a controller of the network, a first PLCA ID of each of N follower nodes of the network. First remapping, by the controller, each read first PLCA ID to one of N+1 unique remapped PLCA IDs. One PLCA ID of the N+1 unique remapped PLCA IDs is reserved for one of the follower nodes requesting a subsequent re-mapping of PLCA IDs. The N+1 unique remapped PLCA IDs start at a lowest PLCA ID and proceed through consecutive PLCA IDs.

Classes IPC  ?

• H04W 24/02 - Dispositions pour optimiser l'état de fonctionnement
• H04W 74/08 - Accès non planifié, p. ex. ALOHA

Abrégé

Various current measurement systems and methods of signal processing are disclosed. In one example, there is a current measurement system that includes a filter with a corner frequency within the operating frequency range of the current measurement system. This provides a system with good SNR, whilst also preventing or reducing the likelihood of output saturation during large di/dt spikes. The system further includes an equaliser arranged to compensate for the phase and/or magnitude response of the filter within the operating frequency range.

Classes IPC  ?

• G01R 19/25 - Dispositions pour procéder aux mesures de courant ou de tension ou pour en indiquer l'existence ou le signe utilisant une méthode de mesure numérique
• G01R 15/18 - Adaptations fournissant une isolation en tension ou en courant, p. ex. adaptations pour les réseaux à haute tension ou à courant fort utilisant des dispositifs inductifs, p. ex. des transformateurs
• H03B 5/24 - Élément déterminant la fréquence comportant résistance, et soit capacité, soit inductance, p. ex. oscillateur à glissement de phase l'élément actif de l'amplificateur étant un dispositif à semi-conducteurs
• H03H 7/06 - Réseaux à deux accès sélecteurs de fréquence comprenant des résistances

Abrégé

Reading, by a controller of the network, a first PLCA ID of each of N follower nodes of the network. First remapping, by the controller, each read first PLCA ID to one of N+1 unique remapped PLCA IDs. One PLCA ID of the N+1 unique remapped PLCA IDs is reserved for one of the follower nodes requesting a subsequent re-mapping of PLCA IDs. The N+1 unique remapped PLCA IDs start at a lowest PLCA ID and proceed through consecutive PLCA IDs.

Classes IPC  ?

• H04L 12/413 - Réseaux à ligne bus avec commande décentralisée avec accès aléatoire, p. ex. accès multiple avec détection de porteuse et détection de collision [CSMA-CD]

Abrégé

In a network host discovers each node n and each audio group at each node, an audio group including audio channel(s) and being one of a source or a sink. The host receives identification of at least one audio stream having a source audio group and sink audio group(s). The host derives, for each node n starting from main downstream to a last node: register values DNMaskReg(n) and register values DNSlotReg(n). The host derives, for node n starting from the last node and proceeding to the main node: register values UPMaskReg(n) and UPSlotReg(n). The host derives, for each node n: register values TXCrossReg(n) and RXMaskReg(n). The host writes, over the network to a corresponding register of each node n, the derived register values.

Classes IPC  ?

• G06F 3/16 - Entrée acoustiqueSortie acoustique

Abrégé

The present disclosure relates to a physical unclonable function, PUF, apparatus. In one example, the PUF apparatus includes a PUF source, for outputting a first signal and a second signal, where a difference between the signals is indicative of a random manufacturing difference between components in the PUF source, and an analog to digital converter, ADC, for coupling to the PUF source. In this example, the PUF apparatus is configured to operate in a plurality of different modes comprising at least a PUF coarse-measurement mode and a PUF fine-measurement mode. When operating in the PUF coarse-measurement mode and when operating in the PUF fine-measurement mode, the PUF apparatus is configured to use the ADC to generate a digital measurement that is a measure of the difference between the first signal and the second signal and generate a PUF value using the digital measurement. However, when the PUF apparatus is operating in the PUF fine-measurement mode, the digital measurement has a greater resolution than when operating in the PUF coarse- measurement mode.

Classes IPC  ?

• G06F 21/73 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information par création ou détermination de l’identification de la machine, p. ex. numéros de série
• H04L 9/08 - Répartition de clés
• H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système

Abrégé

A method is provided for synchronizing a non-primary clock to a primary clock in a network. The aspects include receiving a first, a second, and a third message pair, each including a sync message with an estimated time the sync message was transmitted and a follow-up message with an actual time the sync message was transmitted. The aspects include, responsive to the second message pair, setting a neighbor rate ratio between the primary clock and the non-primary clock to a midpoint value for non-primary clock control based on an ingress timestamp delta and an egress timestamp delta. The aspects include, responsive to the third message pair, fixing a phase value of the primary clock by setting an expected primary clock time value to a current timestamp of the primary clock without modification of the midpoint value. The aspects include adjusting the non-primary clock responsive to at least the midpoint value.

Classes IPC  ?

• H04L 7/00 - Dispositions pour synchroniser le récepteur avec l'émetteur

Abrégé

A method is provided for operating a network node in a multi-node network having one or more Master Control Units (MCUs) configured to control network nodes when the one or more MCUs are available. The aspects include, in one or more memory regions of the network node having a header and a payload: storing one or more conditions in the header, storing one or more commands in the payload associated with the one or more conditions, and configuring at least one of the one or more conditions to comprise using a time base of the network node, the time base including a starting timestamp and a programmable period time T. The aspects further include, in a control device of the network node: determining, according to the time base, whether a condition stored in a header of a selected region occurs, and performing a node control action based on the determining.

Classes IPC  ?

• H04L 41/12 - Découverte ou gestion des topologies de réseau
• H04L 41/0806 - Réglages de configuration pour la configuration initiale ou l’approvisionnement, p. ex. prêt à l’emploi [plug-and-play]

Abrégé

The disclosed technology generally relates to integrated circuit devices with wear out monitoring capability. An integrated circuit device includes a wear-out monitor device configured to record an indication of wear-out of a core circuit separated from the wear-out monitor device, wherein the indication is associated with localized diffusion of a diffusant within the wear-out monitor device in response to a wear-out stress that causes the wear-out of the core circuit.

Classes IPC  ?

• G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
• G01N 27/04 - Recherche ou analyse des matériaux par l'emploi de moyens électriques, électrochimiques ou magnétiques en recherchant l'impédance en recherchant la résistance

Abrégé

The present disclosure relates to a physical unclonable function, PUF, apparatus. In one example, the PUF apparatus includes a PUF source, for outputting a first signal and a second signal, where a difference between the signals is indicative of a random manufacturing difference between components in the PUF source, and an analog to digital converter, ADC, for coupling to the PUF source. In this example, the PUF apparatus is configured to operate in a plurality of different modes comprising at least a PUF coarse-measurement mode and a PUF fine-measurement mode. When operating in the PUF coarse-measurement mode and when operating in the PUF fine-measurement mode, the PUF apparatus is configured to use the ADC to generate a digital measurement that is a measure of the difference between the first signal and the second signal and generate a PUF value using the digital measurement. However, when the PUF apparatus is operating in the PUF fine-measurement mode, the digital measurement has a greater resolution than when operating in the PUF coarse-measurement mode.

Classes IPC  ?

• G06F 21/31 - Authentification de l’utilisateur
• G06F 7/58 - Générateurs de nombres aléatoires ou pseudo-aléatoires

Abrégé

Methods and systems for determining a property of an analyte in a sample, wherein a field is applied to a sensing surface to cause an analyte to debind from a surface, and subsequently the field is modified or removed to allow the analyte to rebind.

Classes IPC  ?

• G01N 27/327 - Électrodes biochimiques

Abrégé

The present disclosure provides systems and method for determining a property of an analyte in a sample, the systems and methods use a sensor assembly comprising a sensing element. The method and systems remove at least a portion of non-specifically-bound species from the sensing element by applying an electric field to the sample matrix, wherein the electric field is configured to remove the non-specifically-bound species but has a strength less than that required to detach any specifically-bound analyte from the sensing element.

Classes IPC  ?

• A61B 5/145 - Mesure des caractéristiques du sang in vivo, p. ex. de la concentration des gaz dans le sang ou de la valeur du pH du sang

Abrégé

A sensor assembly for determining a property of an analyte in a sample, where a modification unit comprising a set of modification electrodes with at least a first modification electrode is provided adjacent or on a sensing element, which includes a capture species, and which modification unit is configured modify a property of at least a portion of a sample received on the sensing element.

Classes IPC  ?

• G01N 27/30 - Électrodes, p. ex. électrodes pour testsDemi-cellules
• G01N 27/327 - Électrodes biochimiques

Abrégé

The present disclosure provides systems and method for determining a property of an analyte in a sample, the systems and methods use a sensor assembly comprising a sensing layer provided with through holes and a capture species configured to specifically bind with the analyte. The capture species is located adjacent and/or in the through holes such that analyte bound to the capture species can interact with the through holes of the sensing layer so as to alter the impedimetric property of the sensing layer. The sensing element provides a measurement signal which is indicative of an impedimetric property of the sensing layer and/or the sensing element comprises an IDE with at least a part of the sensing layer provided between electrodes of the IDE.

Classes IPC  ?

• A61B 5/145 - Mesure des caractéristiques du sang in vivo, p. ex. de la concentration des gaz dans le sang ou de la valeur du pH du sang
• G01N 27/02 - Recherche ou analyse des matériaux par l'emploi de moyens électriques, électrochimiques ou magnétiques en recherchant l'impédance
• G01N 27/327 - Électrodes biochimiques

Abrégé

The present disclosure provides a sensor assembly for a target analyte. The sensor assembly comprises plural sensing sites, each of the sensing sites comprising one or more through holes. Each of the sensing sites has a different through hole configuration corresponding to a different property of the one or more through holes.

Classes IPC  ?

• G01N 1/16 - Dispositifs pour prélever des échantillons à l'état liquide ou fluide avec mesures prises pour aspiration à plusieurs niveaux
• G01N 35/00 - Analyse automatique non limitée à des procédés ou à des matériaux spécifiés dans un seul des groupes Manipulation de matériaux à cet effet

Abrégé

The present disclosure provides systems and methods for determining a property of target analyte in a sample. The systems and methods use a sensor assembly comprising plural sensing sites, each of the sensing sites comprising a capture species configured to specifically bind with the same target analyte. Each capture species is different and has a different binding affinity for the target analyte to the capture species on the other of the plural sensing sites.

Classes IPC  ?

• G01N 33/543 - Tests immunologiquesTests faisant intervenir la formation de liaisons biospécifiquesMatériaux à cet effet avec un support insoluble pour l'immobilisation de composés immunochimiques

Abrégé

A phase interpolator for generating a phase interpolated output signal between two phase separated input signals received at two phase separated input signal nodes may include a plurality of circuit elements. The plurality of circuit elements may include at least one of resistors or capacitors, in a series arrangement between the two phase separated input signal nodes, where respective connection points between respective ones of the plurality of circuit elements may provide at least one intermediate phase interpolated signal. The phase interpolator may also include selection circuitry, which may be configured to select the phase interpolated output signal from the at least one intermediate phase interpolated signal.

Classes IPC  ?

• H04L 7/00 - Dispositions pour synchroniser le récepteur avec l'émetteur
• H04L 7/033 - Commande de vitesse ou de phase au moyen des signaux de code reçus, les signaux ne contenant aucune information de synchronisation particulière en utilisant les transitions du signal reçu pour commander la phase de moyens générateurs du signal de synchronisation, p. ex. en utilisant une boucle verrouillée en phase

Abrégé

The present disclosure relates to imaging systems having functionality for detecting faults in the control and/or readout of the image sensor. In one example, there is a system comprising an image sensor having a plurality of imaging pixels and at least one diagnostic pixel coupled to a reference signal. The system also comprises control and readout circuitry configured to select one or more of the imaging pixels and, for each selected imaging pixel, readout an imaging signal that is indicative of the charge accumulated on the selected imaging pixel, select the at least one diagnostic pixel and, for each selected diagnostic pixel, readout a diagnostic signal that is indicative of the reference signal of the selected diagnostic pixel, and output the diagnostic signal for use in system diagnostics.

Classes IPC  ?

• H04N 25/703 - Architectures de capteurs SSIS incorporant des pixels pour produire des signaux autres que des signaux d'image
• H04N 17/00 - Diagnostic, test ou mesure, ou leurs détails, pour les systèmes de télévision
• H04N 25/78 - Circuits de lecture pour capteurs adressés, p. ex. amplificateurs de sortie ou convertisseurs A/N

Abrégé

CT ADCs based on continuous-time residue generation systems require accurate estimation of analog transfer functions. This is done by using a pseudo random bit sequence, injected using a DAC, that traverses the transfer function to be measured. Mismatch in the injection DAC introduces errors in the transfer function estimation and results in poor NSD at the ADC output. Techniques are described to improve the accuracy of the transfer function estimate despite DAC mismatch and despite the presence of an input signal.

Classes IPC  ?

• H03M 1/50 - Convertisseurs analogiques/numériques avec conversion intermédiaire en intervalle de temps
• H03M 1/10 - Calibrage ou tests
• H03M 1/20 - Augmentation de la résolution par l'utilisation d'un système à n bits pour obtenir n+m bits, p. ex. par addition d'un signal aléatoire
• H03M 1/66 - Convertisseurs numériques/analogiques

Abrégé

Apparatus and methods for dielectric resonator antennas are disclosed herein. In certain embodiments, a dielectric resonator antenna includes a dielectric body, one or more signal conductors formed in the dielectric body and configured to handle a radio frequency wave, and one or more signal ports on an outer surface of the dielectric body and connected to the one or more signal conductors. The dielectric resonator antenna is mountable to a circuit board (for instance, to a PCB), with the one or more signal ports serving as an interface between the dielectric resonator antenna and the circuit board. Such an interface can further include one or more ground ports.

Classes IPC  ?

• H01Q 9/04 - Antennes résonnantes
• H01Q 1/48 - Moyens de mise à la terreÉcrans de terreContrepoids
• H01Q 21/06 - Réseaux d'unités d'antennes, de même polarisation, excitées individuellement et espacées entre elles

Abrégé

The present disclosure relates to an oscillator circuit comprising: a controller configured to generate a frequency control signal, the frequency control signal comprising a first frequency control value; a digitally controlled oscillator (DCO) configured to generate, based on the frequency control signal, an oscillator output signal, wherein the output signal is generated at a first frequency in response to the first frequency control value of the frequency control signal; and a digital feedback circuit configured to receive the output signal and output a first feedback signal, wherein the oscillator circuit is configured such that the first frequency is dependent on, or based at least in part on, a value of the first feedback signal, wherein the controller is configured provide a first control instruction to instruct the digital feedback circuit to update the first feedback signal, wherein the digital feedback circuit is configured to, in response to the first control instruction: measure the first frequency of the output signal; and adjust the value of the first feedback signal to reduce an error between the first frequency and a first target frequency.

Classes IPC  ?

• H03L 7/099 - Détails de la boucle verrouillée en phase concernant principalement l'oscillateur commandé de la boucle
• H03L 7/18 - Synthèse de fréquence indirecte, c.-à-d. production d'une fréquence désirée parmi un certain nombre de fréquences prédéterminées en utilisant une boucle verrouillée en fréquence ou en phase en utilisant un diviseur de fréquence ou un compteur dans la boucle

Abrégé

Embodiments of the invention relate to a clock generation and distribution circuit (“clock circuit”) according to various embodiments of the present disclosure. The clock circuit comprises active impedance reduction circuits which improves bandwidth and jitter performance of the clock circuit by lowering the small-signal impedance within the clock circuit. In certain embodiments, an activation element is positioned at a node along a transmission path to cause a reduction in impedance.

Classes IPC  ?

• H03K 3/013 - Modifications du générateur en vue d'éviter l'action du bruit ou des interférences
• H03K 17/687 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
• H03K 19/20 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion caractérisés par la fonction logique, p. ex. circuits ET, OU, NI, NON

Abrégé

A method is provided for managing data between an ECU and a remote node. The aspects include receiving a PDU from the ECU and differentiating between mailbox data and streaming data being included in the PDU. The mailbox data is required to be received in order and to be intolerable of a data loss. The streaming data is tolerable of the data loss. The aspects include comparing a sequence number of the PDU found in a sequence number field of the PDU to an expected sequence number of the PDU, the sequence number of the PDU being: incremented by one for each transmitted frame; configured to roll over to one; and equal to zero only responsive to an unexpected reset of the remote node. The aspects include sending a message to the ECU indicating a mismatch, responsive to the sequence number of the PDU mismatching the expected sequence number.

Classes IPC  ?

• H04L 47/34 - Commande de fluxCommande de la congestion en assurant l'intégrité de la séquence, p. ex. en utilisant des numéros de séquence
• H04L 47/32 - Commande de fluxCommande de la congestion en supprimant ou en retardant les unités de données, p. ex. les paquets ou les trames
• H04L 67/12 - Protocoles spécialement adaptés aux environnements propriétaires ou de mise en réseau pour un usage spécial, p. ex. les réseaux médicaux, les réseaux de capteurs, les réseaux dans les véhicules ou les réseaux de mesure à distance

Abrégé

A system for reducing clock jitter may include first jitter reducing circuitry. The first jitter reducing circuitry may be arranged between an input clock signal node carrying an input clock signal and an output clock signal node carrying an output clock signal. The first jitter reducing circuitry may include a first intermediate input clock signal node and a first intermediate output clock signal node. The first jitter reducing circuitry may include a first clock delay circuit, which may be configured to: (1) delay a first intermediate input clock signal received on the first intermediate input clock signal node by an odd integer multiple of one half of a period, and (2) invert the first intermediate input clock signal. The first jitter reducing circuitry may also include a first connection, which may be from the first intermediate output clock signal node to the first intermediate input clock signal node.

Classes IPC  ?

• H03B 5/08 - Éléments déterminant la fréquence comportant des inductances ou des capacités localisées
• H03K 5/01 - Mise en forme d'impulsions
• H03K 5/00 - Transformation d'impulsions non couvertes par l'un des autres groupes principaux de la présente sous-classe

Abrégé

The present disclosure provides sensor assemblies comprising a plurality of mixing species provided adjacent or on the sensing surface, wherein each mixing species comprises a polynucleotide chain and wherein each mixing species is anchored to the sensor assembly; and an actuation unit configured to move at least a part of each mixing species in a plurality of directions. Alternatively or additionally, the polynucleotide chain comprises DNA and has a length of at least 10 nm.

Classes IPC  ?

• C12Q 1/6825 - Détecteurs faisant intervenir la détection d’acides nucléiques
• B01F 25/00 - Mélangeurs à écoulementMélangeurs pour matières tombantes, p. ex. particules solides

Abrégé

A radio frequency stacked die assembly can include a laminate substrate with a layer of conductive traces between a first plurality of laminate layers. The stacked die assembly can include surface mount antenna packages mounted to an exterior surface of the substrate, each antenna package including a radio frequency patch antenna embedded within a second plurality of laminate layers. The stacked die assembly further includes one or more surface mount passive devices and a flip chip semiconductor die mounted to opposite sides of the substrate. A plurality of solder balls are provided for mounting the substrate to a printed circuit board. The flip chip die, radio frequency antennas, passive devices, and solder balls are connected by the layer of conductive traces. Separating the patch antenna(s) from the substrate and into an antenna package simplifies construction and testing of the stacked die assembly, and can yield improved antenna performance.

Classes IPC  ?

• H01L 23/66 - Adaptations pour la haute fréquence
• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01Q 1/38 - Forme structurale pour éléments rayonnants, p. ex. cône, spirale, parapluie formés par une couche conductrice sur un support isolant

Abrégé

Apparatus and methods for nanoplasma switches are disclosed. In certain embodiments, a nanoplasma switching system includes a nanoplasma radio frequency (RF) switch that receives an RF signal, and a nanoplasma DC switch that receives a DC bias voltage. The nanoplasma DC switch is positioned adjacent to but spaced apart from the nanoplasma RF switch. The nanoplasma DC switch induces a nanoplasma through the nanoplasma RF switch when the DC bias voltage is set to a first voltage level. By implementing the nanoplasma switching system in this manner, DC bias to turn on or off the nanoplasma RF switch can be realized without needing to use passive components such as DC blocking capacitors, choke inductors, or baluns for isolation.

Classes IPC  ?

• H05H 1/46 - Production du plasma utilisant des champs électromagnétiques appliqués, p. ex. de l'énergie à haute fréquence ou sous forme de micro-ondes
• H05K 1/16 - Circuits imprimés comprenant des composants électriques imprimés incorporés, p. ex. une résistance, un condensateur, une inductance imprimés

Abrégé

The present disclosure provides sensor assemblies comprising a plurality of mixing species provided adjacent or on the sensing surface, wherein each mixing species comprises a polynucleotide chain and wherein each mixing species is anchored to the sensor assembly; and an actuation unit configured to move at least a part of each mixing species in a plurality of directions. Alternatively or additionally, the polynucleotide chain comprises DNA and has a length of at least 10 nm.

Classes IPC  ?

• G01N 27/327 - Électrodes biochimiques
• B01L 3/00 - Récipients ou ustensiles pour laboratoires, p. ex. verrerie de laboratoireCompte-gouttes
• C12Q 1/6825 - Détecteurs faisant intervenir la détection d’acides nucléiques

Abrégé

Aspects of the present disclosure include a battery measurement system having a plurality of capacitors, a plurality of probes each electrically coupled with a corresponding capacitor of the plurality of capacitors and a corresponding battery of a plurality of batteries, a controller configured to measure, via the plurality of probes, a plurality of voltages associated with the plurality of batteries in response to an interrogatory current, and a plurality of sense cables each associated with the corresponding battery of the plurality of batteries, wherein each sense cable of the plurality of sense cables is disposed across the corresponding battery such that the interrogatory current flows in a conduction channel in the corresponding battery in a first direction and in the corresponding cable in a second direction substantially opposite of the first direction.

Classes IPC  ?

• G01R 1/073 - Sondes multiples
• G01R 31/3842 - Dispositions pour la surveillance de variables des batteries ou des accumulateurs, p. ex. état de charge combinant des mesures de tension et de courant
• H01M 50/51 - Connexion seulement en série

Abrégé

Aspects of the present disclosure include a battery measurement system having a plurality of capacitors, a plurality of probes each electrically coupled with a corresponding capacitor of the plurality of capacitors and a corresponding battery of a plurality of batteries, a controller configured to measure, via the plurality of probes, a plurality of voltages associated with the plurality of batteries in response to an interrogatory current, and a plurality of sense cables each associated with the corresponding battery of the plurality of batteries, wherein each sense cable of the plurality of sense cables is disposed across the corresponding battery such that the interrogatory current flows in a conduction channel in the corresponding battery in a first direction and in the corresponding cable in a second direction substantially opposite of the first direction.

Classes IPC  ?

• G01R 19/165 - Indication de ce qu'un courant ou une tension est, soit supérieur ou inférieur à une valeur prédéterminée, soit à l'intérieur ou à l'extérieur d'une plage de valeurs prédéterminée
• G01R 31/396 - Acquisition ou traitement de données pour le test ou la surveillance d’éléments particuliers ou de groupes particuliers d’éléments dans une batterie

Abrégé

Apparatus and methods for nanoplasma switches are disclosed. In certain embodiments, a nanoplasma switching system includes a nanoplasma radio frequency (RF) switch that receives an RF signal, and a nanoplasma DC switch that receives a DC bias voltage. The nanoplasma DC switch is positioned adjacent to but spaced apart from the nanoplasma RF switch. The nanoplasma DC switch induces a nanoplasma through the nanoplasma RF switch when the DC bias voltage is set to a first voltage level. By implementing the nanoplasma switching system in this manner, DC bias to turn on or off the nanoplasma RF switch can be realized without needing to use passive components such as DC blocking capacitors, choke inductors, or baluns for isolation.

Classes IPC  ?

• H03K 17/693 - Dispositifs de commutation comportant plusieurs bornes d'entrée et de sortie, p. ex. multiplexeurs, distributeurs
• H01J 37/32 - Tubes à décharge en atmosphère gazeuse
• H03K 17/88 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de tubes à déviation de faisceau

Abrégé

The present disclosure provides an improved time-of-flight system. The ToF system includes an image sensor, a controller and a light source. The controller is configured to determine at least one of a cyclic error or an offset error of the ToF system. The ToF system modifies the operation of the light source to reduce the cyclic or offset error.

Classes IPC  ?

• G01S 17/894 - Imagerie 3D avec mesure simultanée du temps de vol sur une matrice 2D de pixels récepteurs, p. ex. caméras à temps de vol ou lidar flash
• G01S 7/4911 - Émetteurs
• G01S 7/4915 - Mesure du temps de retard, p. ex. détails opérationnels pour les composants de pixelsMesure de la phase
• G01S 7/497 - Moyens de contrôle ou de calibrage

Abrégé

The present disclosure provides an improved time-of-flight (ToF) system. The ToF system includes a light source, a main image and a plurality of secondary image sensors. A controller is configured to determine an error of the ToF system based on charge accumulated by the plurality of secondary image sensors. The controller may be configured to determine a ToF distance measurement using the main image sensor. The error determined using the plurality of secondary image sensors may be used to correct the ToF distance measurement, improving the accuracy of the ToF system.

Classes IPC  ?

• G01S 7/497 - Moyens de contrôle ou de calibrage
• G01S 17/894 - Imagerie 3D avec mesure simultanée du temps de vol sur une matrice 2D de pixels récepteurs, p. ex. caméras à temps de vol ou lidar flash

Abrégé

The present disclosure relates to a time-of-flight (ToF) system, and in particular a system which includes a controller, a light source, a first image sensor and a second image sensor. An optical path of a known distance is present between the light source and the second image sensor. The controller may be configured to determine a characteristic of the received light at the second image sensor and compare this characteristic to known values. The optical path may include an optical control switch for allowing or preventing transmission of light down the optical path.

Classes IPC  ?

• G01S 17/89 - Systèmes lidar, spécialement adaptés pour des applications spécifiques pour la cartographie ou l'imagerie
• G01S 7/481 - Caractéristiques de structure, p. ex. agencements d'éléments optiques
• G01S 7/497 - Moyens de contrôle ou de calibrage
• G01S 17/32 - Systèmes déterminant les données relatives à la position d'une cible pour mesurer la distance uniquement utilisant la transmission d'ondes continues, soit modulées en amplitude, en fréquence ou en phase, soit non modulées

Abrégé

There is provided a continuous wave time of flight, CW-ToF, camera system comprising: a laser for emitting laser light; an imaging sensor, the image sensor comprising a pixel array for accumulating charge based on incident light comprising reflected laser light off an object, the pixel array comprising a plurality of rows of pixels; and a control system coupled to the imaging sensor and configured to control the pixel array to: reset at least a first row and a second row of the plurality of rows, wherein the first row and the second row are adjacent one another in the pixel array; accumulate charge in the pixels of the pixel array using a first integration setting for a first time period; reset the first row of the plurality of rows; accumulate charge in the pixels of the pixel array using the first integration setting or a second integration setting for a second time period subsequent to the first time period; read out a set of charge samples, wherein the first row contains a first charge from accumulating after the second time period and the second row contains a second charge from accumulating after the first and second time periods; and use the set of charge samples to approximate a charge from sampling after the first time period.

Classes IPC  ?

• G01S 17/894 - Imagerie 3D avec mesure simultanée du temps de vol sur une matrice 2D de pixels récepteurs, p. ex. caméras à temps de vol ou lidar flash
• G01S 7/481 - Caractéristiques de structure, p. ex. agencements d'éléments optiques
• G01S 7/4915 - Mesure du temps de retard, p. ex. détails opérationnels pour les composants de pixelsMesure de la phase

Abrégé

The present disclosure provides an improved indirect time-of-flight (iToF) system. The iToF system includes an imager and a laser driver system. The laser driver system receives an analog laser control signal from the imager, generating an analog laser driver current based on the analog laser control signal. The analog laser driver current is generated such that any change in an amplitude of the analog laser control signal causes a change in an amplitude of the analog laser drive current. Further, the present disclosure provides improved imagers and laser driver systems for use in an indirect time-of-flight system. An indirect time-of-flight system including a high-side multiplicative push-pull current mirror is also provided.

Classes IPC  ?

• G01S 7/4911 - Émetteurs
• G01S 7/481 - Caractéristiques de structure, p. ex. agencements d'éléments optiques
• G01S 17/894 - Imagerie 3D avec mesure simultanée du temps de vol sur une matrice 2D de pixels récepteurs, p. ex. caméras à temps de vol ou lidar flash
• H01S 5/042 - Excitation électrique
• H01S 5/183 - Lasers à émission de surface [lasers SE], p. ex. comportant à la fois des cavités horizontales et verticales comportant uniquement des cavités verticales, p. ex. lasers à émission de surface à cavité verticale [VCSEL]

Abrégé

The present disclosure provides an improved indirect time-of-flight (iToF) system. The iToF system includes an imager and a laser driver system. The laser driver system receives an analog laser control signal from the imager, generating an analog laser driver current based on the analog laser control signal. The analog laser driver current is generated such that any change in an amplitude of the analog laser control signal causes a change in an amplitude of the analog laser drive current. Further, the present disclosure provides improved imagers and laser driver systems for use in an indirect time-of-flight system. An indirect time-of-flight system including a high-side multiplicative push-pull current mirror is also provided.

Classes IPC  ?

• H01S 5/042 - Excitation électrique
• G01S 17/894 - Imagerie 3D avec mesure simultanée du temps de vol sur une matrice 2D de pixels récepteurs, p. ex. caméras à temps de vol ou lidar flash
• H01S 5/0683 - Stabilisation des paramètres de sortie du laser en surveillant les paramètres optiques de sortie

Abrégé

The present disclosure provides a magnetic multi-turn sensor that makes use of a divider type structure. In this respect, a magnetoresistive track is laid out in a loop comprising a plurality of divider portions along at least one side of the loop, the divider portions each being formed as a loop or an arch of magnetoresistive material. Adjacent divider portions are connected by a connecting loop of magnetic material. The legs of the connecting loop are formed over the top of the legs of the divider portions, to thereby form connecting legs with dead ends. In some examples, in the region of the connecting legs, a spacer is also provided between the magnetoresistive track and the magnetic connecting loop. In further arrangements described herein, a siphon structure is provided before the Y-junction of adjacent divider portions.

Classes IPC  ?

• G01D 5/16 - Moyens mécaniques pour le transfert de la grandeur de sortie d'un organe sensibleMoyens pour convertir la grandeur de sortie d'un organe sensible en une autre variable, lorsque la forme ou la nature de l'organe sensible n'imposent pas un moyen de conversion déterminéTransducteurs non spécialement adaptés à une variable particulière utilisant des moyens électriques ou magnétiques influençant la valeur d'un courant ou d'une tension en faisant varier la résistance

Abrégé

There is provided a continuous wave time of flight, CW-ToF, camera system comprising: a laser for emitting laser light; an imaging sensor, the image sensor comprising a pixel array for accumulating charge based on incident light comprising reflected laser light off an object, the pixel array comprising a plurality of rows of pixels; and a control system coupled to the imaging sensor and configured to control the pixel array to: identify at least a first row and a second row of the plurality of rows, wherein the first row and the second row are adjacent one another in the pixel array; accumulate charge in the pixels of the first row using a first integration setting for a first time period; accumulate charge in the pixels of the second row using a second integration setting for the first time period; and read out a set of charge samples, wherein the first row contains a first charge from accumulating using the first integration setting and the second row contains a second charge from accumulating using the second integration setting, and wherein the second integration setting is phase delayed relative to the first integration setting.

Classes IPC  ?

• G01S 17/894 - Imagerie 3D avec mesure simultanée du temps de vol sur une matrice 2D de pixels récepteurs, p. ex. caméras à temps de vol ou lidar flash
• G01S 7/4863 - Réseaux des détecteurs, p. ex. portes de transfert de charge
• G01S 7/4865 - Mesure du temps de retard, p. ex. mesure du temps de vol ou de l'heure d'arrivée ou détermination de la position exacte d'un pic

Abrégé

This disclosure relates to providing an improved synchronization circuit for a sampling device. In particular, it relates to providing a time-to-digital converter for improving the accuracy of a synchronization circuit for a data sampling device.

Classes IPC  ?

• H03L 7/091 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie le détecteur de phase ou de fréquence utilisant un dispositif d'échantillonnage
• H03L 7/081 - Détails de la boucle verrouillée en phase avec un déphaseur commandé additionnel
• H03M 3/00 - Conversion de valeurs analogiques en, ou à partir d'une modulation différentielle

Abrégé

An integrated circuit package can contain a semiconductor die and provide electrical connections between the semiconductor die and additional electronic components. The integrated circuit package can reduce stress placed on the semiconductor die due to movement of the integrated circuit package due to, for example, temperature changes and/or moisture levels. The integrated circuit package can at least partially mechanically isolate the semiconductor die from the integrated circuit package.

Classes IPC  ?

• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 21/52 - Montage des corps semi-conducteurs dans les conteneurs
• H01L 23/06 - ConteneursScellements caractérisés par le matériau du conteneur ou par ses propriétés électriques
• H01L 23/20 - Matériaux de remplissage caractérisés par le matériau ou par ses propriétes physiques ou chimiques, ou par sa disposition à l'intérieur du dispositif complet gazeux à la température normale de fonctionnement du dispositif
• H01L 23/498 - Connexions électriques sur des substrats isolants

Abrégé

An adaptable, generalized digital predistortion system that can increase the accuracy of the distortion applied to a power amplifier input signal is disclosed. Further, the digital predistortion system can be implemented using a reduced circuit area by reducing a number of coefficients used by the models applied to generate the distortion compensation signal. Further, the system can implement an improved digital predistortion adaptation engine that can improve one or more of the following metrics of a complete radio frequency (RF) analog front-end radio signal chain: error vector magnitude (EVM), adjacent channel leakage ratio (ACLR), spectrum emission mask (SEM), and power consumption of the circuits and systems. An example of circuits and systems is a radio frequency power amplifier (PA).

Classes IPC  ?

• H04B 1/04 - Circuits
• H04B 1/00 - Détails des systèmes de transmission, non couverts par l'un des groupes Détails des systèmes de transmission non caractérisés par le milieu utilisé pour la transmission
• H04L 27/26 - Systèmes utilisant des codes à fréquences multiples

Abrégé

A network interface module for coupling a host device to a switched network as a network node is described. The network interface module comprises a single half-duplex port for communicatively coupling to a shared bus of the switched network, at least one frame queue sized to store one multicast read frame received via the shared bus, and logic circuitry. The logic circuitry is configured to decode a read command for the interface module included in a payload of the multicast read frame that includes multiple read commands for other network nodes of the switched network, and transmit a response frame including read data on the shared bus when detecting the shared bus is available for transmitting.

Classes IPC  ?

• G06F 13/42 - Protocole de transfert pour bus, p. ex. liaisonSynchronisation
• H04L 12/18 - Dispositions pour la fourniture de services particuliers aux abonnés pour la diffusion ou les conférences
• H04L 12/413 - Réseaux à ligne bus avec commande décentralisée avec accès aléatoire, p. ex. accès multiple avec détection de porteuse et détection de collision [CSMA-CD]
• H04L 47/62 - Ordonnancement des files d’attente caractérisé par des critères d’ordonnancement

Abrégé

A system and method are described for monitoring batteries at various phases of their lifecycle. The batteries may be monitored in non-operational and operational states. The monitoring may be done wirelessly. The information gathered from monitoring the batteries may be used to make decisions about the use of a battery.

Classes IPC  ?

• G01R 31/392 - Détermination du vieillissement ou de la dégradation de la batterie, p. ex. état de santé
• G01R 31/367 - Logiciels à cet effet, p. ex. pour le test des batteries en utilisant une modélisation ou des tables de correspondance
• G01R 31/371 - Dispositions pour le test, la mesure ou la surveillance de l’état électrique d’accumulateurs ou de batteries, p. ex. de la capacité ou de l’état de charge avec indication à distance, p. ex. sur des chargeurs séparés
• G01R 31/382 - Dispositions pour la surveillance de variables des batteries ou des accumulateurs, p. ex. état de charge
• H01M 10/42 - Procédés ou dispositions pour assurer le fonctionnement ou l'entretien des éléments secondaires ou des demi-éléments secondaires
• H01M 10/48 - Accumulateurs combinés à des dispositions pour mesurer, tester ou indiquer l'état des éléments, p. ex. le niveau ou la densité de l'électrolyte

Abrégé

The present disclosure relates to a lower energy/faster time of flight camera system configured to measure distance to an object. The system is configured to emit laser light modulated with a first frequency and image light reflected by an object in order to determine a first phase difference between the emitted and reflected light. It then emits laser light modulated with a second frequency and images light reflected by the object to determine a second phase difference between the emitted and reflected light. The distance to the object is determined using the first and second phase differences. The system operates at lower energy for obtaining the first phase difference compared with the operation to obtain the second phase difference. This results in lower overall energy consumption, and potentially also faster overall operation, compared with previous continuous wave time of flight systems, without any significant reduction in accuracy of imaging.

Classes IPC  ?

• G01S 17/894 - Imagerie 3D avec mesure simultanée du temps de vol sur une matrice 2D de pixels récepteurs, p. ex. caméras à temps de vol ou lidar flash
• G01B 11/22 - Dispositions pour la mesure caractérisées par l'utilisation de techniques optiques pour mesurer la profondeur
• G01S 7/481 - Caractéristiques de structure, p. ex. agencements d'éléments optiques
• G01S 7/4911 - Émetteurs
• H04N 25/44 - Extraction de données de pixels provenant d'un capteur d'images en agissant sur les circuits de balayage, p. ex. en modifiant le nombre de pixels ayant été échantillonnés ou à échantillonner en lisant partiellement une matrice de capteurs SSIS
• H04N 25/46 - Extraction de données de pixels provenant d'un capteur d'images en agissant sur les circuits de balayage, p. ex. en modifiant le nombre de pixels ayant été échantillonnés ou à échantillonner en combinant ou en groupant les pixels
• H04N 25/709 - Circuits de commande de l'alimentation électrique
• H04N 25/75 - Circuits pour fournir, modifier ou traiter des signaux d'image provenant de la matrice de pixels

Abrégé

A voltage monitor circuit that signals if an input voltage is above or below an internally established reference level proportional to the bandgap voltage of silicon. The voltage monitor circuit mitigates main error sources generally associated with bandgap reference generation such that high accuracy and good performance may be achieved at low power cost. The techniques allow voltage monitors (e.g., brown-out and power on reset (POR) detectors) to be implemented with higher accuracy, lower power consumption, smaller area cost, and support to lower supply voltage than other solutions.

Classes IPC  ?

• G01R 19/165 - Indication de ce qu'un courant ou une tension est, soit supérieur ou inférieur à une valeur prédéterminée, soit à l'intérieur ou à l'extérieur d'une plage de valeurs prédéterminée
• G01R 19/00 - Dispositions pour procéder aux mesures de courant ou de tension ou pour en indiquer l'existence ou le signe

Abrégé

A voltage monitor circuit that signals if an input voltage is above or below an internally established reference level proportional to the bandgap voltage of silicon. The voltage monitor circuit mitigates main error sources generally associated with bandgap reference generation such that high accuracy and good performance may be achieved at low power cost. The techniques allow voltage monitors (e.g., brown-out and power on reset (POR) detectors) to be implemented with higher accuracy, lower power consumption, smaller area cost, and support to lower supply voltage than other solutions.

Classes IPC  ?

• G01R 19/165 - Indication de ce qu'un courant ou une tension est, soit supérieur ou inférieur à une valeur prédéterminée, soit à l'intérieur ou à l'extérieur d'une plage de valeurs prédéterminée

Abrégé

Aspects of this disclosure relate to a power amplifier circuit that is programmable for variations in load impedance. In certain embodiments, the power amplifier circuit includes two power amplifier segments in parallel with each other that drive a load impedance that varies. Each power amplifier segment includes a power amplifier core. At least one of the amplifier segments is programmable based on the impedance of the load.

Classes IPC  ?

• H03F 1/56 - Modifications des impédances d'entrée ou de sortie, non prévues ailleurs
• H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
• H03F 1/32 - Modifications des amplificateurs pour réduire la distorsion non linéaire
• H03F 3/24 - Amplificateurs de puissance, p. ex. amplificateurs de classe B, amplificateur de classe C d'étages transmetteurs de sortie

Abrégé

Aspects of this disclosure relate to a radio frequency system with power amplifier programming for antenna impedance variation. In certain embodiments, the radio frequency system includes a phased antenna array and a plurality of power amplifiers configured to drive the phased antenna array. A first power amplifier is programmable based on an impedance of a first antenna element of the phased antenna array. The radio frequency system is operable to perform beam scanning, and the impedance of the first antenna element varies as the radio frequency system performs beam scanning.

Classes IPC  ?

• H03F 3/24 - Amplificateurs de puissance, p. ex. amplificateurs de classe B, amplificateur de classe C d'étages transmetteurs de sortie
• H03F 1/56 - Modifications des impédances d'entrée ou de sortie, non prévues ailleurs

Abrégé

Aspects of this disclosure relate to generating calibration data for power amplifier programming for load impedance variation. In certain embodiments, generating calibration data includes determining one or more power amplifier parameters for a power amplifier driving a load for different impedance values of the load. The one or more power amplifier parameters can be stored to memory for the different impedance values such that the one or more power amplifier parameters for the different impedance values are accessible to program the power amplifier.

Classes IPC  ?

• H03F 1/56 - Modifications des impédances d'entrée ou de sortie, non prévues ailleurs
• H01Q 3/28 - Dispositifs pour changer ou faire varier l'orientation ou la forme du diagramme de directivité des ondes rayonnées par une antenne ou un système d'antenne faisant varier la phase relative ou l’amplitude relative et l’énergie d’excitation entre plusieurs éléments rayonnants actifsDispositifs pour changer ou faire varier l'orientation ou la forme du diagramme de directivité des ondes rayonnées par une antenne ou un système d'antenne faisant varier la distribution de l’énergie à travers une ouverture rayonnante faisant varier l'amplitude
• H03F 3/24 - Amplificateurs de puissance, p. ex. amplificateurs de classe B, amplificateur de classe C d'étages transmetteurs de sortie

Abrégé

A photometry device can include a first LED to emit light to a target in response to a first current through the first LED, a second LED to emit light to the target in response to a second current through the second LED, and an inductor, coupled to the first and second LEDs, to store energy associated with at least one of the first and second currents.

Classes IPC  ?

• A61B 5/1455 - Mesure des caractéristiques du sang in vivo, p. ex. de la concentration des gaz dans le sang ou de la valeur du pH du sang en utilisant des capteurs optiques, p. ex. des oxymètres à photométrie spectrale
• A61B 5/00 - Mesure servant à établir un diagnostic Identification des individus
• G01J 1/08 - Agencements des sources lumineuses spécialement adaptées à la photométrie
• G01J 1/46 - Circuits électriques utilisant une capacité

Abrégé

A system for monitoring impedance of an electrical connection device includes a first connection port, a second connection port, a first impedance element, an analog-to-digital converter (ADC), clamping circuitry, and processing subsystem. The first connection port is configured to be electrically coupled to a first side of the electrical connection device, and the second connection port is configured to be electrically coupled to a second side of the electrical connection device. The ADC includes a first input port and a second input port. The first input port is electrically coupled to the first connection port, and the second input port is electrically coupled to the second connection port via the first impedance element. The clamping circuitry is electrically coupled to at least one of the first input port and the second input port. The processing subsystem is configured to determine impedance of the electrical connection device.

Classes IPC  ?

• G01R 27/02 - Mesure de résistances, de réactances, d'impédances réelles ou complexes, ou autres caractéristiques bipolaires qui en dérivent, p. ex. constante de temps
• G01R 19/165 - Indication de ce qu'un courant ou une tension est, soit supérieur ou inférieur à une valeur prédéterminée, soit à l'intérieur ou à l'extérieur d'une plage de valeurs prédéterminée
• H02H 3/08 - Circuits de protection de sécurité pour déconnexion automatique due directement à un changement indésirable des conditions électriques normales de travail avec ou sans reconnexion sensibles à une surcharge