A processor core is accessed. The core is configured to execute instructions associated with an instruction set architecture (ISA). The core comprises a plurality of compute slices, a plurality of barrier register files, and a control unit. Each compute slice includes at least one arithmetic logic unit (ALU), a local register file, and is coupled to a successor compute slice and a predecessor compute slice by a barrier register file. Code associated with the ISA is evaluated, where the code includes a first loop. The evaluating includes generating iteration transfer information associated with the first loop. Each slice task within a plurality of slice tasks associated with the first loop is distributed to a compute slice. The processor core executes the plurality of slice tasks. Data forwarding between successive compute slices is based on the plurality of barrier register files and the iteration transfer information.
A processing unit is accessed that includes a plurality of compute slices, a control unit, and a global aliasing table (GAT). Each compute slice within the plurality of compute slices includes at least one execution unit, is known to a compiler, and is coupled to a successor compute slice and a predecessor compute slice. A first compute slice executes a load instruction. The load instruction is associated with a target address. The load instruction is predicted that it will alias with a previous store instruction. The previous store instruction executes on a previous compute slice among the plurality of compute slices. The predicting is based on the GAT. The load instruction is stalled until the previous store instruction completes execution on the previous compute slice. The load instruction is allowed to execute. The predicting includes searching, in the GAT, for an entry which includes the load instruction.
Techniques for checking memory operations are disclosed. A processing unit is accessed, comprising compute slices, control unit, local memory disambiguation units (LMDUs), and a global MDU (GMDU). Each slice includes an execution unit and is coupled to successor and predecessor slices. Each slice is coupled to an LMDU. Each LMDU is coupled to the GMDU. A first slice executes a first slice task. The task includes a load instruction and address. The slice issues the load to an LMDU, saving load information in a memory operation table (MOT). For a not fully serviced load instruction, the LMDU sends the load information to the GMDU, storing load information in a global MOT (GMOT). The GMOT detects address aliasing between the load address and a previously issued address saved in the GMOT. The GMOT forwards memory information from previously issued memory instructions to the MOT to satisfy the load instruction.
A processing unit is accessed, comprising compute slices, a control unit, local memory disambiguation units (LMDUs), and memory system. Each slice includes an execution unit and is coupled to successor and predecessor slices. Each slice is coupled to an LMDU. The control unit distributes a first slice task to a first slice coupled to a first LMDU. The first slice executes the first task. The task includes a load instruction including a load address. The first slice issues the load instruction to the first LMDU. The issuing saves load information in a memory operation table (MOT) within the LMDU. The LMDU detects, based on the MOT, address aliasing between the load address and a store address of a previous store instruction. The MOT forwards store information from the previous store instruction. The store information satisfies one or more bytes of data required for the load instruction.
Techniques for parallel generation of blocks using a compiler are disclosed. A processing unit comprising compute slices, barrier register sets, a control unit, and a memory system is accessed. Each compute slice includes an execution unit and is coupled to other compute slices by a barrier register set. A compiler evaluates a compiled program that includes basic blocks, based on a control flow graph. A first hyperblock is created from at least two basic blocks. One or more branch instructions are replaced with skip instructions that direct instruction execution between basic blocks in the hyperblock. A first slice task is allocated to a first compute slice. A second slice task is allotted based on branch prediction. Pointers to the first compute slice and the second compute slice are initialized. The compiled program is executed, beginning with the first compute slice.
Techniques for managing compute slice tasks are disclosed. A processing unit comprising compute slices, load-store units (LSUs), a control unit, and a memory system is accessed. The compute slices are coupled. Each compute slice includes an LSU which is coupled to a predecessor LSU and a successor LSU. A compiled program is executed as the control unit distributes slice tasks to the compute slices for execution. A slice task, which includes a load instruction, is distributed to a current compute slice. The current compute slice can execute the slice task speculatively. A previously executed store instruction is committed to memory by a predecessor LSU. Address aliasing is checked between an address associated with the previously executed store instruction and the load address associated with the load instruction. The slice task running on the current compute slice can be cancelled when aliasing is detected.
Techniques for managing compute slice tasks are disclosed. A processing unit comprising compute slices, load-store units (LSUs), a control unit, and a memory system is accessed. The compute slices are coupled. Each compute slice includes an LSU which is coupled to a predecessor LSU and a successor LSU. A compiled program is executed as the control unit distributes slice tasks to the compute slices for execution. A slice task, which includes a load instruction, is distributed to a current compute slice. The current compute slice can execute the slice task speculatively. A previously executed store instruction is committed to memory by a predecessor LSU. Address aliasing is checked between an address associated with the previously executed store instruction and the load address associated with the load instruction. The slice task running on the current compute slice can be cancelled when aliasing is detected.
Techniques for monitoring block moves in an array of compute elements and applying backpressure are disclosed. An array of compute elements is accessed. The array of compute elements is coupled to at least one data cache. The data cache provides memory' storage for the array of compute elements. Control for the array of compute elements is enabled by a stream of wide control words generated by the compiler. A load address and a store address comprising memory block move addresses are generated. The memory block move addresses point to memory' storage locations in the at least one data cache. Load buffers are coupled to the array of compute elements. The load buffers are located adjacent to at least one edge of the array of compute elements. A memory block move is executed using at least one of the load buffers, based on the memory block move addresses.
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
G06F 9/38 - Exécution simultanée d'instructions, p. ex. pipeline ou lecture en mémoire
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p. ex. plusieurs processeurs de données à instruction unique
9.
PARALLEL PROCESSING ARCHITECTURE WITH BLOCK MOVE SUPPORT
Techniques for task processing are disclosed. An array of compute elements is accessed. Each compute element within the array is known to a compiler and is coupled to its neighboring compute elements. The array of compute elements is coupled to at least one data cache. The data cache provides memory storage for the array. Control for the compute elements is provided on a cycle-by-cycle basis. Control is enabled by a stream of wide control words generated by the compiler. A load address and a store address are generated. The load and the store addresses comprise memory block move addresses. The memory block move addresses point to memory storage locations in the data cache. A memory block move is executed, based on the memory block move addresses. The data for the memory block move is transferred outside of the array.
G06F 9/48 - Lancement de programmes Commutation de programmes, p. ex. par interruption
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
G06F 15/173 - Communication entre processeurs utilisant un réseau d'interconnexion, p. ex. matriciel, de réarrangement, pyramidal, en étoile ou ramifié
G06F 12/084 - Systèmes de mémoire cache multi-utilisateurs, multiprocesseurs ou multitraitement avec mémoire cache partagée
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
10.
PARALLEL ARCHITECTURE WITH COMPILER-SCHEDULED COMPUTE SLICES
Techniques for task processing based on compiler-scheduled compute slices are disclosed. A processing unit comprising compute slices, barrier register sets, a control unit, and a memory system is accessed. Each compute slice includes an execution unit and is coupled to other compute slices by a barrier register set. A first slice task is distributed to a first compute slice. A second slice task is allotted to a second compute slice, based on a branch prediction logic. The second compute slice is coupled to the first by a first barrier register set. Pointers are initialized. A compiled program is executed, beginning at the first compute slice. The second slice task can be executed in parallel while a branch decision is being made. If the branch decision determines that the second slice task is not the next sequential slice task, results from the second compute slice are discarded.
Techniques for task processing based on compiler-scheduled compute slices are disclosed. A processing unit comprising compute slices, barrier register sets, a control unit, and a memory system is accessed. Each compute slice includes an execution unit and is coupled to other compute slices by a barrier register set. A first slice task is distributed to a first compute slice. A second slice task is allotted to a second compute slice, based on a branch prediction logic. The second compute slice is coupled to the first by a first barrier register set. Pointers are initialized. A compiled program is executed, beginning at the first compute slice. The second slice task can be executed in parallel while a branch decision is being made. If the branch decision determines that the second slice task is not the next sequential slice task, results from the second compute slice are discarded.
Techniques for monitoring block moves in an array of compute elements and applying backpressure are disclosed. An array of compute elements is accessed. The array of compute elements is coupled to at least one data cache. The data cache provides memory storage for the array of compute elements. Control for the array of compute elements is enabled by a stream of wide control words generated by the compiler. A load address and a store address comprising memory block move addresses are generated. The memory block move addresses point to memory storage locations in the at least one data cache. Load buffers are coupled to the array of compute elements. The load buffers are located adjacent to at least one edge of the array of compute elements. A memory block move is executed using at least one of the load buffers, based on the memory block move addresses.
Techniques for task processing are disclosed. An array of compute elements is accessed. Each compute element within the array is known to a compiler and is coupled to its neighboring compute elements. The array of compute elements is coupled to at least one data cache. The data cache provides memory storage for the array. Control for the compute elements is provided on a cycle-by-cycle basis. Control is enabled by a stream of wide control words generated by the compiler. A load address and a store address are generated. The load and the store addresses comprise memory block move addresses. The memory block move addresses point to memory storage locations in the data cache. A memory block move is executed, based on the memory block move addresses. The data for the memory block move is transferred outside of the array.
Techniques for parallel processing based on hazard mitigation avoidance are disclosed. An array of compute elements is accessed. Each compute element within the array is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements. Control for the compute elements is provided on a cycle-by-cycle basis. Control is enabled by a stream of wide control words generated by the compiler. Memory access operation hazard mitigation is enabled. The hazard mitigation is enabled by a control word tag. The control word tag supports memory access precedence information and is provided by the compiler at compile time. A hazardless memory access operation is executed. The hazardless memory access operation is determined by the compiler, and the hazardless memory access operation is designated by a unique set of precedence information contained in the tag. The tag is modified during runtime by hardware.
Techniques for a parallel processing architecture for branch path suppression are disclosed. An array of compute elements is accessed. Each element is known to a compiler and is coupled to its neighboring elements. Control for the elements is provided on a cycle- by -cycle basis. Control is enabled by a stream of wide control words generated by the compiler. The control includes a branch. A plurality of compute elements is mapped. The mapping distributes parallelized operations to the compute elements. The mapping is determined by the compiler. A column of compute elements is enabled to perform vertical data access suppression and a row of compute elements is enabled to perform horizontal data access suppression. Both sides of the branch are executed. The executing includes making a branch decision. Branch operation data accesses are suppressed, based on the branch decision and an invalid indication. The invalid indication is propagated among compute elements.
Techniques for parallel processing based on hazard mitigation avoidance are disclosed. An array of compute elements is accessed. Each compute element within the array is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements. Control for the compute elements is provided on a cycle-by-cycle basis. Control is enabled by a stream of wide control words generated by the compiler. Memory access operation hazard mitigation is enabled. The hazard mitigation is enabled by a control word tag. The control word tag supports memory access precedence information and is provided by the compiler at compile time. A hazardless memory access operation is executed. The hazardless memory access operation is determined by the compiler, and the hazardless memory access operation is designated by a unique set of precedence information contained in the tag. The tag is modified during runtime by hardware.
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p. ex. plusieurs processeurs de données à instruction unique
G06F 12/0895 - Mémoires cache caractérisées par leur organisation ou leur structure de parties de mémoires cache, p. ex. répertoire ou matrice d’étiquettes
17.
PARALLEL PROCESSING WITH HAZARD DETECTION AND STORE PROBES
Techniques for parallel processing using hazard detection and store probes are disclosed. An array of compute elements is accessed. Each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements. Control for the compute elements is provided on a cycle-by-cycle basis. Control is enabled by a stream of wide control words generated by the compiler. Data to be stored by the array of compute elements is managed. The data to be stored is targeted to a data cache coupled to the array of compute elements. The managing includes detecting and mitigating memory hazards. Pending data cache accesses are probed for hazards. The examining comprises a store probe. Store data is committed to the data cache. The committing is based on a result of the store probe.
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 12/0802 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache
18.
Parallel processing architecture for branch path suppression
Techniques for a parallel processing architecture for branch path suppression are disclosed. An array of compute elements is accessed. Each element is known to a compiler and is coupled to its neighboring elements. Control for the elements is provided on a cycle-by-cycle basis. Control is enabled by a stream of wide control words generated by the compiler. The control includes a branch. A plurality of compute elements is mapped. The mapping distributes parallelized operations to the compute elements. The mapping is determined by the compiler. A column of compute elements is enabled to perform vertical data access suppression and a row of compute elements is enabled to perform horizontal data access suppression. Both sides of the branch are executed. The executing includes making a branch decision. Branch operation data accesses are suppressed, based on the branch decision and an invalid indication. The invalid indication is propagated among compute elements.
Techniques for parallel processing based on parallel processing with switch block execution are disclosed. An array of compute elements is accessed. Each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements. Control for the compute elements is provided on a cycle-by-cycle basis. Control is enabled by a stream of wide control words generated by the compiler. A plurality of compute elements is initialized within the array with a switch statement. The switch statement is mapped into a primitive operation in each element of the plurality of compute elements. The initializing is based on a control word from the stream of control words. Each of the primitive operations is executed in an architectural cycle. A result is returned for the switch statement. The returning is determined by a decision variable.
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p. ex. plusieurs processeurs de données à instruction unique
G06F 9/38 - Exécution simultanée d'instructions, p. ex. pipeline ou lecture en mémoire
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
Techniques for parallel processing using hazard detection and store probes are disclosed. An array of compute elements is accessed. Each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements. Control for the compute elements is provided on a cycle-by-cycle basis. Control is enabled by a stream of wide control words generated by the compiler. Data to be stored by the array of compute elements is managed. The data to be stored is targeted to a data cache coupled to the array of compute elements. The managing includes detecting and mitigating memory hazards. Pending data cache accesses are probed for hazards. The examining comprises a store probe. Store data is committed to the data cache. The committing is based on a result of the store probe.
Techniques for parallel processing using hazard detection and mitigation are disclosed. An array of compute elements is accessed. Each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements. Control for the compute elements is provided on a cycle-by-cycle basis. Control is enabled by a stream of wide control words generated by the compiler. Memory access operations are tagged with precedence information. The tagging is contained in the control words. The tagging is provided by the compiler at compile time. Memory access operations are monitored. The monitoring is based on the precedence information and a number of architectural cycles of the cycle-by- cycle basis. The tagging is augmented at run time, based on the monitoring. Memory access data is held before promotion, based on the monitoring.
G06F 9/38 - Exécution simultanée d'instructions, p. ex. pipeline ou lecture en mémoire
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
G06F 9/48 - Lancement de programmes Commutation de programmes, p. ex. par interruption
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p. ex. plusieurs processeurs de données à instruction unique
Techniques for parallel processing based on parallel processing with switch block execution are disclosed. An array of compute elements is accessed. Each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements. Control for the compute elements is provided on a cycle-by-cycle basis. Control is enabled by a stream of wide control words generated by the compiler. A plurality of compute elements is initialized within the array with a switch statement. The switch statement is mapped into a primitive operation in each element of the plurality of compute elements. The initializing is based on a control word from the stream of control words. Each of the primitive operations is executed in an architectural cycle. A result is returned for the switch statement. The returning is determined by a decision variable.
Techniques for task processing based on a parallel processing architecture with memory block transfers are disclosed. An array of compute elements is accessed. Each compute element is known to a compiler and is coupled to its neighboring compute elements. Control for the array is provided on a cycle-by-cycle basis. The control is enabled by a stream of wide control words generated by the compiler. A control word from the stream of control words includes a source address, a target address, a block size, and a stride. Memory block transfer control logic is used. The memory block transfer logic is implemented outside of the array of compute elements. A memory block transfer is executed. The memory block transfer is initiated by a control word from the stream of wide control words. Data for the memory block transfer is moved independently from the array of compute elements.
G06F 9/38 - Exécution simultanée d'instructions, p. ex. pipeline ou lecture en mémoire
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p. ex. plusieurs processeurs de données à instruction unique
24.
Parallel processing using hazard detection and mitigation
Techniques for parallel processing using hazard detection and mitigation are disclosed. An array of compute elements is accessed. Each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements. Control for the compute elements is provided on a cycle-by-cycle basis. Control is enabled by a stream of wide control words generated by the compiler. Memory access operations are tagged with precedence information. The tagging is contained in the control words. The tagging is provided by the compiler at compile time. Memory access operations are monitored. The monitoring is based on the precedence information and a number of architectural cycles of the cycle-by-cycle basis. The tagging is augmented at run time, based on the monitoring. Memory access data is held before promotion, based on the monitoring.
Techniques for parallel processing based on a parallel processing architecture with bin packing are disclosed. An array of compute elements is accessed. Each compute element is known to a compiler and is coupled to its neighboring compute elements. A plurality of compressed control words is generated by the compiler. The plurality of control words enables compute element operation and compute element memory access. The compressed control words are operationally sequenced. The compressed control words are linked by the compiler. Linking information is contained in at least one field of each of the compressed control words. The compressed control words are loaded into a control word cache coupled to the array of compute elements. The compressed control words are loaded into the control word cache in an operationally non-sequenced order. The plurality of compressed control words is ordered into an operationally sequenced execution order, based on the linking information.
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p. ex. plusieurs processeurs de données à instruction unique
G06F 5/01 - Procédés ou dispositions pour la conversion de données, sans modification de l'ordre ou du contenu des données maniées pour le décalage, p. ex. la justification, le changement d'échelle, la normalisation
26.
PARALLEL PROCESSING ARCHITECTURE WITH DUAL LOAD BUFFERS
Techniques for parallel processing based on a parallel processing architecture with dual load buffers are disclosed. A two-dimensional array of compute elements is accessed. Each compute element is known to a compiler and is coupled to its neighboring compute elements. A first data cache is coupled to the array. The first data cache enables loading data to a first portion of the array. The first data cache supports an address space. A second data cache is coupled to the array. The second data cache enables loading data to a second portion of the array. The second data cache supports the address space. Instructions are executed within the array. Instructions executed within the first portion of the array of compute elements use data loaded from the first data cache, and instructions executed within the second portion of the array of compute elements use data loaded from the second data cache.
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
G06F 9/38 - Exécution simultanée d'instructions, p. ex. pipeline ou lecture en mémoire
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p. ex. plusieurs processeurs de données à instruction unique
Techniques for parallel processing based on a parallel processing architecture with bin packing are disclosed. An array of compute elements is accessed. Each compute element is known to a compiler and is coupled to its neighboring compute elements. A plurality of compressed control words is generated by the compiler. The plurality of control words enables compute element operation and compute element memory access. The compressed control words are operationally sequenced. The compressed control words are linked by the compiler. Linking information is contained in at least one field of each of the compressed control words. The compressed control words are loaded into a control word cache coupled to the array of compute elements. The compressed control words are loaded into the control word cache in an operationally non-sequenced order. The plurality of compressed control words is ordered into an operationally sequenced execution order, based on the linking information.
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p. ex. plusieurs processeurs de données à instruction unique
28.
PARALLEL PROCESSING ARCHITECTURE WITH COUNTDOWN TAGGING
Techniques for parallel processing based on a parallel processing architecture with countdown tagging are disclosed. A two-dimensional array of compute elements is accessed. Each compute element within the array is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements. A load operation is tagged with a countdown tag. Tagging is performed by the compiler, and the load operation is targeted to a memory system associated with the array of compute elements. The countdown tag comprises a time value. The time value is decremented as the load operation is being performed. The time value that is decremented is based on an architectural cycle. Countdown tag status is monitored by a control unit. The monitoring occurs as the load operation is performed. A load status is generated by the control unit, based on the monitoring. The load status allows compute element operation.
G06F 9/48 - Lancement de programmes Commutation de programmes, p. ex. par interruption
G06F 9/50 - Allocation de ressources, p. ex. de l'unité centrale de traitement [UCT]
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p. ex. plusieurs processeurs de données à instruction unique
G06F 9/38 - Exécution simultanée d'instructions, p. ex. pipeline ou lecture en mémoire
29.
PARALLEL PROCESSING ARCHITECTURE WITH SPLIT CONTROL WORD CACHES
Techniques for a parallel processing architecture with split control word caches are disclosed. A two-dimensional array of compute elements is accessed. Each compute element is known to a compiler and is coupled to its neighboring compute elements. A first control word cache is coupled to the array. The first control word cache enables loading control words to a first array portion. A second control word cache is coupled to the array. The second control word cache enables loading control words to a second array portion. The control words are split between the first and the second control word caches. The splitting is based on the constituency of the first and the second array portions. Instructions are executed within the array. Instructions executed within the first array portion use control words loaded from the first cache. Instructions executed within the second array portion use control words loaded from the second cache.
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p. ex. plusieurs processeurs de données à instruction unique
G06F 9/38 - Exécution simultanée d'instructions, p. ex. pipeline ou lecture en mémoire
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
G06F 12/0802 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache
30.
PARALLEL PROCESSING ARCHITECTURE WITH MEMORY BLOCK TRANSFERS
Techniques for task processing based on a parallel processing architecture with memory block transfers are disclosed. An array of compute elements is accessed. Each compute element is known to a compiler and is coupled to its neighboring compute elements. Control for the array is provided on a cycle-by-cycle basis. The control is enabled by a stream of wide control words generated by the compiler. A control word from the stream of control words includes a source address, a target address, a block size, and a stride. Memory block transfer control logic is used. The memory block transfer logic is implemented outside of the array of compute elements. A memory block transfer is executed. The memory block transfer is initiated by a control word from the stream of wide control words. Data for the memory block transfer is moved independently from the array of compute elements.
G06F 9/345 - Adressage de l'opérande d'instruction ou du résultat ou accès à l'opérande d'instruction ou au résultat d'opérandes ou de résultats multiples
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
Techniques for parallel processing based on a parallel processing architecture with dual load buffers are disclosed. A two-dimensional array of compute elements is accessed. Each compute element is known to a compiler and is coupled to its neighboring compute elements. A first data cache is coupled to the array. The first data cache enables loading data to a first portion of the array. The first data cache supports an address space. A second data cache is coupled to the array. The second data cache enables loading data to a second portion of the array. The second data cache supports the address space. Instructions are executed within the array. Instructions executed within the first portion of the array of compute elements use data loaded from the first data cache, and instructions executed within the second portion of the array of compute elements use data loaded from the second data cache.
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p. ex. plusieurs processeurs de données à instruction unique
G06F 12/0842 - Systèmes de mémoire cache multi-utilisateurs, multiprocesseurs ou multitraitement pour multitraitement ou multitâche
32.
PARALLEL PROCESSING OF MULTIPLE LOOPS WITH LOADS AND STORES
Techniques for parallel processing of multiple loops with loads and stores are disclosed. A two-dimensional array of compute elements is accessed. Each compute element within the array is known to a compiler and is coupled to its neighboring compute elements within the array. Control for the compute elements is provided on a cycle-by-cycle basis. Control is enabled by a stream of wide control words generated by the compiler. Memory access operations are tagged with precedence information. The tagging is contained in the control words and is implemented for loop operations. The tagging is provided by the compiler at compile time. Control word data is loaded for multiple, independent loops into the compute elements. The multiple, independent loops are executed. Memory is accessed based on the precedence information. The memory access includes loads and/or stores for data relating to the independent loops.
G06F 9/38 - Exécution simultanée d'instructions, p. ex. pipeline ou lecture en mémoire
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p. ex. plusieurs processeurs de données à instruction unique
Techniques for parallel processing based on a parallel processing architecture with countdown tagging are disclosed. A two-dimensional array of compute elements is accessed. Each compute element within the array is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements. A load operation is tagged with a countdown tag. Tagging is performed by the compiler, and the load operation is targeted to a memory system associated with the array of compute elements. The countdown tag comprises a time value. The time value is decremented as the load operation is being performed. The time value that is decremented is based on an architectural cycle. Countdown tag status is monitored by a control unit. The monitoring occurs as the load operation is performed. A load status is generated by the control unit, based on the monitoring. The load status allows compute element operation.
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p. ex. plusieurs processeurs de données à instruction unique
34.
PARALLEL PROCESSING ARCHITECTURE WITH SPLIT CONTROL WORD CACHES
Techniques for a parallel processing architecture with split control word caches are disclosed. A two-dimensional array of compute elements is accessed. Each compute element is known to a compiler and is coupled to its neighboring compute elements. A first control word cache is coupled to the array. The first control word cache enables loading control words to a first array portion. A second control word cache is coupled to the array. The second control word cache enables loading control words to a second array portion. The control words are split between the first and the second control word caches. The splitting is based on the constituency of the first and the second array portions. Instructions are executed within the array. Instructions executed within the first array portion use control words loaded from the first cache. Instructions executed within the second array portion use control words loaded from the second cache.
Techniques for task processing based on autonomous compute element operation using buffers are disclosed. A two-dimensional array of compute elements is accessed. Each compute element is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements. Control is provided for the array of compute elements on a cycle-by-cycle basis. The control is enabled by a stream of wide control words generated by the compiler. An autonomous operation buffer is loaded with at least two operations contained in control words. The autonomous operation buffer is integrated in a compute element. A compute element operation counter coupled to the autonomous operation buffer is set. The compute element operation counter is integrated in the compute element. The at least two operations are executed using the autonomous operation buffer and the compute element operation counter. The operations complete autonomously from direct compiler control.
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p. ex. plusieurs processeurs de données à instruction unique
G06F 7/57 - Unités arithmétiques et logiques [UAL], c.-à-d. dispositions ou dispositifs pour accomplir plusieurs des opérations couvertes par les groupes ou pour accomplir des opérations logiques
36.
HIGHLY PARALLEL PROCESSING ARCHITECTURE WITH OUT-OF-ORDER RESOLUTION
Techniques for task processing based on a highly parallel processing architecture with out-of-order resolution are disclosed. A two-dimensional array of compute elements is accessed. Each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements. The array of compute elements is coupled to supporting logic and to memory, which, along with the array of compute elements, comprise compute hardware. A set of directions is provided to the hardware, through a control word generated by the compiler, for compute element operation. The set of directions is augmented with data access ordering information. The data access ordering is performed by the hardware. A compiled task is executed on the array of compute elements, based on the set of directions that was augmented.
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p. ex. plusieurs processeurs de données à instruction unique
G06F 9/38 - Exécution simultanée d'instructions, p. ex. pipeline ou lecture en mémoire
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
Techniques for parallel processing of multiple loops with loads and stores are disclosed. A two-dimensional array of compute elements is accessed. Each compute element within the array is known to a compiler and is coupled to its neighboring compute elements within the array. Control for the compute elements is provided on a cycle-by-cycle basis. Control is enabled by a stream of wide control words generated by the compiler. Memory access operations are tagged with precedence information. The tagging is contained in the control words and is implemented for loop operations. The tagging is provided by the compiler at compile time. Control word data is loaded for multiple, independent loops into the compute elements. The multiple, independent loops are executed. Memory is accessed based on the precedence information. The memory access includes loads and/or stores for data relating to the independent loops.
Techniques for task processing based on a highly parallel processing architecture with out-of-order resolution are disclosed. A two-dimensional array of compute elements is accessed. Each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements. The array of compute elements is coupled to supporting logic and to memory, which, along with the array of compute elements, comprise compute hardware. A set of directions is provided to the hardware, through a control word generated by the compiler, for compute element operation. The set of directions is augmented with data access ordering information. The data access ordering is performed by the hardware. A compiled task is executed on the array of compute elements, based on the set of directions that was augmented.
Techniques for task processing based on autonomous compute element operation using buffers are disclosed. A two-dimensional array of compute elements is accessed. Each compute element is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements. Control is provided for the array of compute elements on a cycle-by-cycle basis. The control is enabled by a stream of wide control words generated by the compiler. An autonomous operation buffer is loaded with at least two operations contained in control words. The autonomous operation buffer is integrated in a compute element. A compute element operation counter coupled to the autonomous operation buffer is set. The compute element operation counter is integrated in the compute element. The at least two operations are executed using the autonomous operation buffer and the compute element operation counter. The operations complete autonomously from direct compiler control.
Techniques for task processing based on compute element processing using control word templates are disclosed. One or more control word templates are generated for use in a two-dimensional array of compute elements. Each compute element within the array is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements. Each control word template designates a topological set of compute elements from the array of compute elements. The one or more control word templates are customized with a specific set of compute element operations. The one or more control word templates that were customized are stored. The specific set of compute element operations is executed on the topological set of compute elements. The one or more control word templates that were stored are reused. The one or more control word templates that were stored are modified and executed using compute elements.
G06F 15/173 - Communication entre processeurs utilisant un réseau d'interconnexion, p. ex. matriciel, de réarrangement, pyramidal, en étoile ou ramifié
G06F 7/57 - Unités arithmétiques et logiques [UAL], c.-à-d. dispositions ou dispositifs pour accomplir plusieurs des opérations couvertes par les groupes ou pour accomplir des opérations logiques
41.
COMPUTE ELEMENT PROCESSING USING CONTROL WORD TEMPLATES
Techniques for task processing based on compute element processing using control word templates are disclosed. One or more control word templates are generated for use in a two-dimensional array of compute elements. Each compute element within the array is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements. Each control word template designates a topological set of compute elements from the array of compute elements. The one or more control word templates are customized with a specific set of compute element operations. The one or more control word templates that were customized are stored. The specific set of compute element operations is executed on the topological set of compute elements. The one or more control word templates that were stored are reused. The one or more control word templates that were stored are modified and executed using compute elements.
Techniques for task processing based on load latency amelioration using bunch buffers are disclosed. A two-dimensional array of compute elements is accessed. Each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements. Control for the compute elements is provided on a cycle-by-cycle basis. The control is enabled by a stream of wide control words generated by the compiler. Sets of control word bits are loaded into buffers. Each buffer is associated with and coupled to a unique compute element within the array of compute elements. The sets of control word bits provide operational control for the compute element with which it is associated. Operations are executed within the array of elements. The operations are based on a selected set of control word bits which comprise a control word bunch.
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p. ex. plusieurs processeurs de données à instruction unique
G06F 15/78 - Architectures de calculateurs universels à programmes enregistrés comprenant une seule unité centrale
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
G06F 9/50 - Allocation de ressources, p. ex. de l'unité centrale de traitement [UCT]
G06F 9/48 - Lancement de programmes Commutation de programmes, p. ex. par interruption
43.
PARALLEL PROCESSING ARCHITECTURE USING DISTRIBUTED REGISTER FILES
Techniques for task processing based on a parallel processing architecture using distributed register files are disclosed. A two-dimensional array of compute elements is accessed. Each compute element is known to a compiler and is coupled to its neighboring compute elements. The array of compute elements is controlled on a cycle-by-cycle basis. The controlling is enabled by a stream of wide control words generated by the compiler. Virtual registers are mapped to a plurality of physical register files distributed among one or more of the compute elements. Virtual registers are represented by the compiler. The mapping is performed by the compiler. A broadcast write operation is enabled to two or more of the physical register files. Operations contained in the control words are executed. Operations are enabled by at least one of the distributed physical register files. Implementation in separate compute elements enables parallel operation processing.
G06F 9/38 - Exécution simultanée d'instructions, p. ex. pipeline ou lecture en mémoire
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p. ex. plusieurs processeurs de données à instruction unique
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
44.
PARALLEL PROCESSING ARCHITECTURE FOR ATOMIC OPERATIONS
Techniques for task processing in a parallel processing architecture for atomic operations are disclosed. A two-dimensional array of compute elements is accessed, where each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements. Control for the array of compute elements is provided on a cycle-by-cycle basis. The control is enabled by a stream of wide control words generated by the compiler. At least one of the control words involves an operation requiring at least one additional operation. A bit of the control word is set, where the bit indicates a multicycle operation. The control word is executed, on at least one compute element within the array of compute elements, based on the bit. The multicycle operation comprises a read-modify -write operation.
G06F 9/38 - Exécution simultanée d'instructions, p. ex. pipeline ou lecture en mémoire
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p. ex. plusieurs processeurs de données à instruction unique
Techniques for task processing based on load latency amelioration using bunch buffers are disclosed. A two-dimensional array of compute elements is accessed. Each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements. Control for the compute elements is provided on a cycle-by-cycle basis. The control is enabled by a stream of wide control words generated by the compiler. Sets of control word bits are loaded into buffers. Each buffer is associated with and coupled to a unique compute element within the array of compute elements. The sets of control word bits provide operational control for the compute element with which it is associated. Operations are executed within the array of elements. The operations are based on a selected set of control word bits which comprise a control word bunch.
Techniques for task processing based on a parallel processing architecture with distributed register files are disclosed. A two-dimensional array of compute elements is accessed. Each compute element is known to a compiler and is coupled to its neighboring compute elements. The array of compute elements is controlled on a cycle-by-cycle basis. The controlling is enabled by a stream of wide, variable length, control words generated by the compiler. Virtual registers are mapped to a plurality of physical register files distributed among one or more of the compute elements. Virtual registers are represented by the compiler. The mapping is performed by the compiler. A broadcast write operation is enabled to two or more of the physical register files. Operations contained in the control words are executed. Operations are enabled by at least one of the distributed physical register files. Implementation in separate compute elements enables parallel operation processing.
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
G06F 9/38 - Exécution simultanée d'instructions, p. ex. pipeline ou lecture en mémoire
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p. ex. plusieurs processeurs de données à instruction unique
Techniques for task processing in a parallel processing architecture for atomic operations are disclosed. A two-dimensional array of compute elements is accessed, where each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements. Control for the array of compute elements is provided on a cycle-by-cycle basis. The control is enabled by a stream of wide control words generated by the compiler. At least one of the control words involves an operation requiring at least one additional operation. A bit of the control word is set, where the bit indicates a multicycle operation. The control word is executed, on at least one compute element within the array of compute elements, based on the bit. The multicycle operation comprises a read-modify-write operation.
Techniques for task processing based on a parallel processing architecture using distributed register files are disclosed. A two-dimensional array of compute elements is accessed. Each compute element is known to a compiler and is coupled to its neighboring compute elements. The array of compute elements is controlled on a cycle-by-cycle basis. The controlling is enabled by a stream of wide control words generated by the compiler. Virtual registers are mapped to a plurality of physical register files distributed among one or more of the compute elements. Virtual registers are represented by the compiler. The mapping is performed by the compiler. A broadcast write operation is enabled to two or more of the physical register files. Operations contained in the control words are executed. Operations are enabled by at least one of the distributed physical register files. Implementation in separate compute elements enables parallel operation processing.
Techniques for program execution in a parallel processing architecture using speculative encoding are disclosed. A two-dimensional array of compute elements is accessed, where each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements. Control for the array of compute elements is provided on a cycle-by-cycle basis. The control is enabled by a stream of wide, variable length, control words generated by the compiler. Two or more operations are coalesced into a control word, where the control word includes a branch decision and operations associated with the branch decision. The coalesced control word includes speculatively encoded operations for at least two possible branch paths. The at least two possible branch paths generate independent side effects. Operations associated with the branch decision that are not indicated by the branch decision are suppressed.
G06F 9/38 - Exécution simultanée d'instructions, p. ex. pipeline ou lecture en mémoire
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
G06F 9/48 - Lancement de programmes Commutation de programmes, p. ex. par interruption
G06F 7/575 - Unités arithmétiques et logiques de base, c.-à-d. dispositifs pouvant être sélectionnés pour accomplir soit l'addition, soit la soustraction, soit une parmi plusieurs opérations logiques, utilisant, au moins partiellement, les mêmes circuits
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p. ex. plusieurs processeurs de données à instruction unique
Techniques for task processing based on a parallel processing architecture with distributed register files are disclosed. A two-dimensional array of compute elements is accessed. Each compute element is known to a compiler and is coupled to its neighboring compute elements. The array of compute elements is controlled on a cycle-by-cycle basis. The controlling is enabled by a stream of wide, variable length, control words generated by the compiler. Virtual registers are mapped to a plurality of physical register files distributed among one or more of the compute elements. Virtual registers are represented by the compiler. The mapping is performed by the compiler. A broadcast write operation is enabled to two or more of the physical register files. Operations contained in the control words are executed. Operations are enabled by at least one of the distributed physical register files. Implementation in separate compute elements enables parallel operation processing.
Techniques for program execution in a parallel processing architecture using speculative encoding are disclosed. A two-dimensional array of compute elements is accessed, where each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements. Control for the array of compute elements is provided on a cycle-by-cycle basis. The control is enabled by a stream of wide, variable length, control words generated by the compiler. Two or more operations are coalesced into a control word, where the control word includes a branch decision and operations associated with the branch decision. The coalesced control word includes speculatively encoded operations for at least two possible branch paths. The at least two possible branch paths generate independent side effects. Operations associated with the branch decision that are not indicated by the branch decision are suppressed.
Techniques for task processing in a highly parallel processing architecture using dual branch execution are disclosed. A two-dimensional array of compute elements is accessed. Each compute element within the array is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements. Control for the array of compute elements is provided on a cycle-by-cycle basis. The control is enabled by a stream of wide, variable length, control words generated by the compiler. The control includes a branch. Two sides of the branch in the array are executed while waiting for a branch decision to be acted upon by control logic. The branch decision is based on computation results in the array. Data produced by a taken branch path is promoted. Results from a side of the branch not indicated by the branch decision are ignored or invalidated.
Techniques for task processing using a highly parallel processing architecture with a compiler are disclosed. A two-dimensional array of compute elements is accessed. Each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements. A set of directions is provided to the hardware, through a control word generated by the compiler, for compute element operation and memory access precedence. The set of directions enables the hardware to properly sequence compute element results. The set of directions controls data movement for the array of compute elements. A compiled task is executed on the array of compute elements, based on the set of directions. The compute element results are generated in parallel in the array, and the compute element results are ordered independently from control word arrival at each compute element.
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p. ex. plusieurs processeurs de données à instruction unique
G06F 9/38 - Exécution simultanée d'instructions, p. ex. pipeline ou lecture en mémoire
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
54.
PARALLEL PROCESSING ARCHITECTURE WITH BACKGROUND LOADS
Techniques for task processing using a parallel processing architecture with background loads are disclosed. A two-dimensional array of compute elements is accessed. Each compute element is known to a compiler and is coupled to its neighboring compute elements. Operation of the array is paused. The pausing occurs while a memory system continues operation. A bus coupling the array is repurposed. The repurposing couples one or more compute elements in the array to the memory system. A memory system operation is enabled during the pausing. Data is transferred from the memory system to the array of compute elements using the bus that was repurposed. The data from the memory system is transferred to scratchpad memory in the one or more compute elements within the two- dimensional array. The scratchpad memory provides operand storage. The data is tagged. The tagging guides the transferring to a particular compute element.
G06Q 10/06 - Ressources, gestion de tâches, des ressources humaines ou de projetsPlanification d’entreprise ou d’organisationModélisation d’entreprise ou d’organisation
Techniques for task processing in a highly parallel processing architecture using dual branch execution are disclosed. A two-dimensional array of compute elements is accessed. Each compute element within the array is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements. Control for the array of compute elements is provided on a cycle-by-cycle basis. The control is enabled by a stream of wide, variable length, control words generated by the compiler. The control includes a branch. Two sides of the branch in the array are executed while waiting for a branch decision to be acted upon by control logic. The branch decision is based on computation results in the array. Data produced by a taken branch path is promoted. Results from a side of the branch not indicated by the branch decision are ignored or invalidated.
G06F 9/38 - Exécution simultanée d'instructions, p. ex. pipeline ou lecture en mémoire
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
G06F 7/575 - Unités arithmétiques et logiques de base, c.-à-d. dispositifs pouvant être sélectionnés pour accomplir soit l'addition, soit la soustraction, soit une parmi plusieurs opérations logiques, utilisant, au moins partiellement, les mêmes circuits
G06N 3/04 - Architecture, p. ex. topologie d'interconnexion
56.
HIGHLY PARALLEL PROCESSING ARCHITECTURE WITH SHALLOW PIPELINE
Techniques for task processing using a highly parallel processing architecture with a shallow pipeline are disclosed. A two-dimensional array of compute elements is accessed. Each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements. Control for the array of compute elements is provided on a cycle-by-cycle basis. The control is enabled by a stream of wide, variable length, microcode control words generated by the compiler. Relevant portions of the control word are stored within a cache associated with the array of compute elements. The control words are decompressed. The decompressing occurs cycle-by-cycle out of the cache over multiple cycles. A compiled task is executed on the array of compute elements, based on the decompressing. Simultaneous execution of two or more potential compiled task outcomes is provided.
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p. ex. plusieurs processeurs de données à instruction unique
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
G06F 9/28 - Augmentation de la vitesse de fonctionnement, p. ex. en utilisant plusieurs dispositifs de microcommande fonctionnant en parallèle
G06F 9/38 - Exécution simultanée d'instructions, p. ex. pipeline ou lecture en mémoire
57.
PARALLEL PROCESSING ARCHITECTURE WITH BACKGROUND LOADS
Techniques for task processing using a parallel processing architecture with background loads are disclosed. A two-dimensional array of compute elements is accessed. Each compute element is known to a compiler and is coupled to its neighboring compute elements. Operation of the array is paused. The pausing occurs while a memory system continues operation. A bus coupling the array is repurposed. The repurposing couples one or more compute elements in the array to the memory system. A memory system operation is enabled during the pausing. Data is transferred from the memory system to the array of compute elements using the bus that was repurposed. The data from the memory system is transferred to scratchpad memory in the one or more compute elements within the two-dimensional array. The scratchpad memory provides operand storage. The data is tagged. The tagging guides the transferring to a particular compute element.
Techniques for task processing using a highly parallel processing architecture with a compiler are disclosed. A two-dimensional array of compute elements is accessed. Each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements. A set of directions is provided to the hardware, through a control word generated by the compiler, for compute element operation and memory access precedence. The set of directions enables the hardware to properly sequence compute element results. The set of directions controls data movement for the array of compute elements. A compiled task is executed on the array of compute elements, based on the set of directions. The compute element results are generated in parallel in the array, and the compute element results are ordered independently from control word arrival at each compute element.
Techniques for task processing using a highly parallel processing architecture with a shallow pipeline are disclosed. A two-dimensional array of compute elements is accessed. Each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements. Control for the array of compute elements is provided on a cycle-by-cycle basis. The control is enabled by a stream of wide, variable length, microcode control words generated by the compiler. Relevant portions of the control word are stored within a cache associated with the array of compute elements. The control words are decompressed. The decompressing occurs cycle-by-cycle out of the cache over multiple cycles. A compiled task is executed on the array of compute elements, based on the decompressing. Simultaneous execution of two or more potential compiled task outcomes is provided.
G06F 9/38 - Exécution simultanée d'instructions, p. ex. pipeline ou lecture en mémoire
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
G06F 9/48 - Lancement de programmes Commutation de programmes, p. ex. par interruption
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p. ex. plusieurs processeurs de données à instruction unique
60.
Method of placement and routing in a reconfiguration of a dynamically reconfigurable processor
A method and system are provided for deriving a resultant compiled software code with increased compatibility for placement and routing of a dynamically reconfigurable processor.
A method and system are provided for deriving a resultant software code from an originating ordered list of instructions that does not include overlapping branch logic. The method may include deriving a plurality of unordered software constructs from a sequence of processor instructions; associating software constructs in accordance with an original logic of the sequence of processor instructions; determining and resolving memory precedence conflicts within the associated plurality of software constructs; resolving forward branch logic structures into conditional logic constructs; resolving back branch logic structures into loop logic constructs; and/or applying the plurality of unordered software constructs in a programming operation by a parallel execution logic circuitry. The resultant plurality of unordered software constructs may be converted into programming reconfigurable logic, computers or processors, and also by means of a computer network or an electronics communications network.
A method and system are provided for deriving a resultant software code from an originating ordered list of instructions that does not include overlapping branch logic. The method may include deriving a plurality of unordered software constructs from a sequence of processor instructions; associating software constructs in accordance with an original logic of the sequence of processor instructions; determining and resolving memory precedence conflicts within the associated plurality of software constructs; resolving forward branch logic structures into conditional logic constructs; resolving back branch logic structures into loop logic constructs; and/or applying the plurality of unordered software constructs in a programming operation by a parallel execution logic circuitry. The resultant plurality of unordered software constructs may be converted into programming reconfigurable logic, computers or processors, and also by means of a computer network or an electronics communications network.
A method and system are provided for configurable computation and data processing. A logical processor includes an array of logic elements. The processor may be a combinatorial circuit that can be applied to modify computational aspects of an array of reconfigurable circuits. A memory stores a plurality of instructions, each instruction including an instruction-fetch data portion and an output data transfer data portion. One or more memory controllers are coupled to the memory and receive instructions and/or output data from the memory. A back buffer is coupled with the memory controller and receives instructions from the memory controller. The back buffer sequentially asserts each received instruction upon one or more memory controllers. The memory controllers transfer data received from the memory to a target, such as an array of reconfigurable logic circuits that are optionally coupled to the memory, the back buffer, and one or more additional memory controllers.
brevets
