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2025
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Invention
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Memory dependence prediction in a parallel architecture with compute slices.
A processing unit i... |
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Invention
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Global memory disambiguation for a parallel architecture with compute slices.
Techniques for che... |
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Invention
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Local memory disambiguation for a parallel architecture with compute slices.
A processing unit i... |
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Invention
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Compiler generated hyperblocks in a parallel architecture with compute slices.
Techniques for pa... |
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2024
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Invention
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Semantic ordering for parallel architecture with compute slices.
Techniques for managing compute... |
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Invention
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Semantic ordering for parallel architecture with compute slices. Techniques for managing compute ... |
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Invention
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Parallel processing architecture with block move backpressure. Techniques for monitoring block mo... |
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Invention
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Parallel processing architecture with block move backpressure.
Techniques for monitoring block m... |
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Invention
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Parallel processing architecture with block move support. Techniques for task processing are disc... |
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Invention
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Parallel processing architecture with block move support.
Techniques for task processing are dis... |
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Invention
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Parallel architecture with compiler-scheduled compute slices.
Techniques for task processing bas... |
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Invention
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Parallel architecture with compiler-scheduled compute slices. Techniques for task processing base... |
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Invention
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Parallel processing hazard mitigation avoidance. Techniques for parallel processing based on haza... |
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Invention
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Parallel processing hazard mitigation avoidance.
Techniques for parallel processing based on haz... |
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Invention
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Parallel processing architecture for branch path suppression. Techniques for a parallel processin... |
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Invention
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Parallel processing architecture for branch path suppression.
Techniques for a parallel processi... |
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Invention
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Parallel processing with hazard detection and store probes. Techniques for parallel processing us... |
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Invention
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Parallel processing with hazard detection and store probes.
Techniques for parallel processing u... |
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2023
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Invention
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Parallel processing with switch block execution. Techniques for parallel processing based on para... |
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Invention
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Parallel processing with switch block execution.
Techniques for parallel processing based on par... |
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Invention
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Parallel processing using hazard detection and mitigation. Techniques for parallel processing usi... |
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Invention
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Parallel processing architecture with memory block transfers. Techniques for task processing base... |
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Invention
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Parallel processing architecture with memory block transfers.
Techniques for task processing bas... |
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Invention
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Parallel processing architecture with bin packing. Techniques for parallel processing based on a ... |
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Invention
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Parallel processing architecture with bin packing.
Techniques for parallel processing based on a... |
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Invention
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Parallel processing architecture with dual load buffers. Techniques for parallel processing based... |
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Invention
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Parallel processing architecture with dual load buffers.
Techniques for parallel processing base... |
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Invention
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Parallel processing architecture with countdown tagging. Techniques for parallel processing based... |
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Invention
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Parallel processing architecture with countdown tagging.
Techniques for parallel processing base... |
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Invention
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Parallel processing architecture with split control word caches. Techniques for a parallel proces... |
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Invention
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Parallel processing architecture with split control word caches.
Techniques for a parallel proce... |
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Invention
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Parallel processing of multiple loops with loads and stores. Techniques for parallel processing o... |
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Invention
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Parallel processing of multiple loops with loads and stores.
Techniques for parallel processing ... |
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Invention
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Autonomous compute element operation using buffers. Techniques for task processing based on auton... |
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Invention
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Autonomous compute element operation using buffers.
Techniques for task processing based on auto... |
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Invention
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Highly parallel processing architecture with out-of-order resolution. Techniques for task process... |
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Invention
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Highly parallel processing architecture with out-of-order resolution.
Techniques for task proces... |
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2022
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Invention
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Compute element processing using control word templates. Techniques for task processing based on ... |
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Invention
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Compute element processing using control word templates.
Techniques for task processing based on... |
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Invention
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Load latency amelioration using bunch buffers. Techniques for task processing based on load laten... |
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Invention
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Load latency amelioration using bunch buffers.
Techniques for task processing based on load late... |
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Invention
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Parallel processing architecture for atomic operations. Techniques for task processing in a paral... |
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Invention
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Parallel processing architecture for atomic operations.
Techniques for task processing in a para... |
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Invention
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Parallel processing architecture using distributed register files. Techniques for task processing... |
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Invention
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Parallel processing architecture using distributed register files.
Techniques for task processin... |
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Invention
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Parallel processing architecture with distributed register files. Techniques for task processing ... |
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Invention
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Parallel processing architecture with distributed register files.
Techniques for task processing... |
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Invention
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Parallel processing architecture using speculative encoding. Techniques for program execution in ... |
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Invention
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Parallel processing architecture using speculative encoding.
Techniques for program execution in... |
