The present disclosure relates to a fixture and, more particularly, to a fixture for the transport and storage of wafers and methods of use. The fixture includes: a frame having a mounting space provided between a top section, a bottom section and rails extending between the top section and the bottom section; and a clamp slidably mounted to the rails, the clamp including a locking mechanism that locks the clamp to the frame at different heights of the rails.
Disclosed is a radio frequency (RF) circuit including a mixer configured for independent second order intercept point (IP2) calibration. The mixer includes three ports and multiple dual-gate transistors interconnected therebetween for down-converting an RF input signal to a lower frequency baseband output signal. To optimize performance, front gates of the transistors are biased with a front gate bias voltage (Vfg). To adjust second order non-linearity, back gates of the transistors are biased using a first back gate bias voltage (Vbgp) for half of the transistors of the mixer and a second back gate bias voltage (Vbgm) for a different half of the transistors. The circuit can also include a front gate bias voltage generator for generating Vfg and a back gate bias voltage generator (including a digital-to-analog converter (DAC) with multiple DAC units) for generating Vbgp and Vbgm independent of Vfg. Also disclosed is an associated operating method.
H03D 7/12 - Transfert de modulation d'une porteuse à une autre, p. ex. changement de fréquence au moyen de dispositifs à semi-conducteurs ayant plus de deux électrodes
Disclosed is a photonic integrated circuit (PIC) structure including a scattering light-based monitor with photodetectors (e.g., PIN and/or avalanche photodiodes) placed adjacent to one or both sides of an end portion (i.e., a coupler) of a waveguide core at an optical interface with another optical device. The photodetectors are placed in such a way as to enable sensing of scattering light emitted from the end portion as light signals are received (e.g., either from the optical device for propagation to the main body of the waveguide core or from the main body for transmission to the optical device). Also disclosed are a monitoring system and method including the PIC chip structure with the above-described scattering light-based monitor. The system and method assess the optical interface using electric signals generated by the photodetectors.
The present disclosure relates to a fixture and, more particularly, to a fixture which holds a radio frequency identification tag and methods of use. The structure includes a cage comprising a top portion, a bottom portion attached to the top portion and a storage space between the top portion and the bottom portion; a moveable linkage system extending within the storage space; a door attached to a first end of the linkage system, the door being moveable between an open position and a closed position; and a cam mechanism comprising structures with surfaces that permit the door to move from the closed position to the open position and to prevent the door from closing when in the closed position.
Structures for an edge coupler and methods of forming such structures. The structure comprises a waveguide core including a facet, a first tapered section, a second tapered section, and a longitudinal axis. The first tapered section is positioned along the longitudinal axis between the second tapered section and the facet. The first tapered section has a first width dimension that varies non-linearly with position along the longitudinal axis. The second tapered section has a second width dimension that varies non-linearly with position along the longitudinal axis.
Structures for an electrical interconnection and methods of forming a structure for an electrical interconnection. The structure comprises a bond pad and an electrical interconnection including a pillar positioned on a portion of the bond pad. The pillar includes a first section and a second section between the first section and the portion of the bond pad. The second section has a cross section with a perimeter having a non-round closed shape, and the second section is positioned acentric relative to the first section.
A design is schematically displayed using a three-dimensional (3D) graphical user interface (GUI) by displaying, via the 3D GUI, a first plane extending along a first axis and a second axis different from the first axis, including displaying symbols corresponding to a set of first-level components of a first level of the design disposed on the first plane; and a second plane extending along the first axis and second axis, including displaying symbols corresponding to a first set of second-level components of a second level of the design disposed on the second plane. The two planes are displayed simultaneously, and respectively disposed at first and second positions along a third axis different from the first and second axes. Each level of the design may correspond to a respective level of a hierarchy of the design, a respective substrate the design will be implemented on, or a combination thereof.
G06F 3/04815 - Interaction s’effectuant dans un environnement basé sur des métaphores ou des objets avec un affichage tridimensionnel, p. ex. modification du point de vue de l’utilisateur par rapport à l’environnement ou l’objet
Disclosed are a high-density stacked capacitor and an associated formation method. The high-density stacked capacitor includes: first and second terminals; and a stack of parallel-connected capacitors between the terminals. The stack includes a first capacitor (e.g., a planar transistor-type capacitor) including: a channel region positioned laterally between source/drain regions, which are connected to the first terminal; and front and back gates, which are above and below the channel region and connected to the second terminal. The stack also includes at least one additional capacitor (e.g., a metal-oxide-metal capacitor (MOMCAP)) aligned above the front gate of the first capacitor in a back end of the line (BEOL) metal level. Optionally, the capacitor includes multiple additional capacitors aligned above the front gate and stacked vertically one above the other in different BEOL metal levels. Each additional capacitor includes interdigitated first and second capacitor plates connected to the first and second terminals, respectively.
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 29/94 - Dispositifs à métal-isolant-semi-conducteur, p.ex. MOS
A semiconductor device includes a semiconductor substrate, a gate structure on the semiconductor substrate, the gate structure comprising a source region, a drain region, and a gate electrode, and at least one thermally conductive electrical insulator pillar in contact with the gate structure, wherein the at least one thermally conductive electrical insulator pillar extends from the gate structure to a back end of line (BEOL) layer of the semiconductor device.
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
10.
HETEROJUNCTION BIPOLAR TRANSISTORS WITH TERMINALS HAVING A NON-PLANAR ARRANGEMENT
Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. The structure comprises an intrinsic base including a first semiconductor layer, a collector including a second semiconductor layer, and an emitter including a third semiconductor layer. The first semiconductor layer, which comprises silicon-germanium, includes a first portion and a second portion adjacent to the first portion. The second semiconductor layer includes a portion on the first portion of the first semiconductor layer, and the third semiconductor layer includes a portion on the second portion of the first semiconductor layer. The structure further comprises a dielectric spacer laterally between the portion of the second semiconductor layer and the portion of the third semiconductor layer.
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/165 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée comprenant plusieurs des éléments prévus en dans différentes régions semi-conductrices
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
Structures for a quantum sensor and methods of forming such structures. The structure comprises a first waveguide core, a second waveguide core, and a sensor layer laterally between the first waveguide core and the second waveguide core. The first waveguide core is laterally coupled to the sensor layer, the second waveguide core is laterally coupled to the sensor layer, and the sensor layer comprises a material including a plurality of defect centers capable of photoluminescence.
G02B 6/42 - Couplage de guides de lumière avec des éléments opto-électroniques
G01R 33/032 - Mesure de la direction ou de l'intensité de champs magnétiques ou de flux magnétiques en utilisant des dispositifs magnéto-optiques, p. ex. par effet Faraday
H01L 27/144 - Dispositifs commandés par rayonnement
H01L 31/0232 - Dispositifs à semi-conducteurs sensibles aux rayons infrarouges, à la lumière, au rayonnement électromagnétique d'ondes plus courtes, ou au rayonnement corpusculaire, et spécialement adaptés, soit comme convertisseurs de l'énergie dudit rayonnement e; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives; Leurs détails - Détails Éléments ou dispositions optiques associés au dispositif
12.
ANALYSIS AND MANUFACTURE OF CURVED FEATURES FOR INTEGRATED CIRCUITS
The disclosure provides a method for analysis and manufacture of curved features for integrated circuits. The method includes identifying, within an IC layout, a curved feature including a first endline and a second endline each having at least a threshold length and a curvilinear interval connecting the first endline to the second endline. The method also includes calculating a feature angle and a radius of the curvilinear interval between the first endline and the second endline. Further processing includes determining, based on the feature angle and the radius, whether the curvilinear interval is divisible into a plurality of linear segments each having a same orientation differential relative to the first endline and the second endline. The method additionally includes manufacturing an IC from the layout based on the curvilinear interval and the plurality of linear segments in response to curvilinear interval being divisible into the plurality of linear segments.
G05B 19/18 - Commande numérique [CN], c.-à-d. machines fonctionnant automatiquement, en particulier machines-outils, p. ex. dans un milieu de fabrication industriel, afin d'effectuer un positionnement, un mouvement ou des actions coordonnées au moyen de données d'un programme sous forme numérique
G06F 30/392 - Conception de plans ou d’agencements, p. ex. partitionnement ou positionnement
13.
PHOTONIC INTEGRATED CIRCUIT INCLUDING PLURALITY OF DISCRETE OPTICAL GUARD ELEMENTS
The disclosure relates to a PIC structure including a photonic component on a semiconductor substrate. The photonic component includes an optical absorber including a spiral waveguide body and a linear input waveguide coupled to the spiral waveguide body. A plurality of discrete optical guard elements are in proximity to the photonic component. The plurality of discrete optical guard elements are composed of a light absorbing material and surround the spiral waveguide body and the linear input waveguide.
A structure includes a first layer having inductor windings. An inner area of the first layer is at least partially enclosed by the inductor windings and an outer area of the first layer is separated from the inner area by the inductor windings. This structure further includes a second layer having structural fill elements. The first layer and the second layer are parallel, and the second layer is relatively below the first layer in a direction perpendicular to the first layer. The density of the structural fill elements aligned below the inner area is less than the density of the structural fill elements aligned below the outer area.
The present disclosure relates to semiconductor structures and, more particularly, to a device triggered silicon control rectifier (SCR) and methods of manufacture. the structure includes: a vertical silicon controlled rectifier having a diffusion region in a well of a semiconductor substrate; a vertical triggering device sharing the diffusion region with the vertical silicon controlled rectifier; and a body contact adjacent to the vertical triggering device and electrically connecting to the well.
H10D 89/60 - Dispositifs intégrés comprenant des dispositions pour la protection électrique ou thermique, p. ex. circuits de protection contre les décharges électrostatiques [ESD].
16.
Isolation stack for a bipolar transistor and related methods
The disclosure provides an isolation stack for a bipolar transistor (BT), and related methods. A structure of the disclosure includes a first isolation layer on a subcollector. A first air gap is between the first isolation layer and a collector of a BT. A second isolation layer is on the first isolation layer and adjacent an intrinsic base of the BT. A third isolation layer is on the second isolation layer, vertically between the second isolation layer and an extrinsic base of the BT. A second air gap is adjacent the third isolation layer and below the extrinsic base.
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 62/13 - Régions semi-conductrices connectées à des électrodes transportant le courant à redresser, amplifier ou commuter, p. ex. régions de source ou de drain
H10D 62/17 - Régions semi-conductrices connectées à des électrodes ne transportant pas de courant à redresser, amplifier ou commuter, p. ex. régions de canal
The present disclosure relates to structures including charge pump structures and related methods of operating such structures. A structure of the disclosure includes a first charge pump stage including first branches each connected between an input voltage and ground. The first branches each include first capacitors (C1, C2) connected between first intermediate nodes (Q1, Q1_B) and additional first intermediate nodes (V1, V1_B), respectively. A second charge pump stage includes second branches each connected between second intermediate nodes and additional second intermediate nodes, respectively.
H02M 3/07 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des résistances ou des capacités, p. ex. diviseur de tension utilisant des capacités chargées et déchargées alternativement par des dispositifs à semi-conducteurs avec électrode de commande
18.
STRUCTURE WITH DOPED WELL BETWEEN PHOTODETECTOR AND OPTICAL INTERFACE OF SEMICONDUCTOR LAYER
The disclosure provides a structure with a doped well between a photodetector and an optical interface of a semiconductor layer. A structure of the disclosure includes a semiconductor layer having a first surface configured for optically interfacing with incident radiation, and a second surface opposite the first surface. A photodetector is within the semiconductor layer and on the second surface thereof. A doped well is within the semiconductor layer between the photodetector and the first surface. The doped well has a same conductivity type as the semiconductor layer and a higher dopant concentration than the semiconductor layer.
Disclosed are a semiconductor structure and method of forming the semiconductor structure. The semiconductor structure includes a high-density stacked capacitor and, particularly, a stack of capacitors connected in parallel between two nodes. The stack includes a diode-type capacitor (also referred to herein as a PN junction capacitor) within a semiconductor substrate. In different embodiments, the diode-type capacitor has different in-substrate well configurations. The stack also includes a transistor-type capacitor (e.g., a metal oxide semiconductor capacitor (MOSCAP)) on an insulator layer aligned above the diode-type capacitor. Optionally, the stack also includes at least one additional capacitor (e.g., at metal-oxide-metal capacitor (MOMCAP)) on a dielectric layer aligned above the transistor-type capacitor (e.g., in one or more back end of the line (BEOL) metal levels).
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
H01L 29/94 - Dispositifs à métal-isolant-semi-conducteur, p.ex. MOS
20.
ELECTRO-OPTIC BRIDGE CHIPS FOR CHIP-TO-CHIP COMMUNICATION
Structures including a photonic chip and methods of forming and using such structures. The structure comprises a first substrate, a photonic chip attached to a first portion of the first substrate, and an optical connector including a second substrate and a plurality of piezoelectric actuators disposed between a second portion of the first substrate and the second substrate. The second substrate includes a plurality of waveguide cores disposed adjacent to an interface for light transfer between the waveguide cores and the photonic chip, and the piezoelectric actuators are configured to change an alignment of the waveguide cores at the interface relative to the photonic chip.
A component of a communication device includes at least one active element, at least one passive element coupled to the at least one active element, and a first inductor surrounding the at least one active element and the at least one passive element. The first inductor is included in a redistribution structure.
H03F 1/22 - Modifications des amplificateurs pour réduire l'influence défavorable de l'impédance interne des éléments amplificateurs par utilisation de couplage dit "cascode", c.-à-d. étage avec cathode ou émetteur à la masse suivi d'un étage avec grille ou base à la masse respectivement
H03B 5/12 - Éléments déterminant la fréquence comportant des inductances ou des capacités localisées l'élément actif de l'amplificateur étant un dispositif à semi-conducteurs
H03F 3/24 - Amplificateurs de puissance, p. ex. amplificateurs de classe B, amplificateur de classe C d'étages transmetteurs de sortie
Structures for a photonic chip that include photonic device, such as a ring resonator, and methods of forming such structures. The structure comprises a waveguide core including a first section and a second section separated from the first section by a slot. The first section of the waveguide core includes a first side edge, a second side edge opposite from the first side edge, and a plurality of notches in the first side edge.
G02B 6/12 - Guides de lumièreDétails de structure de dispositions comprenant des guides de lumière et d'autres éléments optiques, p. ex. des moyens de couplage du type guide d'ondes optiques du genre à circuit intégré
G02B 6/13 - Circuits optiques intégrés caractérisés par le procédé de fabrication
G02B 6/293 - Moyens de couplage optique ayant des bus de données, c.-à-d. plusieurs guides d'ondes interconnectés et assurant un système bidirectionnel par nature en mélangeant et divisant les signaux avec des moyens de sélection de la longueur d'onde
23.
MODULATORS BASED ON CASCADED MACH-ZEHNDER INTERFEROMETERS
Structures for a modulator and methods of forming a structure for a modulator. The structure comprises a first waveguide core including a delay section, and a second waveguide core including a delay section. The delay section of the second waveguide core has a shorter length than the delay section of the first waveguide core. The structure further comprises an optical phase shifter including a p-n junction in a portion of the delay section of the first waveguide core.
G02F 1/21 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p. ex. commutation, ouverture de porte ou modulationOptique non linéaire pour la commande de l'intensité, de la phase, de la polarisation ou de la couleur par interférence
G02F 1/225 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p. ex. commutation, ouverture de porte ou modulationOptique non linéaire pour la commande de l'intensité, de la phase, de la polarisation ou de la couleur par interférence dans une structure de guide d'ondes optique
The present disclosure relates to semiconductor structures and, more particularly, to a stacked high-power radio frequency (RF) switch and methods of manufacture. The structure includes: a top substrate having at least one top transistor and metal wiring structures; and a bottom substrate having at least one bottom transistor and metal wiring structure. The bottom substrate is attached to the top substrate with the at least one top transistor being electrically connected to the at least one bottom transistor. A portion of the metal wiring structures of the top substrate and a portion of the metal wiring structures of the bottom substrate being at least one shared capacitor between the at least one top transistor and the at least one bottom transistor. Airgaps may be formed above the transistor.
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
25.
STRUCTURE AND METHOD FOR MAGNETIC CORE WITH STACKED MAGNETICALLY ANISOTROPIC LAYERS
Embodiments of the disclosure provide a structure and method for a magnetic core with stacked magnetically anisotropic layers. A structure of the disclosure provides a magnetic core including a plurality of stacked magnetically anisotropic layers. Each of the plurality of stacked magnetically anisotropic layers has a hard axis angularly offset from an adjacent hard axis of an adjacent magnetically anisotropic layer. An inductor coil is on the magnetic core.
H01F 1/03 - Aimants ou corps magnétiques, caractérisés par les matériaux magnétiques appropriésEmploi de matériaux spécifiés pour leurs propriétés magnétiques en matériaux inorganiques caractérisés par leur coercivité
H01F 41/02 - Appareils ou procédés spécialement adaptés à la fabrication ou à l'assemblage des aimants, des inductances ou des transformateursAppareils ou procédés spécialement adaptés à la fabrication des matériaux caractérisés par leurs propriétés magnétiques pour la fabrication de noyaux, bobines ou aimants
26.
GATE STRUCTURE WITH JUTTED REGION OVER CORNER SEGMENT OF SEMICONDUCTOR REGION
Embodiments of the disclosure provide a gate structure including a jutted region over a corner segment of a semiconductor region. A structure according to the disclosure includes a semiconductor region within a substrate. The semiconductor region includes a first edge, a second edge oriented perpendicularly to the first edge, and a first corner segment connecting the first edge to the second edge. A gate structure includes a jutted region including a curvilinear portion(s) or angled linear portion(s) over corner segment(s).
Structures including a photonic device, such as a spot-size converter, and an undercut, and related methods. The structure comprises a photonic device, a semiconductor substrate, and a dielectric layer disposed between the photonic device and the semiconductor substrate. The dielectric layer includes a plurality of D-shaped openings that are laterally offset from the photonic device, and each of the plurality of D-shaped openings has a first sidewall portion that is curved and a second sidewall portion that is substantially planar.
Disclosed is a charge pump circuit including: a single primary charge pump stage or multiple primary charge pump stages connected in series; a pass transistor connected between an output node of the primary charge pump stage (or of the last of the multiple primary charge pump stages, if applicable) and an output terminal; and a supplementary charge pump stage. The supplementary charge pump stage receives the same input voltage as the primary charge pump stage (or the same input voltage as the last of the multiple primary charge pump stages, if applicable) and controls the gate of the pass transistor to reduce ripple at the output terminal. A capacitive load can also be connected to the output terminal to reduce ripple and the size of the capacitive load can be selected to achieve a desired balance between the amount of ripple and circuit size.
H02M 3/07 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des résistances ou des capacités, p. ex. diviseur de tension utilisant des capacités chargées et déchargées alternativement par des dispositifs à semi-conducteurs avec électrode de commande
29.
Field plate structure to reduce self-heating in transistor and related method
A structure includes a transistor, e.g., HEMT, with a field plate positioned laterally to a side of an active gate and including a first portion extending over the active gate. A dielectric layer isolates a lower surface of the first portion from an upper surface of the active gate. A field plate contact includes interconnect layers located directly over the active gate and electrically coupled to the first portion directly over the active gate. The field plate contact allows electrical operation of the field plate, but also acts as a thermally conductive path from the active gate through the interconnect layers to cool likely hot spots within the transistor.
H10D 64/00 - Électrodes de dispositifs ayant des barrières de potentiel
H10D 30/47 - Transistors FET ayant des canaux à gaz de porteurs de charge de dimension nulle [0D], à une dimension [1D] ou à deux dimensions [2D] ayant des canaux à gaz de porteurs de charge à deux dimensions, p. ex. transistors FET à nanoruban ou transistors à haute mobilité électronique [HEMT]
30.
VOLTAGE REGULATOR INCLUDING A PAIR OF FEEDBACK CONTROL LOOPS FOR DRIVE TRANSISTOR CONTROL
A low drop-out voltage regulator (LDO) circuit structure includes a drive transistor with first connected to an input voltage node, a second terminal connected to an output voltage node and a voltage divider, and a third terminal (i.e., a control terminal). The structure employs a pair of concurrently operating feedback control loops between a feedback voltage node of the voltage divider and the control terminal to continuously adjust a control voltage applied to the control terminal and thereby reduce ripple of an output voltage (Vout) at the output voltage node. A first feedback control loop includes comparator and a push capacitor connected between the feedback voltage node and the control terminal. The second feedback control loop includes an operational amplifier connected between the feedback voltage node and the control terminal. The first feedback control loop operates a faster speed than the second to quickly initiate the necessary control voltage adjustments.
G05F 1/575 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final caractérisé par le circuit de rétroaction
31.
STRUCTURES INCLUDING AN ISOTOPICALLY-DEPLETED SEMICONDUCTOR LAYER
Structures that include an isotopically-depleted semiconductor layer and methods of forming such structures. The structure comprises a semiconductor layer comprising a semiconductor material having an isotope with a concentration that is less than a natural abundance of the first isotope and greater than zero parts per million.
H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
32.
ISOLATION STRUCTURE FOR MULTI-VOLTAGE INTEGRATED CIRCUIT
Disclosed are embodiments of an integrated circuit (IC) including a first IC section operating in a first voltage domain, a second IC section operating in a second voltage domain, and an isolation structure between the two sections. The isolation structure can include a trench isolation region within a semiconductor layer, isolating first PFETs and, optionally, isolating second PFETs. The isolating first PFETs can be series-connected and can include a first portion of the semiconductor layer between a functional PFET of the first IC section and a first edge of the trench isolation region. Additionally, the isolating first PFETs can operate in the first voltage domain and can be biased so as to remain always off. The isolating second PFETs can be similarly configured between a functional PFET of the second IC section and a second edge of the trench isolation region opposite the first edge.
H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant
33.
CHARGE PUMP WITH PASS TRANSISTOR CONTROLLED BY A SUPPLEMENTARY CHARGE PUMP STAGE
Disclosed is a charge pump circuit including: a single primary charge pump stage or multiple primary charge pump stages connected in series; a pass transistor connected between an output node of the primary charge pump stage (or of the last of the multiple primary charge pump stages, if applicable) and an output terminal; and a supplementary charge pump stage. The supplementary charge pump stage receives the same input voltage as the primary charge pump stage (or the same input voltage as the last of the multiple primary charge pump stages, if applicable) and controls the gate of the pass transistor to reduce ripple at the output terminal. A capacitive load can also be connected to the output terminal to reduce ripple and the size of the capacitive load can be selected to achieve a desired balance between the amount of ripple and circuit size.
H02M 3/07 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des résistances ou des capacités, p. ex. diviseur de tension utilisant des capacités chargées et déchargées alternativement par des dispositifs à semi-conducteurs avec électrode de commande
H02M 1/15 - Dispositions de réduction des ondulations d'une entrée ou d'une sortie en courant continu utilisant des éléments actifs
34.
CAPACITIVE JUNCTION BETWEEN CONDUCTIVE LINE AND CONDUCTIVE PILLAR WITH METHODS TO FORM SAME
Structures of the disclosure include a first conductive line within a dielectric material. The dielectric material extends over the first conductive line. A second conductive line is within the dielectric material and substantially vertically aligned with the first conductive line. A conductive pillar is within the dielectric material between the first conductive line and the second conductive line. The conductive pillar includes an upper surface contacting a lower surface of the second conductive line or a lower surface contacting an upper surface of the first conductive line. A vertical thickness of the conductive pillar is less than a vertical thickness between the first conductive line and the second conductive line. a first capacitive junction is between the conductive pillar and one of the first conductive line and the second conductive line. A second capacitive junction is between the conductive pillar and a horizontally adjacent conductive pillar.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/528 - Configuration de la structure d'interconnexion
35.
Field-effect transistors with heterogenous doped regions in the substrate of a silicon-on-insulator substrate
Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure comprises a silicon-on-insulator substrate including a semiconductor layer, a semiconductor substrate, and a dielectric layer between the semiconductor layer and the semiconductor substrate. The semiconductor substrate includes first and second doped regions, the first doped region has a first conductivity type, and the second doped region has a second conductivity type different from the first conductivity type. The structure further comprises first and second source/drain regions in the semiconductor layer, and a gate structure laterally between the first source/drain region and the second source/drain region. The first source/drain region overlaps with the first doped region, and the second source/drain region overlaps with the second doped region.
H10D 86/00 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre
H10D 62/13 - Régions semi-conductrices connectées à des électrodes transportant le courant à redresser, amplifier ou commuter, p. ex. régions de source ou de drain
H10D 64/23 - Électrodes transportant le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. sources, drains, anodes ou cathodes
36.
BIPOLAR TRANSISTOR STRUCTURE WITH FERROELECTRIC MATERIAL
Embodiments of the disclosure provide a bipolar transistor structure with a ferroelectric material. A structure of the disclosure may include a base over a substrate. The base includes a first portion laterally between an emitter and a collector, and a second portion over the first portion. A ferroelectric spacer is adjacent the second portion of the base. Other structures include a ferroelectric layer over a back gate terminal of a substrate. A base is on the ferroelectric layer. The base includes a first portion laterally between an emitter and a collector, and a second portion over the first portion.
H01L 29/51 - Matériaux isolants associés à ces électrodes
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
A pre-driver includes first, second, third, and fourth P-channel field effect transistors (PFETs) with voltage ratings equal to a low first voltage (V1). Between power rails at V1 and at a higher second voltage (V2), the first and third PFETs are series-connected and the second and fourth PFETs are also series-connected. The third and fourth PFETs are cross-coupled. The first and second PFETs have gates that receive a pre-driver input signal (Pin) that switches between V2 and ground and an inverted pre-driver input signal (Pinb), respectively. At an output node between the first and third PFETs, the pre-driver outputs a driver input signal (Din) that switches between V2 and V1. A circuit includes this pre-driver (e.g., connected between a voltage level shifter and a driver or connected between a voltage level shifter and a buffer).
H03K 19/0185 - Dispositions pour le couplageDispositions pour l'interface utilisant uniquement des transistors à effet de champ
H03K 17/687 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
38.
THREE-DIMENSIONAL INTEGRATED CIRCUIT (3DIC) AND 3DIC DESIGN METHOD AND SYSTEM
A three-dimensional integrated circuit (3DIC) design method and system includes metal stack and bonding pitch optimization to improve power, performance, and area (PPA). The resulting 3DIC includes a first chip and a second chip. A last metal level of the second chip can be bonded to the last metal level of the first chip by bonding elements. The bonding pitch of the bonding elements can be at least as large as the pitches of the first chip last metal level and the second chip last metal level. The metal stack configurations of each chip may be the same or different. With different metal stack configurations, the total numbers of metal levels on each chip, the thicknesses of the metal levels on each chip and/or the pitches of the last metal levels on each chip may be different.
Structures for a photonic chip that enable the measurement of the group velocity of light in a photonic component and methods of forming such structures. The structure comprises a photonic component having an input and an output, a first waveguide core including a first section coupled to the input of the photonic component, and a second waveguide core including a second section coupled to the output of the photonic component. The structure further comprises a first reflector adjacent to the first section of the first waveguide core, and a second reflector adjacent to the second section of the second waveguide core.
G02B 6/12 - Guides de lumièreDétails de structure de dispositions comprenant des guides de lumière et d'autres éléments optiques, p. ex. des moyens de couplage du type guide d'ondes optiques du genre à circuit intégré
G02B 6/125 - Courbures, branchements ou intersections
G02B 6/126 - Guides de lumièreDétails de structure de dispositions comprenant des guides de lumière et d'autres éléments optiques, p. ex. des moyens de couplage du type guide d'ondes optiques du genre à circuit intégré utilisant des effets de polarisation
A disclosed low noise amplifier (LNA) includes a common-emitter amplifier (CE-A), a common-gate amplifier (CG-A) and various passive devices in CE-A and CG-A. CE-A includes an NPN-type bipolar junction transistor (BJT) with emitter and collector (E/C) regions and a base region between the E/C regions and connected to an input node. CG-A includes P-channel field effect transistor (PFET) with source and drain (S/D) regions, a channel region between the S/D region, and a gate adjacent to the channel region. The drain region of the PFET is connected to an output node. Additionally, a common inductor, collector region of the BJT, and source region of the PFET are connected at an intermediate node. The LNA is implemented on a three-dimensional integrated circuit (3DIC) with the BJT and FET on different chips and with passive devices in back end of the line regions between the BJT and FET.
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/66 - Types de dispositifs semi-conducteurs
H03F 3/213 - Amplificateurs de puissance, p. ex. amplificateurs de classe B, amplificateur de classe C comportant uniquement des dispositifs à semi-conducteurs dans des circuits intégrés
Structures including a photonic device with thermal isolation and related methods. The structure comprises a semiconductor substrate including a first cavity, a second cavity, and a wall between the first cavity and the second cavity. The structure further comprises a photonic device over the first cavity, the second cavity, and the wall, and a dielectric layer between the photonic device and the wall of the semiconductor substrate.
H01L 31/024 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de température
H01L 31/0232 - Dispositifs à semi-conducteurs sensibles aux rayons infrarouges, à la lumière, au rayonnement électromagnétique d'ondes plus courtes, ou au rayonnement corpusculaire, et spécialement adaptés, soit comme convertisseurs de l'énergie dudit rayonnement e; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives; Leurs détails - Détails Éléments ou dispositions optiques associés au dispositif
H01L 31/0352 - Dispositifs à semi-conducteurs sensibles aux rayons infrarouges, à la lumière, au rayonnement électromagnétique d'ondes plus courtes, ou au rayonnement corpusculaire, et spécialement adaptés, soit comme convertisseurs de l'énergie dudit rayonnement e; Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de ces dispositifs ou de leurs parties constitutives; Leurs détails caractérisés par leurs corps semi-conducteurs caractérisés par leur forme ou par les formes, les dimensions relatives ou la disposition des régions semi-conductrices
42.
INDUCTOR STRUCTURE INTEGRATED IN SEMICONDUCTOR DEVICE
The disclosed subject matter relates generally to an inductor structure integrated in a semiconductor device formed from bonded wafers, in which the semiconductor device has a three-dimensional inductor structure aligned vertically between two integrated circuit (IC) components. The inductor structure has a first metal level and a second metal level, the first metal level being in a different wafer from the second metal level.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
A structure includes a first chip having a first surface and a second chip having a second surface adjacent to the first surface of the first chip. The first chip includes a first optical component and an optical waveguide protrusion adjacent to the first optical component. The optical waveguide protrusion extends above the first surface of the first chip. The second chip includes a second optical component and a groove adjacent to the second optical component. The groove extends from the second surface of the second chip and into a portion of the second chip. The optical waveguide protrusion is positioned in the groove in the second chip.
G02B 6/293 - Moyens de couplage optique ayant des bus de données, c.-à-d. plusieurs guides d'ondes interconnectés et assurant un système bidirectionnel par nature en mélangeant et divisant les signaux avec des moyens de sélection de la longueur d'onde
44.
HETEROJUNCTION BIPOLAR TRANSISTOR WITH BURIED TRAP RICH ISOLATION REGION
The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich isolation region and methods of manufacture. The structure includes: a first heterojunction bipolar transistor; a second heterojunction bipolar transistor; and a trap rich isolation region embedded within a substrate underneath both the first heterojunction bipolar transistor and the second heterojunction bipolar transistor.
H10D 84/60 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors BJT
A structure including a first fin-type field effect transistor (finFET) in a first semiconductor fin. The first finFET includes a channel region between a first source/drain (S/D) region and a second S/D region; and a gate all around (GAA) structure. The GAA structure includes an outer gate region over the channel region and a buried gate region under of the channel region and extending between the first S/D region and the second S/D region. The outer gate region and the buried gate region each include a gate metal layer and a gate dielectric layer. The gate dielectric layer is thicker in the buried gate region than in the outer gate region.
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
Disclosed design methods and systems employ linear distance marker(s) (LDM(s)) placed over a layout (e.g., of a device or cell) to be analyzed. Nodes are inserted into LDM(s) at intersections with edges of layout shapes. Node-to-node distances (d) for node-to-node segments on LDM(s) are calculated. Design rules with distance specifications (D) are identified and assigned to the segments. A first table is generated and includes, for each segment, the design rule, d, and D. A second table is generated and includes, for each segment in a user-specified subset of segments, the design rule and either D or a user-specified compacted distance specification (C). An output table is generated and includes, for each segment in the subset, the design rule, d, and either D or C. The output table can be analyzed manually and/or automatically to determine if compaction is feasible. Additional embodiments use LDMs to profile devices within a layout.
G06F 30/392 - Conception de plans ou d’agencements, p. ex. partitionnement ou positionnement
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
The present disclosure relates to semiconductor structures and, more particularly, to a device with a self-aligned inner spacer sidewall structures. The structure includes: a gate structure on a semiconductor substrate; a gate metal connecting to the gate structure and offset from edges of the gate structure; and inner sidewall spacers on an upper surface of the gate structure and surrounding the gate metal.
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
The present disclosure relates to semiconductor structures and, more particularly, to a device with inner and outer spacer structures and methods of manufacture. The structure includes: a gate structure on a semiconductor substrate; a gate metal connecting to the gate structure; inner sidewall spacers contacting and surrounding the gate metal; a passivation layer on the inner sidewall spacers; and outer sidewall spacers on the passivation layer and adjacent to sides of the gate structure.
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
A transceiver front-end (FE) includes a receiver from an I/O pad to an amplifier (e.g., a low noise amplifier (LNA)) and a transmitter from the I/O pad to another amplifier (e.g., a power amplifier (PA)). The receiver further includes a variable inductor connected at one end to the I/O pad and connectable at the opposite end to ground by a switch. The LNA is connected to a node between portions of the inductor. When receiving, the switch is opened so the inductor exhibits low inductance for LNA impedance matching. When transmitting, the switch is closed so the inductor exhibits high inductance for blocking leakage to the LNA. Additionally, or alternatively, the transmitter includes a variable capacitor connected to the I/O pad. When receiving, the capacitor is programmed to exhibit low capacitance for optimal LNA performance. When transmitting, the capacitor is programmed to exhibit high capacitance for optimal PA performance.
H04B 1/525 - Dispositions hybrides, c.-à-d. dispositions pour la transition d’une transmission bilatérale sur une voie à une transmission unidirectionnelle sur chacune des deux voies ou vice versa avec des moyens de réduction de la fuite du signal de l’émetteur vers le récepteur
A multiplexing circuit for a memory, including: a first parallel branch for coupling a program voltage to a first bitline corresponding to a first bit cell of the memory during a program mode of the memory; and a second parallel branch for coupling a program inhibit voltage to a plurality of additional bitlines corresponding to a plurality of additional bit cells of the memory during a program inhibit mode of the memory, wherein the first parallel branch couples an erase inhibit voltage to the plurality of additional bitlines during an erase inhibit mode of the memory, and wherein the second parallel branch couples an erase voltage to the first bitline during an erase mode of the memory.
A structure including a first emitter-collector (E/C) layer over a substrate. The structure further includes an intrinsic base layer over the first E/C layer and a second E/C layer over the intrinsic base layer. The structure includes an extrinsic base layer on the intrinsic base layer and adjacent the second E/C layer. The structure includes a gate structure on the intrinsic base layer and overhanging a lateral sidewall of the intrinsic base.
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
The present disclosure relates to semiconductor structures and, more particularly, to devices with an outer conductive spacer and methods of manufacture. The structure includes: a gate structure; a gate metal connecting to the gate structure; inner spacers contacting and surrounding the gate metal; a passivation layer on the inner spacers; and outer conductive spacers on the passivation layer and adjacent to sides of the gate structure.
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
53.
STRUCTURE AND METHOD FOR AN INDUCTOR HAVING A WINDING WITH A FIRST SEGMENT CONNECTED TO TWO SECOND SEGMENTS
The disclosure provides a structure and method for an inductor having a winding with a first segment connected to two second segments. An inductor according to the disclosure includes a plurality of windings coupled together in series about a magnetic core. At least one of the plurality of windings includes a first segment in a first wiring layer and extending over a width of the magnetic core. A second segment is within a second wiring layer and coupled to the first segment through a vertical interconnect. The second segment includes two sub-segments separated by a gap along a length of the magnetic core.
A radio frequency (RF) switch includes a transistor stack with different sections having different configurations for achieving different parasitic capacitances. Specifically, a first section is connected to an input terminal and a second section is connected between the first section and an output terminal. The second section has over-gate gaps for reduced source-to-drain capacitance, whereas the first section does not. Additionally, gate-to-source/drain contact spacing can be larger in the second section than in the first section, transistor layout length can be longer in the second section than in the first section and/or source and drain interconnect interdigitation can be less in the second section than in the first section. Optionally, sub-sections of the series-connected transistors within the first and/or second sections also have different configurations. Thus, numbers and sizes of compensation capacitors within the switch and overall chip area consumed by the switch are reduced while maintaining a high Pmax.
H03K 17/10 - Modifications pour augmenter la tension commutée maximale admissible
H03K 17/041 - Modifications pour accélérer la commutation sans réaction du circuit de sortie vers le circuit de commande
H03K 17/687 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
In a disclosed Schmitt trigger, an input stage includes a first p-channel field effect transistor (PFET) and a second PFET, which are connected in series to a VDD rail, and a first n-channel field effect transistor (NFET) and a second NFET, which are connected in series between ground and the second PFET. An output stage includes additional FETs for hysteresis. The first PFET and first NFET are different from the other FETs and have a higher voltage rating. For example, the first PFET and first NFET can be buried oxide field effect transistors (BOXFETs) and the other FETs can be laterally diffused metal oxide semiconductor field effect transistors (LDMOSFETs)). Gates of the first PFET and first NFET are connected to an input node. Gates of the second PFET and NFET are connected to receive reference voltages to prevent safe operating area (SOA) violations and control trigger voltage levels.
H10D 30/65 - Transistors FET DMOS latéraux [LDMOS]
H10D 86/00 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre
56.
SEMICONDUCTOR LAYERS FORMED BY LATERAL EPITAXIAL GROWTH
Structures that include a semiconductor layer formed by lateral epitaxial growth and methods of forming such structures. The structure comprises a first semiconductor layer that includes first and second sections, and that comprises a first single-crystal semiconductor material. The structure further comprises a second semiconductor layer that includes a section and a semiconductor region, and that comprises one or more second single-crystal semiconductor materials. The semiconductor region extends between the second section of the first semiconductor layer and the section of the second semiconductor layer. An opening penetrates at least partially through the first semiconductor layer and through the second semiconductor layer. The opening is oriented along a (100) crystal plane of the first single-crystal semiconductor material, and the semiconductor region borders the opening. A dielectric layer is positioned between the first section of the first semiconductor layer and the section of the second semiconductor layer.
G02F 1/015 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p. ex. commutation, ouverture de porte ou modulationOptique non linéaire pour la commande de l'intensité, de la phase, de la polarisation ou de la couleur basés sur des éléments à semi-conducteurs ayant des barrières de potentiel, p. ex. une jonction PN ou PIN
57.
STRUCTURE WITH TWO WORK FUNCTION METALS OVER CONDUCTIVE BRIDGE, AND METHOD TO FORM SAME
A structure, including an insulator within a substrate. The substrate includes a first active region adjacent a first sidewall of the insulator and a second active region adjacent a second sidewall of the insulator opposite the first sidewall. The structure further includes a conductive bridge over the insulator and coupling the first active region of the substrate to the second active region of the substrate. The structure includes a gate dielectric layer over the conductive bridge, a first work function metal over the first active region, and a second work function metal over the second active region.
H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant
H01L 27/085 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ
58.
INTEGRATED CIRCUIT DESIGN METHOD AND SYSTEM EMPLOYING PARASITIC DIODE ANALYSIS
Disclosed are embodiments of computer-aided design (CAD) methods and systems that employ one or more electronic design automation (EDA) tools to flag parasitic diodes within a layout or netlist (depending upon the embodiments). In one embodiment, information contained in process design kit (PDK) tables (e.g., a first table with layer-specific design rules for devices in a processing technology and a second table with descriptions of parasitic diodes in the processing technology) can be used to identify any parasitic diodes within a displayed portion of an IC design layout. Once identified, parasitic diodes can be flagged within the displayed portion of the layout to provide visual cues intended to draw a user's attention to the parasitic diodes during the design process to ensure that any unintended or unwanted parasitic diodes are either accounted for when predicting IC performance or removed from the design to avoid a negative impact on performance.
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
59.
STRUCTURES INCLUDING A SEMICONDUCTOR LAYER FORMED BY LATERAL EPITAXIAL GROWTH
Structures that include a semiconductor layer formed by lateral epitaxial growth and methods of forming such structures. The structure comprises a first semiconductor layer including a first section and a second section adjacent to the first section, a second semiconductor layer including a section and a semiconductor region that projects from the second section of the first semiconductor layer to the section of the second semiconductor layer, and a dielectric layer disposed between the first section of the first semiconductor layer and the section of the second semiconductor layer. The section and the semiconductor region of the second semiconductor layer comprise one or more single-crystal semiconductor materials.
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
C30B 1/02 - Croissance des monocristaux à partir de l'état solide par traitement thermique, p. ex. recuit sous contrainte
H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant
The present disclosure relates to semiconductor structures and, more particularly, to a device triggered silicon control rectifiers (SCR) and methods of manufacture. The structure includes: a first device comprising a first shallow diffusion region of a first conductivity type within a first well of a second conductivity type and a second shallow diffusion region of the first conductivity type within the first well of the second conductivity type.
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
H01L 29/74 - Dispositifs du type thyristor, p.ex. avec un fonctionnement par régénération à quatre zones
61.
EXTENDED DRAIN METAL OXIDE SEMICONDUCTOR (EDMOS) FIELD EFFECT TRANSISTOR (FET) WITH DUAL THICKNESS SEMICONDUCTOR MATERIAL
The present disclosure relates to semiconductor structures and, more particularly, to an extended drain metal oxide semiconductor (EDMOS) field effect transistor (FET) with a fully depleted region comprising a dual thicknesses semiconductor material and methods of manufacture. The structure includes: a semiconductor on insulator (SOI) material including a first portion with a first thickness and a second portion with a second thickness; a gate structure on the SOI material over the first portion with the first thickness; and sidewall spacers adjacent to the gate structure, with at least one sidewall spacer extending over both the first portion with the first thickness and the second portion with the second thickness.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
62.
Device structures for a high-voltage semiconductor device
Device structures for a high-voltage semiconductor device and methods of forming such device structures. The structure comprises a layer stack including a first dielectric layer and a second dielectric layer. The first dielectric layer includes a portion between the second dielectric layer and a semiconductor substrate. The structure further comprises a field-effect transistor including a first source/drain region in the semiconductor substrate, a second source/drain region in the semiconductor substrate, and a gate electrode on the layer stack. The gate electrode is laterally between the first and second source/drain regions, and the gate electrode overlaps with the portion of the first dielectric layer and the second dielectric layer. The structure further comprises a spacer laterally between the first source/drain region and the second dielectric layer.
H10D 64/66 - Électrodes ayant un conducteur couplé capacitivement à un semi-conducteur par un isolant, p. ex. électrodes du type métal-isolant-semi-conducteur [MIS]
H10D 64/68 - Électrodes ayant un conducteur couplé capacitivement à un semi-conducteur par un isolant, p. ex. électrodes du type métal-isolant-semi-conducteur [MIS] caractérisées par l’isolant, p. ex. par l’isolant de grille
Structures for a photonics chip that include a photodetector and methods of forming such structures. The structure comprises a photodetector including a pad and a semiconductor layer on the pad. The pad includes a side edge and a first waveguide core that extends from the side edge adjacent to the semiconductor layer. The structure further comprises a second waveguide core including a section adjoined to the side edge of the pad adjacent to the first waveguide core.
Embodiments of the disclosure provide a crystalline semiconductor layer between a bipolar transistor structure and a field effect transistor (FET) structure. The structure includes a dielectric layer on a back-gate semiconductor layer, a bipolar transistor structure on the dielectric layer, FET structure on the dielectric layer, and a crystalline semiconductor layer on the dielectric layer between the bipolar transistor structure and the FET structure. The crystalline semiconductor layer includes a terminal of the bipolar transistor structure and a terminal of the FET structure.
H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant
Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. The structure comprises a first semiconductor layer including a first portion, a second portion, and a third portion between the first portion and the second portion, a first terminal including a first semiconductor region on the first portion of the first semiconductor layer, a second terminal including a second semiconductor region on the second portion of the first semiconductor layer, an intrinsic base laterally disposed between the first terminal and the second terminal, and an extrinsic base on the intrinsic base. The intrinsic base includes a doped region in the third portion of the first semiconductor layer, and the doped region has a dopant depth profile with a dopant concentration that is asymmetrical relative to the first terminal and the second terminal.
Embodiments of the disclosure provide a structure including a first back-gate well adjacent a second back-gate well. A bipolar transistor (BT) is over the first back-gate well and includes a base structure laterally between a set of emitter/collector (E/C) terminals and extending longitudinally away from the set of E/C terminals. A field effect transistor (FET) is over the second back-gate well and includes a gate structure laterally between a set of source/drain (S/D) terminals and extending longitudinally away from the set of S/D terminals toward the BT. The gate structure is coupled to the base structure.
H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant
H01L 21/84 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant autre chose qu'un corps semi-conducteur, p.ex. étant un corps isolant
67.
PHOTODETECTORS WITH AN ADJOINED SLOTTED WAVEGUIDING STRUCTURE
Structures for a photonics chip that include a photodetector and methods of forming such structures. The structure comprises a photodetector including a pad and a semiconductor layer on the pad. The structure further comprises a waveguiding structure including a first waveguide core, a second waveguide core, a slot between the first waveguide core and the second waveguide core, and a plurality of waveguide core segments. The waveguiding structure is adjoined to a side edge of the pad adjacent to the semiconductor layer. Each of the plurality of waveguide core segments includes a portion that is disposed in the slot.
The present disclosure relates to semiconductor structures and, more particularly, to cell layouts in semiconductor structures and methods of manufacture. A structure includes: a plurality of abutting cells each of which include transistors with gate structures having diffusion regions; a contact spanning across abutting cells of the plurality of abutting cells and contacting to the diffusion regions of separate cells of the abutting cells; and a continuous active region spanning across the plurality of abutting cells, wherein the continuous active region includes a drain-source abutment with L-shape construct, a source-source abutment with U-shape construct, and a drain-drain abutment with a filler cell located between a drain-drain abutment.
H10D 84/03 - Fabrication ou traitement caractérisés par l'utilisation de technologies basées sur les matériaux utilisant une technologie du groupe IV, p. ex. technologie au silicium ou au carbure de silicium [SiC]
H10D 84/85 - Transistors IGFET complémentaires, p. ex. CMOS
H10D 84/90 - Circuits intégrés à tranches maîtresses
The present disclosure relates to semiconductor structures and, more particularly, to a differential circuit with automatic parasitic neutralization and gain boost and methods of manufacture. The structure includes a plurality of auxiliary circuit devices with back-gate controls to perform a boost gain, and a differential pair of circuit devices which are connected to the auxiliary circuit devices.
H03F 1/32 - Modifications des amplificateurs pour réduire la distorsion non linéaire
H03F 3/213 - Amplificateurs de puissance, p. ex. amplificateurs de classe B, amplificateur de classe C comportant uniquement des dispositifs à semi-conducteurs dans des circuits intégrés
A serpentine resistor within a back end of line (BEOL) level of a substrate includes a plurality of first sections oriented in a first horizontal direction, at least one second section oriented in a second horizontal direction, a plurality of vertical sections, and at least one lateral turn between the first horizontal direction and the second horizontal direction. The serpentine resistor may have a serpentine shape in the vertical plane and the horizontal plane, and may extend between two bonded substrates, providing higher resistance values compared to conventional BEOL resistors.
H01L 27/08 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
The present disclosure relates to semiconductor structures and, more particularly, to a transistor triggered silicon control rectifier (SCR) and methods of manufacture. The structure includes: a vertical silicon controlled rectifier; and a triggering device adjacent to the vertical silicon controlled rectifier, the triggering device and the vertical silicon controlled rectifier sharing a diffusion region within a semiconductor substrate.
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
The present disclosure relates to semiconductor structures and, more particularly, to a device triggered silicon control rectifier (SCR) and methods of manufacture. The structure includes: a vertical silicon controlled rectifier; a lateral triggering device including a first diffusion region, a second diffusion region and a third diffusion region, the third diffusion region being shared with the vertical silicon controlled rectifier; and a body contact over the first diffusion region.
H01L 29/74 - Dispositifs du type thyristor, p.ex. avec un fonctionnement par régénération à quatre zones
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
Device structures for a high-voltage semiconductor device and methods of forming such device structures. The structure comprises a semiconductor substrate including a trench, and a field-effect transistor including a first and second source/drain regions in the semiconductor substrate, a gate dielectric inside the trench, and a gate on the gate dielectric. The gate and the gate dielectric are disposed laterally between the first and second source/drain regions.
H10D 84/03 - Fabrication ou traitement caractérisés par l'utilisation de technologies basées sur les matériaux utilisant une technologie du groupe IV, p. ex. technologie au silicium ou au carbure de silicium [SiC]
74.
STACKED TRENCH CAPACITORS AND METHODS OF MAKING THEREOF
Stacked trench capacitors and methods of making the same are provided. Stacked trench capacitor comprises a first conductive layer and a second conductive layer in a first dielectric layer over a first semiconductor substrate, and a third conductive layer and a fourth conductive layer in a second dielectric layer. The first and second conductive layers are spaced by a first insulator layer, and the third and fourth conductive layers are spaced by a second insulator layer, and the second conductive layer is directly contacting the third conductive layer. A second semiconductor substrate is over the fourth conductive layer.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01G 4/012 - Forme des électrodes non autoporteuses
Structures for an optical component, such as an optical reflector or an Echelle grating, and methods of forming such structures. The structure comprises a first waveguide core positioned in a vertical direction over a semiconductor substrate. The first waveguide core includes a tapered section and a plurality of segments separated by a plurality of gaps. A second waveguide core, which is positioned in the vertical direction relative to the first waveguide core, includes a portion positioned adjacent to the first waveguide core.
G02B 6/122 - Éléments optiques de base, p. ex. voies de guidage de la lumière
G02B 6/12 - Guides de lumièreDétails de structure de dispositions comprenant des guides de lumière et d'autres éléments optiques, p. ex. des moyens de couplage du type guide d'ondes optiques du genre à circuit intégré
G02B 6/124 - Lentilles géodésiques ou réseaux intégrés
G02B 6/13 - Circuits optiques intégrés caractérisés par le procédé de fabrication
Structures for a waveguide escalator, as well as methods of forming such structures. The structure comprises a first waveguide core on a substrate, a second waveguide core, and a back-end-of-line stack including a third waveguide core disposed between the first waveguide core and the second waveguide core. The third waveguide core comprises a layer stack that includes a first layer, a second layer, and a third layer between the first layer and the second layer. The first layer and the second layer comprise a first dielectric material with a first refractive index, and the third layer comprises a second dielectric material with a second refractive index that is less than the first refractive index.
G02B 6/12 - Guides de lumièreDétails de structure de dispositions comprenant des guides de lumière et d'autres éléments optiques, p. ex. des moyens de couplage du type guide d'ondes optiques du genre à circuit intégré
G02B 6/122 - Éléments optiques de base, p. ex. voies de guidage de la lumière
G02B 6/13 - Circuits optiques intégrés caractérisés par le procédé de fabrication
77.
HETEROJUNCTION BIPOLAR TRANSISTOR WAFERS WITH BACKSIDE SUB-COLLECTOR CONTACT
The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistor wafers with backside sub-collector contact and methods of manufacture. The structure includes: a first chiplet comprising a first device with a backside contact; and a second chiplet connected to the first chiplet, the second chiplet comprising a second device with a frontside contact.
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor and methods of manufacture. The structure includes: a collector region; an extrinsic base comprising an emitter opening with an angled sidewall; an emitter within the emitter opening; and an intrinsic base between the emitter and the collector.
H10D 62/17 - Régions semi-conductrices connectées à des électrodes ne transportant pas de courant à redresser, amplifier ou commuter, p. ex. régions de canal
79.
IQ phase imbalance calibration using sampling clock delay adjustment
A system for phase imbalance calibration, including: an in-phase (I) signal channel including an analog-to-digital converter (ADC) for sampling an I signal to provide a sampled I signal; a quadrature (Q) signal channel including an ADC for sampling a Q signal to provide a sampled Q signal; a sampling clock for controlling the sampling of the ADC on the I signal channel and the sampling of the ADC on the Q signal channel; and sampling clock delay circuitry for adjusting one of a sampling start time of the ADC on the I channel and a sampling start time of the ADC on the Q channel relative to one another such that the sampled I signal and the sampled Q signal are in phase.
A structure and method include a transistor with semiconductor nanosheets, which extend between source/drain regions and which include at least a lowermost semiconductor nanosheet and an uppermost semiconductor nanosheet above the lowermost semiconductor nanosheet. The transistor includes inner gate sections below the center portions of each semiconductor nanosheet and an outer gate section with a horizontal portion above the center portion of the uppermost semiconductor nanosheet and with vertical portions on opposing sides of the semiconductor nanosheets and inner gate sections. Inner spacers are below the end portions of each semiconductor nanosheet. Outer spacers are adjacent the sidewalls of the outer gate section (including above end portions of the uppermost semiconductor nanosheet), are wider than the inner spacers, and extend onto proximal portions of the source/drain regions. Additional outer spacers are adjacent to the outer spacers (e.g., on the proximal portions or on taller and wider distal portions).
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
A power switch, including: a PFET including a gate, a source coupled to a source voltage, and a drain for outputting a supply voltage; and a level shifter, wherein the level shifter includes: an input node for receiving an input voltage, wherein the input voltage includes first and second voltage levels; a supply node for receiving the supply voltage, wherein the supply voltage includes third and fourth voltage levels; and an output node for outputting an output voltage, wherein the output node is coupled to the gate of the PFET; wherein, when the input voltage is at the first voltage level, the output voltage is at the first voltage level and the PFET is in a conducting state; and wherein a voltage between the gate and drain of the PFET and a voltage between the gate and source of the FET do not exceed a maximum voltage of the PFET.
H03K 19/0185 - Dispositions pour le couplageDispositions pour l'interface utilisant uniquement des transistors à effet de champ
H03K 17/10 - Modifications pour augmenter la tension commutée maximale admissible
H03K 19/173 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants
82.
Shielded inductor structures and methods of forming the same
A structure including a first chip and a second chip stacked over the first chip is provided. The first chip includes a first dielectric over a substrate. The second chip includes a second dielectric over the first dielectric. An inductor is arranged at least in part in the first dielectric of the first chip. An electromagnetic shield structure is arranged around the inductor. The electromagnetic shield structure includes a lower shield portion extending at least partially through the first dielectric of the first chip and an upper shield portion extending at least partially through the second dielectric of the second chip. The electromagnetic shield structure is formed in part in the BEOL metallization structure in each of the first chip and the second chip in a heterogenous integration process.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
83.
IC structure with MFMIS memory cell and CMOS transistor
An IC structure includes an MFMIS memory cell on a semiconductor substrate, and a CMOS transistor adjacent the MFMIS memory cell on the same semiconductor substrate. A method provides co-integration of the MFMIS memory cell with the CMOS transistor. The method may optionally co-integrate an MFIS memory cell. The IC structure and method provide a lower cost approach to forming MFMIS memory cells, which provide a number of advantages over MFIS memory cells.
H10B 51/30 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par la région noyau de mémoire
H10B 51/40 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par la région de circuit périphérique
H10D 64/66 - Électrodes ayant un conducteur couplé capacitivement à un semi-conducteur par un isolant, p. ex. électrodes du type métal-isolant-semi-conducteur [MIS]
84.
Vertical device triggered silicon control rectifier
The present disclosure relates to semiconductor structures and, more particularly, to a device triggered silicon control rectifier (SCR) and methods of manufacture. the structure includes: a vertical silicon controlled rectifier having a diffusion region in a well of a semiconductor substrate; a vertical triggering device sharing the diffusion region with the vertical silicon controlled rectifier; and a body contact adjacent to the vertical triggering device and electrically connecting to the well.
H10D 89/60 - Dispositifs intégrés comprenant des dispositions pour la protection électrique ou thermique, p. ex. circuits de protection contre les décharges électrostatiques [ESD].
85.
STRUCTURE WITH BARRIER-FREE METAL VIA AND METAL WIRE INCLUDING NON-COPPER CONDUCTOR, AND METHOD TO FORM SAME
A structure including a barrier-free metal via over a substrate and in a dielectric layer. The structure further includes a barrier-free metal wire in the dielectric layer and over the barrier-free metal via and coupled to at least an exposed portion of the barrier-free metal via. The barrier-free metal via and the barrier-free metal wire each include a non-copper conductor. By using non-copper conductors in the structure, the structure is substantially without liners and has improved performance without creating or increasing parasitic capacitance.
H01B 1/02 - Conducteurs ou corps conducteurs caractérisés par les matériaux conducteurs utilisésEmploi de matériaux spécifiés comme conducteurs composés principalement de métaux ou d'alliages
H01B 1/04 - Conducteurs ou corps conducteurs caractérisés par les matériaux conducteurs utilisésEmploi de matériaux spécifiés comme conducteurs composés principalement soit de compositions à base de carbone-silicium, soit de carbone soit de silicium
86.
PHOTONICS CHIPS INCLUDING A PHOTONIC COUPLER AND A PHOTODETECTOR
Structures for a photonics chip that include a photodetector and methods of forming such structures. The structure comprises a photodetector, a first waveguide core coupled to the photodetector, and a second waveguide core coupled to the photodetector. The structure further comprises a third waveguide core including a section disposed laterally between a section of the first waveguide core and a section of the second waveguide core.
G02B 6/122 - Éléments optiques de base, p. ex. voies de guidage de la lumière
G02B 6/12 - Guides de lumièreDétails de structure de dispositions comprenant des guides de lumière et d'autres éléments optiques, p. ex. des moyens de couplage du type guide d'ondes optiques du genre à circuit intégré
G02B 6/13 - Circuits optiques intégrés caractérisés par le procédé de fabrication
87.
Structures for a field-effect transistor that include a spacer structure
Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure comprises a silicon-on-insulator substrate including a semiconductor substrate, a dielectric layer on the semiconductor substrate, and a semiconductor layer on the dielectric layer. The structure further comprises a gate electrode on the semiconductor layer. The gate electrode comprises a single-crystal semiconductor material. The structure further comprises a spacer structure including a first portion that overlaps with a side surface of the dielectric layer and a second portion that overlaps with a portion of the semiconductor substrate adjacent to the side surface of the dielectric layer.
H10D 30/60 - Transistors à effet de champ à grille isolée [IGFET]
H10D 86/00 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre
88.
FULLY DEPLETED SEMICONDUCTOR-ON-INSULATOR SWITCH WITH BUILT-IN ELECTROSTATIC DISCHARGE PROTECTION
A disclosed semiconductor structure includes a semiconductor layer including a switch area with side-by-side first and second portions and an RF switch with built-in ESD/power surge protection. The RF switch includes series-connected transistors, which include, within the first portion of the switch area, source/drain regions and channel regions positioned laterally between the source/drain regions; and parallel gates adjacent to the channel regions, respectively, and traversing the first portion of the switch area without extending further onto the second portion. Outer source/drain regions are silicided and contacted, whereas inner source/drain regions are unsilicided and uncontacted. The second portion of the switch area is in contact with the source/drain regions in the first area, is unsilicided, and is either undoped or low doped. Thus, the second portion makes up resistive elements connected in parallel to the series-connected transistors.
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant
H02H 9/04 - Circuits de protection de sécurité pour limiter l'excès de courant ou de tension sans déconnexion sensibles à un excès de tension
H03K 17/081 - Modifications pour protéger le circuit de commutation contre la surintensité ou la surtension sans réaction du circuit de sortie vers le circuit de commande
The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor integrated silicon controlled rectifier and methods of manufacture. The structure includes: a first region having a first dopant type provided in a semiconductor substrate; a second region having a second dopant type provided in the semiconductor substrate; an isolation region between the first region and the second region; a first semiconductor layer vertically contacting the first region, the first semiconductor layer having a dopant type opposite from the first dopant type; a second semiconductor layer vertically contacting the second region, the second semiconductor layer having a dopant type opposite from the second dopant type; a polysilicon material vertically contacting the first semiconductor layer; and a single crystalline semiconductor material vertically contacting the first semiconductor layer and the second semiconductor layer.
H01L 29/04 - Corps semi-conducteurs caractérisés par leur structure cristalline, p.ex. polycristalline, cubique ou à orientation particulière des plans cristallins
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/66 - Types de dispositifs semi-conducteurs
90.
Photodetectors with multiple light-absorbing semiconductor layers
Structures for a photonic chip that include a photodetector and methods of forming such structures. The structure comprises a photodetector including a pad, a first semiconductor layer on the pad, and a second semiconductor layer on the pad. The second semiconductor layer is laterally spaced from the first semiconductor layer. The structure further comprises a first waveguide core connected to the pad adjacent to the first semiconductor layer, and a second waveguide core connected to the pad adjacent to the second semiconductor layer.
H10F 30/223 - Dispositifs individuels à semi-conducteurs sensibles au rayonnement dans lesquels le rayonnement commande le flux de courant à travers les dispositifs, p. ex. photodétecteurs les dispositifs ayant des barrières de potentiel, p. ex. phototransistors les dispositifs étant sensibles au rayonnement infrarouge, visible ou ultraviolet les dispositifs ayant une seule barrière de potentiel, p. ex. photodiodes la barrière de potentiel étant du type PIN
G02B 6/12 - Guides de lumièreDétails de structure de dispositions comprenant des guides de lumière et d'autres éléments optiques, p. ex. des moyens de couplage du type guide d'ondes optiques du genre à circuit intégré
H10F 71/00 - Fabrication ou traitement des dispositifs couverts par la présente sous-classe
H10F 77/122 - Matériaux actifs comportant uniquement des matériaux du groupe IV
Layout design for an electronic device may be performed by providing a representation of a first layout to a client and providing, in response to an input from the client, a collection of design information calculated according to the first layout to the client. The collection of design information may include a dimension extracted from the first layout, and may further include parasitics information related to the dimension, margin information related to a ground rule applicable to the dimension, or both. The collection of design information may be provided to the client as a real-time response to inputs received from the client. By providing the parasitics information, the margin information, or both to the client, the design of sub-ground-rule layouts may be performed in less time and using fewer resources than would otherwise be the case.
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
G06F 30/31 - Saisie informatique, p. ex. éditeurs spécifiquement adaptés à la conception de circuits
G06F 30/392 - Conception de plans ou d’agencements, p. ex. partitionnement ou positionnement
92.
STRUCTURES FOR A PHOTONICS CHIP THAT ENABLE EXTERNAL COMMUNICATION
Structures for a photonics chip that enable external communication and methods of forming such structures. The structure comprises a spot-size converter, a body on a semiconductor substrate, and a dielectric layer on the semiconductor substrate. The body includes a surface adjacent to the spot-size converter and a reflector on the surface. The dielectric layer includes a recess disposed above the spot-size converter and the reflector.
Embodiments of the disclosure provide memory circuit, a sense amplifier and associated method for reading a resistive state in a memory device. The sense amplifier includes a bit cell configurable to a high or low resistance state; a sensing circuit that detects a voltage drop across the bit cell in response to an applied read current during a read operation and generates a high or low logic output at an output node; and a pulse generation circuit that increases the applied read current with an injected current pulse when a low to high transition of the resistive state of the bit cell is detected.
G11C 7/06 - Amplificateurs de lectureCircuits associés
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. circuits de commande E/S de données, mémoires tampon de données E/S
G11C 7/12 - Circuits de commande de lignes de bits, p. ex. circuits d'attaque, de puissance, de tirage vers le haut, d'abaissement, circuits de précharge, circuits d'égalisation, pour lignes de bits
The present disclosure relates to semiconductor structures and, more particularly, to vertical heterojunction bipolar transistors and methods of manufacture. The structure includes: a sub-collector region; a collector region above the sub-collector region; an intrinsic base above the collector region; an emitter above the intrinsic base region; and an extrinsic base on the intrinsic base and adjacent to the emitter, wherein the collector region includes an undercut profile comprising lower inwardly tapered sidewalls and upper inwardly tapered sidewalls which extend to a narrow section between the sub-collector region and the base region.
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/165 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée comprenant plusieurs des éléments prévus en dans différentes régions semi-conductrices
H01L 29/66 - Types de dispositifs semi-conducteurs
95.
STRUCTURE AND METHOD FOR INDUCTOR WITH WINDINGS HAVING DIFFERENT WIDTHS
The disclosure provides a structure and method for an inductor with windings having different widths. A structure may include an inductor including a plurality of windings about a magnetic core. Each winding has a first segment within a first wiring layer coupled to a second segment within a second wiring layer. The plurality of windings includes a first winding having a first width along a same direction as a length of the magnetic core and a second winding having a second width along the same direction as the length of the magnetic core. The second width is larger than the first width.
H01F 1/14 - Aimants ou corps magnétiques, caractérisés par les matériaux magnétiques appropriésEmploi de matériaux spécifiés pour leurs propriétés magnétiques en matériaux inorganiques caractérisés par leur coercivité en matériaux magnétiques doux métaux ou alliages
96.
SILICON CONTROL RECTIFIER INTEGRATED WITH A TRANSISTOR
The present disclosure relates to semiconductor structures and, more particularly, to a silicon control rectifier (SCR) and methods of manufacture. The structure includes: a doped region in a semiconductor substrate; at least two regions of semiconductor material comprising opposite doping types over the doped region; and polysilicon regions over respective ones of the least two regions of semiconductor material.
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
97.
BIPOLAR TRANSISTOR STRUCTURE WITH BOUNDING STRUCTURE AT HORIZONTAL END AND METHODS TO FORM SAME
Embodiments of the disclosure provide a structure including a first emitter/collector (E/C) layer over a substrate. A base structure is over the substrate and adjacent a first horizontal end of the first E/C layer. A bounding structure is over the substrate and adjacent a second horizontal end of the first E/C layer. The bounding structure, in some implementations, may include a gate conductor or a base material. A spacer is between the first E/C layer and the bounding structure.
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/66 - Types de dispositifs semi-conducteurs
98.
MEMORY STRUCTURE INCLUDING A LOW CELL SUPPLY VOLTAGE PROGRAMMING CIRCUIT
A disclosed memory structure includes memory cells connected to first and second cell supply voltage lines. A programming circuit enables programming of a low cell supply voltage (Vcsl) on the first cell supply voltage line and includes transistors with different threshold voltages connected to ground and further connectable, via switches, to the first cell supply voltage line. The programming circuit can further include an additional switch connected between ground and the first cell supply voltage line. In an operational mode, the first cell supply voltage line is discharged to ground via the additional switch. In the retention mode, one of the transistors of the programming circuit is connected by a corresponding switch to the first cell supply voltage line for programming of Vcsl. Optionally, the memory structure can be implemented in FDSOI and the transistors of the programming circuit can also be back biased for fine tuning of Vcsl.
Structures that include a switching memory element and methods of forming a structure including a switching memory element. The structure comprises a switching memory element, and a two-terminal access device including a first terminal coupled to the switching memory element, a second terminal, and a semiconductor layer between the first terminal and the second terminal. The semiconductor layer is electrically floating in the structure.
H10B 63/00 - Dispositifs de mémoire par changement de résistance, p. ex. dispositifs RAM résistifs [ReRAM]
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H10B 63/10 - Dispositifs RAM à changement de phase [PCRAM, PRAM]
H10N 70/00 - Dispositifs à l’état solide n’ayant pas de barrières de potentiel, spécialement adaptés au redressement, à l'amplification, à la production d'oscillations ou à la commutation
Structures for an integrated circuit having a watermark and related methods. The structure comprises a first semiconductor structure including at least one feature with a variation relative to a second semiconductor structure including the at least one feature without the variation. The variation provides a watermark for identifying a Process Design Kit used to form the first semiconductor structure.
H01L 23/544 - Marques appliquées sur le dispositif semi-conducteur, p. ex. marques de repérage, schémas de test
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
