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2026
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Invention
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Memory control component.
In a multirank memory system in which the clock distribution trees of ... |
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Invention
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Protocol including timing calibration between memory request and data transfer.
The described em... |
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Invention
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Dram retention test method for dynamic error correction.
A memory controller for a dynamic rando... |
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Invention
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Variable memory access granularity.
An integrated-circuit memory component receives, as part of ... |
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Invention
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Dynamically changing data access bandwidth by selectively enabling and disabling data links. Band... |
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Invention
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Memory controller having metadata access mode.
Technologies for dynamic random access memory (DR... |
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Invention
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Integrated circuit memory devices with unidirectional ports for concurrent interface operations. ... |
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Invention
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Hybrid memory.
A hybrid memory includes cache of relatively fast and durable dynamic, random-acc... |
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Invention
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High capacity memory system with improved command-address and chip-select signaling mode.
A memo... |
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Invention
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Methods and circuits for streaming data to processing elements in stacked processor-plus-memory a... |
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Invention
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Configurable in-array event tracking.
A random access memory device includes memory cells in eac... |
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2025
|
Invention
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Multiplexed stack identifiers for multi-die stacked memory. A memory device comprises a base die ... |
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Invention
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Multi-configuration stacked die dynamic random access devices. The embodiments herein are directe... |
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Invention
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Multiplexed stacked memory device. A multiplexed stacked memory device comprises a base die and m... |
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Invention
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Latency under load tracking in a memory controller.
A memory controller includes a processing de... |
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Invention
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Dual-channel first-in first-out buffering. Write data bursts directed to two different channels (... |
|
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Invention
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Eight-channel dram. A DRAM device may have eight channels. In a first mode, these channels may al... |
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Invention
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Symmetric i/o ports.
Multiple multi-channel dynamic random access memory (DRAM) die are stacked ... |
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Invention
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Configurable electrical pad die package.
The embodiments herein are directed to technologies for... |
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Invention
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Dram interface mode with improved channel integrity and efficiency at high signaling rates.
Memo... |
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Invention
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High-performance, high-capacity memory modules and systems.
Described are memory modules that in... |
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Invention
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Transmitter with differential signal cross point voltage control circuitry.
Technologies for tra... |
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Invention
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Memory module with memory-ownership exchange.
Described are computational systems in which hosts... |
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Invention
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Dynamic, random-access memory with hidden memory scrubbing.
A memory includes a local control ci... |
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Invention
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Inter-server memory pooling.
A memory allocation device for deployment within a host server comp... |
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Invention
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Dynamic random access memory (dram) device with simultaneous activate and refresh. A dynamic rand... |
|
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Invention
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Base die for stacked memory device with memory controllers and interconnect. A stacked memory dev... |
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Invention
|
Load-reduced dram stack.
Power consumption in a three-dimensional stack of integrated-circuit me... |
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Invention
|
Buffer device with low-latency skid mode for data freshness.
A buffer integrated circuit (IC) ch... |
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Invention
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Co-packaged buffer. A data buffer die is stacked with multiple memory die and interconnected with... |
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Invention
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Memory controller and command buffer for parallel metadata access and enhanced error correction. ... |
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Invention
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Decision feedback equalized receiver monitor circuitry calibration.
A receiver includes variable... |
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Invention
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Memory systems and techniques with support for sparse neural network computations.
Aspects and i... |
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Invention
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Dynamic random access memory (dram) device with variable burst lengths.
Technologies for dynamic... |
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Invention
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Buffer component for interleaving data and metadata for error correction.
A memory buffer servic... |
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Invention
|
Dram cache with stacked, heterogenous tag and data dies.
A high-capacity cache memory is impleme... |
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Invention
|
Stacked memory device with error recovery support. Technologies for stacked memory devices with e... |
|
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Invention
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Memory controller partitioning for hybrid memory system.
A compute system includes an execution ... |
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Invention
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Serial memory buffer for serial attached memory module. A buffer device for a serial attached mem... |
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Invention
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Row hammer mitigation.
A 3D DRAM architecture may have one or more layers of cells where the acc... |
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Invention
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Memory device and module with low-power mode. An intcgratcd-circuit memory device is configurable... |
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Invention
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Low overhead page recompression.
An apparatus and method for low page overhead recompression. In... |
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Invention
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Quad-channel dram.
A DRAM includes at least four groups of memory cores and at least four memory... |
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2023
|
Invention
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In-package error correction for multi-die memory stacks.
A memory device comprises a plurality o... |
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Invention
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Stacked dynamic random access memory (dram) device with multiple master die.
A stacked die devic... |
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Invention
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Memory device stack availability.
As information is written to a memory device stack, partial pa... |
|
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Invention
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Dram for caches.
In response to some access commands, a DRAM device is configured to receive cac... |
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Invention
|
Split-entry dram cache.
A high-capacity cache memory is implemented by one or more DRAM dies in ... |
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Invention
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Configurable memory device.
A memory device may be accessed via multiple channels (e.g., 2 chann... |
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2014
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P/S
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computer hardware and software for electronic design interface validation and testing; computer h... |
|
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P/S
|
Computer hardware and software for validation and testing of electronic circuitry and chips; comp... |
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2012
|
P/S
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Light emitting diode (LED) light controls; light emitting diode (LED) displays; light emitting di... |
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2011
|
P/S
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Appareils et instruments pour l'enregistrement, la transmission, le traitement, le stockage et l'... |
|
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P/S
|
Apparatus and instruments for recording, transmitting,
processing, storing and exchanging data, ... |
|
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P/S
|
Apparatus and instruments for the recording, transmission, processing, storage and exchange of da... |
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2008
|
P/S
|
Computers; computer hardware; computer memories; application-specific integrated circuits and gra... |
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2004
|
P/S
|
Computers; computer hardware; computer memories; memory devices; memory controllers; memory syste... |
|
|
P/S
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Computer memories; memory devices, namely, [ dynamic random access memories (DRAMS), ] memory sys... |
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2003
|
P/S
|
Licensing of intellectual property and technology; patent licensing |
|
|
P/S
|
Computer hardware; computer software; computer peripherals; computer memory components; microproc... |
|
2002
|
P/S
|
LICENSING OF INTELLECTUAL PROPERTY AND PATENTED TECHNOLOGY TO OTHERS |
|
|
P/S
|
Licensing of intellectual property and technology |
|
|
P/S
|
Computer software and hardware, especially in the field of encrypted and secure communication as ... |
|
1996
|
P/S
|
Scientific, nautical, surveying, electric, photographic, cinematographic, optical, weighing, meas... |
|
1995
|
P/S
|
microprocessor components, peripheral controller components and computer memory components, namel... |
