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2025
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Invention
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Method and system for patching a boot process.
A system and method are provided that enable a pr... |
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Invention
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Integrated circuits including error protection of fields in transferred information and field-bas... |
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P/S
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Semiconductor chips; semiconductors; computer hardware; downloadable computer software for operat... |
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P/S
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Semiconductor chips; semiconductors; computer hardware;
downloadable computer software for opera... |
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Invention
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Component die validation built-in self-test (vbist) engine.
A component die validation built-in ... |
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Invention
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Method and system for testing semiconductor circuits.
A system and method are provided that enab... |
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Invention
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Dynamic control of prefetching based on prefetching accuracy in a computing system.
Dynamic cont... |
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Invention
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Core utilization based runtime adaptive operation configuration in a many-core system.
Disclosed... |
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Invention
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Method, apparatus, and system for calibrating a processor power level estimate.
A system and met... |
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2024
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Invention
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Precise destination-based request throttling.
Disclosed are techniques for destination-based req... |
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Invention
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Scalable counters for bursty events including correctable errors.
Disclosed are techniques for p... |
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Invention
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Branch predictor.
Disclosed is a branch predictor unit (BPU), comprising a first branch predicto... |
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Invention
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Gather operation using a common register file entry as destination register for all load subopera... |
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Invention
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Memory coherence with early store completion. In an aspect, an apparatus comprises a writer agent... |
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Invention
|
Loop detector and predictor.
Disclosed is a branch predictor unit (BPU), comprising a loop predi... |
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Invention
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Energy-efficient indirect prefetcher.
Disclosed is a prefetcher, e.g., of a system with one or m... |
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Invention
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Hardware structures and techniques for replaying prefetch virtual addresses.
Disclosed are hardw... |
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Invention
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Virtual to physical partial translation cache for accelerating virtualized page table walks.
Dis... |
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Invention
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Security enhancement for indirect prefetcher.
Disclosed is a prefetcher, e.g., of a system with ... |
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Invention
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Multi-socket computing system employing a parallelized boot architecture with partially concurren... |
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Invention
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Performing snoop filter replacement based on history-augmented victimization priority values of s... |
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Invention
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Apparatus and method of routing a request in a mesh network. Disclosed are techniques for a proce... |
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Invention
|
Advanced initialization bus (aib). Methods and systems for an advanced initialization bus (AIB) a... |
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Invention
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Runtime adaptive prefetching in a many-core system.
Disclosed are techniques for runtime adaptiv... |
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Invention
|
Apparatuses, systems, and methods for controlling cache allocations in a configurable combined pr... |
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Invention
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Parity protected memory blocks merged with error correction code (ecc) protected blocks in a code... |
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Invention
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Multi-core processor-based system implementing directed page table entry invalidation.
A first c... |
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Invention
|
Multi-core processors evicting cache lines from lower-level caches to higher-level caches by core... |
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Invention
|
Cache memory system employing a multiple-level hierarchy cache coherency architecture. Cache memo... |
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Invention
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Multi-trained scalable prefetcher, and related methods.
A multi-trained scalable prefetcher gene... |
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2023
|
Invention
|
Devices transferring cache lines, including metadata on external links. In a processing system, a... |
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Invention
|
Trace width modulation.
Techniques for trace width modulation are disclosed. In an aspect, a met... |
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Invention
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Processor macro-operation fusion.
Disclosed are techniques for macro-operation fusion. In an asp... |
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Invention
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System and method for handling cache updates.
A method of controlling a cache memory is disclose... |
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Invention
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Mechanism for fine-grained device power attribution to software entities.
An integrated circuit ... |
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Invention
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Providing additional operations for a functional unit of a processor core. Aspects of the disclos... |
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Invention
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Techniques for memory resource control using memory resource partitioning and monitoring. Disclos... |
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Invention
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Techniques for optimizing store of common values to memory structures.
Disclosed are techniques ... |
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Invention
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Mechanism for instruction fusion. A compute node capable of enhanced performance and/or energy sa... |
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Invention
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Apparatus and method of workload throttling in a mesh network.
Disclosed are techniques for a re... |
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Invention
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Techniques for performing non-vector micro-operations on vector hardware.
Disclosed are techniqu... |
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Invention
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Performing instruction fetch pipeline synchronization (ifps) in processor-based devices. Performi... |
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Invention
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Extending functionality of memory controllers using a loopback mode for testing in a processor-ba... |
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Invention
|
Processors employing default tags for writes to memory from devices not compliant with a memory t... |
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Invention
|
Processors with toggleable memory tagging extensions and related methods. In processors that incl... |
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2022
|
Invention
|
External quiesce of a core in a multi-core system. Disclosed are techniques for external quiesce ... |
|
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Invention
|
Method and system for testing semiconductor circuits. A system and method are provided that enabl... |
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Invention
|
Component die validation built-in self-test (vbist) engine. A component die validation built-in s... |
|
|
Invention
|
System-on-chip management controller. Disclosed are techniques for management of multiple process... |
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P/S
|
Computer operating systems comprised of silicon based microprocessors, servers, and recorded and ... |
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P/S
|
Computer operating systems comprised of silicon based
microprocessors, servers, and recorded and... |
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P/S
|
Computer services, namely, design and development of computer systems and software for operating ... |
|
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P/S
|
Computer systems comprised of silicon based microprocessors, computer servers, and recorded and d... |
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2020
|
P/S
|
Computer systems, namely, silicon based microprocessors,
servers, and software for operating com... |
|
|
P/S
|
Silicon based microprocessors, computer network servers, and recorded and downloadable software s... |
|
|
P/S
|
Computer systems, namely, silicon based microprocessors, servers, and software for operating comp... |
|
|
P/S
|
Silicon based microprocessors, computer network servers, and
recorded and downloadable software ... |
|
|
P/S
|
Computer systems comprised of silicon based microprocessors, servers, and recorded and downloadab... |
|
|
P/S
|
Computer systems comprised of silicon based microprocessors,
servers, and recorded and downloada... |
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2018
|
P/S
|
Computer systems, namely, silicon based microprocessors,
servers, and software for datacenters a... |
|
|
P/S
|
Computer services, namely, design and development of computer systems and software for datacenter... |
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2017
|
P/S
|
Computer systems comprised of silicon based microprocessors, servers, and software for operating ... |
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2014
|
P/S
|
Embedded microprocessors and systems-on-a-chip for computer
networks, computer interconnections,... |
