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2024
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Invention
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Method, apparatus, and system for energy efficiency and energy conservation including power and p... |
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2023
|
Invention
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Controlling operating voltage of a processor.
In an embodiment, a processor includes a core doma... |
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Invention
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Methods of forming dislocation enhanced strain in nmos and pmos structures.
Methods of forming a... |
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Invention
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Cmos finfet device having strained sige fins and a strained si cladding layer on the nmos channel... |
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2022
|
Invention
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Methods of forming dislocation enhanced strain in nmos and pmos structures. Methods of forming a ... |
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|
Invention
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Methods and apparatuses to form self-aligned caps.
At least one conductive line in a dielectric ... |
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Invention
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Transistor devices having source/drain structure configured with high germanium content portion. ... |
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2021
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Invention
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Controlling operating voltage of a processor. In an embodiment, a processor includes a core domai... |
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Invention
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Contact resistance reduction employing germanium overlayer pre-contact metalization. Techniques a... |
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Invention
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Method of fabricating cmos finfets by selectively etching a strained sige layer. Techniques and m... |
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2020
|
Invention
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Column iv transistors for pmos integration. Techniques are disclosed for forming column IV transi... |
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|
Invention
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Self-aligned gate edge and local interconnect. Self-aligned gate edge and local interconnect stru... |
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|
Invention
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High mobility strained channels for fin-based nmos transistors.
Techniques are disclosed for inc... |
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2019
|
Invention
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Selective germanium p-contact metalization through trench. Techniques are disclosed for forming t... |
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Invention
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Transistors with high concentration of germanium. −3. A buffer providing graded germanium and/or ... |
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|
Invention
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Methods and apparatuses to form self-aligned caps. At least one conductive line in a dielectric l... |
|
|
Invention
|
Methods of forming dislocation enhanced strain in nmos structures. Methods of forming a strained ... |
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|
Invention
|
Cmos implementation of germanium and iii-v nanowires and nanoribbons in gate-all-around architect... |
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Invention
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Enabling a non-core domain to control memory bandwidth in a processor. In one embodiment, the pre... |
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2018
|
Invention
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High mobility strained channels for fin-based nmos transistors. Techniques are disclosed for inco... |
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|
Invention
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Techniques for integration of ge-rich p-mos source/drain. −3. |
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|
Invention
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Visualizing or interacting with a quantum processor. Techniques and a system for visualization or... |
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Invention
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Method of fabricating a semiconductor device with strained sige fins and a si cladding layer. Tec... |
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Invention
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Asymmetric performance multicore architecture with same instruction set architecture. A method is... |
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Invention
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Radio based location power profiles. Methods and systems of managing radio based power may includ... |
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Invention
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Processors having virtually clustered cores and cache slices. A processor of an aspect includes a... |
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2017
|
Invention
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Self-aligned gate edge and local interconnect and method to fabricate same. Self-aligned gate edg... |
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Invention
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Avd hardmask for damascene patterning. A method including forming a dielectric layer on a contact... |
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Invention
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Transistors with high concentration of boron doped germanium.
Techniques are disclosed for formi... |
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Invention
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Secure on-line sign-up and provisioning for wi-fi hotspots using a device-management protocol. Em... |
