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2025
|
Invention
|
Multiple partitions in a data processing array.
An apparatus includes a data processing array ha... |
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Invention
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Host polling of a network adapter.
Embodiments herein describe a host that polls a network adapt... |
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Invention
|
Tamper sensor for 3-dimensional die stack.
An integrated circuit die stack and method thereof ar... |
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Invention
|
Localized and relocatable software placement and noc-based access to memory controllers.
An inte... |
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Invention
|
Edge coupler beam deflection system. embodiments herein describe a system including a first optic... |
|
|
Invention
|
Acceleration unit configured for multi- dimensional block-scaled matrices. To perform matrix mult... |
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|
Invention
|
System-level data compression scheme. An implementation includes an integrated circuit, a network... |
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Invention
|
Network-on-chip architecture for handling different data sizes.
A network-on-chip (NoC) includes... |
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2024
|
Invention
|
Integrated circuit package with multi-chambered thermal control device.
Disclosed herein are the... |
|
|
Invention
|
An area and power efficient clock data recovery (cdr) and adaptation implementation for dense wav... |
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|
Invention
|
Controller for an array of data processing engines. Embodiments herein describe integrating an ac... |
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|
Invention
|
Integrating an ai accelerator with a cpu on a soc. Embodiments herein describe integrating an Al ... |
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Invention
|
Mismatch resistant thermal control loop for cascaded optical ring resonators. An integrated circu... |
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Invention
|
Edge coupler beam deflection system.
Embodiments herein describe a system including a first opti... |
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|
Invention
|
Secure solutions for resource-restrictions on integrated circuits.
Embodiments herein describe s... |
|
|
Invention
|
Programmable congestion monitoring and/or control.
Described herein are systems and methods for ... |
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|
Invention
|
Method for bypassing subsequent lookups in packet processing pipelines.
Systems and methods for ... |
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|
Invention
|
Data packing for power and area-efficient memory structures and performance-efficient decoding of... |
|
|
Invention
|
Acceleration unit configured for multi- dimensional block-scaled matrices.
To perform matrix mul... |
|
|
Invention
|
Pulse generation circuitry.
Examples herein describe pulse generation circuitry. The pulse gener... |
|
|
Invention
|
Emulating a circuit design in communication with a peripheral.
Emulating a circuit design in com... |
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|
Invention
|
Deterministic built-in self-test.
Embodiments herein describe a computer architecture including ... |
|
|
Invention
|
Methodology to achieve transaction redundancy in memory constrained devices.
Embodiments herein ... |
|
|
Invention
|
Memory lifecycle state sensors.
Examples herein describe memory lifecycle state sensors. A memor... |
|
|
Invention
|
3d splintered physically unclonable function (3d-spuf).
Embodiments herein describe a 3D splinte... |
|
|
Invention
|
System-level data compression scheme.
An implementation includes an integrated circuit, a networ... |
|
|
Invention
|
Cram validation using an external device.
Embodiments herein describe CRAM validation using an e... |
|
|
Invention
|
Network-on-chip having an integrated cache controller circuitry.
An integrated circuit device in... |
|
|
Invention
|
On-site updating of machine learning models and machine learning models incorporating hardware an... |
|
|
Invention
|
Multi-wavelength polarization diversified optical receiver configuration.
Examples herein descri... |
|
|
Invention
|
Injection locked phase rotator.
An injection locked ring oscillator (ILRO) system is disclosed. ... |
|
|
Invention
|
Configuration of manager-subordinate connectivity paths of a system-on-chip.
A connectivity tool... |
|
|
Invention
|
Oscillator with offset calibration.
A method of using an oscillator circuit is disclosed. The me... |
|
|
Invention
|
Clock modulation schemes in integrated circuits.
An integrated circuit (IC) includes a clock mod... |
|
|
Invention
|
Pim cancellation adapt architecture.
Embodiments herein describe a circuit including a passive i... |
|
|
Invention
|
Address translation structure for accelerators.
Embodiments herein describe a computer architect... |
|
|
Invention
|
Tdisp support in a fpga-embedded device.
Embodiments herein describe a circuit including a user ... |
|
2023
|
Invention
|
Power reduction in an array of data processing engines.
Embodiments herein describe a hardware a... |
|
|
Invention
|
Controller for an array of data processing engines.
Embodiments herein describe integrating an a... |
|
|
Invention
|
Integrating an ai accelerator with a cpu on a soc.
Embodiments herein describe integrating an AI... |
|
|
Invention
|
Systems and methods for scalable communications.
Described herein are systems and methods for sc... |
|
|
Invention
|
Power domains in a system on a chip.
Embodiments herein describe a hardware accelerator that inc... |
|
|
Invention
|
Transceiver loopback testing. A transceiver circuit is disclosed, the transceiver circuit includi... |
|
|
Invention
|
Reduction of stuck channels at a neural network.
A processing system identifies and removes stuc... |
|
|
Invention
|
Prediction-based extrapolation of pixels for improved video compression.
Methods and systems for... |
|
|
Invention
|
Method and system for rendering event data from subsystems in different clock domains according t... |
|
|
Invention
|
Mitigation of control set packing restrictions for integrated circuits.
Mitigation of controls s... |
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|
Invention
|
Systems and methods for decentralized address translation. The disclosed computer-implemented met... |
|
2021
|
Invention
|
Neural network architecture with high bandwidth memory (hbm). A system includes a high bandwidth ... |
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2020
|
P/S
|
System on module, namely, integrated board-level circuits that integrate a system function in a s... |
|
|
P/S
|
System on module, namely, a board-level circuit that
integrates a system function in a single mo... |
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2019
|
P/S
|
Downloadable computer software platform for the design, programming and operation of integrated c... |
|
|
P/S
|
Downloadable computer software platform for the design,
programming and operation of integrated ... |
|
|
P/S
|
Integrated circuits and semiconductors; computer accelerator
boards; computer accelerator cards;... |
|
|
P/S
|
Integrated circuits; integrated circuits in the nature of
integrated multi-core heterogeneous co... |
|
2018
|
P/S
|
Integrated circuits and semiconductors; computer accelerator boards; computer accelerator cards; ... |
|
|
P/S
|
Integrated circuits; integrated circuits in the nature of integrated multi-core heterogeneous com... |
|
|
P/S
|
Computer accelerator boards; computer accelerator cards; computing memory modules; computer add-i... |
|
2017
|
P/S
|
Computer software for implementing a network protocol stack, not for use in testing website funct... |
|
|
P/S
|
Computer software and hardware for monitoring and securing network data, enable multiple services... |
|
|
P/S
|
Computer hardware, wide-area computer networks hardware, peer-to-peer computer networks hardware,... |
|
2015
|
P/S
|
Semiconductors; integrated circuits; programmable logic integrated circuits; field programmable g... |
|
|
P/S
|
Technical consultation in the field of engineering of semiconductors, integrated circuits, progra... |
|
|
P/S
|
Computer software for design, programming, and operation of integrated circuits |
|
|
P/S
|
Computer software for design, programming, and operation of integrated circuits. |
|
2012
|
P/S
|
Computer software systems for packet recordation or storage, time-stamping, time synchronization,... |
|
2011
|
P/S
|
Computer hardware, namely, integrated circuits; integrated circuit, namely, field programmable ga... |
|
|
P/S
|
Computer hardware, namely, integrated circuits; integrated
circuit, namely, field programmable g... |
|
|
P/S
|
Computer software for design, programming, and operation of programmable gate arrays. |
|
|
P/S
|
Integrated circuits, namely, field programmable gate arrays;
computer software for design, progr... |
|
2010
|
P/S
|
Computer software for implementing network communications, computer software used to accelerate n... |
|
|
P/S
|
Computer software; computer software which implements a network protocol stack. |
|
|
P/S
|
Integrated circuits, namely field programmable gate arrays; computer software for design, program... |
|
|
P/S
|
Computer software for design, programming, and operation of programmable gate arrays |
|
|
P/S
|
Integrated circuits, namely, field programmable gate arrays [ ; computer software for design, pro... |
|
|
P/S
|
Integrated circuits, namely field-programmable gate arrays. |
|
|
P/S
|
Integrated circuits, namely field programmable gate arrays;
computer software for design, progra... |
|
|
P/S
|
Integrated circuits; field programmable gate arrays; computer software for the design, programmin... |
|
|
P/S
|
Integrated circuits, namely, field programmable gate arrays |
|
|
P/S
|
Integrated circuits; field programmable gate arrays;
computer software for the design, programmi... |
|
|
P/S
|
Integrated circuits; Integrated circuits in the nature of field programmable gate arrays |
|
2009
|
P/S
|
Data processing equipment and computers; computer hardware and firmware; computer software; compu... |
|
2007
|
P/S
|
Computer hardware, namely, integrated circuits, semiconductors, computer cables, printed circuit ... |
|
|
P/S
|
Computer software which implements a network protocol stack not for use in testing website functi... |
|
|
P/S
|
Computer software, namely, software for use in design and programming in the field of integrated ... |
