PDF Solutions, Inc.

United States of America

Back to Profile

1-100 of 127 for PDF Solutions, Inc. Sort by
Query
Aggregations
IP Type
        Patent 94
        Trademark 33
Jurisdiction
        United States 101
        World 21
        Canada 3
        Europe 2
Date
2025 May 1
2025 (YTD) 2
2024 9
2023 4
2022 11
See more
IPC Class
H01L 21/66 - Testing or measuring during manufacture or treatment 30
G06F 17/50 - Computer-aided design 23
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier 17
H01L 23/528 - Layout of the interconnection structure 14
G06N 20/00 - Machine learning 13
See more
NICE Class
09 - Scientific and electric apparatus and instruments 32
42 - Scientific, technological and industrial services, research and design 22
37 - Construction and mining; installation and repair services 5
40 - Treatment of materials; recycling, air and water treatment, 1
Status
Pending 8
Registered / In Force 119
  1     2        Next Page

1.

Sequenced Approach for Determining Wafer Path Quality

      
Application Number 19004177
Status Pending
Filing Date 2024-12-27
First Publication Date 2025-05-01
Owner PDF Solutions, Inc. (USA)
Inventor
  • Honda, Tomonori
  • Burch, Richard
  • David, Jeffrey Drue

Abstract

Wafer quality is determined by modeling equipment history as a sequence of events, then evaluating anomalous results for individual events. Identifying an event that generates bad wafers narrows the list of possible root causes.

IPC Classes  ?

  • G05B 19/18 - Numerical control [NC], i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form
  • G05B 19/406 - Numerical control [NC], i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form characterised by monitoring or safety

2.

USE OF LAYOUT ANALYSIS TO ENABLE EFFICIENT AND EFFECTIVE RANDOM DEFECT INSPECTION USING A VECTOR-MODE E-BEAM INSPECTION MACHINE

      
Application Number 18829227
Status Pending
Filing Date 2024-09-09
First Publication Date 2025-03-13
Owner PDF Solutions, Inc. (USA)
Inventor
  • Eisenmann, Hans
  • Rauscher, Markus
  • Sendner, Christian

Abstract

A vector e-beam machine for random defect inspection is disclosed. Contrary to traditional wisdom, it is shown that through a careful choice of target locations, vector machines can provide high-throughput and high coverage even when scanning for random defects. Additionally, by not wastefully scanning locations that provide no additional fault observability, charge accumulation on the wafer—a major concern in e-beam scanning—is reduced. A vector e-beam machine for random defect inspection is disclosed. Contrary to traditional wisdom, it is shown that through a careful choice of target locations, vector machines can provide high-throughput and high coverage even when scanning for random defects. Additionally, by not wastefully scanning locations that provide no additional fault observability, charge accumulation on the wafer—a major concern in e-beam scanning—is reduced. In a preferred embodiment, two approaches are combined: 1) Scan/target only at locations where a random failure can be observed. 2) From the defined list of observable locations, scan/target only the points which have the highest efficiency. A vector e-beam machine for random defect inspection is disclosed. Contrary to traditional wisdom, it is shown that through a careful choice of target locations, vector machines can provide high-throughput and high coverage even when scanning for random defects. Additionally, by not wastefully scanning locations that provide no additional fault observability, charge accumulation on the wafer—a major concern in e-beam scanning—is reduced. In a preferred embodiment, two approaches are combined: 1) Scan/target only at locations where a random failure can be observed. 2) From the defined list of observable locations, scan/target only the points which have the highest efficiency. Use of these and/or other disclosed techniques enables the scanner to target and evaluate a majority of the total observable defects in a single pass.

IPC Classes  ?

  • G01N 21/95 - Investigating the presence of flaws, defects or contamination characterised by the material or shape of the object to be examined

3.

Predicting Equipment Fail Mode from Process Trace

      
Application Number 18141389
Status Pending
Filing Date 2023-04-29
First Publication Date 2024-10-31
Owner PDF Solutions, Inc. (USA)
Inventor
  • Burch, Richard
  • Kunitoshi, Kazuki

Abstract

A predictive model for equipment fail modes. An anomaly is detected in a collection of trace data, then key features are calculated. A search is conducted for the same or similar anomalies having the same key features in a database of past trace data. If the same anomaly occurred before and is in the database, then the type of anomaly, its root cause, and action steps to correct can be retrieved from the database.

IPC Classes  ?

  • G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance

4.

SYSTEMS, DEVICES, AND METHODS FOR PERFORMING A NON-CONTACT ELECTRICAL MEASUREMENT ON A CELL, NON-CONTACT ELECTRICAL MEASUREMENT CELL VEHICLE, CHIP, WAFER, DIE, OR LOGIC BLOCK

      
Application Number 18741726
Status Pending
Filing Date 2024-06-12
First Publication Date 2024-10-03
Owner PDF SOLUTIONS, INC. (USA)
Inventor
  • De, Indranil
  • Mankos, Marian
  • Ciplickas, Dennis
  • Hess, Christopher
  • Cheng, Jeremy
  • Murugan, Balasubramanian
  • Hu, Qi

Abstract

Systems, devices, and methods for performing a non-contact electrical measurement (NCEM) on a NCEM-enabled cell included in a NCEM-enabled cell vehicle may be configured to perform NCEMs while the NCEM-enabled cell vehicle is moving. The movement may be due to vibrations in the system and/or movement of a movable stage on which the NCEM-enabled cell vehicle is positioned. Position information for an electron beam column producing the electron beam performing the NCEMs and/or for the moving stage may be used to align the electron beam with targets on the NCEM-enabled cell vehicle while it is moving.

IPC Classes  ?

5.

PDF SOLUTIONS

      
Application Number 1812259
Status Registered
Filing Date 2023-04-18
Registration Date 2023-04-18
Owner PDF Solutions, Inc. (USA)
NICE Classes  ?
  • 09 - Scientific and electric apparatus and instruments
  • 37 - Construction and mining; installation and repair services
  • 42 - Scientific, technological and industrial services, research and design

Goods & Services

Downloadable and recorded computer software and hardware for use in semiconductor design and manufacturing; downloadable and recorded computer software and hardware for semiconductor integrated circuit design for use in semiconductor design, manufacturing, and testing; downloadable and recorded computer software and hardware for semiconductor design for use in tracking devices during the semiconductor design, manufacturing, assembly, and testing; downloadable and recorded computer software and hardware providing automated characterization and analysis of test chip and structures and cell library layouts in the field of semiconductor manufacturing; downloadable and recorded software for managing equipment sensor data, equipment control, and data analytics of semiconductor design and manufacturing processes; downloadable and recorded software for managing equipment sensor data, equipment controls and data analytics of electronics design and manufacturing processes; downloadable and recorded computer software and hardware using analytics of semiconductor design manufacturing execution systems data to increase efficiencies in the manufacture of semiconductors; downloadable and recorded computer software and hardware using analytics of semiconductor design consumable parts and materials data to decrease costs in the manufacture of semiconductors; downloadable and recorded computer programs using artificial intelligence and machine learning for use in semiconductor design, manufacturing, assembly, and testing, to improve yields and increase efficiencies in the manufacture of semiconductors; downloadable software for development of machine learning and deep learning algorithms, pattern recognition, and modeling technologies for use in the field of semiconductor design, test and manufacturing; electrical measurement computer hardware for use in the field of semiconductor manufacturing; traceability computer hardware for use in the field of semiconductor manufacturing device tracking; test equipment, namely, electronic sensors for testing electronic circuits and devices; test structures and test chips, namely, semiconductor test chips; downloadable and recorded computer software for semiconductor test data analytics; downloadable and recorded computer software for use in operating semiconductor testing machines; downloadable and recorded computer software for driving or enabling semiconductor devices and signal processors, or extending their functionality; integrated circuit modules for electronic data transfer and wireless communication. Installation and maintenance of computer hardware and hardware systems; technical support services, namely, troubleshooting in the nature of repair of computer hardware. Consulting, engineering, design and testing services in the field of the manufacture of semiconductors and for yield and performance improvement in the manufacture of semiconductors; analysis of technical data in the field of the manufacture of semiconductors and for yield and performance improvement in the manufacture of semiconductors; testing of semiconductors for quality control purposes; design of semiconductor test chips for others; product design and development services in the field of providing enhancements to hardware and software for manufacturing of semiconductors; providing technical support and consulting services, namely, troubleshooting in the nature of diagnosing computer hardware problems by providing design solutions in the field of integrated circuits and signal processing; providing technical information via temporary use of non-downloadable software for displaying models in the field of integrated circuits and signal processing solutions; providing temporary use of non-downloadable software for evaluating analog design circuitry, calibrating analog design circuitry, and driving analog design circuitry, featuring an online reference design library, circuit notes, and evaluation software code sets for IC design; cloud computing featuring software for processing data in the field of semiconductor design, test and manufacturing; providing temporary use of non-downloadable software for providing simulation, modeling and design tools for analog and mixed signal IC design; rental and leasing of computer hardware and computer peripherals; technical support services, namely, troubleshooting of computer software problems; technical support services, namely, troubleshooting in the nature of diagnosing computer hardware and software problems; computer hosting services, namely, providing computer hardware, computer software, computer peripherals to others on a subscription or pay-per-use basis; providing virtual computer systems and virtual computer environments through cloud computing; providing on-line non-downloadable software using artificial intelligence for use in machine learning and data analysis in the field of semiconductor design, test and manufacturing; application service provider (ASP) featuring software using artificial intelligence for use in machine learning and data analysis in the field of semiconductor design, test and manufacturing; software as a service (SaaS) services featuring software for use in machine learning in the field of semiconductor design, test and manufacturing; software as a service (SaaS) services featuring software that utilizes machine learning algorithms to discover patterns and perform analytics for use in machine learning in the field of semiconductor design, test and manufacturing; software as a service (SaaS) featuring cloud-based metrics and analytic algorithms for use in manufacturing processes, namely, for yield and performance improvement in the manufacture of semiconductors; software as a service (SaaS) services featuring software for sharing large and dimensional datasets for enterprise clients for the purpose of delivering automated data modeling, machine learning, predictive analytics, automated reasoning, diagnostics, optimization and recommendation services; software as a service (SaaS) services featuring software for use in developing, executing, monitoring, managing, and optimizing algorithms, business processes, and analytics in the fields of semiconductor design, test, process control, assembly and manufacturing; software as a service (SaaS) services, namely, hosting software for use by others for use in store, query, and sharing functionality for management of high dimensional big data sets, machine learning algorithms, and predictive models; providing temporary use of on-line non-downloadable software and applications using artificial intelligence for use in machine learning and data analysis in the field of semiconductor design, test, process control, assembly and manufacturing; providing temporary use of on-line non-downloadable cloud computing software using artificial intelligence for use in machine learning and data analysis in the field of semiconductor design, test, process control, assembly and manufacturing; configuration, installation and maintenance of computer software.

6.

PDF / SOLUTIONS

      
Application Number 1812069
Status Registered
Filing Date 2023-04-18
Registration Date 2023-04-18
Owner PDF Solutions, Inc. (USA)
NICE Classes  ?
  • 09 - Scientific and electric apparatus and instruments
  • 37 - Construction and mining; installation and repair services
  • 42 - Scientific, technological and industrial services, research and design

Goods & Services

Downloadable and recorded computer software and hardware for use in semiconductor design and manufacturing; downloadable and recorded computer software and hardware for semiconductor integrated circuit design for use in semiconductor design, manufacturing, and testing; downloadable and recorded computer software and hardware for semiconductor design for use in tracking devices during the semiconductor design, manufacturing, assembly, and testing; downloadable and recorded computer software and hardware providing automated characterization and analysis of test chip and structures and cell library layouts in the field of semiconductor manufacturing; downloadable and recorded software for managing equipment sensor data, equipment control, and data analytics of semiconductor design and manufacturing processes; downloadable and recorded software for managing equipment sensor data, equipment controls and data analytics of electronics design and manufacturing processes; downloadable and recorded computer software and hardware using analytics of semiconductor design manufacturing execution systems data to increase efficiencies in the manufacture of semiconductors; downloadable and recorded computer software and hardware using analytics of semiconductor design consumable parts and materials data to decrease costs in the manufacture of semiconductors; downloadable and recorded computer programs using artificial intelligence and machine learning for use in semiconductor design, manufacturing, assembly, and testing, to improve yields and increase efficiencies in the manufacture of semiconductors; downloadable software for development of machine learning and deep learning algorithms, pattern recognition, and modeling technologies for use in the field of semiconductor design, test and manufacturing; electrical measurement computer hardware for use in the field of semiconductor manufacturing; traceability computer hardware for use in the field of semiconductor manufacturing device tracking; test equipment, namely, electronic sensors for testing electronic circuits and devices; test structures and test chips, namely, semiconductor test chips; downloadable and recorded computer software for semiconductor test data analytics; downloadable and recorded computer software for use in operating semiconductor testing machines; downloadable and recorded computer software for driving or enabling semiconductor devices and signal processors, or extending their functionality; integrated circuit modules for electronic data transfer and wireless communication. Installation and maintenance of computer hardware and hardware systems; technical support services, namely, troubleshooting in the nature of repair of computer hardware. Consulting, engineering, design and testing services in the field of the manufacture of semiconductors and for yield and performance improvement in the manufacture of semiconductors; analysis of technical data in the field of the manufacture of semiconductors and for yield and performance improvement in the manufacture of semiconductors; testing of semiconductors for quality control purposes; design of semiconductor test chips for others; product design and development services in the field of providing enhancements to hardware and software for manufacturing of semiconductors; providing technical support and consulting services, namely, troubleshooting in the nature of diagnosing computer hardware problems by providing design solutions in the field of integrated circuits and signal processing; providing technical information via temporary use of non-downloadable software for displaying models in the field of integrated circuits and signal processing solutions; providing temporary use of non-downloadable software for evaluating analog design circuitry, calibrating analog design circuitry, and driving analog design circuitry, featuring an online reference design library, circuit notes, and evaluation software code sets for IC design; cloud computing featuring software for processing data in the field of semiconductor design, test and manufacturing; providing temporary use of non-downloadable software for providing simulation, modeling and design tools for analog and mixed signal IC design; rental and leasing of computer hardware and computer peripherals; technical support services, namely, troubleshooting of computer software problems; technical support services, namely, troubleshooting in the nature of diagnosing computer hardware and software problems; computer hosting services, namely, providing computer hardware, computer software, computer peripherals to others on a subscription or pay-per-use basis; providing virtual computer systems and virtual computer environments through cloud computing; providing on-line non-downloadable software using artificial intelligence for use in machine learning and data analysis in the field of semiconductor design, test and manufacturing; application service provider (ASP) featuring software using artificial intelligence for use in machine learning and data analysis in the field of semiconductor design, test and manufacturing; software as a service (SaaS) services featuring software for use in machine learning in the field of semiconductor design, test and manufacturing; software as a service (SaaS) services featuring software that utilizes machine learning algorithms to discover patterns and perform analytics for use in machine learning in the field of semiconductor design, test and manufacturing; software as a service (SaaS) featuring cloud-based metrics and analytic algorithms for use in manufacturing processes, namely, for yield and performance improvement in the manufacture of semiconductors; software as a service (SaaS) services featuring software for sharing large and dimensional datasets for enterprise clients for the purpose of delivering automated data modeling, machine learning, predictive analytics, automated reasoning, diagnostics, optimization and recommendation services; software as a service (SaaS) services featuring software for use in developing, executing, monitoring, managing, and optimizing algorithms, business processes, and analytics in the fields of semiconductor design, test, process control, assembly and manufacturing; software as a service (SaaS) services, namely, hosting software for use by others for use in store, query, and sharing functionality for management of high dimensional big data sets, machine learning algorithms, and predictive models; providing temporary use of on-line non-downloadable software and applications using artificial intelligence for use in machine learning and data analysis in the field of semiconductor design, test, process control, assembly and manufacturing; providing temporary use of on-line non-downloadable cloud computing software using artificial intelligence for use in machine learning and data analysis in the field of semiconductor design, test, process control, assembly and manufacturing; configuration, installation and maintenance of computer software.

7.

SYSTEMS, DEVICES, AND METHODS FOR ALIGNING A PARTICLE BEAM AND PERFORMING A NON-CONTACT ELECTRICAL MEASUREMENT ON A CELL AND/OR NON-CONTACT ELECTRICAL MEASUREMENT CELL VEHICLE USING A REGISTRATION CELL

      
Application Number 18663041
Status Pending
Filing Date 2024-05-13
First Publication Date 2024-09-12
Owner PDF SOLUTIONS, INC. (USA)
Inventor
  • De, Indranil
  • Cheng, Jeremy
  • Sokollik, Thomas
  • Schwarz, Yoram
  • Lam, Stephen
  • Shen, Xumin

Abstract

Systems, devices, and methods for performing a non-contact electrical measurement (NCEM) on a NCEM-enabled cell included in a NCEM-enabled cell vehicle may be configured to perform NCEMs while the NCEM-enabled cell vehicle is moving. The movement may be due to vibrations in the system and/or movement of a movable stage on which the NCEM-enabled cell vehicle is positioned. Position information for an electron beam column producing the electron beam performing the NCEMs and/or for the moving stage may be used to align the electron beam with targets on the NCEM-enabled cell vehicle while it is moving.

IPC Classes  ?

  • H01J 37/317 - Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. ion implantation
  • G01R 31/265 - Contactless testing
  • G01R 31/306 - Contactless testing using electron beams of printed or hybrid circuits
  • H01J 37/30 - Electron-beam or ion-beam tubes for localised treatment of objects

8.

Time-Series Segmentation and Anomaly Detection

      
Application Number 18527156
Status Pending
Filing Date 2023-12-01
First Publication Date 2024-06-06
Owner PDF Solutions, Inc. (USA)
Inventor
  • Honda, Tomonori
  • Zhou, Edward
  • David, Jeffrey D.

Abstract

Detection of data anomalies resulting from maintenance activities on semiconductor processing equipment. Time-series representation of the key indicators for equipment performance is cleaned then segmented according to sharp breaks in the data. The cleaned and segmented data is modeled, for example, by determining a linear fit for each segment. The slope and intercept of each modeled segment linear fit are compared and evaluated to identify anomalies in the data.

IPC Classes  ?

9.

TIME-SERIES SEGMENTATION AND ANOMALY DETECTION

      
Application Number US2023081966
Publication Number 2024/119004
Status In Force
Filing Date 2023-11-30
Publication Date 2024-06-06
Owner PDF SOLUTIONS, INC. (USA)
Inventor
  • Honda, Tomonori
  • Zhou, Edward
  • David, Jeffrey, D.

Abstract

Detection of data anomalies resulting from maintenance activities on semiconductor processing equipment. Time-series representation of the key indicators for equipment performance is cleaned then segmented according to sharp breaks in the data. The cleaned and segmented data is modeled, for example, by determining a linear fit for each segment. The slope and intercept of each modeled segment linear fit are compared and evaluated to identify anomalies in the data.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • G01R 31/317 - Testing of digital circuits
  • H01L 21/66 - Testing or measuring during manufacture or treatment
  • G01R 31/00 - Arrangements for testing electric propertiesArrangements for locating electric faultsArrangements for electrical testing characterised by what is being tested not provided for elsewhere

10.

EVALUATING A SURFACE MICROSTRUCTURE

      
Application Number US2023077023
Publication Number 2024/086543
Status In Force
Filing Date 2023-10-16
Publication Date 2024-04-25
Owner PDF SOLUTIONS, INC. (USA)
Inventor
  • Kostka, Peter
  • Slomowitz, Jenna
  • Montgomery, Darcy

Abstract

A method of evaluating the microstructure of a surface, such as a coating on a substrate. The surface is illuminated using at least one light source. One or more images of the illuminated surface are captured. The captured images are processed to identify one or more features of the microstructure, and then determine one or more parameters of the microstructure features. The parameters are compared to thresholds or limits to determine whether remedial action is needed.

IPC Classes  ?

  • G01N 21/88 - Investigating the presence of flaws, defects or contamination
  • G03F 1/84 - Inspecting

11.

Evaluating a Surface Microstructure

      
Application Number 18487960
Status Pending
Filing Date 2023-10-16
First Publication Date 2024-04-18
Owner PDF Solutions, Inc. (USA)
Inventor
  • Kostka, Peter
  • Slomowitz, Jenna
  • Montgomery, Darcy

Abstract

A method of evaluating the microstructure of a surface, such as a coating on a substrate. The surface is illuminated using at least one light source. One or more images of the illuminated surface are captured. The captured images are processed to identify one or more features of the microstructure, and then determine one or more parameters of the microstructure features. The parameters are compared to thresholds or limits to determine whether remedial action is needed.

IPC Classes  ?

  • G06T 7/00 - Image analysis
  • H01M 4/139 - Processes of manufacture
  • H01M 10/42 - Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells

12.

Wafer bin map based root cause analysis

      
Application Number 18365157
Grant Number 12229945
Status In Force
Filing Date 2023-08-03
First Publication Date 2023-11-23
Grant Date 2025-02-18
Owner PDF Solutions, Inc. (USA)
Inventor
  • Honda, Tomonori
  • Cheong, Lin Lee
  • Burch, Richard
  • Zhu, Qing
  • David, Jeffrey Drue
  • Keleher, Michael

Abstract

A template for assigning the most probable root causes for wafer defects. The bin map data for a subject wafer can be compared with bin map data for prior wafers to find wafers with similar issues. A probability can be determined as to whether the same root cause should be applied to the subject wafer, and if so, the wafer can be labeled with that root cause accordingly.

IPC Classes  ?

  • G06V 10/74 - Image or video pattern matchingProximity measures in feature spaces
  • G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
  • G06T 7/00 - Image analysis

13.

Systems, devices, and methods for performing a non-contact electrical measurement on a cell, non-contact electrical measurement cell vehicle, chip, wafer, die, or logic block

      
Application Number 18144146
Grant Number 12038476
Status In Force
Filing Date 2023-05-05
First Publication Date 2023-11-09
Grant Date 2024-07-16
Owner PDF SOLUTIONS, INC. (USA)
Inventor
  • De, Indranil
  • Mankos, Marian
  • Ciplickas, Dennis
  • Hess, Christopher
  • Cheng, Jeremy
  • Murugan, Balasubramanian
  • Hu, Qi

Abstract

Systems, devices, and methods for performing a non-contact electrical measurement (NCEM) on a NCEM-enabled cell included in a NCEM-enabled cell vehicle may be configured to perform NCEMs while the NCEM-enabled cell vehicle is moving. The movement may be due to vibrations in the system and/or movement of a movable stage on which the NCEM-enabled cell vehicle is positioned. Position information for an electron beam column producing the electron beam performing the NCEMs and/or for the moving stage may be used to align the electron beam with targets on the NCEM-enabled cell vehicle while it is moving.

IPC Classes  ?

14.

Systems, devices, and methods for aligning a particle beam and performing a non-contact electrical measurement on a cell and/or non-contact electrical measurement cell vehicle using a registration cell

      
Application Number 18108583
Grant Number 12020897
Status In Force
Filing Date 2023-02-11
First Publication Date 2023-09-07
Grant Date 2024-06-25
Owner PDF SOLUTIONS, INC. (USA)
Inventor
  • De, Indranil
  • Cheng, Jeremy
  • Sokollik, Thomas
  • Schwarz, Yoram
  • Lam, Stephen
  • Shen, Xumin

Abstract

Systems, devices, and methods for performing a non-contact electrical measurement (NCEM) on a NCEM-enabled cell included in a NCEM-enabled cell vehicle may be configured to perform NCEMs while the NCEM-enabled cell vehicle is moving. The movement may be due to vibrations in the system and/or movement of a movable stage on which the NCEM-enabled cell vehicle is positioned. Position information for an electron beam column producing the electron beam performing the NCEMs and/or for the moving stage may be used to align the electron beam with targets on the NCEM-enabled cell vehicle while it is moving.

IPC Classes  ?

  • H01J 37/30 - Electron-beam or ion-beam tubes for localised treatment of objects
  • G01R 31/265 - Contactless testing
  • G01R 31/306 - Contactless testing using electron beams of printed or hybrid circuits
  • H01J 37/317 - Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. ion implantation

15.

PDF / SOLUTIONS

      
Application Number 018818534
Status Registered
Filing Date 2023-01-02
Registration Date 2023-09-14
Owner PDF Solutions, Inc. (USA)
NICE Classes  ?
  • 09 - Scientific and electric apparatus and instruments
  • 37 - Construction and mining; installation and repair services
  • 42 - Scientific, technological and industrial services, research and design

Goods & Services

Downloadable and recorded computer software and hardware for use in semiconductor design and manufacturing; Downloadable and recorded computer software and hardware for semiconductor integrated circuit design for use in semiconductor design, manufacturing, and testing; Downloadable and recorded computer software and hardware for semiconductor design for use in tracking devices during the semiconductor design, manufacturing, assembly, and testing; Downloadable and recorded computer software and hardware providing automated characterization and analysis of test chip and structures and cell library layouts in the field of semiconductor manufacturing; Downloadable and recorded software for managing equipment sensor data, equipment control, and data analytics of semiconductor design and manufacturing processes; Downloadable and recorded software for managing equipment sensor data, equipment controls and data analytics of electronics design and manufacturing processes; Downloadable and recorded computer software and hardware using analytics of semiconductor design manufacturing execution systems data to increase efficiencies in the manufacture of semiconductors; Downloadable and recorded computer software and hardware using analytics of semiconductor design consumable parts and materials data to decrease costs in the manufacture of semiconductors; Downloadable and recorded computer programs using artificial intelligence and machine learning for use in semiconductor design, manufacturing, assembly, and testing, to improve yields and increase efficiencies in the manufacture of semiconductors; Downloadable software for development of machine learning and deep learning algorithms, pattern recognition, and modeling technologies for use in the field of semiconductor design, test and manufacturing; Electrical measurement computer hardware for use in the field of semiconductor manufacturing; Traceability computer hardware for use in the field of semiconductor manufacturing device tracking; Test equipment, namely, electronic sensors for testing electronic circuits and devices; Test structures and test chips, namely, semiconductor test chips; Downloadable and recorded computer software for semiconductor test data analytics; Downloadable and recorded computer software for use in operating semiconductor testing machines; Downloadable and recorded computer software for driving or enabling semiconductor devices and signal processors, or extending their functionality; Integrated circuit modules for electronic data transfer and wireless communication. Configuration, installation, and maintenance of computer hardware and computer hardware systems; technical support services, namely troubleshooting in the nature of repair of computer hardware. Consulting, engineering, design and testing services in the field of the manufacture of semiconductors and for yield and performance improvement in the manufacture of semiconductors; Analysis of technical data in the field of the manufacture of semiconductors and for yield and performance improvement in the manufacture of semiconductors; Testing of semiconductors for quality control purposes; Design of semiconductor test chips for others; Product design and development services in the field of providing enhancements to hardware and software for manufacturing of semiconductors; Providing technical support and consulting services, namely, troubleshooting in the nature of diagnosing computer hardware problems by providing design solutions in the field of integrated circuits and signal processing; Providing technical information via temporary use of non-downloadable software for displaying models in the field of integrated circuits and signal processing solutions; Providing temporary use of non-downloadable software for evaluating analog design circuitry, calibrating analog design circuitry, and driving analog design circuitry, featuring an online reference design library, circuit notes, and evaluation software code sets for IC design; Providing temporary use of non-downloadable software for providing simulation, modeling and design tools for analog and mixed signal IC design; Rental and leasing of computer hardware and computer peripherals; Providing on-line non-downloadable software using artificial intelligence for use in machine learning and data analysis in the field of semiconductor design, test and manufacturing; Software as a service (SaaS) services, namely, hosting software for use by others for use in store, query, and sharing functionality for management of high dimensional big data sets, machine learning algorithms, and predictive models; Providing temporary use of on-line non-downloadable software and applications using artificial intelligence for use in machine learning and data analysis in the field of semiconductor design, test, process control, assembly and manufacturing; Providing temporary use of on-line non-downloadable cloud computing software using artificial intelligence for use in machine learning and data analysis in the field of semiconductor design, test, process control, assembly and manufacturing.

16.

PDF SOLUTIONS

      
Serial Number 97733191
Status Registered
Filing Date 2022-12-27
Registration Date 2024-08-06
Owner PDF Solutions, Inc. ()
NICE Classes  ?
  • 09 - Scientific and electric apparatus and instruments
  • 37 - Construction and mining; installation and repair services
  • 42 - Scientific, technological and industrial services, research and design

Goods & Services

Downloadable and recorded computer software and hardware for use in semiconductor design and manufacturing; Downloadable and recorded computer software and hardware for semiconductor integrated circuit design for use in semiconductor design, manufacturing, and testing; Downloadable and recorded computer software and hardware for semiconductor design for use in tracking devices during the semiconductor design, manufacturing, assembly, and testing; Downloadable and recorded computer software and hardware providing automated characterization and analysis of test chip and structures and cell library layouts in the field of semiconductor manufacturing; Downloadable and recorded software for managing equipment sensor data, equipment control, and data analytics of semiconductor design and manufacturing processes; Downloadable and recorded software for managing equipment sensor data, equipment controls and data analytics of electronics design and manufacturing processes; Downloadable and recorded computer software and hardware using analytics of semiconductor design manufacturing execution systems data to increase efficiencies in the manufacture of semiconductors; Downloadable and recorded computer software and hardware using analytics of semiconductor design consumable parts and materials data to decrease costs in the manufacture of semiconductors; Downloadable and recorded computer programs using artificial intelligence and machine learning for use in semiconductor design, manufacturing, assembly, and testing, to improve yields and increase efficiencies in the manufacture of semiconductors; Downloadable software for development of machine learning and deep learning algorithms, pattern recognition, and modeling technologies for use in the field of semiconductor design, test and manufacturing; Electrical measurement computer hardware for use in the field of semiconductor manufacturing; Traceability computer hardware for use in the field of semiconductor manufacturing device tracking; Test equipment, namely, electronic sensors for testing electronic circuits and devices; Test structures and test chips, namely, semiconductor test chips; Downloadable and recorded computer software for semiconductor test data analytics; Downloadable and recorded computer software for use in operating semiconductor testing machines; Downloadable and recorded computer software for driving or enabling semiconductor devices and signal processors, or extending their functionality; Integrated circuit modules for electronic data transfer and wireless communication Installation and maintenance of computer hardware and hardware systems; technical support services, namely, troubleshooting in the nature of repair of computer hardware Consulting, engineering, design and testing services in the field of the manufacture of semiconductors and for yield and performance improvement in the manufacture of semiconductors; Analysis of technical data in the field of the manufacture of semiconductors and for yield and performance improvement in the manufacture of semiconductors; Testing of semiconductors for quality control purposes; Design of semiconductor test chips for others; Product design and development services in the field of providing enhancements to hardware and software for manufacturing of semiconductors; Providing technical support and consulting services, namely, troubleshooting in the nature of diagnosing computer hardware problems by providing design solutions in the field of integrated circuits and signal processing; Providing technical information via temporary use of non-downloadable software for displaying models in the field of integrated circuits and signal processing solutions; Providing temporary use of non-downloadable software for evaluating analog design circuitry, calibrating analog design circuitry, and driving analog design circuitry, featuring an online reference design library, circuit notes, and evaluation software code sets for IC design; Cloud computing featuring software for processing data in the field of semiconductor design, test and manufacturing; Providing temporary use of non-downloadable software for providing simulation, modeling and design tools for analog and mixed signal IC design; Rental and leasing of computer hardware and computer peripherals; Technical support services, namely, troubleshooting of computer software problems; Technical support services, namely, troubleshooting in the nature of diagnosing computer hardware and software problems; Computer hosting services, namely, providing computer hardware, computer software, computer peripherals to others on a subscription or pay-per-use basis; providing virtual computer systems and virtual computer environments through cloud computing; Providing on-line non-downloadable software using artificial intelligence for use in machine learning and data analysis in the field of semiconductor design, test and manufacturing; Application service provider (ASP) featuring software using artificial intelligence for use in machine learning and data analysis in the field of semiconductor design, test and manufacturing; Software as a service (SaaS) services featuring software for use in machine learning in the field of semiconductor design, test and manufacturing; Software as a Service (SaaS) services featuring software that utilizes machine learning algorithms to discover patterns and perform analytics for use in machine learning in the field of semiconductor design, test and manufacturing; Software as a Service (SaaS) featuring cloud-based metrics and analytic algorithms for use in manufacturing processes, namely, for yield and performance improvement in the manufacture of semiconductors; Software as a service (SaaS) services featuring software for sharing large and dimensional datasets for enterprise clients for the purpose of delivering automated data modeling, machine learning, predictive analytics, automated reasoning, diagnostics, optimization and recommendation services; Software as a service (SaaS) services featuring software for use in developing, executing, monitoring, managing, and optimizing algorithms, business processes, and analytics in the fields of semiconductor design, test, process control, assembly and manufacturing; Software as a service (SaaS) services, namely, hosting software for use by others for use in store, query, and sharing functionality for management of high dimensional big data sets, machine learning algorithms, and predictive models; Providing temporary use of on-line non-downloadable software and applications using artificial intelligence for use in machine learning and data analysis in the field of semiconductor design, test, process control, assembly and manufacturing; Providing temporary use of on-line non-downloadable cloud computing software using artificial intelligence for use in machine learning and data analysis in the field of semiconductor design, test, process control, assembly and manufacturing; Configuration of computer hardware and computer software and hardware systems; Installation, maintenance and repair of software for computer systems; Maintenance of computer software

17.

PDF/SOLUTIONS

      
Serial Number 97733196
Status Registered
Filing Date 2022-12-27
Registration Date 2024-08-06
Owner PDF Solutions, Inc. ()
NICE Classes  ?
  • 09 - Scientific and electric apparatus and instruments
  • 37 - Construction and mining; installation and repair services
  • 42 - Scientific, technological and industrial services, research and design

Goods & Services

Downloadable and recorded computer software and hardware for use in semiconductor design and manufacturing; Downloadable and recorded computer software and hardware for semiconductor integrated circuit design for use in semiconductor design, manufacturing, and testing; Downloadable and recorded computer software and hardware for semiconductor design for use in tracking devices during the semiconductor design, manufacturing, assembly, and testing; Downloadable and recorded computer software and hardware providing automated characterization and analysis of test chip and structures and cell library layouts in the field of semiconductor manufacturing; Downloadable and recorded software for managing equipment sensor data, equipment control, and data analytics of semiconductor design and manufacturing processes; Downloadable and recorded software for managing equipment sensor data, equipment controls and data analytics of electronics design and manufacturing processes; Downloadable and recorded computer software and hardware using analytics of semiconductor design manufacturing execution systems data to increase efficiencies in the manufacture of semiconductors; Downloadable and recorded computer software and hardware using analytics of semiconductor design consumable parts and materials data to decrease costs in the manufacture of semiconductors; Downloadable and recorded computer programs using artificial intelligence and machine learning for use in semiconductor design, manufacturing, assembly, and testing, to improve yields and increase efficiencies in the manufacture of semiconductors; Downloadable software for development of machine learning and deep learning algorithms, pattern recognition, and modeling technologies for use in the field of semiconductor design, test and manufacturing; Electrical measurement computer hardware for use in the field of semiconductor manufacturing; Traceability computer hardware for use in the field of semiconductor manufacturing device tracking; Test equipment, namely, electronic sensors for testing electronic circuits and devices; Test structures and test chips, namely, semiconductor test chips; Downloadable and recorded computer software for semiconductor test data analytics; Downloadable and recorded computer software for use in operating semiconductor testing machines; Downloadable and recorded computer software for driving or enabling semiconductor devices and signal processors, or extending their functionality; Integrated circuit modules for electronic data transfer and wireless communication Installation and maintenance of computer hardware and hardware systems; technical support services, namely, troubleshooting in the nature of repair of computer hardware Consulting, engineering, design and testing services in the field of the manufacture of semiconductors and for yield and performance improvement in the manufacture of semiconductors; Analysis of technical data in the field of the manufacture of semiconductors and for yield and performance improvement in the manufacture of semiconductors; Testing of semiconductors for quality control purposes; Design of semiconductor test chips for others; Product design and development services in the field of providing enhancements to hardware and software for manufacturing of semiconductors; Providing technical support and consulting services, namely, troubleshooting in the nature of diagnosing computer hardware problems by providing design solutions in the field of integrated circuits and signal processing; Providing technical information via temporary use of non-downloadable software for displaying models in the field of integrated circuits and signal processing solutions; Providing temporary use of non-downloadable software for evaluating analog design circuitry, calibrating analog design circuitry, and driving analog design circuitry, featuring an online reference design library, circuit notes, and evaluation software code sets for IC design; Cloud computing featuring software for processing data in the field of semiconductor design, test and manufacturing; Providing temporary use of non-downloadable software for providing simulation, modeling and design tools for analog and mixed signal IC design; Rental and leasing of computer hardware and computer peripherals; Technical support services, namely, troubleshooting of computer software problems; Technical support services, namely, troubleshooting in the nature of diagnosing computer hardware and software problems; Computer hosting services, namely, providing computer hardware, computer software, computer peripherals to others on a subscription or pay-per-use basis; providing virtual computer systems and virtual computer environments through cloud computing; Providing on-line non-downloadable software using artificial intelligence for use in machine learning and data analysis in the field of semiconductor design, test and manufacturing; Application service provider (ASP) featuring software using artificial intelligence for use in machine learning and data analysis in the field of semiconductor design, test and manufacturing; Software as a service (SaaS) services featuring software for use in machine learning in the field of semiconductor design, test and manufacturing; Software as a Service (SaaS) services featuring software that utilizes machine learning algorithms to discover patterns and perform analytics for use in machine learning in the field of semiconductor design, test and manufacturing; Software as a Service (SaaS) featuring cloud-based metrics and analytic algorithms for use in manufacturing processes, namely, for yield and performance improvement in the manufacture of semiconductors; Software as a service (SaaS) services featuring software for sharing large and dimensional datasets for enterprise clients for the purpose of delivering automated data modeling, machine learning, predictive analytics, automated reasoning, diagnostics, optimization and recommendation services; Software as a service (SaaS) services featuring software for use in developing, executing, monitoring, managing, and optimizing algorithms, business processes, and analytics in the fields of semiconductor design, test, process control, assembly and manufacturing; Software as a service (SaaS) services, namely, hosting software for use by others for use in store, query, and sharing functionality for management of high dimensional big data sets, machine learning algorithms, and predictive models; Providing temporary use of on-line non-downloadable software and applications using artificial intelligence for use in machine learning and data analysis in the field of semiconductor design, test, process control, assembly and manufacturing; Providing temporary use of on-line non-downloadable cloud computing software using artificial intelligence for use in machine learning and data analysis in the field of semiconductor design, test, process control, assembly and manufacturing; Configuration of computer hardware and computer software and hardware systems; Installation, maintenance and repair of software for computer systems; Maintenance of computer software

18.

Systems, devices, and methods for performing a non-contact electrical measurement on a cell, non-contact electrical measurement cell vehicle, chip, wafer, die, or logic block

      
Application Number 17750405
Grant Number 11668746
Status In Force
Filing Date 2022-05-23
First Publication Date 2022-11-17
Grant Date 2023-06-06
Owner PDF SOLUTIONS, INC. (USA)
Inventor
  • De, Indranil
  • Mankos, Marian
  • Ciplickas, Dennis
  • Hess, Christopher
  • Cheng, Jeremy
  • Murugan, Balasubramanian
  • Hu, Qi

Abstract

Systems, devices, and methods for performing a non-contact electrical measurement (NCEM) on a NCEM-enabled cell included in a NCEM-enabled cell vehicle may be configured to perform NCEMs while the NCEM-enabled cell vehicle is moving. The movement may be due to vibrations in the system and/or movement of a movable stage on which the NCEM-enabled cell vehicle is positioned. Position information for an electron beam column producing the electron beam performing the NCEMs and/or for the moving stage may be used to align the electron beam with targets on the NCEM-enabled cell vehicle while it is moving.

IPC Classes  ?

19.

Sequenced Approach For Determining Wafer Path Quality

      
Application Number 17459657
Status Pending
Filing Date 2021-08-27
First Publication Date 2022-03-03
Owner PDF SOLUTIONS, INC. (USA)
Inventor
  • Honda, Tomonori
  • Burch, Richard
  • David, Jeffrey Drue

Abstract

Wafer quality is determined by modeling equipment history as a sequence of events, then evaluating anomalous results for individual events. Identifying an event that generates bad wafers narrows the list of possible root causes.

IPC Classes  ?

  • G05B 19/18 - Numerical control [NC], i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form
  • G05B 19/406 - Numerical control [NC], i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form characterised by monitoring or safety

20.

SEQUENCED APPROACH FOR DETERMINING WAFER PATH QUALITY

      
Application Number US2021048027
Publication Number 2022/047208
Status In Force
Filing Date 2021-08-27
Publication Date 2022-03-03
Owner PDF SOLUTIONS, INC. (USA)
Inventor
  • Honda, Tomonori
  • Burch, Richard
  • David, Jeffrey Drue

Abstract

Wafer quality is determined by modeling equipment history as a sequence of events, then evaluating anomalous results for individual events. Identifying an event that generates bad wafers narrows the list of possible root causes.

IPC Classes  ?

  • G06F 19/00 - Digital computing or data processing equipment or methods, specially adapted for specific applications (specially adapted for specific functions G06F 17/00;data processing systems or methods specially adapted for administrative, commercial, financial, managerial, supervisory or forecasting purposes G06Q;healthcare informatics G16H)

21.

Pattern-enhanced spatial correlation of test structures to die level responses

      
Application Number 17395632
Grant Number 11640160
Status In Force
Filing Date 2021-08-06
First Publication Date 2022-02-10
Grant Date 2023-05-02
Owner PDF Solutions, Inc. (USA)
Inventor
  • Burch, Richard
  • Zhu, Qing

Abstract

Enhancement of less dominant patterns for parametric wafer measurements. Dominant patterns are removed from the parametric pattern thereby revealing a less dominant pattern. The less dominant patterns can be used to identify root causes for yield loss that are not visible in the original parametric measurements.

IPC Classes  ?

  • G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM]

22.

PATTERN-ENHANCED SPATIAL CORRELATION OF TEST STRUCTURES TO DIE LEVEL RESPONSES

      
Application Number US2021044882
Publication Number 2022/032056
Status In Force
Filing Date 2021-08-06
Publication Date 2022-02-10
Owner PDF SOLUTIONS, INC. (USA)
Inventor
  • Burch, Richard
  • Zhu, Qing

Abstract

Enhancement of less dominant patterns for parametric wafer measurements. Dominant patterns are removed from the parametric pattern thereby revealing a less dominant pattern. The less dominant patterns can be used to identify root causes for yield loss that are not visible in the original parametric measurements.

IPC Classes  ?

  • G06F 17/50 - Computer-aided design
  • G01B 5/28 - Measuring arrangements characterised by the use of mechanical techniques for measuring roughness or irregularity of surfaces
  • H01L 21/66 - Testing or measuring during manufacture or treatment

23.

Predicting equipment fail mode from process trace

      
Application Number 17383334
Grant Number 11640328
Status In Force
Filing Date 2021-07-22
First Publication Date 2022-01-27
Grant Date 2023-05-02
Owner PDF Solutions, Inc. (USA)
Inventor
  • Burch, Richard
  • Kunitoshi, Kazuki

Abstract

A predictive model for equipment fail modes. An anomaly is detected in a collection of trace data, then key features are calculated. A search is conducted for the same or similar anomalies having the same key features in a database of past trace data. If the same anomaly occurred before and is in the database, then the type of anomaly, its root cause, and action steps to correct can be retrieved from the database.

IPC Classes  ?

  • G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

24.

PREDICTING EQUIPMENT FAIL MODE FROM PROCESS TRACE

      
Application Number US2021042842
Publication Number 2022/020642
Status In Force
Filing Date 2021-07-22
Publication Date 2022-01-27
Owner PDF SOLUTIONS, INC. (USA)
Inventor
  • Burch, Richard
  • Kunitoshi, Kazuki

Abstract

A predictive model for equipment fail modes. An anomaly is detected in a collection of trace data, then key features are calculated. A search is conducted for the same or similar anomalies having the same key features in a database of past trace data. If the same anomaly occurred before and is in the database, then the type of anomaly, its root cause, and action steps to correct can be retrieved from the database.

IPC Classes  ?

  • G06K 9/62 - Methods or arrangements for recognition using electronic means

25.

Automatic window generation for process trace

      
Application Number 17383325
Grant Number 11687439
Status In Force
Filing Date 2021-07-22
First Publication Date 2022-01-27
Grant Date 2023-06-27
Owner PDF Solutions, Inc. (USA)
Inventor
  • Burch, Richard
  • Kunitoshi, Kazuki
  • Aruga, Michio
  • Akiya, Nobichika

Abstract

Automatic definition of windows for trace analysis. For each process step, the trace data are aligned to both the start of the process step and the end of the process step, and statistics including rate of change are calculated from both the start of the process step and the end of the process step. Windows are generated based on analysis of the calculated statistics.

IPC Classes  ?

  • G06F 11/00 - Error detectionError correctionMonitoring
  • G06F 11/34 - Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation

26.

AUTOMATIC WINDOW GENERATION FOR PROCESS TRACE

      
Application Number US2021042840
Publication Number 2022/020640
Status In Force
Filing Date 2021-07-22
Publication Date 2022-01-27
Owner PDF SOLUTIONS, INC. (USA)
Inventor
  • Burch, Richard
  • Kunitoshi, Kazuki
  • Aruga, Michio
  • Akiya, Nobuchika

Abstract

Automatic definition of windows for trace analysis. For each process step, the trace data are aligned to both the start of the process step and the end of the process step, and statistics including rate of change are calculated from both the start of the process step and the end of the process step. Windows are generated based on analysis of the calculated statistics.

IPC Classes  ?

  • G06K 9/62 - Methods or arrangements for recognition using electronic means

27.

WAFER BIN MAP BASED ROOT CAUSE ANALYSIS

      
Application Number US2021030306
Publication Number 2021/222836
Status In Force
Filing Date 2021-04-30
Publication Date 2021-11-04
Owner PDF SOLUTIONS, INC. (USA)
Inventor
  • Honda, Tomonori
  • Cheong, Lin, Lee
  • Burch, Richard
  • Zhu, Qing
  • David, Jeffrey, Drue
  • Keleher, Michael

Abstract

A template for assigning the most probable root causes for wafer defects. The bin map data for a subject wafer can be compared with bin map data for prior wafers to find wafers with similar issues. A probability can be determined as to whether the same root cause should be applied to the subject wafer, and if so, the wafer can be labeled with that root cause accordingly.

IPC Classes  ?

  • G01N 31/00 - Investigating or analysing non-biological materials by the use of the chemical methods specified in the subgroupsApparatus specially adapted for such methods
  • G01F 19/00 - Calibrated capacity measures for fluids or fluent solid material, e.g. measuring cups
  • H01L 21/66 - Testing or measuring during manufacture or treatment

28.

Wafer bin map based root cause analysis

      
Application Number 17246397
Grant Number 11763446
Status In Force
Filing Date 2021-04-30
First Publication Date 2021-11-04
Grant Date 2023-09-19
Owner PDF Solutions, Inc. (USA)
Inventor
  • Honda, Tomonori
  • Cheong, Lin Lee
  • Burch, Richard
  • Zhu, Qing
  • David, Jeffrey Drue
  • Keleher, Michael

Abstract

A template for assigning the most probable root causes for wafer defects. The bin map data for a subject wafer can be compared with bin map data for prior wafers to find wafers with similar issues. A probability can be determined as to whether the same root cause should be applied to the subject wafer, and if so, the wafer can be labeled with that root cause accordingly.

IPC Classes  ?

  • G06V 10/74 - Image or video pattern matchingProximity measures in feature spaces
  • G06T 7/00 - Image analysis
  • G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance

29.

Abnormal wafer image classification

      
Application Number 17237516
Grant Number 11972552
Status In Force
Filing Date 2021-04-22
First Publication Date 2021-10-28
Grant Date 2024-04-30
Owner PDF Solutions, Inc. (USA)
Inventor
  • Honda, Tomonori
  • Burch, Richard
  • Zhu, Qing
  • David, Jeffrey Drue

Abstract

A semiconductor image classifier. Convolution functions are applied to modify the wafer images in order to extract key information about the image. The modified images are condensed then processed through a series of pairwise classifiers, each classifier configured to determine that the image is more like one of the pair than the other. Probabilities from each classifier are collected to form a prediction for each image.

IPC Classes  ?

  • G06K 9/62 - Methods or arrangements for recognition using electronic means
  • G06F 18/2415 - Classification techniques relating to the classification model, e.g. parametric or non-parametric approaches based on parametric or probabilistic models, e.g. based on likelihood ratio or false acceptance rate versus a false rejection rate
  • G06F 18/2431 - Multiple classes
  • G06N 5/04 - Inference or reasoning models
  • G06N 20/00 - Machine learning
  • G06T 7/00 - Image analysis
  • G06V 10/44 - Local feature extraction by analysis of parts of the pattern, e.g. by detecting edges, contours, loops, corners, strokes or intersectionsConnectivity analysis, e.g. of connected components
  • G06V 10/764 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using classification, e.g. of video objects
  • G06V 10/82 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using neural networks

30.

ABNORMAL WAFER IMAGE CLASSIFICATION

      
Application Number US2021028563
Publication Number 2021/216822
Status In Force
Filing Date 2021-04-22
Publication Date 2021-10-28
Owner PDF SOLUTIONS, INC. (USA)
Inventor
  • Honda, Tomonori
  • Burch, Richard
  • Zhu, Qing
  • David, Jeffrey, Drue

Abstract

A semiconductor image classifier. Convolution functions are applied to modify the wafer images in order to extract key information about the image. The modified images are condensed then processed through a series of pairwise classifiers, each classifier configured to determine that the image is more like one of the pair than the other. Probabilities from each classifier are collected to form a prediction for each image.

IPC Classes  ?

31.

PREDICTING DIE SUSCEPTIBLE TO EARLY LIFETIME FAILURE

      
Application Number US2021020396
Publication Number 2021/178361
Status In Force
Filing Date 2021-03-02
Publication Date 2021-09-10
Owner PDF SOLUTIONS, INC. (USA)
Inventor
  • Burch, Richard
  • Zhu, Qing
  • Arnold, Keith

Abstract

Semiconductor yield is modeled at the die level to predict die that are susceptible to early lifetime failure (ELF). A first die yield calculation is made from parametric data obtained from wafer testing in a semiconductor manufacturing process. A second die yield calculation is made from die location only. The difference between the first die yield calculation and the second die yield calculation is a prediction delta. Based on an evaluation of the first die yield calculation and the prediction delta, the likelihood of early lifetime failure can be identified and an acceptable level of die loss can be established to remove die from further processing.

IPC Classes  ?

  • G06N 20/00 - Machine learning
  • G06N 3/08 - Learning methods
  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • G06N 3/04 - Architecture, e.g. interconnection topology
  • H01L 21/66 - Testing or measuring during manufacture or treatment

32.

Predicting die susceptible to early lifetime failure

      
Application Number 17189621
Grant Number 11328108
Status In Force
Filing Date 2021-03-02
First Publication Date 2021-09-09
Grant Date 2022-05-10
Owner PDF Solutions, Inc. (USA)
Inventor
  • Burch, Richard
  • Zhu, Qing
  • Arnold, Keith

Abstract

Semiconductor yield is modeled at the die level to predict die that are susceptible to early lifetime failure (ELF). A first die yield calculation is made from parametric data obtained from wafer testing in a semiconductor manufacturing process. A second die yield calculation is made from die location only. The difference between the first die yield calculation and the second die yield calculation is a prediction delta. Based on an evaluation of the first die yield calculation and the prediction delta, the likelihood of early lifetime failure can be identified and an acceptable level of die loss can be established to remove die from further processing.

IPC Classes  ?

  • G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
  • G06F 119/02 - Reliability analysis or reliability optimisationFailure analysis, e.g. worst case scenario performance, failure mode and effects analysis [FMEA]
  • G06F 119/22 - Yield analysis or yield optimisation

33.

IC with test structures and e-beam pads embedded within a contiguous standard cell area

      
Application Number 16458095
Grant Number 11107804
Status In Force
Filing Date 2019-06-30
First Publication Date 2021-08-31
Grant Date 2021-08-31
Owner PDF Solutions, Inc. (USA)
Inventor
  • Lam, Stephen
  • Ciplickas, Dennis
  • Brozek, Tomasz
  • Cheng, Jeremy
  • Comensoli, Simone
  • De, Indranil
  • Doong, Kelvin
  • Eisenmann, Hans
  • Fiscus, Timothy
  • Haigh, Jonathan
  • Hess, Christopher
  • Kibarian, John
  • Lee, Sherry
  • Liao, Marci
  • Lin, Sheng-Che
  • Matsuhashi, Hideki
  • Michaels, Kimon
  • O'Sullivan, Conor
  • Rauscher, Markus
  • Rovner, Vyacheslav
  • Strojwas, Andrzej
  • Strojwas, Marcin
  • Taylor, Carl
  • Vallishayee, Rakesh
  • Weiland, Larg
  • Yokoyama, Nobuharu
  • Moe, Matthew

Abstract

An IC that includes a contiguous standard cell area with a 4x3 e-beam pad that is compatible with advanced manufacturing processes and an associated e-beam testable structure.

IPC Classes  ?

  • H01L 21/66 - Testing or measuring during manufacture or treatment
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/45 - Ohmic electrodes
  • H01L 21/8234 - MIS technology
  • H01J 37/26 - Electron or ion microscopesElectron- or ion-diffraction tubes
  • H03K 19/0944 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET
  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • G06F 30/39 - Circuit design at the physical level

34.

IC with test structures and e-beam pads embedded within a contiguous standard cell area

      
Application Number 16458085
Grant Number 11081476
Status In Force
Filing Date 2019-06-30
First Publication Date 2021-08-03
Grant Date 2021-08-03
Owner PDF Solutions, Inc. (USA)
Inventor
  • Lam, Stephen
  • Ciplickas, Dennis
  • Brozek, Tomasz
  • Cheng, Jeremy
  • Comensoli, Simone
  • De, Indranil
  • Doong, Kelvin
  • Eisenmann, Hans
  • Fiscus, Timothy
  • Haigh, Jonathan
  • Hess, Christopher
  • Kibarian, John
  • Lee, Sherry
  • Liao, Marci
  • Lin, Sheng-Che
  • Matsuhashi, Hideki
  • Michaels, Kimon
  • O'Sullivan, Conor
  • Rauscher, Markus
  • Rovner, Vyacheslav
  • Strojwas, Andrzej
  • Strojwas, Marcin
  • Taylor, Carl
  • Vallishayee, Rakesh
  • Weiland, Larg
  • Yokoyama, Nobuharu
  • Moe, Matthew

Abstract

An IC that includes a contiguous standard cell area with a 4×3 e-beam pad that is compatible with advanced manufacturing processes and an associated e-beam testable structure.

IPC Classes  ?

  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 21/66 - Testing or measuring during manufacture or treatment
  • G01R 31/303 - Contactless testing of integrated circuits
  • H01L 21/8234 - MIS technology
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
  • H01L 27/118 - Masterslice integrated circuits
  • G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
  • G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]

35.

IC with test structures and e-beam pads embedded within a contiguous standard cell area

      
Application Number 16458087
Grant Number 11081477
Status In Force
Filing Date 2019-06-30
First Publication Date 2021-08-03
Grant Date 2021-08-03
Owner PDF Solutions, Inc. (USA)
Inventor
  • Lam, Stephen
  • Ciplickas, Dennis
  • Brozek, Tomasz
  • Cheng, Jeremy
  • Comensoli, Simone
  • De, Indranil
  • Doong, Kelvin
  • Eisenmann, Hans
  • Fiscus, Timothy
  • Haigh, Jonathan
  • Hess, Christopher
  • Kibarian, John
  • Lee, Sherry
  • Liao, Marci
  • Lin, Sheng-Che
  • Matsuhashi, Hideki
  • Michaels, Kimon
  • O'Sullivan, Conor
  • Rauscher, Markus
  • Rovner, Vyacheslav
  • Strojwas, Andrzej
  • Strojwas, Marcin
  • Taylor, Carl
  • Vallishayee, Rakesh
  • Weiland, Larg
  • Yokoyama, Nobuharu
  • Moe, Matthew

Abstract

An IC that includes a contiguous standard cell area with a 4×3 e-beam pad that is compatible with advanced manufacturing processes and an associated e-beam testable structure.

IPC Classes  ?

  • H01L 21/26 - Bombardment with wave or particle radiation
  • H01L 21/66 - Testing or measuring during manufacture or treatment
  • H01L 29/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor bodies or of electrodes thereof
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/45 - Ohmic electrodes
  • H01L 21/8234 - MIS technology
  • H01J 37/26 - Electron or ion microscopesElectron- or ion-diffraction tubes
  • H03K 19/0944 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET
  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • G06F 30/39 - Circuit design at the physical level

36.

IC with test structures and E-beam pads embedded within a contiguous standard cell area

      
Application Number 16458088
Grant Number 11075194
Status In Force
Filing Date 2019-06-30
First Publication Date 2021-07-27
Grant Date 2021-07-27
Owner PDF Solutions, Inc. (USA)
Inventor
  • Lam, Stephen
  • Ciplickas, Dennis
  • Brozek, Tomasz
  • Cheng, Jeremy
  • Comensoli, Simone
  • De, Indranil
  • Doong, Kelvin
  • Eisenmann, Hans
  • Fiscus, Timothy
  • Haigh, Jonathan
  • Hess, Christopher
  • Kibarian, John
  • Lee, Sherry
  • Liao, Marci
  • Lin, Sheng-Che
  • Matsuhashi, Hideki
  • Michaels, Kimon
  • O'Sullivan, Conor
  • Rauscher, Markus
  • Rovner, Vyacheslav
  • Strojwas, Andrzej
  • Strojwas, Marcin
  • Taylor, Carl
  • Vallishayee, Rakesh
  • Weiland, Larg
  • Yokoyama, Nobuharu
  • Moe, Matthew

Abstract

An IC that includes a contiguous standard cell area with a 4×3 e-beam pad that is compatible with advanced manufacturing processes and an associated e-beam testable structure.

IPC Classes  ?

  • H01L 21/66 - Testing or measuring during manufacture or treatment
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/45 - Ohmic electrodes
  • H01L 21/8234 - MIS technology
  • H01J 37/26 - Electron or ion microscopesElectron- or ion-diffraction tubes
  • H03K 19/0944 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET
  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • G06F 30/39 - Circuit design at the physical level

37.

IC with test structures and e-beam pads embedded within a contiguous standard cell area

      
Application Number 16458082
Grant Number 11018126
Status In Force
Filing Date 2019-06-30
First Publication Date 2021-05-25
Grant Date 2021-05-25
Owner PDF Solutions, Inc. (USA)
Inventor
  • Lam, Stephen
  • Ciplickas, Dennis
  • Brozek, Tomasz
  • Cheng, Jeremy
  • Comensoli, Simone
  • De, Indranil
  • Doong, Kelvin
  • Eisenmann, Hans
  • Fiscus, Timothy
  • Haigh, Jonathan
  • Hess, Christopher
  • Kibarian, John
  • Lee, Sherry
  • Liao, Marci
  • Lin, Sheng-Che
  • Matsuhashi, Hideki
  • Michaels, Kimon
  • O'Sullivan, Conor
  • Rauscher, Markus
  • Rovner, Vyacheslav
  • Strojwas, Andrzej
  • Strojwas, Marcin
  • Taylor, Carl
  • Vallishayee, Rakesh
  • Weiland, Larg
  • Yokoyama, Nobuharu
  • Moe, Matthew

Abstract

An IC that includes a contiguous standard cell area with a 4×3 e-beam pad that is compatible with advanced manufacturing processes and an associated e-beam testable structure.

IPC Classes  ?

  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01J 37/26 - Electron or ion microscopesElectron- or ion-diffraction tubes
  • H01L 21/66 - Testing or measuring during manufacture or treatment
  • H03K 19/0944 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/45 - Ohmic electrodes
  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • H01L 21/8234 - MIS technology
  • G06F 30/39 - Circuit design at the physical level

38.

Collaborative learning model for semiconductor applications

      
Application Number 17070520
Grant Number 12038802
Status In Force
Filing Date 2020-10-14
First Publication Date 2021-05-13
Grant Date 2024-07-16
Owner PDF Solutions, Inc. (USA)
Inventor
  • Honda, Tomonori
  • Burch, Richard
  • Kibarian, John
  • Cheong, Lin Lee
  • Zhu, Qing
  • Reddipalli, Vaishnavi
  • Harris, Kenneth
  • Akar, Said
  • David, Jeffrey D
  • Keleher, Michael
  • Stine, Brian
  • Ciplickas, Dennis

Abstract

Classifying wafers using Collaborative Learning. An initial wafer classification is determined by a rule-based model. A predicted wafer classification is determined by a machine learning model. Multiple users can manually review the classifications to confirm or modify, or to add user classifications. All of the classifications are input to the machine learning model to continuously update its scheme for detection and classification.

IPC Classes  ?

  • G06N 20/00 - Machine learning
  • G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
  • G06F 18/211 - Selection of the most significant subset of features
  • G06F 18/241 - Classification techniques relating to the classification model, e.g. parametric or non-parametric approaches
  • G06F 18/40 - Software arrangements specially adapted for pattern recognition, e.g. user interfaces or toolboxes therefor
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • G06F 3/0482 - Interaction with lists of selectable items, e.g. menus
  • G06N 3/08 - Learning methods
  • G06N 7/01 - Probabilistic graphical models, e.g. probabilistic networks

39.

Machine learning variable selection and root cause discovery by cumulative prediction

      
Application Number 17072830
Grant Number 12223012
Status In Force
Filing Date 2020-10-16
First Publication Date 2021-04-22
Grant Date 2025-02-11
Owner PDF Solutions, Inc. (USA)
Inventor
  • Burch, Richard
  • Zhu, Qing
  • Holt, Jonathan
  • Honda, Tomonori

Abstract

A sequence of models accumulates r-squared values for an increasing number of variables in order to quantify the importance of each variable to the prediction of a targeted yield or parametric response.

IPC Classes  ?

  • G06N 20/00 - Machine learning
  • G06F 17/18 - Complex mathematical operations for evaluating statistical data
  • G06F 18/2113 - Selection of the most significant subset of features by ranking or filtering the set of features, e.g. using a measure of variance or of feature cross-correlation
  • G06N 5/04 - Inference or reasoning models

40.

COLLABORATIVE LEARNING MODEL FOR SEMICONDUCTOR APPLICATIONS

      
Application Number US2020055556
Publication Number 2021/076609
Status In Force
Filing Date 2020-10-14
Publication Date 2021-04-22
Owner PDF SOLUTIONS, INC. (USA)
Inventor
  • Honda, Tomonori
  • Burch, Richard
  • Kibarian, John
  • Cheong, Lin, Lee
  • Zhu, Qing
  • Reddipalli, Vaishnavi
  • Harris, Kenneth
  • Akar, Said
  • David, Jeffrey, D.
  • Keleher, Michael
  • Stein, Brian
  • Ciplickas, Dennis

Abstract

Classifying wafers using Collaborative Learning. An initial wafer classification is determined by a rule-based model. A predicted wafer classification is determined by a machine learning model. Multiple users can manually review the classifications to confirm or modify, or to add user classifications. All of the classifications are input to the machine learning model to continuously update its scheme for detection and classification.

IPC Classes  ?

  • G06K 9/00 - Methods or arrangements for reading or recognising printed or written characters or for recognising patterns, e.g. fingerprints
  • G06K 9/62 - Methods or arrangements for recognition using electronic means
  • G06T 7/00 - Image analysis
  • H01L 21/66 - Testing or measuring during manufacture or treatment

41.

MACHINE LEARNING VARIABLE SELECTION AND ROOT CAUSE DISCOVERY BY CUMULATIVE PREDICTION

      
Application Number US2020056053
Publication Number 2021/076943
Status In Force
Filing Date 2020-10-16
Publication Date 2021-04-22
Owner PDF SOLUTIONS, INC. (USA)
Inventor
  • Burch, Richard
  • Zhu, Qing
  • Holt, Jonathan
  • Honda, Tomonori

Abstract

A sequence of models accumulates r-squared values for an increasing number of variables in order to quantify the importance of each variable to the prediction of a targeted yield or parametric response.

IPC Classes  ?

  • G06N 20/10 - Machine learning using kernel methods, e.g. support vector machines [SVM]
  • G06F 15/18 - in which a program is changed according to experience gained by the computer itself during a complete run; Learning machines (adaptive control systems G05B 13/00;artificial intelligence G06N)
  • G06N 3/08 - Learning methods
  • G06N 5/02 - Knowledge representationSymbolic representation
  • G06N 5/04 - Inference or reasoning models

42.

Die level product modeling without die level input data

      
Application Number 17072817
Grant Number 11972987
Status In Force
Filing Date 2020-10-16
First Publication Date 2021-04-22
Grant Date 2024-04-30
Owner PDF Solutions, Inc. (USA)
Inventor
  • Burch, Richard
  • Zhu, Qing
  • Holt, Jonathan

Abstract

A machine learning model for each die for imputing process control parameters at the die. The model is based on wafer sort parametric measurements at multiple test sites across the entire wafer, as well as yield results for the wafer. This allows for a better analysis of outlier spatial patterns leading to improved yield results.

IPC Classes  ?

43.

DIE LEVEL PRODUCT MODELING WITHOUT DIE LEVEL INPUT DATA

      
Application Number US2020056047
Publication Number 2021/076937
Status In Force
Filing Date 2020-10-16
Publication Date 2021-04-22
Owner PDF SOLUTIONS, INC. (USA)
Inventor
  • Burch, Richard
  • Zhu, Qing
  • Holt, Jonathan

Abstract

A machine learning model for each die for imputing process control parameters at the die. The model is based on wafer sort parametric measurements at multiple test sites across the entire wafer, as well as yield results for the wafer. This allows for a better analysis of outlier spatial patterns leading to improved yield results.

IPC Classes  ?

  • G06F 17/50 - Computer-aided design
  • H01L 21/82 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
  • H01L 23/00 - Details of semiconductor or other solid state devices

44.

ANOMALOUS EQUIPMENT TRACE DETECTION AND CLASSIFICATION

      
Application Number US2020054431
Publication Number 2021/071854
Status In Force
Filing Date 2020-10-06
Publication Date 2021-04-15
Owner PDF SOLUTIONS, INC. (USA)
Inventor
  • Burch, Richard
  • David, Jeffrey, D.
  • Zhu, Qing
  • Honda, Tomonori
  • Cheong, Lin, Lee

Abstract

Scheme for detection and classification of semiconductor equipment faults. Sensor traces are monitored and processed to separate known abnormal operating conditions from unknown abnormal operating conditions. Feature engineering permits focus on relevant traces for a targeted feature. A machine learning model is built to detect and classify based on an initial classification set of anomalies. The machine learning model is continuously updated as more traces are processed and learned.

IPC Classes  ?

45.

IC with test structures and E-beam pads embedded within a contiguous standard cell area

      
Application Number 16458042
Grant Number 10978438
Status In Force
Filing Date 2019-06-29
First Publication Date 2021-04-13
Grant Date 2021-04-13
Owner PDF Solutions, Inc. (USA)
Inventor
  • Lam, Stephen
  • Ciplickas, Dennis
  • Brozek, Tomasz
  • Cheng, Jeremy
  • Comensoli, Simone
  • De, Indranil
  • Doong, Kelvin
  • Eisenmann, Hans
  • Fiscus, Timothy
  • Haigh, Jonathan
  • Hess, Christopher
  • Kibarian, John
  • Lee, Sherry
  • Liao, Marci
  • Lin, Sheng-Che
  • Matsuhashi, Hideki
  • Michaels, Kimon
  • O'Sullivan, Conor
  • Rauscher, Markus
  • Rovner, Vyacheslav
  • Strojwas, Andrzej
  • Strojwas, Marcin
  • Taylor, Carl
  • Vallishayee, Rakesh
  • Weiland, Larg
  • Yokoyama, Nobuharu
  • Moe, Matthew

Abstract

An IC that includes a contiguous standard cell area with a 4×3 e-beam pad that is compatible with advanced manufacturing processes and an associated e-beam testable structure.

IPC Classes  ?

  • H01L 21/66 - Testing or measuring during manufacture or treatment
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
  • H01L 21/8234 - MIS technology
  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
  • H01L 29/45 - Ohmic electrodes
  • H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes

46.

Anomalous equipment trace detection and classification

      
Application Number 17064422
Grant Number 11609812
Status In Force
Filing Date 2020-10-06
First Publication Date 2021-04-08
Grant Date 2023-03-21
Owner PDF Solutions, Inc. (USA)
Inventor
  • Burch, Richard
  • David, Jeffrey D.
  • Zhu, Qing
  • Honda, Tomonori
  • Cheong, Lin Lee

Abstract

Scheme for detection and classification of semiconductor equipment faults. Sensor traces are monitored and processed to separate known abnormal operating conditions from unknown abnormal operating conditions. Feature engineering permits focus on relevant traces for a targeted feature. A machine learning model is built to detect and classify based on an initial classification set of anomalies. The machine learning model is continuously updated as more traces are processed and learned.

IPC Classes  ?

  • G06N 20/00 - Machine learning
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • G06F 3/0482 - Interaction with lists of selectable items, e.g. menus
  • G06N 3/08 - Learning methods
  • G06N 7/00 - Computing arrangements based on specific mathematical models
  • G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
  • G06K 9/62 - Methods or arrangements for recognition using electronic means

47.

Methods for performing a non-contact electrical measurement on a cell, chip, wafer, die, or logic block

      
Application Number 17061352
Grant Number 11340293
Status In Force
Filing Date 2020-10-01
First Publication Date 2021-04-01
Grant Date 2022-05-24
Owner PDF SOLUTIONS, INC. (USA)
Inventor
  • De, Indranil
  • Mankos, Marian
  • Ciplickas, Dennis
  • Hess, Christopher
  • Cheng, Jeremy
  • Murugan, Balasubramanian
  • Hu, Qi

Abstract

Systems, devices, and methods for performing a non-contact electrical measurement (NCEM) on a NCEM-enabled cell included in a NCEM-enabled cell vehicle may be configured to perform NCEMs while the NCEM-enabled cell vehicle is moving. The movement may be due to vibrations in the system and/or movement of a movable stage on which the NCEM-enabled cell vehicle is positioned. Position information for an electron beam column producing the electron beam performing the NCEMs and/or for the moving stage may be used to align the electron beam with targets on the NCEM-enabled cell vehicle while it is moving.

IPC Classes  ?

48.

Methods for aligning a particle beam and performing a non-contact electrical measurement on a cell using a registration cell

      
Application Number 17061401
Grant Number 11328899
Status In Force
Filing Date 2020-10-01
First Publication Date 2021-04-01
Grant Date 2022-05-10
Owner PDF SOLUTIONS, INC. (USA)
Inventor
  • De, Indranil
  • Cheng, Jeremy
  • Sokollik, Thomas
  • Schwarz, Yoram
  • Lam, Stephen
  • Shen, Xumin

Abstract

Systems, devices, and methods for performing a non-contact electrical measurement (NCEM) on a NCEM-enabled cell included in a NCEM-enabled cell vehicle may be configured to perform NCEMs while the NCEM-enabled cell vehicle is moving. The movement may be due to vibrations in the system and/or movement of a movable stage on which the NCEM-enabled cell vehicle is positioned. Position information for an electron beam column producing the electron beam performing the NCEMs and/or for the moving stage may be used to align the electron beam with targets on the NCEM-enabled cell vehicle while it is moving.

IPC Classes  ?

  • H01J 37/30 - Electron-beam or ion-beam tubes for localised treatment of objects
  • H01J 37/317 - Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. ion implantation
  • G01R 31/306 - Contactless testing using electron beams of printed or hybrid circuits
  • G01R 31/265 - Contactless testing

49.

Maintenance scheduling for semiconductor manufacturing equipment

      
Application Number 17002250
Grant Number 11295993
Status In Force
Filing Date 2020-08-25
First Publication Date 2020-12-10
Grant Date 2022-04-05
Owner PDF Solutions, Inc. (USA)
Inventor
  • Honda, Tomonori
  • David, Jeffrey Drue
  • Cheong, Lin Lee

Abstract

A maintenance tool for semiconductor process equipment and components. Sensor data is evaluated by machine learning tools to determine when to schedule maintenance action.

IPC Classes  ?

  • G06F 11/22 - Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
  • G06F 7/50 - AddingSubtracting
  • H01L 21/66 - Testing or measuring during manufacture or treatment
  • G06N 20/00 - Machine learning
  • G01R 31/26 - Testing of individual semiconductor devices

50.

Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, corner short, and via open test areas

      
Application Number 15942475
Grant Number 10854522
Status In Force
Filing Date 2018-03-31
First Publication Date 2020-12-01
Grant Date 2020-12-01
Owner PDF Solutions, Inc. (USA)
Inventor
  • Lam, Stephen
  • Ciplickas, Dennis
  • Brozek, Tomasz
  • Cheng, Jeremy
  • Comensoli, Simone
  • De, Indranil
  • Doong, Kelvin
  • Eisenmann, Hans
  • Fiscus, Timothy
  • Haigh, Jonathan
  • Hess, Christopher
  • Kibarian, John
  • Lee, Sherry
  • Liao, Marci
  • Lin, Sheng-Che
  • Matsuhashi, Hideki
  • Michaels, Kimon
  • O'Sullivan, Conor
  • Rauscher, Markus
  • Rovner, Vyacheslav
  • Strojwas, Andrzej
  • Strojwas, Marcin
  • Taylor, Carl
  • Vallishayee, Rakesh
  • Weiland, Larg
  • Yokoyama, Nobuharu

Abstract

A method for processing a semiconductor wafer uses non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, corner short, and via open test areas.

IPC Classes  ?

  • H01L 23/528 - Layout of the interconnection structure
  • H01L 21/66 - Testing or measuring during manufacture or treatment
  • H01L 27/118 - Masterslice integrated circuits
  • H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • G06F 30/30 - Circuit design
  • G06F 30/39 - Circuit design at the physical level
  • G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
  • G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]

51.

Snap-to valid pattern system and method

      
Application Number 15695933
Grant Number 10803221
Status In Force
Filing Date 2017-09-05
First Publication Date 2020-10-13
Grant Date 2020-10-13
Owner PDF Solutions, Inc. (USA)
Inventor
  • Lagnese, Elizabeth
  • Haigh, Jonathan

Abstract

Described is a method for implementing a snap to capability that enables the manufactured of a valid pattern in a semiconductor device, based upon an originally invalid pattern.

IPC Classes  ?

52.

IC with test structures embedded within a contiguous standard cell area

      
Application Number 16147631
Grant Number 10777472
Status In Force
Filing Date 2018-09-29
First Publication Date 2020-09-15
Grant Date 2020-09-15
Owner PDF Solutions, Inc. (USA)
Inventor
  • Lam, Stephen
  • Ciplickas, Dennis
  • Brozek, Tomasz
  • Cheng, Jeremy
  • Comensoli, Simone
  • De, Indranil
  • Doong, Kelvin
  • Eisenmann, Hans
  • Fiscus, Timothy
  • Haigh, Jonathan
  • Hess, Christopher
  • Kibarian, John
  • Lee, Sherry
  • Liao, Marci
  • Lin, Sheng-Che
  • Matsuhashi, Hideki
  • Michaels, Kimon
  • O'Sullivan, Conor
  • Rauscher, Markus
  • Rovner, Vyacheslav
  • Strojwas, Andrzej
  • Strojwas, Marcin
  • Taylor, Carl
  • Vallishayee, Rakesh
  • Weiland, Larg
  • Yokoyama, Nobuharu

Abstract

An IC includes a contiguous standard cell area with first, second, and third TS-GATE-short-configured test area geometries disposed therein. In some embodiments, the contiguous standard cell area may further include: fourth and fifth TS-GATE-short-configured test area geometries, and/or other test area geometries, such as tip-to-tip-short, tip-to-side-short, diagonal-short, corner-short, interlayer-overlap-short, via-chamfer-short, merged-via-short, snake-open, stitch-open, via-open, or metal-island-open.

IPC Classes  ?

  • H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for
  • H01L 21/66 - Testing or measuring during manufacture or treatment
  • H01L 23/528 - Layout of the interconnection structure

53.

Method and apparatus for direct testing and characterization of a three dimensional semiconductor memory structure

      
Application Number 15997411
Grant Number 10768222
Status In Force
Filing Date 2018-06-04
First Publication Date 2020-09-08
Grant Date 2020-09-08
Owner PDF SOLUTIONS, INC. (USA)
Inventor Brozek, Tomasz

Abstract

Described here is an apparatus and method of testing a vertical (3D) semiconductor memory structure coupled between word lines and bit lines, by means of a direct connections of a plurality of test pads to word lines and bit lines of the memory structure on memory product wafer. Such connections are created by modified patterns of metal lines through contacts and vias created on the memory product wafer. The described apparatus and method are used for detecting electrical continuity (opens and shorts) in the memory structure, calculating resistance of selected word lines or bit cell strings, or performing more complex tests of memory bit cell transistors. The result of this detection can then be used to find defective regions or memory cells in the semiconductor memory structure. Such a testing device may be referred to as a direct testing system.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

54.

Direct memory characterization using periphery transistors

      
Application Number 16211545
Grant Number 10679723
Status In Force
Filing Date 2018-12-06
First Publication Date 2020-06-09
Grant Date 2020-06-09
Owner PDF SOLUTIONS, INC. (USA)
Inventor
  • Lee, Dong Kyu
  • Doong, Kelvin Yih-Yuh
  • Pham, Tuan
  • Schuegraf, Klaus
  • Dolainsky, Christoph
  • Huang, Huan Tsung
  • Schneider, Hendrik

Abstract

Disclosed is a system and method for performing direct memory characterization of memory cells in a memory array using peripheral transistors. A memory array is fabricated using a mask layer defining routing for a set of first stage periphery transistors electrically connected to the word lines of the memory array. A revised mask is used for defining a different routing for a set of second stage periphery transistors including different characteristics than the first stage periphery transistors. Testing is conducted by applying a simulated Erase signal to the nonvolatile memory cells and determining which cells are erased. Based on this test, certain characteristics of the first and/or second stage periphery transistors can be identified that provide improved conditions for the nonvolatile memory cells. A product chip can be manufactured using modified versions of the first stage periphery transistors that incorporate the characteristics that provide the improved condition(s).

IPC Classes  ?

  • G11C 29/56 - External testing equipment for static stores, e.g. automatic test equipment [ATE]Interfaces therefor
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 27/11526 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the peripheral circuit region
  • H01L 21/66 - Testing or measuring during manufacture or treatment
  • G11C 16/14 - Circuits for erasing electrically, e.g. erase voltage switching circuits
  • H01L 27/11573 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the peripheral circuit region
  • G06F 30/394 - Routing
  • G06F 30/333 - Design for testability [DFT], e.g. scan chain or built-in self-test [BIST]

55.

Passive array test structure for cross-point memory characterization

      
Application Number 16033156
Grant Number 10643735
Status In Force
Filing Date 2018-07-11
First Publication Date 2020-05-05
Grant Date 2020-05-05
Owner PDF Solutions, Inc. (USA)
Inventor
  • Brozek, Tomasz
  • Hess, Christopher
  • Vallishayee, Rakesh
  • Lunenborg, Meindert
  • Schneider, Hendrik
  • Yu, Yuan
  • Joag, Amit
  • Ng, Siewhoon

Abstract

An apparatus and method for testing two-terminal memory elements organized as a cross-point memory array. The apparatus allows functional testing of two-terminal memory elements organized as a cross-point memory array, and built in a short flow manufacturing process. The proposed apparatus substantially eliminates the use of any type of additional active or passive switches, selectors, or decoders. A large number of memory elements of various memory types including planar (two dimensional) or three dimensional memory structures can be tested without the need of manufacturing selectors or running the full flow process.

IPC Classes  ?

  • G11C 29/44 - Indication or identification of errors, e.g. for repair
  • G11C 29/52 - Protection of memory contentsDetection of errors in memory contents
  • G11C 16/14 - Circuits for erasing electrically, e.g. erase voltage switching circuits
  • G11C 29/56 - External testing equipment for static stores, e.g. automatic test equipment [ATE]Interfaces therefor
  • G11C 29/04 - Detection or location of defective memory elements

56.

Method for applying charge-based-capacitance-measurement with switches using only NMOS or only PMOS transistors

      
Application Number 15269843
Grant Number 10641804
Status In Force
Filing Date 2016-09-19
First Publication Date 2020-05-05
Grant Date 2020-05-05
Owner PDF Solutions, Inc. (USA)
Inventor Saxena, Sharad

Abstract

Described is a CBCM technique that works only with PMOS transistors or only with NMOS transistors. Specifically, a method of monitoring performance of an integrated circuit device using a CBCM technique is disclosed, the method comprising: providing a metrology structure having a pseudo-inverter comprising a pull-up pull-down transistor switch, wherein the transistor switch comprises a pull-up transistor and a pull-down transistor of the same type; charging and discharging a device under test (DUT) coupled to the pseudo-inverter using a non-overlapping clock; measuring capacitance of the DUT with a gate voltage of the pull-up transistor at a preset value; and, using the value of the measured capacitance to estimate a dimension of a structure in the integrated circuit device. The non-overlapping clock is generated by: turning the pull-down transistor off when the pull-up transistor is on; and, turning the pull-down transistor on when the pull-up transistor is off.

IPC Classes  ?

  • G01R 27/26 - Measuring inductance or capacitanceMeasuring quality factor, e.g. by using the resonance methodMeasuring loss factorMeasuring dielectric constants
  • G01R 31/01 - Subjecting similar articles in turn to test, e.g. "go/no-go" tests in mass productionTesting objects at points as they pass through a testing station
  • G01B 7/02 - Measuring arrangements characterised by the use of electric or magnetic techniques for measuring length, width, or thickness
  • G01N 27/22 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating capacitance

57.

Characterization vehicles for printed circuit board and system design

      
Application Number 16717668
Grant Number 10897814
Status In Force
Filing Date 2019-12-17
First Publication Date 2020-04-16
Grant Date 2021-01-19
Owner PDF Solutions, Inc. (USA)
Inventor Stine, Brian E.

Abstract

A characterization vehicle may include a first test circuit and a second test circuit located on separate panels of a panelized printed circuit (PC) board. The first test circuit may be fabricated in accordance with a first plurality of design parameters. The second test circuit may be fabricated in accordance with a second plurality of design parameters. The first plurality of design parameters and the second plurality of design parameters may be chosen in accordance with a design of experiment (DOE) concerning one or more design rules or design trade-offs such that at least two corresponding design parameters from the first and second test circuits have identical values, and at least two corresponding design parameters from the first and second test circuits have different values.

IPC Classes  ?

  • G06F 17/50 - Computer-aided design
  • H05K 1/02 - Printed circuits Details
  • G01R 31/317 - Testing of digital circuits
  • H03K 19/00 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits
  • H01L 21/66 - Testing or measuring during manufacture or treatment

58.

IC chips containing a mixture of standard cells obtained from an original set of design rules and enhanced standard cells that are a substantially uniform variant of the original set of design rules and methods for making the same

      
Application Number 15644081
Grant Number 10622344
Status In Force
Filing Date 2017-07-07
First Publication Date 2020-04-14
Grant Date 2020-04-14
Owner PDF SOLUTIONS, INC. (USA)
Inventor
  • Haigh, Jonathan
  • Lagnese, Elizabeth

Abstract

The present invention relates to IC chips containing a mixture of standard cells obtained from an original set of design rules and enhanced standard cells that are a variant of the original set of design rules and methods for making the same.

IPC Classes  ?

  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 23/528 - Layout of the interconnection structure
  • G06F 17/50 - Computer-aided design
  • H01L 27/118 - Masterslice integrated circuits
  • H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched

59.

Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of NCEM-enabled fill cells

      
Application Number 15090267
Grant Number 10593604
Status In Force
Filing Date 2016-04-04
First Publication Date 2020-03-17
Grant Date 2020-03-17
Owner PDF Solutions, Inc. (USA)
Inventor
  • Lam, Stephen
  • Ciplickas, Dennis
  • Brozek, Tomasz
  • Cheng, Jeremy
  • Comensoli, Simone
  • De, Indranil
  • Doong, Kelvin
  • Eisenmann, Hans
  • Fiscus, Timothy
  • Haigh, Jonathan
  • Hess, Christopher
  • Kibarian, John
  • Lee, Sherry
  • Liao, Marci
  • Lin, Sheng-Che
  • Matsuhashi, Hideki
  • Michaels, Kimon
  • O'Sullivan, Conor
  • Rauscher, Markus
  • Rovner, Vyacheslav
  • Strojwas, Andrzej
  • Strojwas, Marcin
  • Taylor, Carl
  • Vallishayee, Rakesh
  • Weiland, Larg
  • Yokoyama, Nobuharu

Abstract

Improved processes for manufacturing wafers, chips, or dies utilize in-line data obtained from non-contact electrical measurements (“NCEM”) of fill cells that contain structures configured target/expose a variety of open-circuit, short-circuit, leakage, or excessive resistance failure modes. Such processes may involve evaluating Designs of Experiments (“DOEs”), comprised of multiple NCEM-enabled fill cells, in at least two variants, all targeted to the same failure mode(s).

IPC Classes  ?

  • H01L 21/66 - Testing or measuring during manufacture or treatment
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • G06K 9/03 - Detection or correction of errors, e.g. by rescanning the pattern
  • G06K 9/62 - Methods or arrangements for recognition using electronic means
  • G01R 31/307 - Contactless testing using electron beams of integrated circuits
  • G01N 21/956 - Inspecting patterns on the surface of objects
  • H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • G01N 21/66 - Systems in which the material investigated is excited whereby it emits light or causes a change in wavelength of the incident light electrically excited, e.g. electroluminescence
  • G06T 7/00 - Image analysis

60.

Standard cell design conformance using boolean assertions

      
Application Number 16205875
Grant Number 10565344
Status In Force
Filing Date 2018-11-30
First Publication Date 2020-02-18
Grant Date 2020-02-18
Owner PDF Solutions, Inc. (USA)
Inventor Lagnese, Elizabeth

Abstract

Disclosed techniques conform standard cells in an integrated circuit design into a valid template pattern using a template-based approach to standard cell design. The template architecture stores valid patterns of circuit elements for the design. A Boolean expression comprising an aggregated set of Boolean assertions can be generated for each different combination of cell shape features and edge locations with the cell design to compute a solution that matches with a valid pattern in one of the templates. If the solution evaluates to a Boolean TRUE result, the cell shape(s) can be modified in accordance with the solution. If not, the granularity can be updated by incrementing an “adjustment neighborhood” value and iterating the computations for shape features and edge locations using the updated values for the analysis until a Boolean TRUE result is found or it is determined there is no solution for the set of expressions.

IPC Classes  ?

61.

Test structures and method for electrical measurement of FinFET fin height

      
Application Number 15269854
Grant Number 10529631
Status In Force
Filing Date 2016-09-19
First Publication Date 2020-01-07
Grant Date 2020-01-07
Owner PDF SOLUTIONS, INC. (USA)
Inventor
  • Saxena, Sharad
  • Cheng, Jianjun
  • Yu, Yuan

Abstract

Methods of measuring fin height electrically for devices fabricated using FinFET technology are disclosed here. One method uses an interleaving comb-like test structure with no gate. The other method extracts fin height from total gate capacitance from FinFETS with varying gate lengths. When a comb-like structure with no gate is used to measure fin height, if there is another structure with a gate is used, then the gate capacitance may be measured to independently measure thickness of gate dielectric.

IPC Classes  ?

  • H01L 29/66 - Types of semiconductor device
  • H01L 21/66 - Testing or measuring during manufacture or treatment

62.

Characterization vehicles for printed circuit board and system design

      
Application Number 16162072
Grant Number 10517169
Status In Force
Filing Date 2018-10-16
First Publication Date 2019-10-17
Grant Date 2019-12-24
Owner PDF SOLUTIONS, INC. (USA)
Inventor Stine, Brian E

Abstract

A characterization vehicle may include a first test circuit and a second test circuit located on separate panels of a panelized printed circuit (PC) board. The first test circuit may be fabricated in accordance with a first plurality of design parameters. The second test circuit may be fabricated in accordance with a second plurality of design parameters. The first plurality of design parameters and the second plurality of design parameters may be chosen in accordance with a design of experiment (DOE) concerning one or more design rules or design trade-offs such that at least two corresponding design parameters from the first and second test circuits have identical values, and at least two corresponding design parameters from the first and second test circuits have different values.

IPC Classes  ?

  • G06F 17/50 - Computer-aided design
  • H05K 1/02 - Printed circuits Details
  • G01R 31/317 - Testing of digital circuits
  • H03K 19/00 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits
  • H01L 21/66 - Testing or measuring during manufacture or treatment

63.

Selective inclusion/exclusion of semiconductor chips in accelerated failure tests

      
Application Number 16365538
Grant Number 10777470
Status In Force
Filing Date 2019-03-26
First Publication Date 2019-10-03
Grant Date 2020-09-15
Owner PDF Solutions, Inc. (USA)
Inventor
  • Cheong, Lin Lee
  • Honda, Tomonori
  • Kekatpure, Rohan D.
  • Kuravi, Lakshmikar
  • David, Jeffrey Drue

Abstract

Testing data is evaluated by machine learning tools to determine whether to include or exclude chips from further testing.

IPC Classes  ?

  • G06F 11/22 - Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
  • G06F 17/50 - Computer-aided design
  • H01L 21/66 - Testing or measuring during manufacture or treatment
  • G06N 20/00 - Machine learning
  • G01R 31/26 - Testing of individual semiconductor devices

64.

Failure detection and classsification using sensor data and/or measurement data

      
Application Number 16297403
Grant Number 11029359
Status In Force
Filing Date 2019-03-08
First Publication Date 2019-09-12
Grant Date 2021-06-08
Owner PDF Solutions, Inc. (USA)
Inventor
  • Honda, Tomonori
  • Cheong, Lin Lee
  • Kuravi, Lakshmikar

Abstract

A model is generated for predicting failures at the wafer production level. Input data from sensors is stored as an initial dataset, then data exhibiting excursions or useless impact is removed from the dataset. The dataset is converted into target features, where the target features are useful in predicting whether a wafer will be normal or not. A trade-off between positive and negative results is selected, and a plurality of predictive models are created. The final model is selected based on the trade-off criteria, and deployed.

IPC Classes  ?

65.

Direct access memory characterization vehicle

      
Application Number 15441016
Grant Number 10410735
Status In Force
Filing Date 2017-02-23
First Publication Date 2019-09-10
Grant Date 2019-09-10
Owner PDF SOLUTIONS, INC. (USA)
Inventor
  • Doong, Yih-Yuh
  • Lin, Chao-Hsiung
  • Lin, Sheng-Che
  • Kuo, Shihpin
  • Shen, Tzupin
  • Lin, Chia-Chi
  • Michaels, Kimon

Abstract

A memory-specific implementation of a test and characterization vehicle utilizes a design layout that is a modified version of the product mask. Specific routing is used to modify the product mask in order to facilitate memory cell characterization. This approach can be applied to any memory architecture with word-line and bit-line perpendicular or substantially perpendicular to each other, including but not limited to, volatile memories such as Static Random Access Memory (SRAM), Dynamic RAM (DRAM), non-volatile memory such as NAND Flash (including three-dimensional NAND Flash), NOR Flash, Phase-change RAM (PRAM), Ferroelectric RAM (FeRAM), Correlated electron RAM (CeRAM), Magnetic RAM (MRAM), Resistive RAM (RRAM), XPoint memory and the like.

IPC Classes  ?

  • G11C 29/12 - Built-in arrangements for testing, e.g. built-in self testing [BIST]
  • G06F 1/3206 - Monitoring of events, devices or parameters that trigger a change in power modality
  • G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
  • G11C 29/48 - Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths

66.

Direct probing characterization vehicle for transistor, capacitor and resistor testing

      
Application Number 15273545
Grant Number 10380305
Status In Force
Filing Date 2016-09-22
First Publication Date 2019-08-13
Grant Date 2019-08-13
Owner PDF Solutions, Inc. (USA)
Inventor
  • Doong, Yih-Yuh
  • Lin, Sheng-Che
  • Lin, Chia-Chi
  • Eisenmann, Hans
  • Huang, Cho-Si
  • Shen, Tzupin
  • Hess, Christopher
  • Michaels, Kimon

Abstract

A method is disclosed for designing a test vehicle utilizing a layout of a real integrated circuit (IC) product. The method comprises: importing an original full-chip layout of the real IC product; partitioning the original full-chip layout into probe groups, each probe group comprising probe pads, and, a plurality of IC devices within an area of interest (AOI) having original routing interconnect for those IC devices; selecting a set of IC devices within the AOI; and, for the selected set of IC devices, using pattern extraction to remove the original routing interconnect, and create customized interconnect layers (CIL) to reconfigure connection between the individual IC devices. Incorporating the selected set of IC devices with the CIL into the original full-chip layout creates a modified full-chip layout such that a wafer fabricated using the modified full-chip layout comprises a real product with a built-in test vehicle.

IPC Classes  ?

  • G06F 9/455 - EmulationInterpretationSoftware simulation, e.g. virtualisation or emulation of application or operating system execution engines
  • G06F 17/50 - Computer-aided design

67.

Failure detection for wire bonding in semiconductors

      
Application Number 16138928
Grant Number 10656204
Status In Force
Filing Date 2018-09-21
First Publication Date 2019-05-16
Grant Date 2020-05-19
Owner PDF Solutions, Inc. (USA)
Inventor
  • Stine, Brian
  • Burch, Richard
  • Akiya, Nobuchika

Abstract

Disclosed is a system and method for collecting trace data of integrated circuits from the back-end assembly tools and using yield, reliability, and burn-in data to distinguish good circuit traces from bad ones. Described further is an system and method for implementing a heuristic mapping of trace data for distinguishing between good or bad traces in an Internet-based or offline application. The result of this detection can then be used for yield improvement or for burn-in reduction where for example burn-in chips having “good” circuit traces are subjected to thermal stress for less time than for chips identified as having “bad” circuit traces.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • G06F 11/00 - Error detectionError correctionMonitoring
  • G01R 31/3177 - Testing of logic operation, e.g. by logic analysers
  • G06N 20/00 - Machine learning
  • G01R 31/317 - Testing of digital circuits
  • G06N 3/04 - Architecture, e.g. interconnection topology
  • G06N 3/08 - Learning methods
  • G06N 20/10 - Machine learning using kernel methods, e.g. support vector machines [SVM]

68.

Process for making ICs from standard logic cells that utilize TS cut mask(s) and avoid DFM problems caused by closely spaced gate contacts and TSCUT jogs

      
Application Number 15712723
Grant Number 10263011
Status In Force
Filing Date 2017-09-22
First Publication Date 2019-04-16
Grant Date 2019-04-16
Owner PDF Solutions, Inc. (USA)
Inventor Haigh, Jonathan

Abstract

An improved standard cell chip, library and/or process ensures that there is adequate spacing between TSCUT jogs and nearby gate contacts to avoid inadvertent shorts/leakages that can degrade manufacturing yield or performance.

IPC Classes  ?

  • G06F 17/50 - Computer-aided design
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 27/118 - Masterslice integrated circuits

69.

Semiconductor yield prediction

      
Application Number 16112278
Grant Number 11022642
Status In Force
Filing Date 2018-08-24
First Publication Date 2019-02-28
Grant Date 2021-06-01
Owner PDF Solutions, Inc. (USA)
Inventor
  • David, Jeffrey Drue
  • Honda, Tomonori
  • Cheong, Lin Lee

Abstract

A method for predicting yield for a semiconductor process. A particular type of wafer is fabricated to have a first set of features disposed on the wafer, with a wafer map identifying a location for each of the first set of features on the wafer. Data from wafer acceptance tests and circuit probe tests is collected over time for wafers of that particular type as made in a semiconductor fabrication process, and at least one training dataset and a least one validation dataset are created from the collected data. A second set of “engineered” features are created and also incorporated onto the wafer and wafer map. Important features from the first and second sets of features are identified and selected, and using those important features as inputs, a number of different process models are run, with yield as the target. The results of the different models can be combined, for example, statistically.

IPC Classes  ?

  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • G01R 31/26 - Testing of individual semiconductor devices
  • H01L 21/66 - Testing or measuring during manufacture or treatment
  • G06N 3/08 - Learning methods

70.

Generating robust machine learning predictions for semiconductor manufacturing processes

      
Application Number 16006614
Grant Number 11029673
Status In Force
Filing Date 2018-06-12
First Publication Date 2018-12-13
Grant Date 2021-06-08
Owner PDF Solutions, Inc. (USA)
Inventor
  • Honda, Tomonori
  • Kekatpure, Rohan D.
  • David, Jeffrey Drue

Abstract

Robust machine learning predictions. Temporal dependencies of process targets for different machine learning models can be captured and evaluated for the impact on process performance for target. The most robust of these different models is selected for deployment based on minimizing variance for the desired performance characteristic.

IPC Classes  ?

  • G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM]
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • G05B 13/02 - Adaptive control systems, i.e. systems automatically adjusting themselves to have a performance which is optimum according to some preassigned criterion electric

71.

Process control techniques for semiconductor manufacturing processes

      
Application Number 15604240
Grant Number 10734293
Status In Force
Filing Date 2015-11-25
First Publication Date 2018-12-13
Grant Date 2020-08-04
Owner PDF SOLUTIONS, INC. (USA)
Inventor David, Jeffrey Drue

Abstract

Techniques for measuring and/or compensating for process variations in a semiconductor manufacturing processes. Machine learning algorithms are used on extensive sets of input data, including upstream data, to organize and pre-process the input data, and to correlate the input data to specific features of interest. The correlations can then be used to make process adjustments. The techniques may be applied to any feature or step of the semiconductor manufacturing process, such as overlay, critical dimension, and yield prediction.

IPC Classes  ?

  • H01L 21/66 - Testing or measuring during manufacture or treatment
  • G03F 7/20 - ExposureApparatus therefor
  • G06N 20/00 - Machine learning
  • G06N 7/00 - Computing arrangements based on specific mathematical models
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

72.

CIMETRIX EQUIPMENTTEST

      
Serial Number 87950502
Status Registered
Filing Date 2018-06-06
Registration Date 2019-07-30
Owner PDF SOLUTIONS, INC. ()
NICE Classes  ? 09 - Scientific and electric apparatus and instruments

Goods & Services

Computer software for testing communication interfaces on factory production equipment for compliance with industry standards and for suitability for specific factory processing scenarios

73.

CIMETRIX SAPIENCE

      
Serial Number 87948767
Status Registered
Filing Date 2018-06-05
Registration Date 2019-07-23
Owner PDF SOLUTIONS, INC. ()
NICE Classes  ? 09 - Scientific and electric apparatus and instruments

Goods & Services

Computer software that monitors, controls, stores, and displays factory manufacturing data

74.

CIMETRIX INSIGHT

      
Serial Number 87948776
Status Registered
Filing Date 2018-06-05
Registration Date 2019-07-23
Owner PDF SOLUTIONS, INC. ()
NICE Classes  ? 09 - Scientific and electric apparatus and instruments

Goods & Services

Computer software that monitors, controls, stores, and displays factory manufacturing data

75.

exensio

      
Application Number 1375527
Status Registered
Filing Date 2017-06-29
Registration Date 2017-06-29
Owner PDF Solutions, Inc. (USA)
NICE Classes  ?
  • 09 - Scientific and electric apparatus and instruments
  • 42 - Scientific, technological and industrial services, research and design

Goods & Services

Software for equipment control and data analytics of semiconductor design and manufacturing processes, and software for equipment control and data analytics of electronics design and manufacturing processes. Engineering and consulting services in the fields of technical support, namely, assisting users with use of the software and troubleshooting in the nature of diagnosing computer software and hardware problems, engineering know-how, and engineering and technological consultancy related to the best practices for the manufacturing of electronics and semiconductors; engineering and technological consulting services in the fields of yield, performance improvement, and productivity improvement in the manufacture, testing and packaging of electronics and semiconductors; cloud computing featuring an analytic software platform to access and visualize big data for decision support; platform as a service (PAAS) and software as a service (SaaS) featuring computer software platforms for business, product design, and manufacturing data analysis.

76.

Test structures for measuring silicon thickness in fully depleted silicon-on-insulator technologies

      
Application Number 15611576
Grant Number 10852337
Status In Force
Filing Date 2017-06-01
First Publication Date 2017-10-26
Grant Date 2020-12-01
Owner PDF Solutions, Inc. (USA)
Inventor
  • Saxena, Sharad
  • Brozek, Tomasz
  • Yu, Yuan
  • Pak, Mike Kyu Hyon
  • Lunenborg, Meindert Martin

Abstract

Described are test structures and methods for measuring silicon thickness in fully depleted silicon-on-insulator technologies.

IPC Classes  ?

  • G01B 7/06 - Measuring arrangements characterised by the use of electric or magnetic techniques for measuring length, width, or thickness for measuring thickness
  • G01R 27/26 - Measuring inductance or capacitanceMeasuring quality factor, e.g. by using the resonance methodMeasuring loss factorMeasuring dielectric constants
  • H01L 21/66 - Testing or measuring during manufacture or treatment

77.

Process for making semiconductor dies, chips, and wafers using non-contact measurements obtained from DOEs of NCEM-enabled fill cells on wafers that include multiple steps for enabling NC detecteion of AACNT-TS via opens

      
Application Number 15456482
Grant Number 09785496
Status In Force
Filing Date 2017-03-11
First Publication Date 2017-10-10
Grant Date 2017-10-10
Owner PDF Solutions, Inc. (USA)
Inventor
  • Lam, Stephen
  • Ciplickas, Dennis
  • Brozek, Tomasz
  • Cheng, Jeremy
  • Comensoli, Simone
  • De, Indranil
  • Doong, Kelvin
  • Eisenmann, Hans
  • Fiscus, Timothy
  • Haigh, Jonathan
  • Hess, Christopher
  • Kibarian, John
  • Lee, Sherry
  • Liao, Marci
  • Lin, Sheng-Che
  • Matsuhashi, Hideki
  • Michaels, Kimon
  • O'Sullivan, Conor
  • Rauscher, Markus
  • Rovner, Vyacheslav
  • Strojwas, Andrzej
  • Strojwas, Marcin
  • Taylor, Carl
  • Vallishayee, Rakesh
  • Weiland, Larg
  • Yokoyama, Nobuharu

Abstract

Improved processes for manufacturing semiconductor wafers, chips, or dies utilize in-line data obtained from non-contact electrical measurements (“NCEM”) of fill cells that contain structures configured to target/expose a variety of open-circuit, short-circuit, leakage, and/or excessive resistance failure modes. Such processes include evaluating one or more Designs of Experiments (“DOEs”), each comprised of multiple NCEM-enabled fill cells, in at least two variants, targeted to the same failure mode. Such DOEs include multiple means/steps for enabling non-contact (NC) detection of AACNT-TS via opens.

IPC Classes  ?

  • H01L 29/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor bodies or of electrodes thereof
  • G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • G06F 17/50 - Computer-aided design
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier

78.

exensio

      
Application Number 1363537
Status Registered
Filing Date 2017-06-29
Registration Date 2017-06-29
Owner PDF Solutions, Inc. (USA)
NICE Classes  ?
  • 09 - Scientific and electric apparatus and instruments
  • 42 - Scientific, technological and industrial services, research and design

Goods & Services

Software for equipment control and data analytics of semiconductor design and manufacturing processes, and software for equipment control and data analytics of electronics design and manufacturing processes. Engineering and consulting services in the fields of technical support, namely, assisting users with use of the software and troubleshooting in the nature of diagnosing computer software and hardware problems, engineering know-how, and best practices for the manufacturing of electronics and semiconductors; engineering and consulting services in the fields of yield, performance improvement, and productivity improvement in the manufacture test and packaging of electronics and semiconductors; cloud computing featuring an analytic software platform to access and visualize big data for decision support; platform as a service (PAAS) and software as a service (SaaS) featuring computer software platforms for business, product design, and manufacturing data analysis.

79.

EXENSIO

      
Application Number 1362007
Status Registered
Filing Date 2017-06-29
Registration Date 2017-06-29
Owner PDF Solutions, Inc. (USA)
NICE Classes  ?
  • 09 - Scientific and electric apparatus and instruments
  • 42 - Scientific, technological and industrial services, research and design

Goods & Services

Software for equipment control and data analytics of semiconductor design and manufacturing processes, and software for equipment control and data analytics of electronics design and manufacturing processes. Engineering and consulting services in the fields of technical support, namely, assisting users with use of the software and troubleshooting in the nature of diagnosing computer software and hardware problems, engineering know-how, and best practices for the manufacturing of electronics and semiconductors; engineering and consulting services in the fields of yield, performance improvement, and productivity improvement in the manufacture test and packaging of electronics and semiconductors; cloud computing featuring an analytic software platform to access and visualize big data for decision support; platform as a service (PAAS) and software as a service (SaaS) featuring computer software platforms for business, product design, and manufacturing data analysis.

80.

exensio

      
Application Number 1354439
Status Registered
Filing Date 2017-05-09
Registration Date 2017-05-09
Owner PDF Solutions, Inc. (USA)
NICE Classes  ?
  • 09 - Scientific and electric apparatus and instruments
  • 42 - Scientific, technological and industrial services, research and design

Goods & Services

Computer software for use in providing automated characterization and analysis of product chip and cell library layouts in the field of semiconductor manufacturing. Engineering and consulting services in the fields of technical support, namely, assisting users with use of the software and troubleshooting in the nature of diagnosing computer software and hardware problems, engineering know-how, and best practices for semiconductor companies; engineering and consulting services in the fields of yield, performance improvement, and productivity improvement in the manufacture test and packaging of semiconductors; cloud computing featuring an analytic software platform to access and visualize big data for decision support; platform as a service (PAAS) featuring computer software platforms for business and manufacturing data analysis and decision support.

81.

EXENSIO

      
Application Number 184473600
Status Registered
Filing Date 2017-06-27
Registration Date 2019-08-26
Owner PDF Solutions, Inc. (USA)
NICE Classes  ?
  • 09 - Scientific and electric apparatus and instruments
  • 42 - Scientific, technological and industrial services, research and design

Goods & Services

(1) Software for managing equipment control and data analytics of semiconductor design and manufacturing processes, and software for managing equipment control and data analytics of electronics design and manufacturing processes (1) Engineering and consulting services in the fields of technical support, namely, assisting users with use of the software and troubleshooting in the nature of diagnosing computer software and hardware problems, engineering know-how, and best practices for the manufacturing of electronics and semiconductors; engineering and consulting services in the fields of yield, performance improvement, and productivity improvement in the manufacture, testing and packaging of electronics and semiconductors; cloud computing featuring an analytic software platform to access and visualize big data for decision support; platform as a service (PAAS) and software as a service (SaaS) featuring computer software platforms for business, product design, and manufacturing data analysis.

82.

EXENSIO

      
Application Number 184473700
Status Registered
Filing Date 2017-06-27
Registration Date 2019-08-26
Owner PDF Solutions, Inc. (USA)
NICE Classes  ?
  • 09 - Scientific and electric apparatus and instruments
  • 42 - Scientific, technological and industrial services, research and design

Goods & Services

(1) Software for managing equipment control and data analytics of semiconductor design and manufacturing processes, and software for managing equipment control and data analytics of electronics design and manufacturing processes (1) Engineering and consulting services in the fields of technical support, namely, assisting users with use of the software and troubleshooting in the nature of diagnosing computer software and hardware problems, engineering know-how, and best practices for the manufacturing of electronics and semiconductors; engineering and consulting services in the fields of yield, performance improvement, and productivity improvement in the manufacture, testing and packaging of electronics and semiconductors; cloud computing featuring an analytic software platform to access and visualize big data for decision support; platform as a service (PAAS) and software as a service (SaaS) featuring computer software platforms for business, product design, and manufacturing data analysis.

83.

EXENSIO

      
Application Number 184473800
Status Registered
Filing Date 2017-06-27
Registration Date 2019-08-26
Owner PDF Solutions, Inc. (USA)
NICE Classes  ?
  • 09 - Scientific and electric apparatus and instruments
  • 42 - Scientific, technological and industrial services, research and design

Goods & Services

(1) Software for managing equipment control and data analytics of semiconductor design and manufacturing processes, and software for managing equipment control and data analytics of electronics design and manufacturing processes (1) Engineering and consulting services in the fields of technical support, namely, assisting users with use of the software and troubleshooting in the nature of diagnosing computer software and hardware problems, engineering know-how, and best practices for the manufacturing of electronics and semiconductors; engineering and consulting services in the fields of yield, performance improvement, and productivity improvement in the manufacture, testing and packaging of electronics and semiconductors; cloud computing featuring an analytic software platform to access and visualize big data for decision support; platform as a service (PAAS) and software as a service (SaaS) featuring computer software platforms for business, product design, and manufacturing data analysis.

84.

INTEGRATED CIRCUIT CONTAINING DOES OF NCEM-ENABLED FILL CELLS

      
Application Number US2016067050
Publication Number 2017/106575
Status In Force
Filing Date 2016-12-15
Publication Date 2017-06-22
Owner PDF SOLUTIONS, INC. (USA)
Inventor
  • Lam, Stephen
  • Ciplickas, Dennis
  • Brozek, Tomasz
  • Cheng, Jeremy
  • Comensoli, Simone
  • De, Indranil
  • Doong, Kelvin
  • Eisenmann, Hans
  • Fiscus, Timothy
  • Haigh, Jonathan
  • Hess, Christopher
  • Kibarian, John
  • Lee, Sherry
  • Liao, Marci
  • Lin, Sheng-Che
  • Matsuhashi, Hideki
  • Michaels, Kimon
  • O'Sullivan, Conor
  • Rauscher, Markus
  • Rovner, Vyacheslav
  • Strojwas, Andrzej
  • Strojwas, Marcin
  • Taylor, Carl
  • Vallishayee, Rakesh
  • Weiland, Larg
  • Yokoyama, Nobuharu

Abstract

Wafers, chips, or dies that contain fill cells with structures configured to obtain in-line data via non-contact electrical measurements ("NCEM"). Such NCEM-enabled fill cells may target/expose a variety of open-circuit, short-circuit, leakage, or excessive resistance failure modes. Such wafers, chips, or dies may include Designs of Experiments ("DOEs"), comprised of multiple NCEM-enabled fill cells, in at least two variants, all targeted to the same failure mode(s).

IPC Classes  ?

  • G06F 17/50 - Computer-aided design
  • G01N 23/00 - Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups , or
  • G01R 31/26 - Testing of individual semiconductor devices
  • H01L 21/66 - Testing or measuring during manufacture or treatment

85.

EXENSIO

      
Serial Number 87497273
Status Registered
Filing Date 2017-06-20
Registration Date 2019-01-22
Owner PDF Solutions, Inc. ()
NICE Classes  ?
  • 09 - Scientific and electric apparatus and instruments
  • 42 - Scientific, technological and industrial services, research and design

Goods & Services

Software for managing equipment control and data analytics of semiconductor design and manufacturing processes; Software for managing equipment control and data analytics of electronics design and manufacturing processes Engineering and consulting services, namely, technical support service in the nature of assisting users with use of the software and troubleshooting in the nature of diagnosing computer software and hardware problems; engineering and consulting services in the fields of testing of electronics and semiconductors; cloud computing featuring an analytic software platform to access and visualize big data for decision support; platform as a service (PAAS) and software as a service (SaaS) featuring computer software platforms for analyzing product design, and business and manufacturing data analysis

86.

EXENSIO

      
Serial Number 87497196
Status Registered
Filing Date 2017-06-20
Registration Date 2019-01-22
Owner PDF Solutions, Inc. ()
NICE Classes  ?
  • 09 - Scientific and electric apparatus and instruments
  • 42 - Scientific, technological and industrial services, research and design

Goods & Services

Software for managing equipment control and data analytics of semiconductor design and manufacturing processes; Software for managing equipment control and data analytics of electronics design and manufacturing processes Engineering and consulting services, namely, technical support service in the nature of assisting users with use of the software and troubleshooting in the nature of diagnosing computer software and hardware problems; engineering and consulting services in the fields of testing of electronics and semiconductors; cloud computing featuring an analytic software platform to access and visualize big data for decision support; platform as a service (PAAS) and software as a service (SaaS) featuring computer software platforms for analyzing product design, and business and manufacturing data analysis

87.

Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and AA-short-configured, NCEM-enabled fill cells

      
Application Number 15391018
Grant Number 09627371
Status In Force
Filing Date 2016-12-27
First Publication Date 2017-04-18
Grant Date 2017-04-18
Owner PDF Solutions, Inc. (USA)
Inventor
  • Lam, Stephen
  • Ciplickas, Dennis
  • Brozek, Tomasz
  • Cheng, Jeremy
  • Comensoli, Simone
  • De, Indranil
  • Doong, Kelvin
  • Eisenmann, Hans
  • Fiscus, Timothy
  • Haigh, Jonathan
  • Hess, Christopher
  • Kibarian, John
  • Lee, Sherry
  • Liao, Marci
  • Lin, Sheng-Che
  • Matsuhashi, Hideki
  • Michaels, Kimon
  • O'Sullivan, Conor
  • Rauscher, Markus
  • Rovner, Vyacheslav
  • Strojwas, Andrzej
  • Strojwas, Marcin
  • Taylor, Carl
  • Vallishayee, Rakesh
  • Weiland, Larg
  • Yokoyama, Nobuharu

Abstract

An IC includes logic cells, selected from a standard cell library, and fill cells, configured for compatibility with the standard logic cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The IC includes such NCEM-enabled fill cells configured to enable detection and/or measurement of a variety of open-circuit and short-circuit failure modes, including at least one via-open-related failure mode, one GATE-short-related failure mode, one GATECNT-short-related failure mode, and one AA-short-related failure mode.

IPC Classes  ?

  • G06F 17/50 - Computer-aided design
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 21/66 - Testing or measuring during manufacture or treatment
  • H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 23/528 - Layout of the interconnection structure

88.

Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and TS-short-configured, NCEM-enabled fill cells

      
Application Number 15391001
Grant Number 09627370
Status In Force
Filing Date 2016-12-27
First Publication Date 2017-04-18
Grant Date 2017-04-18
Owner PDF Solutions, Inc. (USA)
Inventor
  • Lam, Stephen
  • Ciplickas, Dennis
  • Brozek, Tomasz
  • Cheng, Jeremy
  • Comensoli, Simone
  • De, Indranil
  • Doong, Kelvin
  • Eisenmann, Hans
  • Fiscus, Timothy
  • Haigh, Jonathan
  • Hess, Christopher
  • Kibarian, John
  • Lee, Sherry
  • Liao, Marci
  • Lin, Sheng-Che
  • Matsuhashi, Hideki
  • Michaels, Kimon
  • O'Sullivan, Conor
  • Rauscher, Markus
  • Rovner, Vyacheslav
  • Strojwas, Andrzej
  • Strojwas, Marcin
  • Taylor, Carl
  • Vallishayee, Rakesh
  • Weiland, Larg
  • Yokoyama, Nobuharu

Abstract

An IC includes logic cells, selected from a standard cell library, and fill cells, configured for compatibility with the standard logic cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The IC includes such NCEM-enabled fill cells configured to enable detection and/or measurement of a variety of open-circuit and short-circuit failure modes, including at least one via-open-related failure mode, one GATE-short-related failure mode, one GATECNT-short-related failure mode, and one TS-short-related failure mode.

IPC Classes  ?

  • H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for
  • H01L 29/76 - Unipolar devices
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 21/66 - Testing or measuring during manufacture or treatment
  • H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 23/528 - Layout of the interconnection structure

89.

D flip-flop cells, with DFM-optimized M0 cuts and V0 adjacencies

      
Application Number 15259333
Grant Number 09627408
Status In Force
Filing Date 2016-09-08
First Publication Date 2017-04-18
Grant Date 2017-04-18
Owner PDF Solutions, Inc. (USA)
Inventor Haigh, Jonathan

Abstract

A library of a DFM-improved standard logic cells (including D flip-flop cells) that avoid pattern-degrading configurations in the M0 and/or V0 layer(s) is disclosed, along with wafers, chips and systems constructed from such cells.

IPC Classes  ?

  • H01L 27/118 - Masterslice integrated circuits
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • G06F 17/50 - Computer-aided design

90.

Standard cell library that includes 13-CPP and 17-CPP D flip-flop cells, with DFM-optimized M0 cuts and V0 adjacencies

      
Application Number 15134420
Grant Number 09595536
Status In Force
Filing Date 2016-04-21
First Publication Date 2017-03-14
Grant Date 2017-03-14
Owner PDF Solutions, Inc. (USA)
Inventor Haigh, Jonathan

Abstract

A library of a DFM-improved standard logic cells that avoid pattern-degrading configurations in the M0 and/or V0 layer(s), and includes 13-CPP and 17-CPP D flip-flop cells, is disclosed, along with wafers, chips and systems constructed from such cells.

IPC Classes  ?

  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
  • H01L 27/118 - Masterslice integrated circuits
  • G06F 17/50 - Computer-aided design
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

91.

Standard cell library with DFM-optimized M0 cuts

      
Application Number 15067252
Grant Number 09529954
Status In Force
Filing Date 2016-03-11
First Publication Date 2016-12-27
Grant Date 2016-12-27
Owner PDF Solutions, Inc. (USA)
Inventor Haigh, Jonathan

Abstract

A library of a DFM-improved standard logic cells that avoid pattern-degrading configurations in the M0 layer is disclosed, along with wafers, chips and systems constructed from such cells.

IPC Classes  ?

  • G06F 17/50 - Computer-aided design
  • H01L 27/118 - Masterslice integrated circuits
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier

92.

EXENSIO

      
Serial Number 87237924
Status Registered
Filing Date 2016-11-15
Registration Date 2017-09-05
Owner PDF Solutions, Inc. ()
NICE Classes  ?
  • 09 - Scientific and electric apparatus and instruments
  • 42 - Scientific, technological and industrial services, research and design

Goods & Services

Computer software for use in providing automated characterization and analysis of product chip and cell library layouts in the field of semiconductor manufacturing Engineering and consulting services in the fields of technical support, namely, assisting users with use of the software and troubleshooting in the nature of diagnosing computer software and hardware problems, engineering know-how, and best practices for semiconductor companies; engineering and consulting services in the fields of yield, performance improvement, and productivity improvement in the manufacture test and packaging of semiconductors; cloud computing featuring an analytic software platform to access and visualize big data for decision support; platform as a service (PAAS) featuring computer software platforms for business and manufacturing data analysis and decision support

93.

E-beam inspection apparatus and method of using the same on various integrated circuit chips

      
Application Number 14989743
Grant Number 09496119
Status In Force
Filing Date 2016-01-06
First Publication Date 2016-11-15
Grant Date 2016-11-15
Owner PDF Solutions, Inc. (USA)
Inventor
  • De, Indranil
  • Mankos, Marian
  • Hess, Christopher
  • Ciplickas, Dennis J.

Abstract

The present invention discloses an e-beam inspection tool, and an apparatus for detecting defects. In one aspect is described an apparatus for detecting defects that includes a dual-deflection system that moves the e-beam over the integrated circuit to each of the plurality of predetermined locations, the dual deflection system including a magnetic deflection component that provides by magnetic deflection for movement of the e-beam through a plurality of areas on the integrated circuit and an electrostatic deflection component that provides by electrostatic deflection for movement of the e-beam within each of the plurality of areas.

IPC Classes  ?

  • H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for
  • H01J 37/22 - Optical or photographic arrangements associated with the tube
  • H01J 37/285 - Emission microscopes, e.g. field-emission microscopes
  • H01J 37/147 - Arrangements for directing or deflecting the discharge along a desired path

94.

Standard cell library with DFM-optimized M0 cuts and V0 adjacencies

      
Application Number 15131020
Grant Number 09461065
Status In Force
Filing Date 2016-04-17
First Publication Date 2016-10-04
Grant Date 2016-10-04
Owner PDF Solutions, Inc. (USA)
Inventor Haigh, Jonathan

Abstract

A library of a DFM-improved standard logic cells that avoid pattern-degrading configurations in the M0 and/or V0 layer(s) is disclosed, along with wafers, chips and systems constructed from such cells.

IPC Classes  ?

  • H01L 27/118 - Masterslice integrated circuits
  • G06F 17/50 - Computer-aided design
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

95.

High-yielding standard cell library and circuits made therefrom

      
Application Number 13866487
Grant Number 09438237
Status In Force
Filing Date 2013-04-19
First Publication Date 2016-09-06
Grant Date 2016-09-06
Owner PDF Solutions, Inc. (USA)
Inventor
  • Haigh, Jonathan
  • Rovner, Vyacheslav V.

Abstract

An improved 20/22 nm standard cell library, as depicted in FIGS. 1-491, achieves surprisingly significant improvements in manufacturing yield, as compared to a commercially-used library for the same fabrication process. The invention relates to product ICs made using this library (or topologically equivalent variants thereof), as well as processes for making such product ICs using said library (or its variants).

IPC Classes  ?

  • H03K 19/177 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components arranged in matrix form
  • H03K 19/0175 - Coupling arrangementsInterface arrangements

96.

OPPORTUNISTIC PLACEMENT OF IC TEST STRUCTURES AND/OR E-BEAM TARGET PADS IN AREAS OTHERWISE USED FOR FILLER CELLS, TAP CELLS, DECAP CELLS, SCRIBE LINES, AND/OR DUMMY FILL, AS WELL AS PRODUCT IC CHIPS CONTAINING SAME

      
Application Number US2015035647
Publication Number 2015/192069
Status In Force
Filing Date 2015-06-12
Publication Date 2015-12-17
Owner PDF SOLUTIONS, INC. (USA)
Inventor
  • De, Indranil
  • Ciplickas, Dennis, J.
  • Lam, Stephen
  • Haigh, Jonathan
  • Rovner, Vyacheslav, V.
  • Hess, Christopher
  • Brozek, Tomasz, W.
  • Stroljwas, Andrezej, J.
  • Doong, Kelvin
  • Kibarian, John, K.
  • Lee, Sherry, F.
  • Michaels, Kimon, W.
  • Strojwas, Marcin, A.
  • O'Sullivan, Conor
  • Jain, Mehul

Abstract

Product ICs/wafers include additional diagnostic, test, or monitoring structures opportunistically placed in filler cell positions, within tap cells, within decap cells, within scribe line areas, and/or within dummy fill regions. Improved fabrication processes utilize data from such structure (s) in wafer disposition decisions, rework decisions, process control, yield learning, or fault diagnosis.

IPC Classes  ?

  • H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for

97.

SECUREWISE

      
Application Number 014185185
Status Registered
Filing Date 2015-05-29
Registration Date 2015-10-02
Owner PDF Solutions, Inc. (USA)
NICE Classes  ? 09 - Scientific and electric apparatus and instruments

Goods & Services

Software applications for the secure transport of production data and collaboration information from within a facility to either an external partner or to an internal application or user; computer software data transmission security tools to prevent the interception of sensitive data.

98.

EPROBE

      
Serial Number 86613977
Status Registered
Filing Date 2015-04-29
Registration Date 2016-10-25
Owner PDF Solutions, Inc., ()
NICE Classes  ? 09 - Scientific and electric apparatus and instruments

Goods & Services

Semiconductor capital equipment, namely, an electron beam inspection and metrology tool

99.

EPROBE

      
Serial Number 86613106
Status Registered
Filing Date 2015-04-28
Registration Date 2016-10-25
Owner PDF Solutions, Inc. ()
NICE Classes  ? 09 - Scientific and electric apparatus and instruments

Goods & Services

Semiconductor capital equipment, namely, an electron beam inspection and metrology tool

100.

EXENSIO

      
Serial Number 86597562
Status Registered
Filing Date 2015-04-14
Registration Date 2016-08-16
Owner PDF Solutions, Inc. ()
NICE Classes  ?
  • 09 - Scientific and electric apparatus and instruments
  • 42 - Scientific, technological and industrial services, research and design

Goods & Services

Computer software for use in providing automated characterization and analysis of product chip and cell library layouts in the field of semiconductor manufacturing Engineering and consulting services in the fields of technical support, namely providing technical advice related to the manufacture of semiconductors and troubleshooting in the nature of diagnosing computer software and hardware problems, engineering know-how, and the formulation of best practices for semiconductor companies; Engineering and consulting services in the field of design and development of engineering processes, namely, yield improvement, performance improvement, and productivity improvement of the manufacturing, testing and packaging of semiconductors; cloud computing featuring an analytic software platform to access and visualize big data for decision support; platform as a service (PAAS) featuring computer software platforms for business and manufacturing data analysis and decision support
  1     2        Next Page