Abstract

In an embodiment an integrated device includes a first physical unclonable function module configured to generate an initial data group and management module configured to generate an output data group from at least the initial data group, authorize only D successive deliveries of the output data group on a first output interface of the device, D being a non-zero positive integer, and prevent any new generation of the output data group.

IPC Classes  ?

• H03K 19/17768 - Structural details of configuration resources for security
• H03K 19/08 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using semiconductor devices
• H03K 19/1776 - Structural details of configuration resources for memories

Goods & Services

Chips being integrated circuits; electric or electronic components, namely semiconductors; electronic circuits; microcircuits; integrated circuits; smart integrated circuits; integrated circuits chips being integrated circuits; printed electronic circuits being electronic circuit cards, boards, micromodules, smart cards, for integrated circuit apparatus and cards bearing integrated circuits; electrical or electronic circuits, namely protection circuits being circuit overload protector devices; electric or electronic components, namely chips being integrated circuits related to contactless payment; electric or electronic components, namely chips being integrated circuits related to contactless financial transactions; electric or electronic components, namely semiconductors related to contactless financial transactions; electric or electronic components, namely chips being integrated circuits related to contactless financial transactions; electric or electronic components, namely chips being integrated circuits; near-field communication technology chips being integrated circuits; near-field communication technology chips being integrated circuits used in the field of contactless payment solution; near-field communication technology chips being integrated circuits used in the field of contactless financial transactions; near-field communication technology chips being integrated circuits used in the field of mobile ticketing; cryptography software being preloaded, namely, recorded and downloadable software for generating cryptographic keys for receiving and spending fiat and crypto currency; secure integrated circuits; Software solution in the field of contactless financial transactions, namely preloaded, namely, recorded and downloadable software for processing, securing, and managing payment transactions and ensuring user authentication; Software solution in the field of contactless payment transactions, namely preloaded, namely, recorded and downloadable software for processing, securing, and managing payment transactions and ensuring user authentication; preloaded, namely, recorded and downloadable software for processing, securing, and managing payment transactions and ensuring user authentication; preloaded, namely, recorded and downloadable software for processing payment applications and performing user authentication; software applications, namely preloaded, namely, recorded and downloadable software for processing payment applications and performing user authentication Engineering services in the field of contactless payment solution; engineering services in the field of financial transactions; design of chips being integrated circuits for others; design of chips being integrated circuits related to contactless payment solution; design of near-field communication technology chips being integrated circuits; design of software solutions in the field of contactless payment solution; data encryption services

Goods & Services

Microcontrollers with embedded operating system software; downloadable computer software development tools; downloadable middleware for software application integration; microcontrollers. Software design and development; Providing technical support services, namely, troubleshooting of computer software problems relating to software design and programming.

Abstract

A device include on-board memory, an applications processor, a digital signal processor (DSP) cluster, a configurable accelerator framework (CAF), and a communication bus architecture. The communication bus communicatively couples the applications processor, the DSP cluster, and the CAF to the on-board memory. The CAF includes a reconfigurable stream switch and data volume sculpting circuitry, which has an input and an output coupled to the reconfigurable stream switch. The data volume sculpting circuitry receives a series of frames, each frame formed as a two dimensional (2D) data structure, and determines a first dimension and a second dimension of each frame of the series of frames. Based on the first and second dimensions, the data volume sculpting circuitry determines for each frame a position and a size of a region-of-interest to be extracted from the respective frame, and extracts from each frame, data in the frame that is within the region-of-interest.

IPC Classes  ?

• G06T 7/62 - Analysis of geometric attributes of area, perimeter, diameter or volume
• G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
• G06F 16/901 - IndexingData structures thereforStorage structures
• G06F 18/22 - Matching criteria, e.g. proximity measures
• G06N 3/045 - Combinations of networks
• G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
• G06N 3/08 - Learning methods
• G06T 7/11 - Region-based segmentation
• G06T 15/08 - Volume rendering
• G06V 10/82 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using neural networks
• G06V 20/00 - ScenesScene-specific elements
• G06V 10/75 - Organisation of the matching processes, e.g. simultaneous or sequential comparisons of image or video featuresCoarse-fine approaches, e.g. multi-scale approachesImage or video pattern matchingProximity measures in feature spaces using context analysisSelection of dictionaries

Abstract

An integrated circuit includes a reconfigurable stream switch and an arithmetic circuit. The stream switch, in operation, streams data. The arithmetic circuit has a plurality of inputs coupled to the reconfigurable stream switch. In operation, the arithmetic circuit generates an output according to AX+BY+C, where A, B and C are vector or scalar constants, and X and Y are data streams streamed to the arithmetic circuit through the reconfigurable stream switch.

IPC Classes  ?

• G06F 17/11 - Complex mathematical operations for solving equations
• G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
• G06N 3/045 - Combinations of networks
• G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
• G06N 3/08 - Learning methods
• G06N 20/00 - Machine learning

Abstract

A method includes receiving, at a master agent, announcements from candidate consumer agents indicating the presence of the candidate consumer agents. Each announcement includes display parameters for a display of the corresponding candidate consumer agent. The method further includes receiving at the master agent content parameters from a producer agent, the content parameters defining characteristics of content to be provided by the consumer agent. A mosaic screen is configured based on the received announcements and the content parameters. This configuring of the mosaic screen includes selecting ones of the consumer agents for which an announcement was received and generating content distribution parameters based on the content parameters and the display parameters of the selected ones of the consumer agents. The generated content distribution parameters are provided to the consumer agent.

IPC Classes  ?

• G06F 3/14 - Digital output to display device
• G01P 1/07 - Indicating devices, e.g. for remote indication
• G06F 3/12 - Digital output to print unit

Abstract

The present disclosure is directed to a circuit layout of a dual port static random-access-memory (SRAM) cell. The memory cell includes active regions in a substrate, with polysilicon gate electrodes on the active regions to define transistors of the memory cell. The eight transistor (8T) memory cell layout includes a reduced aspect ratio and non-polysilicon bit line discharge path routing by positioning an active region for the first port opposite an active region for the second port and consolidating power line nodes at a central portion of the memory cell.

IPC Classes  ?

• G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• H10B 10/00 - Static random access memory [SRAM] devices
• G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
• G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
• G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
• G11C 11/417 - Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type

Abstract

In an embodiment a non-volatile memory device includes a memory plane including at least one memory area including an array of memory cells having two rows and N columns, wherein each memory cell comprises a state transistor having a control gate and a floating gate selectable by a vertical selection transistor buried in a substrate and including a buried selection gate, and wherein each column of memory cells includes a pair of twin memory cells, two selection transistors of the pair of twin memory cells having a common selection gate and a processing device configured to store in the memory area information including a succession of N bits so that, with exception of the last bit of the succession, a current bit of the succession is stored in two memory cells located on the same row and on two adjacent columns and a current bit and the following bit are respectively stored in two twin cells.

IPC Classes  ?

• G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
• G11C 16/08 - Address circuitsDecodersWord-line control circuits
• G11C 16/10 - Programming or data input circuits
• G11C 16/26 - Sensing or reading circuitsData output circuits
• H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND

Abstract

In an embodiment an integrated device includes a first physical unclonable function module configured to generate an initial data group and management module configured to generate an output data group from at least the initial data group, authorize only D successive deliveries of the output data group on a first output interface of the device, D being a non-zero positive integer, and prevent any new generation of the output data group.

IPC Classes  ?

• H03K 19/17768 - Structural details of configuration resources for security
• H03K 19/08 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using semiconductor devices
• H03K 19/1776 - Structural details of configuration resources for memories
• H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system

Abstract

A method includes receiving a plurality of digital feedback signals from a voltage converter, controlling the voltage converter based upon a user desired brightness level and the plurality of digital feedback signals, the voltage converter receiving input from a DC voltage bus and providing output to drive a lighting load, and receiving a plurality of feedback signals from a power factor correction circuit that receives a rectified mains voltage and provides output to the DC voltage bus, and based thereupon operating the power factor correction circuit in transition mode or discontinuous mode based upon the user desired brightness level and a threshold brightness. The plurality of feedback signals include an input sense signal that is a function of the rectified mains voltage as drawn by the power factor correction circuit and an output sense signal that is a function of the output provided to the DC voltage bus.

IPC Classes  ?

• H05B 45/355 - Power factor correction [PFC]Reactive power compensation
• H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• H02M 1/42 - Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
• H05B 45/18 - Controlling the intensity of the light using temperature feedback
• H05B 45/375 - Switched mode power supply [SMPS] using buck topology
• H05B 45/44 - Details of LED load circuits with an active control inside an LED matrix
• H02M 1/00 - Details of apparatus for conversion

Abstract

A sensor package includes a first die having a capacitor sensor that includes an active sensing portion and a shield surrounding the active sensing portion. The sensor package further includes a second die that includes a voltage regulator configured to produce a shield voltage and a compensation circuit configured to produce a compensation signal. The voltage regulator and the compensation circuit are electrically coupled to the shield. The voltage regulator is configured to regulate the shield to the shield voltage and the compensation signal produced by the compensation circuit is configured to reduce an interference signal on the shield voltage. The compensation circuit includes one or more coupling capacitors that may be programmable capacitor arrays and calibration methodology entails selecting capacitance values for the programmable capacitor arrays that minimizes the error on an output signal of the sensor package.

IPC Classes  ?

• G01D 5/24 - Mechanical means for transferring the output of a sensing memberMeans for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for convertingTransducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying capacitance
• G01P 15/125 - Measuring accelerationMeasuring decelerationMeasuring shock, i.e. sudden change of acceleration by making use of inertia forces with conversion into electric or magnetic values by capacitive pick-up
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
• G05F 1/46 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC
• H03K 3/037 - Bistable circuits

Abstract

A diode and method of design the layout of the same having reduced parasitic capacitance is disclosed. In particular, the diode for providing fast response protection of an RF circuit from a high power noise event, such as an ESD, voltage spike, power surge or other noise is disclose. The parasitic capacitance in disclosed circuit is a greatly reduced compared to the prior art, thus significantly increasing the speed of the response to dissipate all high power noise events.

IPC Classes  ?

• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
• H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
• H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect

Abstract

The present disclosure is directed to a circuit layout of a dual port static random-access-memory (SRAM) cell. The memory cell includes active regions in a substrate, with polysilicon gate electrodes on the active regions to define transistors of the memory cell. The eight transistor (8T) memory cell layout includes a reduced aspect ratio and non-polysilicon bit line discharge path routing by positioning an active region for the first port opposite an active region for the second port and consolidating power line nodes at a central portion of the memory cell.

IPC Classes  ?

• G11C 11/00 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor
• H01L 27/11 - Static random access memory structures
• G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
• G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
• G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
• G11C 11/417 - Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type

Abstract

A reference current generator circuit generating a reference current that is proportional to absolute temperature as a function of a difference between bias voltages of first and second transistors. A voltage generator generates an input voltage from the reference current by applying the reference current that is proportional to absolute temperature through a plurality of transistors coupled in series between the bias voltage of the second transistor and ground, with the input voltage being generated at a node between given adjacent ones of the plurality of transistors. The input voltage is complementary to absolute temperature. A differential amplifier is biased by a current derived from the reference current and generates a temperature insensitive output reference voltage from the input voltage and a voltage proportional to absolute temperature.

IPC Classes  ?

• G05F 3/26 - Current mirrors

Abstract

The present disclosure is directed to a lead frame design that includes a copper alloy base material coated with an electroplated copper layer, a precious metal, and an adhesion promotion compound. The layers compensate for scratches or surface irregularities in the base material while promoting adhesion from the lead frame to the conductive connectors, and to the encapsulant by coupling them to different layers of a multilayer coating on the lead frame. The first layer of the multilayer coating is a soft electroplated copper to smooth the surface of the base material. The second layer of the multilayer coating is a thin precious metal to facilitate a mechanical coupling between leads of the lead frame and conductive connectors. The third layer of the multilayer coating is the adhesion promotion compound for facilitating a mechanical coupling to an encapsulant around the lead frame.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• C25D 3/38 - ElectroplatingBaths therefor from solutions of copper
• C25D 5/10 - Electroplating with more than one layer of the same or of different metals
• C25D 5/48 - After-treatment of electroplated surfaces
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/495 - Lead-frames
• C25D 5/00 - Electroplating characterised by the processPretreatment or after-treatment of workpieces
• C25D 7/00 - Electroplating characterised by the article coated

Abstract

X−1); and M switches associated with the M resistors. Each of the M resistors is between a first node and its associated one of the M switches. Each of the M switches couples its associated one of the M resistors to a second node.

IPC Classes  ?

• H01C 17/26 - Apparatus or processes specially adapted for manufacturing resistors adapted for trimming by converting resistive material
• H01L 21/66 - Testing or measuring during manufacture or treatment

Abstract

A method includes receiving, at a master agent, announcements from candidate consumer agents indicating the presence of the candidate consumer agents. Each announcement includes display parameters for a display of the corresponding candidate consumer agent. The method further includes receiving at the master agent content parameters from a producer agent, the content parameters defining characteristics of content to be provided by the consumer agent. A mosaic screen is configured based on the received announcements and the content parameters. This configuring of the mosaic screen includes selecting ones of the consumer agents for which an announcement was received and generating content distribution parameters based on the content parameters and the display parameters of the selected ones of the consumer agents. The generated content distribution parameters are provided to the consumer agent.

IPC Classes  ?

• G06F 3/14 - Digital output to display device
• G01P 1/07 - Indicating devices, e.g. for remote indication

Abstract

A distributed computing system for artificial intelligence in autonomously appreciating a circumstance context of a smart device. Raw context data is detected by sensors associated with the smart device. The raw context data is pre-processed by the smart device and then provided to a cloud based server for further processing. At the cloud based server, various sets of feature data are obtained from the pre-processed context data. The various sets of feature data are compared with corresponding classification parameters to determine a classification of a continuous event and/or a classification of transient event, if any, which occur in the context. The determined classification of the continuous event and the transient event will be used to autonomously configure the smart device or another related smart device to fit the context.

IPC Classes  ?

• G06F 1/16 - Constructional details or arrangements
• H04W 4/029 - Location-based management or tracking services
• G06N 20/10 - Machine learning using kernel methods, e.g. support vector machines [SVM]
• G10L 21/10 - Transforming into visible information
• G06K 9/62 - Methods or arrangements for recognition using electronic means
• G01P 15/00 - Measuring accelerationMeasuring decelerationMeasuring shock, i.e. sudden change of acceleration
• G01P 15/18 - Measuring accelerationMeasuring decelerationMeasuring shock, i.e. sudden change of acceleration in two or more dimensions
• H04W 4/50 - Service provisioning or reconfiguring
• G06F 3/0346 - Pointing devices displaced or positioned by the userAccessories therefor with detection of the device orientation or free movement in a 3D space, e.g. 3D mice, 6-DOF [six degrees of freedom] pointers using gyroscopes, accelerometers or tilt-sensors
• G10L 25/51 - Speech or voice analysis techniques not restricted to a single one of groups specially adapted for particular use for comparison or discrimination
• G06F 3/01 - Input arrangements or combined input and output arrangements for interaction between user and computer
• H04M 1/72454 - User interfaces specially adapted for cordless or mobile telephones with means for adapting the functionality of the device according to specific conditions according to context-related or environment-related conditions
• G10L 25/78 - Detection of presence or absence of voice signals
• H04W 4/38 - Services specially adapted for particular environments, situations or purposes for collecting sensor information
• H04L 67/12 - Protocols specially adapted for proprietary or special-purpose networking environments, e.g. medical networks, sensor networks, networks in vehicles or remote metering networks

Abstract

A device include on-board memory, an applications processor, a digital signal processor (DSP) cluster, a configurable accelerator framework (CAF), and at least one communication bus architecture. The communication bus communicatively couples the applications processor, the DSP cluster, and the CAF to the on-board memory. The CAF includes a reconfigurable stream switch and data volume sculpting circuitry, which has an input and an output coupled to the reconfigurable stream switch. The data volume sculpting circuitry receives a series of frames, each frame formed as a two dimensional (2D) data structure, and determines a first dimension and a second dimension of each frame of the series of frames. Based on the first and second dimensions, the data volume sculpting circuitry determines for each frame a position and a size of a region-of-interest to be extracted from the respective frame, and extracts from each frame, data in the frame that is within the region-of-interest.

IPC Classes  ?

• G06T 7/62 - Analysis of geometric attributes of area, perimeter, diameter or volume
• G06T 7/11 - Region-based segmentation
• G06T 15/08 - Volume rendering
• G06F 16/901 - IndexingData structures thereforStorage structures
• G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
• G06K 9/62 - Methods or arrangements for recognition using electronic means
• G06N 3/08 - Learning methods
• G06N 3/04 - Architecture, e.g. interconnection topology
• G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
• G06V 20/00 - ScenesScene-specific elements
• G06V 10/82 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using neural networks
• G06V 10/75 - Organisation of the matching processes, e.g. simultaneous or sequential comparisons of image or video featuresCoarse-fine approaches, e.g. multi-scale approachesImage or video pattern matchingProximity measures in feature spaces using context analysisSelection of dictionaries

Abstract

In an integrated circuit supporting complementary metal oxide semiconductor (CMOS) integrated circuits, latch-up immunity is supported by surrounding a hot n-well with an n-well strap spaced from the hot n-well by a specified distance in accordance with design rules. The n-well strap is positioned between the hot n-well and other n-well or n-type diffusion structures.

IPC Classes  ?

• H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
• H01L 27/11 - Static random access memory structures
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/74 - Thyristor-type devices, e.g. having four-zone regenerative action
• H01L 27/118 - Masterslice integrated circuits

Abstract

A LED driving circuit includes a power factor correction circuit receiving a rectified mains voltage and providing output to a DC voltage bus, a string of LEDs connected in series, a voltage converter receiving input from the DC voltage bus and providing output to the string of LEDs, and a microcontroller. The microcontroller receives a plurality of digital feedback signals from the voltage converter, controls the voltage converter based upon a user desired brightness level and the plurality of digital feedback signals, and receive a plurality of feedback signals from the power factor correction circuit. Based on the plurality of feedback signals, the microcontroller operates the power factor correction circuit in transition mode where the user desired brightness level is above a threshold brightness, and operates the power factor correction circuit in discontinuous mode where the user desired brightness level is below the threshold brightness.

IPC Classes  ?

• H05B 45/18 - Controlling the intensity of the light using temperature feedback
• H05B 45/355 - Power factor correction [PFC]Reactive power compensation
• H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• H02M 1/42 - Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
• H05B 45/44 - Details of LED load circuits with an active control inside an LED matrix
• H05B 45/375 - Switched mode power supply [SMPS] using buck topology
• H02M 1/00 - Details of apparatus for conversion

Abstract

Embodiments are directed towards a method to create a reconfigurable interconnect framework in an integrated circuit. The method includes accessing a configuration template directed toward the reconfigurable interconnect framework, editing parameters of the configuration template, functionally combining the configuration template with a plurality of modules from an IP library to produce a register transfer level (RTL) circuit model, generating at least one automated test-bench function, and generating at least one logic synthesis script. Editing parameters of the configuration template includes confirming a first number of output ports of a reconfigurable stream switch and confirming a second number of input ports of the reconfigurable stream switch. Each output port and each input port has a respective architectural composition. The output port architectural composition is defined by a plurality of N data paths including A data outputs and B control outputs. The input port architectural composition is defined by a plurality of M data paths including A data inputs and B control inputs.

IPC Classes  ?

• G06F 30/327 - Logic synthesisBehaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• G06N 20/10 - Machine learning using kernel methods, e.g. support vector machines [SVM]
• G06N 3/084 - Backpropagation, e.g. using gradient descent
• G06F 30/34 - Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• G06N 20/00 - Machine learning
• G06N 3/044 - Recurrent networks, e.g. Hopfield networks
• G06N 3/045 - Combinations of networks
• G06N 3/047 - Probabilistic or stochastic networks
• G06N 3/04 - Architecture, e.g. interconnection topology
• G06N 3/08 - Learning methods
• G06F 115/08 - Intellectual property [IP] blocks or IP cores
• G06N 7/01 - Probabilistic graphical models, e.g. probabilistic networks
• G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
• G06F 9/445 - Program loading or initiating
• G06F 13/40 - Bus structure
• G06F 15/78 - Architectures of general purpose stored program computers comprising a single central processing unit

Abstract

Electrostatic discharge (ESD) protection is provided in using a supply clamp circuit using an ESD event actuated MOSFET device. Triggering of the MOSFET device is made at both the gate terminal and the substrate (back gate) terminal. Additionally, the MOSFET device can be formed of cascoded MOSFETs.

IPC Classes  ?

• H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier

Abstract

A voltage doubler circuit supports operation in both a positive voltage boosting mode to positively boost voltage from a first node to a second node and a negative voltage boosting mode to negatively boost voltage from the second node to the first node. The voltage doubler circuit is formed by transistors of a same conductivity type that share a common bulk that is not tied to a source of any of the voltage doubler circuit transistors. A bias generator circuit is coupled to receive a first voltage from the first node and second voltage from the second node. The bias generator circuit operates to apply a lower one of the first and second voltages to the common bulk.

IPC Classes  ?

• H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
• H03K 19/096 - Synchronous circuits, i.e. using clock signals
• G05F 1/10 - Regulating voltage or current

Abstract

A method is for operating an electronic device formed by a low dropout regulator (LDO) having an output coupled to a first conduction terminal of a transistor, with a second conduction terminal of the transistor being coupled to an output node. The electronic device is turned on by turning on the LDO, removing a DC bias from the second conduction terminal of the transistor by opening a first switch that selectively couples the second conduction terminal of the transistor to a supply node through a first diode coupled transistor and by opening a second switch that selectively couples the second conduction terminal of the transistor to a ground node through a second diode coupled transistor, and turning on the transistor. The electronic device is turned off by turning off the transistor, forming the DC bias at the second conduction terminal of the transistor, and turning off the LDO.

IPC Classes  ?

• G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
• G05F 1/46 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC
• G05F 1/613 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in parallel with the load as final control devices
• G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices

Abstract

A method is provided to access a data storage memory that stores data signals in a plurality of indexed memory locations. An access control circuit receives a memory access request signals from a processing circuit. The method includes replicating the respective memory access request signals to provide for each a respective replicated memory access request signal, accessing indexed internal memory locations to retrieve a first data signal retrieved as a function of the respective memory access request signal and a second data signal retrieved as a function of the respective replicated memory access request signal, and checking for identity the first data signal and the at least one second data signal. The access control circuit transmits to the processing circuit a data signal or an integrity error flag signal as a result of the identity check.

IPC Classes  ?

• G06F 12/14 - Protection against unauthorised use of memory
• G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
• G06F 13/40 - Bus structure
• H04L 9/40 - Network security protocols

Abstract

The present disclosure provides supports for microfluidic die that allow for nozzles of the microfluidic die to be on a different plane or face a different direction from electrical contacts on the same support. This includes a rigid support having electrical contacts on a different side of the rigid support with respect to a direction of ejection of the nozzles, and a semi-flexible support or semi-rigid support that allow the electrical contacts to be moved with respect to a direction of ejection of the nozzles. The semi-flexible and semi-rigid supports allow the die to be up to and beyond a 90 degree angle with respect to a plane of the electrical contacts. The different supports allow for a variety of positions of the microfluidic die with respect to a position of the electrical contacts.

IPC Classes  ?

• B41J 2/14 - Structure thereof
• B41J 2/175 - Ink supply systems

Goods & Services

Electric or electronic components, namely, semiconductors, semiconductor devices, electronic circuits, micro-circuits, integrated circuits, smart integrated circuits; integrated circuit chips; semiconductor chips; discrete semiconductor modules; semiconductor substrates in the nature of semiconductor wafers; semiconductor inverters; semiconductor drivers; semiconductor sensors; semiconductor transistors

Abstract

A system on a chip (SoC) includes a plurality of processing cores and a stream switch coupled to two or more of the plurality of processing cores. The stream switch includes a plurality of N multibit input ports, wherein N is a first integer, a plurality of M multibit output ports, wherein M is a second integer, and a plurality of M multibit stream links dedicated to respective output ports of the plurality of M multibit output ports. The M multibit stream links are reconfigurably coupleable at run time to a selectable number of the N multibit input ports, wherein the selectable number is an integer between zero and N.

IPC Classes  ?

• G02B 6/35 - Optical coupling means having switching means
• G06F 30/327 - Logic synthesisBehaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• G06N 20/10 - Machine learning using kernel methods, e.g. support vector machines [SVM]
• G06N 3/04 - Architecture, e.g. interconnection topology
• G06N 3/08 - Learning methods
• G06F 30/34 - Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• G06N 20/00 - Machine learning
• G06N 7/00 - Computing arrangements based on specific mathematical models
• G06F 115/08 - Intellectual property [IP] blocks or IP cores
• G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
• G06F 9/445 - Program loading or initiating
• G06F 13/40 - Bus structure
• G06F 15/78 - Architectures of general purpose stored program computers comprising a single central processing unit

Goods & Services

Electric or electronic components, namely, semiconductors, semiconductor devices, electronic circuits, micro-circuits, integrated circuits, smart integrated circuits, microprocessors, microcontrollers and embedded microprocessors

Goods & Services

Electric or electronic components, namely, semiconductors, semiconductor devices, electronic circuits, micro-circuits, integrated circuits, smart integrated circuits, microprocessors, microcontrollers and embedded microprocessors

Goods & Services

Electric or electronic components, namely, semiconductors, semiconductor devices, electronic circuits, micro-circuits, integrated circuits, smart integrated circuits, microprocessors, microcontrollers and embedded microprocessors

Abstract

A row decoder located on one side of a memory array selectively drives word lines in response to a row address. A word line fault detection circuit located on an opposite side of the first memory array operates to detect an open word line fault between the opposed sides of the memory array. The word line fault detection circuit includes a first clamp circuit that operates to clamp the word lines to ground. An encoder circuit encodes signals on the word lines to generate an encoded address. The encoded address is compared to the row address by a comparator circuit which sets an error flag indicating the open word line fault has been detected if the encoded address does not match the row address.

IPC Classes  ?

• G11C 29/38 - Response verification devices
• G11C 29/44 - Indication or identification of errors, e.g. for repair
• G11C 8/10 - Decoders

Abstract

A clock signal is generated with an oscillator. A crystal oscillator core within the oscillator circuit is switched on to produce first and second oscillation signals that are approximately opposite in phase. When a difference between a voltage of the first oscillation signal and a voltage of the second oscillation signal exceeds an upper threshold range, the crystal oscillator core is switched off. When the difference between the voltage of the first oscillation signal and the voltage of the second oscillation signal falls below the upper threshold range, the crystal oscillator core is switched back on. This operation is repeated so as to produce the clock signal.

IPC Classes  ?

• H03B 5/36 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator active element in amplifier being semiconductor device
• H03B 5/06 - Modifications of generator to ensure starting of oscillations

Abstract

A charge pump circuit generates a charge pump output signal at a first node and is enabled by a control signal. A diode has an anode coupled to the first node and a cathode coupled to a second node. A current mirror arrangement sources a first current to the second node and sinks a second current from a third node. A comparator causes the control signal to direct the charge pump circuit to generate the charge pump output signal as having a voltage that ramps upwardly in magnitude (but negative in sign) if the voltage at the second node is greater than the voltage at the third node, and causes the control signal to direct the charge pump circuit to cease the ramping of the voltage of the charge pump output signal if the voltage at the second node is at least equal to the voltage at the third node.

IPC Classes  ?

• H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode

Abstract

A charge pump circuit generates a charge pump output signal at a first node and is enabled by a charge pump control signal. A diode has first and second terminals coupled to first and second nodes. A comparator has an inverting input coupled to the second node and a non-inverting input coupled to a third node, and causes generation of the charge pump control signal. A first current mirror produces a first current at the second node, and a second current mirror produces a second current (equal in magnitude to the first current) at the third node. The first terminal and second terminals may be a cathode and an anode. The first current mirror may be a current sink sinking a first current from the second node. The second current mirror may be current source sourcing a second current (equal in magnitude to the first current) to the third node.

IPC Classes  ?

• H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
• G11C 16/30 - Power supply circuits
• G11C 5/14 - Power supply arrangements

Abstract

A decoder decodes a memory address and selectively drives a select line (such as a word line or mux line) of a memory. An encoding circuit encodes the data on select lines to generate an encoded address. The encoded address and the memory address are compared by a comparison circuit to generate a test result signal which is indicative of whether the decoder is operating properly. To test the comparison circuit for proper operation, a subset of an MBIST scan routine causes the encoded address to be blocked from the comparison circuit and a force signal to be applied in its place. A test signal from the scan routine and the force signal are then compared by the comparison circuit, with the test result signal generated from the comparison being indicative of whether the comparison circuit itself is operating properly.

IPC Classes  ?

• G11C 29/38 - Response verification devices
• G11C 29/14 - Implementation of control logic, e.g. test mode decoders

Goods & Services

Apparatus for data and information authentication, namely, computer hardware being security modules embedded in consumer, commercial, industrial, medical, electronic devices used in systems like gaming, mobile phone accessories, computers, computer accessories, consumer good and consumer goods accessories, gateways, printers, pcb parts, smart computer, communication networks smart grids and home automation allowing the protection, availability, confidentiality and integrity of data; electric and electronic components for computers; semiconductors; integrated circuits; microprocessors; microcontrollers; embedded microprocessors; integrated circuit cards; integrated circuit chips; printed electronic circuits for integrated circuit apparatus and cards bearing integrated circuits; computer memory devices Engineering services in the field of semiconductors and integrated circuits; design of semiconductors and integrated circuits for others; design, development and update of secure computer firmware

Abstract

A voltage regulator includes an error amplifier producing an error voltage from a reference voltage and a feedback voltage. A voltage-to-current converter converts the error voltage to an output current, and a feedback resistance generates the feedback voltage from the output current. The error amplifier includes a differential pair of transistors receiving the feedback voltage and the reference voltage, a first pair of transistors operating in saturation and coupled to the differential pair of transistors at an output node and a bias node, a second pair of transistors operating in a linear region and coupled to the first pair of transistors at a pair of intermediate nodes. A compensation capacitor is coupled to one of the pair of intermediate nodes so as to compensate the error amplifier for a parasitic capacitance. An output at the output node is a function of a difference between the reference voltage and feedback voltage.

IPC Classes  ?

• G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
• H03F 3/16 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only with field-effect devices
• H03F 3/45 - Differential amplifiers
• G05F 3/26 - Current mirrors

Abstract

An oscillator circuit powered by a source voltage generates an oscillating output signal. The oscillating output signal is level shifted and applied to a first input of a multiplexer. A second input of the multiplexer receives the oscillating output signal. The multiplexer selects one of the oscillating output signal and the level shifted oscillating output signal for output as a selected oscillating output signal in response to a select signal. A locked loop circuit generates controls a frequency of the oscillating output signal as a function of the selected oscillating output signal and a reference oscillating signal. The select signal further selects one of a reference voltage and the source voltage of the oscillator circuit as an error amplifier reference voltage for a voltage regulator circuit that generates the first power supply voltage.

IPC Classes  ?

• H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
• H03L 7/10 - Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
• H03L 7/087 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop

Abstract

A continuous time Delta-Sigma (CT-ΔΣ) modulator has an input node configured to receive an input signal and an output node configured to output a digital output signal. The CT-ΔΣ modulator includes a feedback loop with a summation circuit configured to sum the digital output signal with a jitter perturbed test signal to generate a signal supplied to an input of a digital to analog converter circuit. A single tone signal is injected with a jitter error of a clock signal to generate the jitter perturbed test signal. A processing circuit processes the digital output signal to detect a signal to noise ratio of the CT-ΔΣ modulator. The detected signal to noise ratio is indicative of presence of jitter in the clock signal.

IPC Classes  ?

• H03M 3/00 - Conversion of analogue values to or from differential modulation
• G06F 1/10 - Distribution of clock signals
• H03K 3/037 - Bistable circuits

Abstract

An RFID transponder includes a coding and modulation unit that generates a transmission signal by modulating an oscillator signal with an encoded bit signal. During a first and a second time segment, the encoded bit signal assumes a first and a second logic level, respectively. The transmission signal includes a first signal pulse having a first phase within the first time segment and a second signal pulse having a second phase that is shifted with respect to the first phase by a predefined phase difference within the second time segment. The transmission signal is paused for a pause period between the first and the second signal pulse. The pause period is shorter than a mean value of a period of the first time segment and a period of the second time segment.

IPC Classes  ?

• H04B 5/00 - Near-field transmission systems, e.g. inductive or capacitive transmission systems
• G06K 7/00 - Methods or arrangements for sensing record carriers
• G06K 19/07 - Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards with integrated circuit chips
• G06K 19/077 - Constructional details, e.g. mounting of circuits in the carrier

Abstract

An integrated circuit die has a peripheral edge and a seal ring extending along the peripheral edge and surrounding a functional integrated circuit area. A test logic circuit located within the functional integrated circuit area generates a serial input data signal for application to a first end of a sensing conductive wire line extending around the seal ring between the seal ring and the peripheral edge of the integrated circuit die. Propagation of the serial input data signal along the sensing conductive wire line produces a serial output data signal at a second end of the sensing conductive wire line. The test logic circuit compares data patterns of the serial input data signal and serial output data signal to detect damage at the peripheral edge of the integrated circuit die.

IPC Classes  ?

• G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
• H05K 1/02 - Printed circuits Details
• H01L 21/66 - Testing or measuring during manufacture or treatment
• H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections

Abstract

A method of quickly locking a locked loop includes generating an intermediate reference signal having an intermediate reference frequency between a desired output frequency and a reference frequency of a reference signal, and setting an output frequency of a controllable oscillator to the desired output frequency using a first locked loop having a first loop divider value. The first loop divider value is set such that the intermediate reference frequency multiplied by the first loop divider value is equal to the desired output frequency. The controllable oscillator is then coupled to a second locked loop when the first locked loop locks, with the second locked loop is being activated. The first locked loop is then deactivated.

IPC Classes  ?

• H03L 7/07 - Automatic control of frequency or phaseSynchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
• H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
• H03L 7/095 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector

Abstract

An electronic device includes a power management circuit generating output for a plurality of voltage monitors that each detect whether voltages received from a test apparatus are at least a different minimum threshold. The power management circuit also generates a test enable signal indicative of whether the test apparatus is supplying the minimum required voltages to the electronic device. A control circuit receives the output for the plurality of voltage monitors and the test enable signal and generates at least one control signal as a function of the output for the plurality of voltage monitors and the test enable signal. An output circuit receives the at least one control signal and generates an interface control signal that selectively enables or disables interface with analog intellectual property packages within the electronic device, in response to the at least one control signal.

IPC Classes  ?

• G06F 1/24 - Resetting means
• H03K 19/00 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits
• G01R 31/319 - Tester hardware, i.e. output processing circuits
• G06F 1/3206 - Monitoring of events, devices or parameters that trigger a change in power modality
• H03K 17/22 - Modifications for ensuring a predetermined initial state when the supply voltage has been applied

Abstract

A sense amplifier enable signal and a tracking signal are generated in response to an indication that a sufficient voltage difference has developed across bit lines of a memory. The sense amplifier enable signal has a pulse width between a leading edge and a trailing edge. The sense amplifier enable signal is propagated along a first U-turn signal line that extends parallel to rows of the memory array and is coupled to sense amplifiers arranged in a row to generate a sense amplifier enable return signal. The tracking signal is propagated along a second U-turn signal line extending parallel to columns of the memory array to generate a tracking return signal. The sense amplifier enable return signal and the tracking return signal are logically combined to generate a reset signal. Timing of the trailing edge of the pulse width is controlled by the reset signal.

IPC Classes  ?

• G11C 11/419 - Read-write [R-W] circuits
• G11C 11/417 - Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type

Goods & Services

Semi-conductors, integrated circuits, sensor devices, namely, motion sensors and electronic sensors for environmental use, touch panels, proximity sensors, optical and infrared sensors, anti-intruder systems in the nature of burglar alarms, accelerometers, gyroscopes, magnetometers, wireless transceivers radio, integrated circuits with built-in microcontrollers, printed circuit boards, wireless microcontrollers and transceivers, downloadable computer software for printed circuit boards and integrated systems for environmental, user, machine, apparatus status and events detection

Abstract

A diode and method of design the layout of the same having reduced parasitic capacitance is disclosed. In particular, the diode for providing fast response protection of an RF circuit from a high power noise event, such as an ESD, voltage spike, power surge or other noise is disclose. The parasitic capacitance in disclosed circuit is a greatly reduced compared to the prior art, thus significantly increasing the speed of the response to dissipate all high power noise events.

IPC Classes  ?

• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
• H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
• H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched

Abstract

A circuit includes a frequency detector generating a comparison signal as a function of a comparison between a reference signal and a feedback signal. An oscillator generates an output signal as a function of the comparison signal. A frequency divider, in operation, divides the output signal by a division value to produce the feedback signal as having a frequency that is a multiple of a frequency of the reference signal. A frequency counter circuit measures the frequency of the reference signal and generates a count signal based thereupon. A control circuit adjusts the division value used by the frequency divider, in operation, based upon the count signal.

IPC Classes  ?

• H03L 1/00 - Stabilisation of generator output against variations of physical values, e.g. power supply
• H03L 7/183 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
• H03L 7/087 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
• H03L 7/085 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal

Abstract

A sub-bandgap reference voltage generator includes a reference current generator generating a reference current (proportional to absolute temperature), a voltage generator generating an input voltage (proportional to absolute temperature) from the reference current, and a differential amplifier. The differential amplifier is biased by the reference current and has an input receiving the input voltage and a resistor generating a voltage proportional to absolute temperature summed with the input voltage to produce a temperature insensitive output reference voltage. The reference current generator may generate the reference current as a function of a difference between bias voltages of first and second transistors. The voltage generator may generate the input voltage by applying the current proportional to absolute temperature through a plurality of transistors coupled in series between the bias voltage of the second transistor and ground, and tapping a node between given adjacent ones of the plurality of transistors.

IPC Classes  ?

• G05F 3/26 - Current mirrors

Abstract

A circuit includes a test data input (TDI) pin receiving a test data input signal, a test data out (TDO) pin outputting a test data output signal, and debugging test access port (TAP) having a test data input coupled to the TDI pin and a bypass register having an input coupled to the test data input of the debugging TAP. A multiplexer has inputs coupled to the TDI pin and the debugging TAP. A testing TAP has a test data input coupled to the output of the multiplexer, and a data register having an input coupled to the test data input of the testing TAP. The multiplexer switches so the test data input signal is selectively coupled to the input of the data register of the testing TAP so the output of the debugging TAP is selectively coupled to the input of the data register of the testing TAP.

IPC Classes  ?

• G01R 31/3185 - Reconfiguring for testing, e.g. LSSD, partitioning
• G06F 11/267 - Reconfiguring circuits for testing, e.g. LSSD, partitioning
• G06F 11/27 - Built-in tests
• G01R 31/3183 - Generation of test inputs, e.g. test vectors, patterns or sequences
• G01R 31/317 - Testing of digital circuits

Abstract

An RC oscillator generates a periodic trigger signal, and a clock generator generates clock edges in response. A stuck-at-fault detection circuit detects a stuck-at-logic state of the periodic trigger signal and causes the RC oscillator to reset and causes a change in logic state of the periodic trigger signal. The RC oscillator includes first and second comparison circuits, a logic circuit receiving output from the first and second comparison circuits and generating the periodic trigger signal, and a clock generation circuit generating a clock signal therefrom. The stuck-at-fault detection circuit includes a capacitive node, charge circuitry charging the capacitive node based upon the periodic trigger signal, discharge circuitry discharging the capacitive node based upon the periodic trigger signal, and triggering circuitry asserting a reset signal to cause the RC oscillator to reset when the charge on the capacitive node indicates a stuck-at-logic state of the periodic trigger signal.

IPC Classes  ?

• H03K 3/0231 - Astable circuits
• H03K 4/502 - Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices in which a sawtooth voltage is produced across a capacitor the starting point of the flyback period being determined by the amplitude of the voltage across the capacitor, e.g. by a comparator the capacitor being charged from a constant-current source
• H03K 5/19 - Monitoring patterns of pulse trains
• H03K 3/011 - Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature

Abstract

A low-voltage-differential-signaling (LVDS) fault detector includes first and second LVDS lines, and a window comparator provides a first output indicating whether a difference between voltages at the first and second LVDS lines is greater than a threshold voltage, and a second output indicating whether a difference between the voltages at the second and first LVDS lines is greater than the threshold voltage. A charge circuit charges a capacitive node when either the first or second output is at a logic low, and discharges the capacitive node when neither the first nor second output is at a logic low. A Schmitt trigger generates a fault flag if charge on the capacitive node falls to a threshold.

IPC Classes  ?

• H03K 19/007 - Fail-safe circuits
• H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only
• G01R 31/317 - Testing of digital circuits

Abstract

A latch is provided. The latch includes a plurality of storage nodes including a plurality of data storage nodes configured to store a data bit having one of two states and a plurality of complementary data storage nodes configured to store a complement of the data bit. The latch includes a plurality of supply voltage multi-dependency stages respectively corresponding to the plurality of storage nodes. Each supply voltage multi-dependency stage has an output coupled to a storage node and at least two control inputs respectively coupled to at least two other storage nodes of the plurality of storage nodes. The supply voltage multi-dependency stage is configured to cause a state of the data bit stored in the storage node to change from a first state to a second state in response a change in both states of two data bits respectively stored in the at least two other storage nodes.

IPC Classes  ?

• H03K 19/003 - Modifications for increasing the reliability
• H03K 3/037 - Bistable circuits
• G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• G01R 31/3181 - Functional testing
• H03K 3/356 - Bistable circuits

Abstract

In an integrated circuit supporting complementary metal oxide semiconductor (CMOS) integrated circuits, latch-up immunity is supported by surrounding a hot n-well with an n-well strap spaced from the hot n-well by a specified distance in accordance with design rules. The n-well strap is positioned between the hot n-well and other n-well or n-type diffusion structures.

IPC Classes  ?

• H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions

Abstract

A voltage doubler circuit supports operation in both a positive voltage boosting mode to positively boost voltage from a first node to a second node and a negative voltage boosting mode to negatively boost voltage from the second node to the first node. The voltage doubler circuit is formed by transistors of a same conductivity type that share a common bulk that is not tied to a source of any of the voltage doubler circuit transistors. A bias generator circuit is coupled to receive a first voltage from the first node and second voltage from the second node. The bias generator circuit operates to apply a lower one of the first and second voltages to the common bulk.

IPC Classes  ?

• H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
• G05F 1/10 - Regulating voltage or current
• H03K 19/096 - Synchronous circuits, i.e. using clock signals

Abstract

A recursive digital sinusoid generator generates recursive values used in the production of a digital sinusoid output. The recursive values are generated at a first frequency. A sinusoid value generator generates replacement values at a second frequency, wherein the second frequency is less than the first frequency. The generated recursive values are periodically replaced with the generated replacement values without interrupting production of the digital sinusoid output at the first frequency. This periodic replacement effectively corrects for a finite precision error which accumulates in the recursive values over time.

IPC Classes  ?

• G06F 1/02 - Digital function generators
• H03K 4/02 - Generating pulses having essentially a finite slope or stepped portions having stepped portions, e.g. staircase waveform
• H03K 3/80 - Generating trains of sinusoidal oscillations

Abstract

Embodiments are directed towards a method to create a reconfigurable interconnect framework in an integrated circuit. The method includes accessing a configuration template directed toward the reconfigurable interconnect framework, editing parameters of the configuration template, functionally combining the configuration template with a plurality of modules from an IP library to produce a register transfer level (RTL) circuit model, generating at least one automated test-bench function, and generating at least one logic synthesis script. Editing parameters of the configuration template includes confirming a first number of output ports of a reconfigurable stream switch and confirming a second number of input ports of the reconfigurable stream switch. Each output port and each input port has a respective architectural composition. The output port architectural composition is defined by a plurality of N data paths including A data outputs and B control outputs. The input port architectural composition is defined by a plurality of M data paths including A data inputs and B control inputs.

IPC Classes  ?

• G06F 30/327 - Logic synthesisBehaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• G06N 3/04 - Architecture, e.g. interconnection topology
• G06N 3/08 - Learning methods
• G06F 30/34 - Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
• G06F 9/445 - Program loading or initiating
• G06F 13/40 - Bus structure
• G06F 15/78 - Architectures of general purpose stored program computers comprising a single central processing unit
• G06N 20/10 - Machine learning using kernel methods, e.g. support vector machines [SVM]
• G06N 7/00 - Computing arrangements based on specific mathematical models
• G06F 115/08 - Intellectual property [IP] blocks or IP cores

Abstract

Disclosed herein is a circuit including a transistor, with a resonant tank coupled between a DC supply node and a first conduction terminal of the transistor. A gate driver generates a gate drive signal for biasing a control terminal of the transistor to cause it to conduct current through the resonant tank. Control circuitry monitors a voltage across the transistor to determine that the transistor is an overvoltage condition if that voltage exceeds a threshold, and monitors a current through the transistor to determine that the transistor is an overcurrent condition if that current exceeds a threshold. If overvoltage is determined, the control circuitry causes the gate driver to pull up the gate drive signal. If overcurrent is determined, the control circuitry causes the gate driver to pull down the gate drive signal. If either overvoltage or overcurrent is present, a pulse width of the gate drive signal is reduced.

IPC Classes  ?

• H05B 6/06 - Control, e.g. of temperature, of power
• H05B 6/12 - Cooking devices
• H02H 3/20 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess voltage
• H02H 7/10 - Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for convertersEmergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for rectifiers
• H02M 1/32 - Means for protecting converters other than by automatic disconnection
• H03K 17/082 - Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
• H05B 6/10 - Induction heating apparatus, other than furnaces, for specific applications
• H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• H02M 7/04 - Conversion of AC power input into DC power output without possibility of reversal by static converters

Abstract

A method for a phase calibration in a frontend circuit of a near field communication (NFC) tag device is disclosed. An active load modulation signal is generated with a preconfigured value of a phase difference with respect to a reference signal of an NFC signal generator device. An amplitude of a test signal present at an antenna of the NFC tag device is measured. The test signal results from overlaying of the reference signal with the active load modulation signal. The following steps are repeated: modifying the value of the phase difference, providing the active load modulation signal with the modified value of the phase difference, measuring an amplitude of the test signal and comparing the measured amplitude with the previously measured amplitude until the measured amplitude fulfills a predefined condition. The value of the phase difference corresponding to the previously measured amplitude is stored.

IPC Classes  ?

• H04B 17/21 - MonitoringTesting of receivers for calibrationMonitoringTesting of receivers for correcting measurements
• G06K 7/00 - Methods or arrangements for sensing record carriers
• G06K 7/10 - Methods or arrangements for sensing record carriers by electromagnetic radiation, e.g. optical sensingMethods or arrangements for sensing record carriers by corpuscular radiation
• H04B 5/00 - Near-field transmission systems, e.g. inductive or capacitive transmission systems

Abstract

A system on a chip (SoC) includes a plurality of processing cores and a stream switch coupled to two or more of the plurality of processing cores. The stream switch includes a plurality of N multibit input ports, wherein N is a first integer. a plurality of M multibit output ports, wherein M is a second integer, and a plurality of M multibit stream links dedicated to respective output ports of the plurality of M multibit output ports. The M multibit stream links are reconfigurably coupleable at run time to a selectable number of the N multibit input ports, wherein the selectable number is an integer between zero and N.

IPC Classes  ?

• G06F 9/455 - EmulationInterpretationSoftware simulation, e.g. virtualisation or emulation of application or operating system execution engines
• G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
• G06F 30/327 - Logic synthesisBehaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• G06N 3/04 - Architecture, e.g. interconnection topology
• G06N 3/08 - Learning methods
• G06F 30/34 - Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
• G06F 9/445 - Program loading or initiating
• G06F 13/40 - Bus structure
• G06F 15/78 - Architectures of general purpose stored program computers comprising a single central processing unit
• G06N 20/10 - Machine learning using kernel methods, e.g. support vector machines [SVM]
• G06N 7/00 - Computing arrangements based on specific mathematical models
• G06F 115/08 - Intellectual property [IP] blocks or IP cores

Abstract

A circuit includes a voltage converter converting a source voltage to a supply voltage at a first node as a function of a feedback voltage at a feedback node. A first output path is coupled between the first node and a second node. Feedback circuitry compares the voltage at the second node to first and second overvoltages, and selectively couples the second node to the feedback node based thereupon. Impedance circuitry is coupled between the first node and a third node. A light emitting diode (LED) chain is coupled to the third node, and is selectively turned on and off as a function of the selective coupling of the second node to the feedback node by the feedback circuitry.

IPC Classes  ?

• H05B 45/37 - Converter circuits
• H02M 3/15 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using discharge tubes only
• H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• H02M 3/156 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
• H05B 45/10 - Controlling the intensity of the light
• H02M 1/00 - Details of apparatus for conversion

Abstract

A JTAG interface in an IC includes a test mode select (TMS) pin receiving a TMS signal, a testing test access port (TAP) having a TMS signal input, a debugging test access port (TAP) having a TMS signal and glue logic coupled to receive a first output from the testing TAP and a second output from the debugging TAP. A flip-flop receives input from the testing TAP and the debugging TAP through the glue logic. A first AND gate has output coupled to the TMS signal input of the debugging TAP, and receives input from an output of the flip-flop and the TMS signal. An inverter has an input coupled to receive input from the flip-flop. A second AND gate has output coupled to the TMS signal input of the testing TAP, and receives input from the TMS signal and output of the inverter.

IPC Classes  ?

• G01R 31/317 - Testing of digital circuits
• G01R 31/3185 - Reconfiguring for testing, e.g. LSSD, partitioning

Abstract

A PLL includes a phase frequency detector (PFD) receiving an input signal and feedback signal, and producing a control signal. A charge pump receives the control signal and produces an initial VCO control. A loop filter generates a fine VCO control and intermediate output based upon the initial VCO control. A coarse control circuit includes an integrator having a first input receiving the intermediate output, a second input, and generating a coarse VCO control, a first switch coupling a reference voltage to the second input, a buffer buffering output of the integrator, and a second switch coupling output of the integrator to the second input of the integrator. A VCO receives the fine VCO control and the coarse VCO control, and generates an output signal having a frequency based thereupon. A feedback path receives the output signal and produces the feedback signal.

IPC Classes  ?

• H03L 7/085 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
• H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop

Abstract

A device for managing operation of an object capable of contactless communication with a reader magnetically coupled to the object includes a modulator configured to modulate an impedance of a load connected across terminals of an antenna of the object during a transmission phase during which information is transmitted from the object to the reader. The device further includes a monitor configured to carry out a monitoring phase, prior to the transmission phase. The monitoring phase includes a test modulation of the impedance of the load, a monitoring of a level of amplitude modulation of a modulated test signal present at the antenna of the object and resulting from the test modulation, and a capacitive modification of the impedance of the load if this level is lower than a threshold.

IPC Classes  ?

• G06K 19/07 - Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards with integrated circuit chips
• G06K 7/00 - Methods or arrangements for sensing record carriers
• H04B 5/00 - Near-field transmission systems, e.g. inductive or capacitive transmission systems
• G06K 19/073 - Special arrangements for circuits, e.g. for protecting identification code in memory
• H03C 1/08 - Amplitude modulation by means of variable impedance element

Abstract

A level shifting circuit receives a first input signal and complement of the first input signal as inputs and generates a level shifted first output signal and complement of the first output signal as outputs. The level shifting circuit includes a number of transistors that support body biasing. One set of body bias signals applied to certain ones of those transistors is generated as a function of the logical combination of the first input signal and the first output signal. Another set of body bias signals applied to certain other ones of those transistors is generated as a function of the logical combination of the complement of the first input signal and the complement of the first output signal. The conditional body bias applied to the transistors of the level shifting circuit makes the circuit operational for level shift at very low supply voltage levels.

IPC Classes  ?

• H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only
• H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

Abstract

A memory includes error correction circuitry that receives a data packet, outputs a correctable error flag indicating presence or absence of a correctable error in the data packet, and outputs an uncorrectable error flag indicating presence or absence of an uncorrectable error in the data packet. A response manager, operating in availability mode, generates output indicating that a correctable error was present if the correctable error flag indicates presence thereof, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof. In a coverage mode, the response manager generates an output indicating that a correctable error was potentially present but should be treated as an uncorrectable error if the correctable error flag indicates presence of the correctable error, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof.

IPC Classes  ?

• G06F 11/00 - Error detectionError correctionMonitoring
• H04L 1/00 - Arrangements for detecting or preventing errors in the information received
• G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

An output stage of an output buffer circuit includes a first drive transistor and a first cascode transistor (coupled in series between a first supply node and an output node) and a second drive transistor and a second cascode transistor (coupled in series between the output node and a second supply node). Gates of the first and second cascode transistors are biased with first and second bias voltages, respectively. The first bias voltage equals the first supply voltage at the first supply node when the first supply voltage is less than a threshold, and is fixed at a fixed voltage for any first supply voltage exceeding the threshold voltage. The second bias voltage equals a fixed voltage when the first supply voltage is less than a threshold voltage, and is offset from the first supply voltage by a fixed difference for any first supply voltage exceeding the threshold.

IPC Classes  ?

• H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only
• H03K 17/082 - Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
• G05F 3/16 - Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
• H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors

Goods & Services

Electric or electronic components, namely, semiconductors, semiconductor devices, electronic circuits, micro-circuits in the nature of electronic circuits, integrated circuits, microprocessors, microcontrollers and embedded microprocessors, electronic memory circuit cards

Goods & Services

Semiconductors; integrated circuits; microprocessors; microcontrollers; embedded microprocessors; integrated circuit cards; integrated circuit chips; printed electronic circuits for integrated circuit apparatus and cards bearing integrated circuits; computer memory devices

Abstract

An RFID transponder includes a coding and modulation unit that generates a transmission signal by modulating an oscillator signal with an encoded bit signal. During a first and a second time segment, the encoded bit signal assumes a first and a second logic level, respectively. The transmission signal includes a first signal pulse having a first phase within the first time segment and a second signal pulse having a second phase that is shifted with respect to the first phase by a predefined phase difference within the second time segment. The transmission signal is paused for a pause period between the first and the second signal pulse. The pause period is shorter than a mean value of a period of the first time segment and a period of the second time segment.

IPC Classes  ?

• H04B 5/00 - Near-field transmission systems, e.g. inductive or capacitive transmission systems
• G06K 19/077 - Constructional details, e.g. mounting of circuits in the carrier
• G06K 19/07 - Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards with integrated circuit chips
• G06K 7/00 - Methods or arrangements for sensing record carriers

Abstract

Disclosed is a method of locking a locked loop quickly, including receiving an input signal having an input frequency, and generating an intermediate signal having an intermediate frequency intended to be equal to a geometric mean of the input frequency and a desired frequency, but not equal. Results of division of the desired output frequency by the intermediate frequency are estimated, producing a first divider value. A first locked loop utilizing a controllable oscillator is activated. A divider value of the first locked loop is set to the first divider value, and the intermediate signal is provided to the first locked loop, so that when the first locked loop reaches lock, the controllable oscillator produces the desired frequency. When the first locked loop reaches lock, a second locked loop that utilizes the controllable oscillator is activated, the first locked loop is deactivated, and generation of the intermediate signal is ceased.

IPC Classes  ?

• H03L 7/07 - Automatic control of frequency or phaseSynchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
• H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
• H03L 7/095 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector

Abstract

The present disclosure is directed to a lead frame design that includes a copper alloy base material coated with an electroplated copper layer, a precious metal, and an adhesion promotion compound. The layers compensate for scratches or surface irregularities in the base material while promoting adhesion from the lead frame to the conductive connectors, and to the encapsulant by coupling them to different layers of a multilayer coating on the lead frame. The first layer of the multilayer coating is a soft electroplated copper to smooth the surface of the base material. The second layer of the multilayer coating is a thin precious metal to facilitate a mechanical coupling between leads of the lead frame and conductive connectors. The third layer of the multilayer coating is the adhesion promotion compound for facilitating a mechanical coupling to an encapsulant around the lead frame.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/495 - Lead-frames
• C25D 5/48 - After-treatment of electroplated surfaces
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• C25D 3/38 - ElectroplatingBaths therefor from solutions of copper

Abstract

A memory device includes first and second dummy word line portions. A dummy word line driver drives the first dummy word line portion. A voltage dropping circuit causes a voltage on the second dummy word line to be less than a voltage on the first dummy word line. At least one dummy memory cell is coupled to the second dummy word line portion, remains in standby until assertion of the second dummy word line, and performs a dummy cycle in response to assertion of the second dummy word line. A reset signal generation circuit generates a reset signal in response to completion of a dummy cycle by the at least one dummy memory cell. An internal clock signal is generated from an external clock signal and the reset signal and is used in performing a read and/or write cycle to a memory array.

IPC Classes  ?

• G11C 7/00 - Arrangements for writing information into, or reading information out from, a digital store
• G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
• G11C 7/14 - Dummy cell managementSense reference voltage generators
• G11C 11/419 - Read-write [R-W] circuits
• G11C 8/08 - Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• G11C 11/413 - Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• G11C 11/418 - Address circuits

Abstract

The present disclosure is directed to a master-slave flip-flop memory circuit having a partial pass gate transistor at the input of the master latch. The partial pass gate transistor includes a pull-up clock enabled transistor for selectively coupling a high output of a test switch to the input of the master latch. The input of the master latch is also directly coupled to a low output of the test switch around the partial pass gate. In addition, a revised circuit layout is provided in which the master latch has three inverters. A first inverter is coupled to the input of the master latch. Second and third inverters are coupled to an output of the first inverter, with the second inverter having an output coupled to the input of the first inverter, and the third inverter having an output coupled to an output of the master latch. The first and second inverters are clock enabled, and the third inverter is reset enabled.

IPC Classes  ?

• H03K 3/356 - Bistable circuits
• H03K 3/3562 - Bistable circuits of the primary-secondary type
• G11C 29/00 - Checking stores for correct operationTesting stores during standby or offline operation
• G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only

Abstract

Embodiments of a device include an integrated circuit, a reconfigurable stream switch formed in the integrated circuit, and an arithmetic unit coupled to the reconfigurable stream switch. The arithmetic unit has a plurality of inputs and at least one output, and the arithmetic unit is solely dedicated to performance of a plurality of parallel operations. Each one of the plurality of parallel operations carries out a portion of the formula: output=AX+BY+C.

IPC Classes  ?

• G06F 9/02 - Arrangements for program control, e.g. control units using wired connections, e.g. plugboards
• G06N 3/08 - Learning methods
• G06N 20/00 - Machine learning
• G06F 17/11 - Complex mathematical operations for solving equations
• G06N 3/04 - Architecture, e.g. interconnection topology
• G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
• G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode

Abstract

Embodiments of a device include on-board memory, an applications processor, a digital signal processor (DSP) cluster, a configurable accelerator framework (CAF), and at least one communication bus architecture. The communication bus communicatively couples the applications processor, the DSP cluster, and the CAF to the on-board memory. The CAF includes a reconfigurable stream switch and a data volume sculpting unit, which has an input and an output coupled to the reconfigurable stream switch. The data volume sculpting unit has a counter, a comparator, and a controller. The data volume sculpting unit is arranged to receive a stream of feature map data that forms a three-dimensional (3D) feature map. The 3D feature map is formed as a plurality of two-dimensional (2D) data planes. The data volume sculpting unit is also arranged to identify a 3D volume within the 3D feature map that is dimensionally smaller than the 3D feature map and isolate data from the 3D feature map that is within the 3D volume for processing in a deep learning algorithm.

IPC Classes  ?

• G06T 7/11 - Region-based segmentation
• G06K 9/00 - Methods or arrangements for reading or recognising printed or written characters or for recognising patterns, e.g. fingerprints
• G06T 15/08 - Volume rendering
• G06T 7/62 - Analysis of geometric attributes of area, perimeter, diameter or volume
• G06F 16/901 - IndexingData structures thereforStorage structures
• G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
• G06K 9/62 - Methods or arrangements for recognition using electronic means
• G06N 3/08 - Learning methods
• G06N 3/04 - Architecture, e.g. interconnection topology
• G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means

Abstract

According to principles as discussed herein, an EEPROM cell is provided and then, after testing the code, using the exact same architecture, transistors, memory cells, and layout, the EEPROM cell is converted to a read-only memory (“ROM”) cell. This conversion is done on the very same integrated circuit die using the same layout, design, and timing with only a single change in an upper level mask in the memory array. In one embodiment, the mask change is the via mask connecting metal 1 to poly. This allows the flexibility to store the programming code as non-volatile memory code, and then after it has been tested, at time selected by the customer, some or all of that code from a code that can be written to a read-only code that is stored in a ROM cell that is composed the same transistors and having the same layout.

IPC Classes  ?

• H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
• H01L 27/11521 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region
• G11C 29/00 - Checking stores for correct operationTesting stores during standby or offline operation
• H01L 27/112 - Read-only memory structures
• H01L 27/11519 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the top-view layout
• H01L 27/11558 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate the control gate being a doped region, e.g. single-poly memory cells
• G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
• H01L 21/66 - Testing or measuring during manufacture or treatment

Abstract

Embodiments of a device include an integrated circuit, a reconfigurable stream switch formed in the integrated circuit along with a plurality of convolution accelerators and an arithmetic unit coupled to the reconfigurable stream switch. The arithmetic unit has at least one input and at least one output. The at least one input is arranged to receive streaming data passed through the reconfigurable stream switch, and the at least one output is arranged to stream resultant data through the reconfigurable stream switch. The arithmetic unit also has a plurality of data paths. At least one of the plurality of data paths is solely dedicated to performance of operations that accelerate an activation function represented in the form of a piece-wise second order polynomial approximation.

IPC Classes  ?

• G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
• G06F 17/17 - Function evaluation by approximation methods, e.g. interpolation or extrapolation, smoothing or least mean square method
• G06N 20/00 - Machine learning
• G06F 1/26 - Power supply means, e.g. regulation thereof
• G06F 17/16 - Matrix or vector computation
• G06N 3/045 - Combinations of networks
• G06N 3/08 - Learning methods

Abstract

A distributed computing system for artificial intelligence in autonomously appreciating a circumstance context of a smart device. Raw context data is detected by sensors associated with the smart device. The raw context data is pre-processed by the smart device and then provided to a cloud based server for further processing. At the cloud based server, various sets of feature data are obtained from the pre-processed context data. The various sets of feature data are compared with corresponding classification parameters to determine a classification of a continuous event and/or a classification of transient event, if any, which occur in the context. The determined classification of the continuous event and the transient event will be used to autonomously configure the smart device or another related smart device to fit the context.

IPC Classes  ?

• G01P 15/00 - Measuring accelerationMeasuring decelerationMeasuring shock, i.e. sudden change of acceleration
• G06F 1/16 - Constructional details or arrangements
• G01P 15/18 - Measuring accelerationMeasuring decelerationMeasuring shock, i.e. sudden change of acceleration in two or more dimensions
• H04W 4/029 - Location-based management or tracking services
• G06N 20/10 - Machine learning using kernel methods, e.g. support vector machines [SVM]
• G10L 21/10 - Transforming into visible information
• G06K 9/62 - Methods or arrangements for recognition using electronic means
• H04W 4/50 - Service provisioning or reconfiguring
• G06F 3/0346 - Pointing devices displaced or positioned by the userAccessories therefor with detection of the device orientation or free movement in a 3D space, e.g. 3D mice, 6-DOF [six degrees of freedom] pointers using gyroscopes, accelerometers or tilt-sensors
• G10L 25/51 - Speech or voice analysis techniques not restricted to a single one of groups specially adapted for particular use for comparison or discrimination
• G06F 3/01 - Input arrangements or combined input and output arrangements for interaction between user and computer
• H04M 1/725 - Cordless telephones
• G10L 25/78 - Detection of presence or absence of voice signals
• H04W 4/38 - Services specially adapted for particular environments, situations or purposes for collecting sensor information
• H04L 29/08 - Transmission control procedure, e.g. data link level control procedure

Abstract

A level shifting circuit receives a first input signal and complement of the first input signal as inputs and generates a level shifted first output signal and complement of the first output signal as outputs. The level shifting circuit includes a number of transistors that support body biasing. One set of body bias signals applied to certain ones of those transistors is generated as a function of the logical combination of the first input signal and the first output signal. Another set of body bias signals applied to certain other ones of those transistors is generated as a function of the logical combination of the complement of the first input signal and the complement of the first output signal. The conditional body bias applied to the transistors of the level shifting circuit makes the circuit operational for level shift at very low supply voltage levels.

IPC Classes  ?

• H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only
• H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

Abstract

A frequency demodulated signal includes a frequency modulation in time that is shifted by a DC level corresponding to a carrier frequency offset. A number of different frequency offsets are applied to the frequency demodulated signal to generate a corresponding number of offset frequency demodulated signals. Each offset frequency demodulated signal is correlated against a reference signal and a determination is made as to which correlation produces a highest correlation value. One offset frequency demodulated signal of the number of offset frequency demodulated signals is then selected for output as an offset corrected frequency demodulated signal. The selected signal is the one having the highest correlation value.

IPC Classes  ?

• H04L 27/06 - Demodulator circuitsReceiver circuits
• H04L 27/16 - Frequency regulation arrangements
• H04L 27/00 - Modulated-carrier systems
• H04L 27/14 - Demodulator circuitsReceiver circuits
• H04L 27/156 - Demodulator circuitsReceiver circuits with demodulation using temporal properties of the received signal, e.g. detecting pulse width

Abstract

The present disclosure is directed to a circuit layout of a dual port static random-access-memory (SRAM) cell. The memory cell includes active regions in a substrate, with polysilicon gate electrodes on the active regions to define transistors of the memory cell. The eight transistor (8T) memory cell layout includes a reduced aspect ratio and non-polysilicon bit line discharge path routing by positioning an active region for the first port opposite an active region for the second port and consolidating power line nodes at a central portion of the memory cell.

IPC Classes  ?

• G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
• H01L 27/11 - Static random access memory structures
• G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
• G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
• G11C 11/417 - Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type

Abstract

Various embodiments provide a content addressable memory (CAM) architecture that utilizes non-bit addressable memory, such as a single or dual port random access memory. The CAM includes a first non-bit addressable memory, a second non-bit addressable memory, a multiplexer, a write operation encoder, a read operation encoder, and a match signal generator. In contrast to bit addressable memories, non-bit addressable memories are widely available, have high performance frequency, and are area efficient as compared to bit addressable memories. Accordingly, the CAM architecture described herein has low costs and time to market, increased processing time, and improved area efficiency.

IPC Classes  ?

• G06F 16/90 - Details of database functions independent of the retrieved data types
• G06F 15/78 - Architectures of general purpose stored program computers comprising a single central processing unit
• G06F 16/903 - Querying

Abstract

Electrostatic discharge (ESD) protection is provided in using a supply clamp circuit including a trigger actuated MOSFET device. Triggering of the MOSFET device is made in response to detection of either a positive ESD event or a negative ESD event.

IPC Classes  ?

• H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
• H02H 1/00 - Details of emergency protective circuit arrangements
• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
• H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
• H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
• H01L 23/528 - Layout of the interconnection structure

Abstract

Data words are received in parallel in response to an edge of a master clock signal and selected for serial output in response to a select signal. For a detected temporal offset of the serially output data words, the generation of the select signal and the master clock signal are controlled to correct for the temporal offset by shifting timing of the edge of the master clock signal and adjusting a sequence of values for the select signal that are generated within one cycle of the master clock signal. For a backward temporal offset, at least one count value in the sequence of values is skipped and the edge of the master clock signal occurs earlier in time. For a forward temporal offset, at least one count value in the sequence of values is held and the edge of the master clock signal occurs later in time.

IPC Classes  ?

• H04L 7/00 - Arrangements for synchronising receiver with transmitter

Abstract

A LED driving circuit includes a power factor correction circuit receiving a rectified mains voltage and providing output to a DC voltage bus, a string of LEDs connected in series, a voltage converter receiving input from the DC voltage bus and providing output to the string of LEDs, and a microcontroller. The microcontroller receives a plurality of digital feedback signals from the voltage converter, controls the voltage converter based upon a user desired brightness level and the plurality of digital feedback signals, and receive a plurality of feedback signals from the power factor correction circuit. Based on the plurality of feedback signals, the microcontroller operates the power factor correction circuit in transition mode where the user desired brightness level is above a threshold brightness, and operates the power factor correction circuit in discontinuous mode where the user desired brightness level is below the threshold brightness.

IPC Classes  ?

• H05B 45/10 - Controlling the intensity of the light
• H05B 45/37 - Converter circuits
• H05B 45/355 - Power factor correction [PFC]Reactive power compensation
• H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• H02M 1/42 - Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
• H05B 45/44 - Details of LED load circuits with an active control inside an LED matrix
• H02M 1/00 - Details of apparatus for conversion

Abstract

Electrostatic discharge (ESD) protection is provided in using a supply clamp circuit formed by an ESD event actuated transistor device. A bias current is generated in response to operation of a voltage independent current generator circuit. The bias current is sourced to ensure that the transistor device is deactuated after the ESD event is dissipated.

IPC Classes  ?

• H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
• H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
• H01L 23/528 - Layout of the interconnection structure
• H02H 9/00 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
• H01L 27/04 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
• H02H 3/22 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess voltage of short duration, e.g. lightning

Abstract

A digital filtering method includes receiving a digital signal, and passing the digital signal through a Pth order comb cascade. The method includes beginning pre-computing of intermediate integrator states of a Pth order integrator cascade as a function of the digital signal, prior to receiving output from a last comb of the Pth order comb cascade. The outputs from each comb of the Pth order comb cascade are then applied to the pre-computed intermediate integrator states to thereby produce a filtered version of the digital signal. The Pth order comb cascade may operate at a sampling frequency, and the pre-computing of the intermediate integrator states is performed at the sampling frequency, while the application of the outputs from each comb of the Pth order comb cascade to the pre-computed intermediate integrator states is performed at a multiple of the sampling frequency.

IPC Classes  ?

• G06F 17/10 - Complex mathematical operations
• H03H 17/06 - Non-recursive filters

Abstract

One or more embodiments are directed to inter-integrated circuit (I2C) transmitters, receivers, and devices that utilize a stable reference voltage for driving a pre-driver of the transmitter and for driving a first input stage of the receiver. One embodiment is directed to a device A device that includes an inter-integrated circuit (I2C) transmitter and an I2C receiver. The I2C transmitter includes a driver coupled to an I2C data line, and a pre-driver coupled to a variable first supply voltage, a second supply voltage, and a reference voltage. The pre-driver is configured to output a control signal to a control terminal of the driver. The I2C receiver includes a first stage coupled to the I2C data line, the variable first supply voltage, the second supply voltage, and the reference voltage.

IPC Classes  ?

• H03B 1/00 - GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNERGENERATION OF NOISE BY SUCH CIRCUITS Details
• H03K 3/00 - Circuits for generating electric pulsesMonostable, bistable or multistable circuits
• H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
• G05F 3/24 - Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode-transistor combinations wherein the transistors are of the field-effect type only
• G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
• H03K 19/0175 - Coupling arrangementsInterface arrangements
• H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only
• H03K 3/037 - Bistable circuits

Abstract

Video encoders and decoders and video encoding and decoding methods are provided. A video encoder includes an input buffer configured to receive a video data stream and to supply current frame data, a frame buffer configured to store reconstructed frame data, and an encoder circuit configured to read reference frame data from the frame buffer, to encode the current frame data received from the input buffer using the reference frame data and to write the reconstructed frame data to the frame buffer. The encoder circuit may be configured to write the reconstructed frame data by overwriting the reference frame data in the frame buffer.

IPC Classes  ?

• H04N 19/00 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
• H04N 19/433 - Hardware specially adapted for motion estimation or compensation characterised by techniques for memory access

Abstract

Application data and error correction code (ECC) checkbits associated with that application data are stored in a first memory. The ECC checkbits, but not the application data, are stored in a second memory. In response to a request to read the application data from the first memory, the ECC checkbits from the first memory are also read and used to detect, and possibly correct, errors in the read application data. The ECC checkbits are further output from both the first and second memories for bit-by-bit comparison. In response to a failure of the bit-by-bit comparison, a signal indicating possible malfunction of one or the other or both of the first and second memories is generated.

IPC Classes  ?

• G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
• G11C 29/52 - Protection of memory contentsDetection of errors in memory contents

Abstract

A circuit has a first window comparator determining whether a signal at a first input has a voltage higher than a first threshold but lower than a second threshold, and a second window comparator determining whether a signal at a second input has a voltage higher than the first threshold but lower than the second threshold. A logic circuit generates pulses in response to either the first window comparator determining that the signal at the first differential input has a voltage higher than the first threshold but lower than the second threshold or the second window comparator determining that the signal at the second input has a voltage higher than the first threshold but lower than the second threshold. A filter circuit receives the pulses from the logic circuit and generates a flag indicating that the signal is invalid, based upon pulses received from the logic circuit.

IPC Classes  ?

• H04B 1/10 - Means associated with receiver for limiting or suppressing noise or interference
• H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
• H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
• H03K 3/027 - Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
• H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only
• H03H 11/04 - Frequency selective two-port networks
• H04L 25/02 - Baseband systems Details
• H03H 11/12 - Frequency selective two-port networks using amplifiers with feedback

Abstract

A modulation circuit includes a locked loop circuit with two-point modulation control and a phase-frequency detector configured to compare a reference frequency signal with a feedback frequency signal. A two-point modulation control circuit includes a first modulation path having a controllable gain and coupled to one of the first and second modulation control points and a second modulation path coupled to another of the first and second modulation control points. Gain matching of the first and second modulation paths is accomplished through the operation of a calibration circuit. The calibration circuit includes a phase detector circuit configured to compare the reference frequency signal with the feedback frequency signal to generate a phase detect signal, and a gain control circuit configured to adjust the controllable gain of the first modulation path as a function a correlation of the phase detect signal with signs of the modulation data.

IPC Classes  ?

• H03L 7/087 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
• H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
• H04L 7/00 - Arrangements for synchronising receiver with transmitter
• H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
• H04B 1/7073 - Synchronisation aspects

Abstract

Disclosed herein is a memory circuit including a dummy word line driver driving a dummy word line, dummy memory cells coupled to a dummy bit line and a dummy complementary bit line, and a transmission gate coupled to the dummy word line to pass a word line signal from the dummy word line driver to an input of the dummy memory cells. A transistor is coupled to the dummy word line between the transmission gate and a pair of pass gates of a given one of the dummy memory cells closest to the transmission gate along the dummy word line. A reset signal output is coupled to the dummy complementary bit line. The transistor serves to lower a voltage on the dummy word line, and a reset signal indicating an end of a measured dummy cycle is generated at the reset signal output.

IPC Classes  ?

• G11C 7/00 - Arrangements for writing information into, or reading information out from, a digital store
• G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
• G11C 7/14 - Dummy cell managementSense reference voltage generators
• G11C 11/419 - Read-write [R-W] circuits

Abstract

A voltage level shifter is provided. The voltage level shifter includes an input stage and at least one level shifting stage. The input stage receives an input voltage and a complementary input voltage and receives a first supply voltage and a ground voltage. The input stage outputs one of the first supply voltage and the ground voltage over a first output voltage node and a first complementary output voltage node based on the input voltage and the complementary input voltage. A level shifting stage is coupled to the input stage. The level shifting stage receives the first supply voltage and a second supply voltage and outputs one of the ground voltage, the first supply voltage and the second supply voltage over second and third output voltage nodes and second and third complementary output voltage nodes based on voltages of the first output voltage node and the first complementary output voltage node.

IPC Classes  ?

• H03L 5/00 - Automatic control of voltage, current, or power
• H03K 19/00 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits
• H03K 19/017 - Modifications for accelerating switching in field-effect transistor circuits
• H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only

Abstract

Various embodiments provide a parallel checker to determine whether a device under test (DUT) is functioning properly or outputting erroneous bits. A test pattern or test data is injected into the DUT, and the parallel checker compares output data of the DUT to expected data stored in the parallel checker. The parallel checker determines an error in the event that a bit in the output data does not match in the expected data. The parallel checker is independent of test pattern length and data width at the parallel input of the parallel checker. Accordingly, the parallel checker may be used for multiple different test patterns, such as a PRBS 7, a CJTPAT, CRPAT, etc. Further, the parallel checker provides high-speed synchronization between data received from the DUT and expected test data stored in the parallel checker. In addition, the parallel checker consumes relatively low power and chip area in, for example, a SoC environment.

IPC Classes  ?

• G01R 31/317 - Testing of digital circuits
• G01R 31/3177 - Testing of logic operation, e.g. by logic analysers

Abstract

A memory includes error correction circuitry that receives a data packet, outputs a correctable error flag indicating presence or absence of a correctable error in the data packet, and outputs an uncorrectable error flag indicating presence or absence of an uncorrectable error in the data packet. A response manager, operating in availability mode, generates output indicating that a correctable error was present if the correctable error flag indicates presence thereof, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof. In a coverage mode, the response manager generates an output indicating that a correctable error was potentially present but should be treated as an uncorrectable error if the correctable error flag indicates presence of the correctable error, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof.

IPC Classes  ?

• G06F 11/00 - Error detectionError correctionMonitoring
• G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

The present disclosure is directed to a master-slave flip-flop memory circuit having a partial pass gate transistor at the input of the master latch. The partial pass gate transistor includes a pull-up clock enabled transistor for selectively coupling a high output of a test switch to the input of the master latch. The input of the master latch is also directly coupled to a low output of the test switch around the partial pass gate. In addition, a revised circuit layout is provided in which the master latch has three inverters. A first inverter is coupled to the input of the master latch. Second and third inverters are coupled to an output of the first inverter, with the second inverter having an output coupled to the input of the first inverter, and the third inverter having an output coupled to an output of the master latch. The first and second inverters are clock enabled, and the third inverter is reset enabled.

IPC Classes  ?

• H03K 3/00 - Circuits for generating electric pulsesMonostable, bistable or multistable circuits
• H03K 3/3562 - Bistable circuits of the primary-secondary type
• G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only

Abstract

An embodiment circuit includes a first reference source configured to provide a first reference signal to an analog-to-digital convertor (ADC). The circuit also includes a filter coupled to an output of the first reference source and configured to filter the first reference signal to produce a filtered first reference signal. The circuit further includes a second reference source coupled to an output of the filter. The second reference source is configured to provide a second reference signal to the ADC, and the second reference signal is generated based on the filtered first reference signal.

IPC Classes  ?

• H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
• H03M 1/38 - Analogue value compared with reference values sequentially only, e.g. successive approximation type
• H03M 1/12 - Analogue/digital converters
• H03M 1/10 - Calibration or testing
• H03M 1/08 - Continuously compensating for, or preventing, undesired influence of physical parameters of noise
• H03M 1/16 - Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps
• H03M 1/44 - Sequential comparisons in series-connected stages with change in value of analogue signal