A data processing apparatus is provided in which receive circuitry receives a memory access instruction containing an indication of a target address. The target address is associated with one of a plurality of memory targets. Prediction circuitry performs a prediction of one of the plurality of memory targets to which the memory access instruction is associated, based on an address associated with the memory access instruction and forward circuitry forwards a memory access request based on the memory access instruction to the one of the plurality of memory targets.
An order controlling interconnect circuit node of a data processing system couples to an interconnect circuit of a network and to target nodes. The node includes transmitting interface circuitry, message receiving interface circuitry, and control circuitry. The control circuitry is configured to monitor incoming “ready” response messages at the message receiving circuitry and to control the message transmitting interface circuity to send a cancellation request message to the target node of the oldest write request of the one or more second write-push requests when a “ready” response message has not been received for the first write-push request within a designated time period. Subsequent to sending the cancellation request message, a continuation request message is to the target node of the oldest write-push request of the one or more second write-push requests when a “ready” response message has been received for the first write-push request.
An interconnect circuit comprises an unblock-request-receiving interconnect circuit node configured to receive a given write push request specifying write target data and write target address information identifying one or more addressed locations to which the write target data is to be written, and to enforce a requirement that a conflicting read request, which requests a read to one of the one or more addressed locations identified by the write target address information specified by the given write push request, is blocked from completing until an unblocking condition is satisfied for the given write push request, where for at least one type of write push request, satisfaction of the unblocking condition is dependent on an unblock request for the given write push request being received by the unblock-request-receiving interconnect circuit node; and an unblock-request-transmitting interconnect circuit node configured to transmit the given write push request to the unblock-request-receiving interconnect circuit node, and to transmit the unblock request for the given write push request in response to receipt of a completion response for an older write push request transmitted by the unblock-request-transmitting interconnect circuit node.
A data processing system is disclosed that includes a data processing unit and a codec unit. A set of addresses of an address space is associated with the codec unit, and the codec unit, in response to a request from the data processing unit to access an address of the set of addresses associated with the codec unit, provides decoded data to the data processing unit or causes data provided by the data processing unit to be encoded.
An apparatus comprises processing circuitry comprising execution units and issue circuitry to issue an instruction. In response to a consumer instruction identifying a source data operand, the issue circuitry identifies a set of one or more candidate producer instructions for the consumer instruction from a plurality of outstanding instructions that have not yet completed, each candidate producer instruction being capable of producing a data value to be used for the source data operand; and in a case where the set comprises two or more candidate producer instructions of which at least one candidate producer instruction is a conditional instruction to be executed in dependence on a respective condition being satisfied, prior to determining which of the two or more candidate producer instructions is an actual producer instruction that will produce the data value to be used for the source data operand, issues the consumer instruction to be executed.
There is provided an apparatus comprising processing circuitry to issue a memory access request specifying a target address. The apparatus comprises memory access control circuitry to control handling of the memory access request based on a memory access control attribute associated with the target address. The memory access control circuitry comprises attribute storage circuitry to store entries each identifying a region of address space and a memory access control attribute. The memory access control circuitry is responsive to the memory access request to perform a lookup in the attribute storage circuitry. The processing circuitry comprises current region identifying information indicative of a current region of address space and a current memory access control attribute. The processing circuitry is configured, when the target address is comprised in the current region, to indicate the current memory access control attribute to the memory access control circuitry, and to omit the lookup.
An apparatus includes offload circuitry to transmit to coprocessing circuitry an instruction packet comprising one or more instructions offloaded by processing circuitry for execution by the coprocessing circuitry; and packet merging circuitry to perform a packet merge. The packet merge includes determining whether the instruction packet has capacity to include one or more additional instructions offloaded by the processing circuitry for execution by the coprocessing circuitry; and including the one or more additional instructions in the instruction packet in response to determining that the instruction packet has capacity to include the one or more additional instructions.
An apparatus includes conditional branch future instruction processing circuitry configured to process a conditional branch future instruction, the conditional branch future instruction specifying a branch point, a branch condition, and a branch target, wherein the branch point is indicative of a point in program flow subsequent to the conditional branch future instruction where program flow is to conditionally branch to a point in program flow corresponding to the branch target dependent on satisfaction of the branch condition. The apparatus also includes branch condition evaluating circuitry configured to determine whether the branch condition is satisfied at a point in program flow subsequent to processing of the conditional branch future instruction, to determine whether the program flow is to branch from the branch point to the point in program flow corresponding to the branch target.
An apparatus includes decoding circuitry configured to decode instructions; processing circuitry configured to perform data processing operations in response to the instructions decoded by the decoding circuitry; extension processing circuitry configured to perform other data processing operations asynchronously with respect to data processing operations performed by the processing circuitry; an extension task offload interface separate from an interface by which the processing circuitry issues a memory system request to a memory system, wherein the extension task offload interface is responsive to at least one task offloading instruction decoded by the decoding circuitry to offload the other data processing operations to the extension processing circuitry; and resource allocation adjustment circuitry configured to adjust a resource allocation between the processing circuitry and the extension processing circuitry responsive to a resource adjustment indication.
Briefly, example apparatuses, articles of manufacture, and/or techniques are disclosed that may be implemented, in whole or in part, to implement, facilitate and/or support integrated circuitry comprising a chiplet having semiconductor circuitry corresponding to an active interface and an inactive interface, where the chiplet may further include contacts connected to the active interface circuitry.
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H03K 17/56 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices
There is described delay circuitry including: a pulse generator to generate a pulse responsive to receiving an input signal edge and to buffer and invert the input signal edge; and a signal output element to receive the pulse and the buffered and inverted signal edge from the pulse generator and to generate a delayed signal edge responsive to a trailing edge of the pulse and based on the buffered and inverted signal edge. In addition, there is described delay circuitry including: a buffer-inverter unit to receive, buffer and invert an input signal and to generate a delayed output signal, the buffer-inverter unit including a signal-controlled gate to invert the input signal arranged in series with a mode-controlled gate to pass the input signal. Finally, there is described apparatus including the delay circuitry and a flip flop.
H03K 5/135 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
Briefly, example apparatuses, articles of manufacture, and/or techniques are disclosed that may be implemented, in whole or in part, to implement, facilitate and/or support integrated circuitry comprising a plurality of central chiplets and a plurality wing chiplets.
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
13.
GRAPHICS PROCESSING APPARATUS AND METHOD FOR PERFORMANCE METRIC SAMPLING
A graphics processing apparatus includes a workload execution circuit to execute workloads and a performance counting circuit to count instances of performance metrics. A workload handling circuit receives commands and responds to performance counter sampling commands that indicate performance counter sampling contexts comprising performance metrics to be sampled and sampling intervals. The workload handling circuit monitors sampling intervals and triggers the workload execution circuit to write out sample values for performance metrics upon interval elapse. A driver receives performance metric sampling indications, allocates memory for sample values, generates performance counter sampling commands, and provides these to the workload handling circuit. The workload handling circuit writes out workload scheduling metadata, configures sampling according to sampling contexts, and manages the writing of sample values either directly to memory or back to the workload handling circuit with associated timestamp information.
There are provided apparatuses, methods, systems, chip-containing products and computer-readable storage media. Prefetching retrieves content from a memory system. History storage stores plural entries, each identifying a basic block of memory addresses, wherein the basic block of memory addresses is a contiguous range of memory addresses from which content has been requested to be retrieved from the memory system. An entry order of the plural entries corresponds to a basic block order in which corresponding basic blocks have been requested to be retrieved from the memory system. An entry-order-older basic block is associated with with an entry-order-younger basic block for which respective entries are stored in the history storage circuitry, these basic blocks being separated by at least a defined minimum number of entries in entry order in the history storage. A sequence of request addresses from which content is requested to be retrieved from the memory system is monitored. When a requested address corresponds to the entry-order-older basic block prefetching corresponding to the entry-order-younger basic block is triggered.
An apparatus includes a branch predictor to generate a prediction associated with a branch instruction outcome for a block of at least one instruction. The branch predictor includes: lookup circuitry configured to perform a lookup of stored prediction information to identify a plurality of prediction entries associated with alternative paths of program flow, the plurality of prediction entries comprising a main prediction entry to be used for generating the prediction and one or more alternative prediction entries each associated with an alternative path of program flow; prediction generation circuitry configured to generate the prediction based on the main prediction entry; and alternative prediction storage circuitry configured to store the one or more alternative prediction entries identified by the lookup circuitry; in which responsive to a flush signal indicative of the prediction being incorrect, the prediction generation circuitry is configured to generate an alternative prediction associated with the block of the at least one instruction based on the one or more alternative prediction entries stored by the alternative prediction storage circuitry.
An integrated circuit assembly comprises an integrated circuit die and a substrate electrically and physically coupled to the integrated circuit die. A capacitor is physically coupled to the substrate at a location physically between the integrated circuit die and the substrate, the capacitor electrically coupled to the integrated circuit die via at least one electrical connection.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
An apparatus comprises branch prediction circuitry to generate predictions in respect of a given block of one or more instructions, the predictions comprising at least a main path prediction in respect of a given branch instruction and at least one alternate path prediction in respect of an alternate path of program flow predicted to be followed if the main path prediction is incorrect. The branch prediction circuitry stores the at least one alternate path prediction in an alternate prediction cache. Block skipping circuitry is responsive to a flush signal indicative of the main path prediction being incorrect to control the branch prediction circuitry to begin generating predictions in respect of a subsequent block of instructions identified by a prediction resumption address, identified based on the at least one alternate path prediction which may indicate that the alternate path of program flow includes at least one taken branch.
G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
G06F 12/0875 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
18.
MULTI-TAKEN PREDICTION ENTRIES FOR PREDICTION RESUMPTION
An apparatus comprising prediction storage circuitry to store a plurality of prediction entries, each prediction entry indicative of whether a respective branch instruction is predicted to be taken or not taken. At least one prediction entry supports an encoding of a multi-taken entry indicating that the respective branch instruction and at least one subsequent branch instruction are each predicted to be taken. The apparatus also comprises prediction resumption circuitry to identify, based on stored information dependent on the multi-taken entry, a prediction resumption address in response to a flush signal, where the prediction resumption address is an address in respect of which at least one prediction is to be generated after the flush signal.
Processing circuitry 16 performs a stack pointer switch validity checking operation associated with a switch of the stack pointer from an outgoing stack pointer value to an incoming stack pointer value. The validity checking operation comprises verifying whether an incoming data value obtained by memory access circuitry 26 in response to a memory access request specifying an address determined based on the incoming stack pointer value meets at least one stack cap value validity condition, including a condition that a predetermined portion of the incoming data value corresponds to a given page address indicative of a page of address space comprising the address determined based on the incoming stack pointer value. The at least one stack cap value validity condition is determined independent of whether a further portion of the incoming data value other than the predetermined portion corresponds to sub-page address bits of the address determined based on the incoming stack pointer value. An error handling response is triggered in response to determining that the incoming data value fails to meet the at least one stack cap value validity condition.
Exception control circuitry (40) controls taking of exception by processing circuitry (4), depending on control information stored in at least one register (14), the control information including masking control information settable to a masked state or unmasked state; and trap-masked-exception control information settable to an untrapped state or trapped state. In response to a given exception of a maskable class of exceptions, in at least one scenario when the masking control information is in the masked state and a current exception level is less privileged than a predetermined trap target exception level, the exception control circuitry controls whether to trap the given exception to the predetermined trap target exception level depending on whether the trap-masked-exception control information is in the trapped state. When the masking control information is in the unmasked state, a target exception level for handling the given exception is selected independent of the trap-masked-exception control information.
An integrated circuit assembly comprises an integrated circuit die and a substrate electrically and physically coupled to the integrated circuit die. A capacitor is physically coupled to the substrate at a location physically between the integrated circuit die and the substrate, the capacitor electrically coupled to the integrated circuit die via at least one electrical connection.
An apparatus comprises bridge circuitry configured to bridge between a memory system interconnect and a port controller. In a first state, the bridge circuitry is configured to control the internal communication link interface to transmit a given type of packet to the port controller using a first type of credit. In a second state, the bridge circuitry is configured to control the internal communication link interface to transmit the given type of packet to the port controller without using the first type of credit. The first type of credit represents availability of buffer storage at the link partner.
There is provided an apparatus comprising bridge circuitry to couple processing circuitry to an allocated subset of a plurality of port controllers for connecting the processing circuitry to link partners. The bridge circuitry is configured to perform a data transfer between the processing circuitry and the allocated subset according to a bandwidth quota. The apparatus is provided with control circuitry to receive configuration information identifying the allocated subset, and to allocate a bandwidth share to each port controller identified in the allocated subset. The control circuitry is configured to determine the bandwidth share based on the configuration information. The control circuitry is configured, for each given port controller identified in the allocated subset, to implement a restriction to limit the data transfer between the given port controller and the processing circuitry according to the bandwidth share allocated to the given port controller.
There is provided an apparatus comprising storage circuitry to store a plurality of entries each identifying a corresponding contiguous range of addresses spanning one or more of a plurality of addressable regions. Content stored at each of the plurality of addressable regions is individually retrievable by fetch circuitry. The apparatus is also provided with control circuitry to store information indicative of a candidate new entry identifying a contiguous range of addresses. The control circuitry is responsive to receipt of an indication of a memory access request specifying an addressable region other than one of the plurality of addressable regions which is both contiguous with and subsequent to the contiguous range of addresses, to determine if the addressable region is within a predefined range. The control circuitry is responsive to the addressable region being within the predefined range, to modify the contiguous range of addresses to include the addressable region.
G06F 12/0811 - Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
G06F 12/0862 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
A method performed by an information processing apparatus is provided. The method may comprise obtaining input data, determining a parameter value of an input data parameter associated with the input data, and configuring a machine learning model to the parameter value, comprising determining a set of inference model parameters associated with the determined parameter value by performing either of: (i) interpolating model parameter values from two or more sets of model parameters to obtain the set of inference model parameters, each set being associated with a respective reference value of the input data parameter, or (ii) applying a second machine learning model to the parameter value to obtain the inference model parameters. The method may further comprise processing the input data using the configured machine learning model to generate output data associated with the parameter value comprising applying the inference model parameters to the input data.
An apparatus comprises bridge circuitry configured to bridge between a memory system interconnect and a port controller. In a first state, the bridge circuitry is configured to control the internal communication link interface to transmit a given type of packet to the port controller using a first type of credit. In a second state, the bridge circuitry is configured to control the internal communication link interface to transmit the given type of packet to the port controller without using the first type of credit. The first type of credit represents availability of buffer storage at the link partner.
There is provided an apparatus comprising bridge circuitry to couple processing circuitry to an allocated subset of a plurality of port controllers for connecting the processing circuitry to link partners. The bridge circuitry is configured to perform a data transfer between the processing circuitry and the allocated subset according to a bandwidth quota. The apparatus is provided with control circuitry to receive configuration information identifying the allocated subset, and to allocate a bandwidth share to each port controller identified in the allocated subset. The control circuitry is configured to determine the bandwidth share based on the configuration information. The control circuitry is configured, for each given port controller identified in the allocated subset, to implement a restriction to limit the data transfer between the given port controller and the processing circuitry according to the bandwidth share allocated to the given port controller.
Disclosed is a graphics processor that comprises a plurality of processing cores and a cache that is operable to transfer data between the processing cores and a memory that the graphics processor has access to. Access logic is provided to control how memory accesses issued by the processing cores are distributed across the cache slices. The cache slice that is used for a memory access is determined using a function computed by the access logic based on one or more properties associated with the memory access, and the function can be changed over time to vary how memory accesses from the plurality of processing cores are distributed across the plural cache slices.
An apparatus comprises: an external port controller to control communication, via an external communication link for communicating with a link partner, of external link protocol packets defined according to an external link protocol; and bridge circuitry to map between the external link protocol packets and memory system interconnect transactions defined according to a memory system interconnect protocol used by a memory system interconnect. The bridge circuitry and the external port controller are coupled via an internal communication link and use an internal link protocol to transport the external link protocol packets between the bridge circuitry and external port controller. The bridge circuitry comprises transaction ordering circuitry to enforce external link protocol transaction ordering rules imposed by the external link protocol to restrict ordering between respective data access transactions corresponding to external link protocol packets communicated with the link partner on the external communication link.
40 - Treatment of materials; recycling, air and water treatment,
Goods & Services
Custom manufacturing of chips [integrated circuits] for others; Custom manufacture of semiconductor wafers; Custom manufacture of semiconductor circuits; Custom manufacture of semiconductor components; Encapsulation of semiconductors.
40 - Treatment of materials; recycling, air and water treatment,
Goods & Services
Custom manufacturing of chips [integrated circuits] for others; Custom manufacture of semiconductor wafers; Custom manufacture of semiconductor circuits; Custom manufacture of semiconductor components; Encapsulation of semiconductors.
An apparatus comprising processing circuitry configured to generate an instruction for configuring a hardware accelerator to perform a task. The instruction comprises a predefined set of fields comprising a control field indicative of a selected set of fields of the predefined set of fields to be provided to the hardware accelerator to configure the hardware accelerator to perform the task. The apparatus comprises accelerator control interface circuitry configured to exchange messages, each with a size less than or equal to a predefined size, with the hardware accelerator. To configure the hardware accelerator to perform the task, the accelerator control interface circuitry is configured to send the selected set of fields to the hardware accelerator, using a set of command messages with a combined size greater than the predefined size. The application further relates to a hardware accelerator.
An apparatus comprising storage, an execution unit and a handling unit. The handling unit is configured to obtain task data that describes a task to be executed. The task comprises a plurality of operations representable as a directed graph of operations. The task data comprises task-specific variable data representative of a task-specific variable for use in executing an operation of the plurality of operations. The handling unit is configured to obtain a data move instruction and, based on the data move instruction, move the task-specific variable data into a physical storage location of the storage. The handling unit is configured to dispatch invocation data, based on the task data and the physical storage location, to the execution unit to cause the execution unit to execute the operation.
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
Goods & Services
Integrated circuits; semiconductors; system-on-chip devices;
microprocessors; processors [central processing units];
microprocessors in the field of artificial intelligence;
neural network processors; electronic chips;
application-specific integrated circuits; graphics
processing units; semiconductor intellectual property cores;
computer interfaces, namely instruction set architectures;
printed circuit boards; semiconductors, microprocessors for
Internet of Things (IOT) devices; computer software for
integrated circuits; downloadable computer operating
software; computer hardware and recorded computer software,
namely, computer subsystems featuring standardized and
optimized hardware and software components for providing
specific levels of computing performance and functionality
sold as a unit; electronic downloadable materials, namely,
electronic downloadable instruction and development manuals,
datasheets and brochures, all in the area of design and
development of integrated circuits, microprocessors,
microprocessor cores, macro cells, microcontrollers, bus
interfaces, and printed circuit boards. Design of semiconductors, microprocessors, system-on-chip
devices, processors [central processing units], chips
[integrated circuits], application-specific integrated
circuits, graphics processing units, machine learning
processors and semiconductor cores; research, development,
and design relating to computer hardware for semiconductor
intellectual property, instruction set architectures,
microprocessors; research, development and design, all
relating to computer software used in, and for use in the
design, verification and construction of microprocessors,
processors, microcontrollers, microprocessor design files,
semiconductor intellectual property cores, computer hardware
accelerators, neural network processors and machine learning
processors.
Doorbell physical interrupt control circuitry (20) comprises interrupt detection circuitry (22) to detect an incoming interrupt to be raised as a given virtual interrupt (having a given priority) for a given virtual interrupt handling context, and doorbell physical interrupt generation circuitry (24) responsive to detection of the incoming interrupt by the interrupt detection circuitry, to determine whether the given priority of the given virtual interrupt is indicated, by doorbell-enabled-priority configuration data (28), as enabled for doorbell physical interrupt generation, and if so, to generate a doorbell physical interrupt to be processed in a given physical interrupt handling context. The doorbell physical interrupt indicates to a physical processor handling interrupts for the given physical interrupt handling context that the given virtual interrupt is pending for the given virtual interrupt handling context.
A reset generation manager (RGM) of a first die, of a data processing system with two or more dies, has a local state and is configured to observe a remote state of an RGM of at least one second die of the data processing system. The RGM of the first die is configured to transition the local state to a next state when the local state lags the remote state and wait for the remote state to catch up to the local state when the local state leads the remote state. A recovery action may be performed when the remote state is out of synchronization with the local state, or when the RGM of the first die remains in a non-functional state for too long. Operating states of the RGM may include a first functional state, a first resetting state, a second functional state, and a second resetting state.
An apparatus comprises training storage circuitry to store one or more training entries, each training entry associated with a target instruction and storing training data corresponding to the target instruction. Training circuitry is configured to update the training data of the one or more training entries based on monitoring sequences of instructions, and prediction circuitry is configured to make a prediction in respect of a given target instruction based on given training data corresponding to the given target instruction. Selection circuitry is configured to select which target instructions are associated with the one or more training entries of the training storage circuitry, wherein the selection circuitry is responsive to a determination that a candidate instruction is a biased instruction, to select the biased instruction with a higher priority for storage in a training entry of the training storage circuitry than at least one non-biased instruction.
A method is described for processing a neural network. The method comprises generating a Winograd neural network by applying a Winograd convolution to at least a portion of one or more layers of the neural network and quantizing at least one operation in the Winograd convolution. The Winograd neural network is trained with at least two of a weight scale matrix, a data scale matrix, and an output scale matrix as trainable parameters by comparing an output of the neural network and an output of the Winograd neural network and adjusting the trainable parameters to generate a trained Winograd neural network. The method generates data, such as trained scale matrices, to process the trained Winograd neural network on a processing unit.
An apparatus comprising processing circuitry configured to generate an instruction for configuring a hardware accelerator to perform a task. The instruction comprises a predefined set of fields comprising a control field indicative of a selected set of fields of the predefined set of fields to be provided to the hardware accelerator to configure the hardware accelerator to perform the task. The apparatus comprises accelerator control interface circuitry configured to exchange messages, each with a size less than or equal to a predefined size, with the hardware accelerator. To configure the hardware accelerator to perform the task, the accelerator control interface circuitry is configured to send the selected set of fields to the hardware accelerator, using a set of command messages with a combined size greater than the predefined size. The application further relates to a hardware accelerator.
Storage circuitry devices, systems, and methods including a bitcell array having a plurality of bitcells, each bitcell accessible via a bitline and wordline, where the bitcell array is provided at a first layer of the storage circuitry; a redundant array associated with the bitcell array, the redundant array having a plurality of redundant bitcells, each redundant bitcell accessed via a redundant bitline and redundant wordline, where the bitcell array is provided at a second layer of the storage circuitry.
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
There is provided an apparatus comprising training storage circuitry configured to store training entries, each comprising training data indicative of a trigger memory access request to local storage. The apparatus comprises filter circuitry to generate a filtered sequence of memory access requests by applying a filter to a sequence of memory access requests. The apparatus comprises training circuitry to monitor the filtered sequence, and responsive to observation of the trigger memory access request indicated in a training entry, to update the training data in the training entry. The filter circuitry is configured for each memory access request of the sequence that resulted in a hit on a data item in the local storage, to include the memory access request in the filtered sequence in dependence on a filter criterion independent of a type of request that resulted in the data item being allocated to the local storage.
The present disclosure relates generally to multi-processor arrangements and, more particularly, to dynamic frequency adjustments for multi-chiplet arrangements.
An apparatus comprises a plurality of hardware counters each corresponding to a separate sub-range of a contiguous range of target values, and histogram control circuitry to perform an indexing operation to identify and increment a selected hardware counter corresponding to a selected sub-range comprising an input value. Responsive to a histogram range update trigger, adding circuitry adds a count value of one or more first hardware counters corresponding to one or more first sub-ranges to a second hardware counter corresponding to a second sub-range neighbouring the one or more first sub-ranges, and the histogram control circuitry updates a previous indexing operation to an updated indexing operation, wherein the updated indexing operation identifies one of the one or more first hardware counters in response to an input value lying within a newly defined sub-range of the contiguous range of target values.
An apparatus comprising storage, an execution unit and a handling unit. The handling unit is configured to obtain task data that describes a task to be executed. The task comprises a plurality of operations representable as a directed graph of operations. The task data comprises task-specific variable data representative of a task-specific variable for use in executing an operation of the plurality of operations. The handling unit is configured to obtain a data move instruction and, based on the data move instruction, move the task-specific variable data into a physical storage location of the storage. The handling unit is configured to dispatch invocation data, based on the task data and the physical storage location, to the execution unit to cause the execution unit to execute the operation.
An apparatus comprises processing circuitry configured to perform data processing in response to instructions executed in one of a plurality of exception levels supported by the processing circuitry; a plurality of system registers configured to store system register state information; and at least one system register lockdown control register, writable in response to an instruction executed in a predetermined exception level other than a most privileged exception level, and configured to store lockdown control information for controlling updates to a subset of the system register state information. The lockdown control information specifies, for each item of system register state information in the subset, whether that item is in a locked state or unlocked state. In response to a system register update instruction executed in the predetermined exception level requesting an update to a target item of system register state information from the subset of system register state information, when the lockdown control information specifies that the target item of system register state information is in the locked state, the processing circuitry suppresses the update to the target item of system register state information.
A training input tensor and a ground truth output are received in a neural network that comprises a kernel and an associated dilation factor. A predicted output is provided from the neural network based, at least in part, on applying the kernel and the dilation factor to the input tensor. The neural network is trained by modifying the kernel and the associated dilation factor to reduce an error between the predicted output and the ground truth output. The neural network may comprise a different dilation factor per kernel and/or per layer.
G06V 10/774 - Generating sets of training patternsBootstrap methods, e.g. bagging or boosting
G06V 10/77 - Processing image or video features in feature spacesArrangements for image or video recognition or understanding using pattern recognition or machine learning using data integration or data reduction, e.g. principal component analysis [PCA] or independent component analysis [ICA] or self-organising maps [SOM]Blind source separation
G06V 10/82 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using neural networks
Direct Cache Transfer is enabled in a multi-chip data processing apparatus which one or more links do not support forwarding snoop requests. A gateway of a link in the multi-chip data processing apparatus is configured to intercept data messages. A data message is generated when a request node of a network sends a data request to a home node, and the home node sends a corresponding snoop request to a snoop target. When the gateway determines that a data message is associated with a response to a forwarding snoop request from a home node, the message is rerouted to the request node, bypassing the home node.
Storage circuitry including a bitcell array including a plurality of bitcells arranged in one or more columns and one or more rows, a first bitline to select bitcells of a first column, a first dummy bitline associated with the first bitline, where the first dummy bitline includes dummy control circuitry having a plurality of electrical paths arranged between the dummy bitline and a first voltage level, where a first electrical path of the plurality of electrical paths includes a first load electrically couplable thereto to control a property of a dummy bitline signal.
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
A data processing apparatus is provided in which initial processing circuitry executes program instructions - each of the program instructions relating to one or more confidential virtual machines. Initial storage circuitry stores data pages belonging to the one or more confidential virtual machines. Management circuitry causes a migration of a migrating confidential virtual machine of the confidential virtual machines to subsequent processing circuitry so that a future execution of those of the program instructions associated with the migrating confidential virtual machine are executed by the subsequent processing circuitry instead of the initial processing circuitry. The management circuitry causes the migration by causing one of the data pages belonging to the migrating confidential virtual machine to be migrated from the initial storage circuitry to subsequent storage circuitry. Confidential access circuitry accesses the data pages belonging to the migrating confidential virtual machine to determine the one of the data pages. The data pages are unreadable by the management circuitry.
An apparatus has history storage for maintaining history information comprising a sequence of history indicators generated during execution of a program by processing circuitry, and update circuitry, responsive to a given update event detected during execution of the program, to generate a history indicator associated with the given update event, and to update the history information using the generated history indicator. Prediction circuitry, responsive to a given prediction event detected during execution of the program, uses at least a portion of the history information to identify prediction information and generates a prediction associated with the given prediction event in dependence on the identified prediction information. The update circuitry is configured to detect whether an aliasing concern condition is present indicating that the history information may be insufficient, for at least one prediction event, to enable the prediction circuitry to discriminate between different contexts of that at least one prediction event that are dependent on execution history of the program. Absent detection of the aliasing concern condition, the update circuitry performs a default indicator generation operation to generate the history indicator associated with the given update event, but when the aliasing concern condition is detected, it instead performs a modified indicator generation operation to generate the history indicator associated with the given update event.
An interpolated output frame may be generated by generating a preceding warped motion vector frame from a preceding image frame and a following warped motion vector frame from a following image frame using motion vectors. A preceding warped optical flow frame is also generated from a preceding image frame and a following warped optical flow frame is generated from a following image frame using optical flow. Blending parameters are predicted, associated with each of the motion vector frames and the optical flow frames for blending the motion vector frames and the optical flow frames to generate an interpolated output frame. Either the motion vector frames or the optical flow frames are blended using the predicted blending parameters for each pixel in the interpolated output frame, based on whether a highest blending parameter for the pixel is associated with a motion vector frame or an optical flow frame.
Image signal values of an image are received as an input tensor in a kernel predicting neural network, the kernel predicting neural network trained to predict parameters for determining a plurality of sampling positions for application of an atrous filter kernel to the image. An output is provided from the kernel predicting neural network, comprising a sparse or atrous filter kernel comprising parameters for determining a plurality of sampling positions.
An integrated circuit assembly comprises a plurality of die connection points configured to couple to an integrated circuit die, and a plurality of external connection points configured to couple to external circuitry. A metal power signal trace and a metal ground signal trace are each coupled to at least a respective one of the plurality of die connection points to provide electrical power to the integrated circuit. A first metal-insulator-metal capacitor comprises a plurality of first extensions interleaved with a plurality of extensions of the metal power signal trace and is separated from the plurality of extensions of the metal power signal trace by an insulator. A second metal-insulator-metal capacitor comprises a plurality of second extensions interleaved with a plurality of extensions of the metal ground trace and is also separated from the plurality of extensions of the metal ground trace by an insulator.
H02M 3/06 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider
H02M 3/137 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
Write gathering circuitry of a data processing network is configured to receive data streams of cracked writes transmitted across an interconnect. Each data stream is associated with a stream identifier. The write gathering circuitry includes write gathering buffers configured to gather cracked writes from the interconnect in accordance with a stream identifier until the last write of a stream is gathered, the write gathering buffer fills, or the write gathering buffer is evicted for re-use. The gathered writes are transmitted in a gathered write burst via an external interface to the target endpoint of the data processing network. When the write gathering buffer that was allocated to the stream identifier is full, a new write gathering buffer is allocated to the stream identifier, and the new write gathering buffer is marked as a child write gathering buffer of the filled write gathering buffer.
A computing device and a method of operating a computing device, implementable as a computer program product, the method including first operating a first transceiver in the computing device to collect a first biosensor device data element into a storage and processing location; second operating the first or a second transceiver to collect a second biosensor device data element into the storage and processing location; applying, in the storage and processing location, machine learning model inferencing over at least the first biosensor device data element and the second biosensor device data element to derive a user condition indication for a biosensor device user; and on detecting, in the user condition indication, a predictive value above a threshold indicating a user condition requiring notification, emitting a message at an output of the computing device, where the user condition requiring notification includes one or both of a physical and mental condition.
G16H 40/67 - ICT specially adapted for the management or administration of healthcare resources or facilitiesICT specially adapted for the management or operation of medical equipment or devices for the operation of medical equipment or devices for remote operation
G16H 10/60 - ICT specially adapted for the handling or processing of patient-related medical or healthcare data for patient-specific data, e.g. for electronic patient records
56.
Systems, Methods, and Devices of Design-For-Test Circuitry
A circuit for design-for-test (DFT)-mixing and internal clock pulse generation in test and functional modes includes a tristate inverter; a reset circuitry; and a clamp circuitry, where such clamp circuitry is configured for design-for-test (DFT)-mixing. A method for design-for-test DFT-mixing includes: in a test mode, providing a DFT information signal to a circuit; in response to receiving a clock signal at a clamp circuitry, retaining the DFT information signal at the clamp circuitry; and in response to a transition of the clock signal, deactivating the clamp circuitry and generating an internal clock pulse. A method for DFT-mixing includes: in a functional mode, providing, from a tristate inverter, a CTR signal on a critical path of a circuit; in response to an external clock signal, receiving at a logic circuitry coupled to the critical path, at least the CTR signal; and generating, by a first stage of the logic circuitry, an internal clock pulse.
A method of operating a processor having a permanent fault; the method including: receiving, at a controller, an indication that a permanent fault is detected in a processing unit of the processor; generating, by the controller and in response to the indication, a workload allocation scheme to allocate a workload among processing units in which no permanent fault is detected; instructing, by the controller, the processor to process the workload according to the workload allocation scheme. A host processor configured to execute a driver to allocate a workload among processing units of a subject processor in response to a permanent fault. A processor including a plurality of processing units and controller circuitry configured, responsive to an indication from fault detection circuitry, to communicate with fault detection circuitry and to allocate a workload among processing units of a subject processor.
The present disclosure relates generally to multi-processor arrangements and, more particularly, to dynamic frequency adjustments for multi-chiplet arrangements.
There is provided tensor processing circuitry comprising a plurality of dot-product units, each of which is configured to perform a multiply accumulate operation. A format conversion unit is configured to convert the format of a first data element before processing by the plurality of dot product units. The format conversion unit is configured to convert the first data element from a first data format to one or more data elements in a second floating point data format, the first data format being one of a plurality of data formats supported by the tensor processing circuitry and the second data format being a predefined floating-point data format in which data elements are input to the dot-product units. If the first data format is a higher precision data format than the second floating-point data format, the format conversion unit generates two or more data elements in the second floating-point data format.
G06F 7/483 - Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
An apparatus comprises processing circuitry comprising a plurality of execution units; issue circuitry to issue an instruction to be executed by the processing circuitry during a plurality of pipeline stages such that younger instructions are not permitted to be issued before older instructions and scheduling circuitry to schedule instructions for execution in a given cycle during the plurality of pipeline stages, such that the instruction is permitted to be executed in an order different to a program order in response to input operand data being available, by dynamically allocating which of the plurality of pipeline stages a given execution unit of the plurality of execution units is assigned to in the given cycle. In a configuration selectable for the given cycle, the scheduling circuitry causes the given execution unit of the plurality of execution units to be assigned to any pipeline stage of the plurality of pipeline stages.
There is provided an apparatus, a system, a chip containing product, a method, and a computer-readable medium. The apparatus comprises training storage circuitry to store training entries, each comprising training data indicative of a trigger operation and one or more relationships between the trigger operation and operations observed subsequent to the trigger operation. The apparatus comprises training circuitry to monitor operations during a training period having a predefined training duration, and responsive to observation of the trigger operation indicated in a training entry, to update the training data in the training entry. The training storage circuitry is configured to maintain update information associated with each training entry indicating whether that training entry has been updated during the training period. The training circuitry is responsive to a determination that the update information for a given training entry meets a predetermined condition, to truncate the training period for the given training entry.
A graphics processing system that is operable to perform ray tracing using micromaps is disclosed. A tree representation of a micromap is generated, and when it is desired to determine whether and/or how a ray interacts with a sub-region of a primitive, the tree representation of the micromap is traversed to determine a property value for the sub-region of the primitive.
Methods and apparatus for compressing and decompressing weight values associated with neural networks. Input weight values are divided into groups, with each group being processed using a scale factor. For each group of scaled input weight values, a codebook is identified from multiple codebooks, where each codebook represents a discrete set of centroid values. Input weight values within each group are encoded using centroid values from the identified codebook, resulting in encoded weight values comprising codebook indices and centroid indices. During decompression, the encoded weight values are processed to reconstruct output weight values using the corresponding codebooks and scale factors. The codebooks are generated by identifying similar distributions of scaled input weight values across different groups and clustering these values to determine centroid values. A processing element performs the decompression operations to reconstruct the weight values for use in neural network operations.
Image data includes a plurality of data values arranged in two or more sequences, each sequence comprising a first number of data positions each having a data value of the plurality, and each data value comprising a second number of bits. Upon receiving each sequence of the two or more sequences, the data values of the sequence are processed to determine, for each given data position of the first number of data positions, a representative value for the given data position based on a relationship between the data value at the given data position and the data value at one or more neighbouring data positions.
A graphics processing unit (GPU) comprises instruction decoding circuitry configured to decode instructions according to a GPU instruction set architecture; and processing circuitry configured to perform data processing in response to instructions decoded by the instruction decoding circuitry. In response to a masked load/store instruction specifying an address operand and a register bitmask operand specifying a plurality of mask bitfields, each mask bitfield corresponding to a register group of one or more registers and indicating whether that register group is masked or non-masked, the instruction decoding circuitry controls the processing circuitry to perform a load/store operation in respect of each register within a target set of registers identified based at least on the register bitmask operand. The register bitmask operand indicates which register groups are masked register groups which are permitted to be excluded from the target set of registers. The load/store operation for a given register in the target set of registers comprising transferring data between the given register and a memory system location determined based on the address operand.
A processor comprising storage, execution circuitry and a handling unit. The handling unit is configured to obtain operation data indicative of an operation to be executed using the execution circuitry. The execution circuitry is configured to operate over a multi-dimensional nested loop defining an operation space. The handling unit obtains a dimensional combination instruction and, in response, combines a plurality of dimensions of the operation space to obtain a local space dimension in an operation-specific local space as part of a procedure to map each operation block of a plurality of operation blocks in the operation space to a different respective local block in the local space dimension. The handling unit dispatches invocation data for the plurality of operation blocks to the execution circuitry. The invocation data for each respective operation block specifies a local space dimension range of a local block to be operated on for the respective operation block.
A graphics processing system that provides a micromap defining property values for sub-regions of a primitive of a scene to be rendered; and generates a first tree representation of the micromap; and applies a first barycentric rotational transform to the micromap and for the first barycentric rotational transform generates a second tree representation of the micromap; and selects one of the first or second tree representations for processing as the selected tree representation. The selected tree representation of a micromap is used when it is desired to determine whether and/or how a ray interacts with a sub-region of a primitive, the tree representation of the micromap is traversed to determine a property value for the sub-region of the primitive.
A processor comprising a neural processing unit is provided. The neural processing unit comprises a local storage and a handling unit configured to generate invocation data to cause loading of a block of a tensor into the local storage from a storage of the processor. The tensor has a first predetermined number of dimensions, and the block of the tensor has a size of one in one or more of the first predetermined number of dimensions such that the block consists of tensor elements arrayed in a second predetermined number of dimensions that is fewer than the first predetermined number of dimensions. A storage access controller configured to receive the invocation data and load data of the identified block into the local storage.
A processor comprises a handling unit configured to issue invocation data to a storage access controller to load multi-dimensional bricks from the tensor. The multidimensional bricks comprise a brick of primary data and a brick of auxiliary data. The storage access controller configured to: identify a location of the brick of primary data in the storage of the processor using one or more stride of the primary data in one or more dimension of the tensor, load the brick of primary data from the identified location, determine one or more virtual strides for one or more dimensions of the auxiliary data based on the one or more strides of the primary data, identify a location of the brick of auxiliary data in the first storage using the determined one or more virtual strides, and load the brick of the auxiliary data from the identified location.
A tensor processing circuitry comprising a plurality of dot product units and normalization circuitry. Each dot product unit comprises first-stage circuitry and second-stage circuitry. The first-stage circuitry is configured to receive a plurality of input values and perform at least a multiply-accumulate operation on pairs of the plurality of input values, the multiply-accumulate operation produces an output value in a unnormalized floating-point format. The second stage circuitry is configured to receive a plurality of the unnormalized floating-point output values from the first stage circuitry and perform an accumulate operation on each of the received unnormalized floating-point output values to generate an unnormalized result. The unnormalized result of the accumulate operation is then output to the normalization circuitry which normalizes the unnormalized results.
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
G06F 5/01 - Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
An apparatus comprises instruction decoding circuitry and processing circuitry. In response to a permute prefix instruction specifying at least one permute source vector register and a destination vector register, the instruction decoding circuitry is configured to generate a micro-operation to control the processing circuitry to perform at least a permute operation to permute vector elements of at least one permute source vector operand specified by the at least one permute source vector register to generate a permuted vector operand corresponding to the destination vector register. The permute prefix instruction has an encoding providing an instruction fusion hint indicating to the instruction decoding circuitry that a next instruction in program order after the permute prefix instruction is expected to be a vector processing instruction specifying, as a source vector register for defining a source vector operand to which a vector processing operation is to be applied, the destination vector register of the permute prefix instruction.
A tensor processing circuitry comprising a plurality of dot product units and normalization circuitry. Each dot product unit comprises first-stage circuitry and second-stage circuitry. The first-stage circuitry is configured to receive a plurality of input values and perform at least a multiply-accumulate operation on pairs of the plurality of input values, the multiply-accumulate operation produces an output value in a unnormalized floating-point format. The second stage circuitry is configured to receive a plurality of the unnormalized floating-point output values from the first stage circuitry and perform an accumulate operation on each of the received unnormalized floating-point output values to generate an unnormalized result. The unnormalized result of the accumulate operation is then output to the normalization circuitry which normalizes the unnormalized results.
G06F 7/483 - Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
A processor comprises a handling unit configured to issue invocation data to a storage access controller to load multi-dimensional bricks from the tensor. The multidimensional bricks comprise a brick of primary data and a brick of auxiliary data. The storage access controller configured to: identify a location of the brick of primary data in the storage of the processor using one or more stride of the primary data in one or more dimension of the tensor, load the brick of primary data from the identified location, determine one or more virtual strides for one or more dimensions of the auxiliary data based on the one or more strides of the primary data, identify a location of the brick of auxiliary data in the first storage using the determined one or more virtual strides, and load the brick of the auxiliary data from the identified location.
A processor comprising storage, execution circuitry and a handling unit. The handling unit is configured to obtain task data that describes a task to be executed. The task comprises a plurality of operations representable as a directed graph of operations comprising operations connected by connections corresponding to respective logical storage locations. In executing the task, the execution circuitry is configured to operate over a multi-dimensional nested loop. The task data comprises operation-specific control data for an operation of the operations, the operation-specific control data providing an indication, for each respective dimension of a plurality of dimensions of the multi-dimensional nested loop on a per-dimension basis, of whether the operation is to be executed for each iteration of a plurality of iterations over the respective dimension. The handling unit manages execution of the operation, using the execution circuitry, based on the operation- specific control data.
A graphics processor is disclosed. A packet processing unit of the graphics processor processes an input packet of primitives by subjecting the input packet to one or more processing operations, and storing data produced by the one or more processing operations in local storage. The packet processing unit stores a corresponding output packet of primitives in memory by allocating an amount of memory space for storing the output packet based on an amount of data produced by the one or more processing operations stored in the local storage, and storing the output packet in the allocated memory space.
A processor comprising storage, execution circuitry and a handling unit. The handling unit is configured to obtain operation data indicative of an operation to be executed using the execution circuitry. The execution circuitry is configured to operate over a multi-dimensional nested loop defining an operation space. The handling unit obtains a dimensional combination instruction and, in response, combines a plurality of dimensions of the operation space to obtain a local space dimension in an operation-specific local space as part of a procedure to map each operation block of a plurality of operation blocks in the operation space to a different respective local block in the local space dimension. The handling unit dispatches invocation data for the plurality of operation blocks to the execution circuitry. The invocation data for each respective operation block specifies a local space dimension range of a local block to be operated on for the respective operation block.
G06F 7/14 - Merging, i.e. combining at least two sets of record carriers each arranged in the same ordered sequence to produce a single set having the same ordered sequence
A processor comprising storage, execution circuitry and a handling unit. The handling unit is configured to obtain task data that describes a task to be executed. The task comprises a plurality of operations representable as a directed graph of operations comprising operations connected by connections corresponding to respective logical storage locations. In executing the task, the execution circuitry is configured to operate over a multi-dimensional nested loop. The task data comprises operation-specific control data for an operation of the operations, the operation-specific control data providing an indication, for each respective dimension of a plurality of dimensions of the multi-dimensional nested loop on a per-dimension basis, of whether the operation is to be executed for each iteration of a plurality of iterations over the respective dimension. The handling unit manages execution of the operation, using the execution circuitry, based on the operation-specific control data.
40 - Treatment of materials; recycling, air and water treatment,
Goods & Services
Custom manufacturing of chips [integrated circuits] for others; Custom manufacture of semiconductor wafers; Custom manufacture of semiconductor circuits; Custom manufacture of semiconductor components; Encapsulation of semiconductors
40 - Treatment of materials; recycling, air and water treatment,
Goods & Services
Custom manufacturing of computer chips being integrated circuits for others; Custom manufacture of semiconductor wafers; Custom manufacture of semiconductor circuits; Custom manufacture of semiconductor components; Encapsulation of semiconductors
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
Goods & Services
(1) Integrated circuits; semiconductors; system-on-chip devices; microprocessors; processors [central processing units]; microprocessors in the field of artificial intelligence; neural network processors; electronic chips; application-specific integrated circuits; graphics processing units; semiconductor intellectual property cores; computer interfaces, namely instruction set architectures; printed circuit boards; semiconductors, microprocessors for Internet of Things (IOT) devices; computer software for integrated circuits; downloadable computer operating software; computer hardware and recorded computer software, namely, computer subsystems featuring standardized and optimized hardware and software components for providing specific levels of computing performance and functionality sold as a unit; electronic downloadable materials, namely, electronic downloadable instruction and development manuals, datasheets and brochures, all in the area of design and development of integrated circuits, microprocessors, microprocessor cores, macro cells, microcontrollers, bus interfaces, and printed circuit boards. (1) Design of semiconductors, microprocessors, system-on-chip devices, processors [central processing units], chips [integrated circuits], application-specific integrated circuits, graphics processing units, machine learning processors and semiconductor cores; research, development, and design relating to computer hardware for semiconductor intellectual property, instruction set architectures, microprocessors; research, development and design, all relating to computer software used in, and for use in the design, verification and construction of microprocessors, processors, microcontrollers, microprocessor design files, semiconductor intellectual property cores, computer hardware accelerators, neural network processors and machine learning processors.
A circuit for level-shifting includes a pulse-shaper circuit comprising a first PMOS transistor; and a level-shifting circuit, where the first PMOS transistor is configured to precharge a node on a wordline generation path of the level-shifting circuit. Also, a method of level-shifting includes detecting, at a PMOS transistor of a pulse-shaping circuit, a falling edge of a clock signal; and generating, by the pulse-shaping circuit, a pulse to activate the PMOS transistor to precharge a node on a wordline generation path of a level-shifting circuit. Another circuit for level-shifting includes a first PMOS transistor; and a level-shifting circuitry, where the circuit is configured to generate a pulse on a second voltage domain from a clock signal on a first voltage domain.
H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only
G11C 8/06 - Address interface arrangements, e.g. address buffers
G11C 8/08 - Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
G11C 8/18 - Address timing or clocking circuitsAddress control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
H03K 5/135 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
A circuit to precharge a dummy wordline includes a first branch comprising first and second PMOS devices; and a second branch comprising a single PMOS device. Also, in response to a power supply transition, the second branch can be configured to precharge the dummy wordline through the single PMOS device. Also, a method to precharge a dummy wordline includes: precharging, by a first branch of a circuit, a dummy wordline, and in response to a power supply transition, precharging the dummy wordline through a single PMOS device of a second branch of the circuit.
G11C 8/08 - Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
G11C 8/06 - Address interface arrangements, e.g. address buffers
G11C 8/18 - Address timing or clocking circuitsAddress control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
A computer-implemented method for generating a physical design of a circuit supporting a top-down black-boxed approach, includes: receiving a file indicating a set of components of a circuit design, wherein at least one component of the set of components of the circuit design is a black-box component; for each of the at least one component of the set of components that is a black-box component, assigning a boundary shape and layout area to that component; initiating at least one simulation for evaluating a physical design metric; updating a feature of at least one of the at least one component of the set of components that is the black-box component based on the at least one simulation for evaluating the physical design metric; and initiating the at least one simulation for evaluating the physical design metric for the circuit design having the updated feature.
This disclosure describes a computer-readable medium storing instructions for detecting malicious activity by monitoring the execution of intentionally weak code paths embedded within executable code. A monitoring system receives a mapping that associates each injected weak path with a unique identifier, then observes the executable during runtime to determine whether any such abnormal path is taken. Because these paths are designed not to execute during normal operation (implemented through inhibited or dead code reachable only under adversarial manipulation) their activation serves as a signal of potential attack behavior. When the monitoring system detects execution of a mapped intentionally weak code path, it generates a notification within a secure environment, enabling rapid identification of suspicious or unauthorized activity. This technique enhances software security by providing a lightweight, observable mechanism for detecting deviations from expected execution flows.
An apparatus comprises decoding circuitry configured to decode instructions; processing circuitry configured to perform data processing operations in response to the instructions decoded by the decoding circuitry; extension processing circuitry configured to perform a low-precision computation extension task asynchronously with respect to other data processing operations performed by the processing circuitry, the low-precision computation extension task comprising processing one or more sets of data elements for which at least one of the sets of data elements comprises low-precision data represented in a low-precision number format with lower precision than a single-precision floating-point format; and an extension task offload interface separate from an interface by which the processing circuitry issues a memory system request to a memory system, wherein the extension task offload interface is responsive to at least one task offloading instruction decoded by the decoding circuitry to offload the low-precision computation extension task to the extension processing circuitry.
There is provided an apparatus, a method, and a computer program. The apparatus comprises a plurality of registers to store data, the plurality of registers comprising at least one array register. The apparatus comprises data processing circuitry for processing a sequence of instructions. The data processing circuitry comprises decoder circuitry responsive to receipt of one or more instructions specifying the at least one array register to control the data processing circuitry to perform array processing operations in relation to the at least one array register. The apparatus comprises extension processing circuitry responsive to identification, by the data processing circuitry, of a delegated task to perform the delegated task asynchronously to the data processing circuitry. The decoder circuitry is responsive to a delegation instruction to trigger the extension processing circuitry to perform, as the delegated task, one or more operations associated with one of the array processing operations.
There is provided an apparatus a method and a computer program. The apparatus comprises processing circuitry configured to perform processing operations associated with one or more processes, each of the one or more processes associated with an identifier. The apparatus comprises sampling circuitry configured to maintain, for the identifier, information indicative of a plurality of samples, each of the plurality of samples identifying a metric associated with the identifier. The apparatus comprises monitoring circuitry configured to perform a determination of whether the metric identified by a given sample of the plurality of samples maintained for the identifier falls outside of a dynamically varying range and, in response to the determination indicating that the metric identified in the given sample falls outside of the dynamically varying range, to generate a software visible indication associated with the identifier.
An apparatus comprises first control information storage and second control information storage, to store control information entries corresponding to a given address and providing control information for controlling processing operations relating to the given address. Lookup circuitry is configured to perform a precise lookup operation in the first control information storage to identify a target control information entry corresponding to a target address determined based on a plurality of target address calculation operands, and perform an imprecise lookup operation in the second control information storage to identify the target control information entry based on an imprecise lookup value. Checking circuitry is configured to cause a miss to be detected in the second control information storage in response to determining that the imprecise lookup value does not correspond to the target address.
Disclosed is memory access logic that is operable to perform different accesses to a particular memory element depending on whether or not a memory error checking scheme is being implemented for the memory element. A set of error checking bits are stored in the memory element for implementing the memory error checking scheme. The memory error checking scheme can thus be selectively enabled and memory accesses performed accordingly such that when the memory error checking scheme is enabled, it is ensured that the required error checking bits are accessed.
According to the present techniques there is provided a method of operating a data processor unit to generate transformed geometric data, the method performed at the data processor unit comprising: receiving, first input data comprising geometric data; receiving second input data comprising shader context data associated with a graphics processing operation to be performed; and operating, at the data processor, on the geometric data using one or more machine learning models to generate transformed geometric data, wherein the machine learning model is responsive to the shader context data when generating the transformed geometric data to generate transformed geometric data adapted to support the graphics processing operation.
An optical flow mask is generated based, at least in part, on a calculated degree of confidence of one or more motion vectors relating a prior frame and a current frame in a rendered image sequence. A pyramidal block matching algorithm is applied to calculate an optical flow relating the prior image frame and the current image frame, where applying the pyramidal block matching excludes portions of an image sequence masked by the generated optical flow mask.
A processing unit has processing circuitry for performing data processing operations on data accessible in memory, and cache storage to store a subset of the data accessible in the memory, for access by the processing circuitry. Memory control circuitry controls access to a given portion of the memory associated with the processing unit, the given portion of memory comprising at least a shareable memory region to store data that is also accessible by at least one external processing element. Snoop circuitry, responsive to a snoop request identifying a memory address, performs a coherency action in respect of data stored in the cache storage for the identified memory address. Power control circuitry enables the processing unit to be transitioned between a plurality of operating modes, including a data retention mode where the data in the cache storage is retained whilst the processing circuitry and the snoop circuitry are inactive. When transitioning the processing unit into the data retention mode, a given invalidation coherency action is performed in order to invalidate each cache entry storing data associated with a memory address in the shareable memory region. Whilst the processing unit is in the data retention mode, the memory control circuitry allows a write operation instigated by the at least one external processing element, that specifies a given memory address within the shareable memory region, to be performed without waking up the snoop circuitry to process a corresponding snoop request for the given memory address.
An apparatus comprises instruction decoding circuitry configured to decode instructions according to an instruction set architecture; and processing circuitry configured to perform data processing in response to the instructions decoded by the instruction decoding circuitry. The processing circuitry comprises Keccak round computation circuitry configured to perform, in response to the instruction decoding circuitry decoding a Keccak-operation-specifying instruction, an atomic operation comprising at least one round of a Keccak function applied to Keccak state information representing an array of working state data elements, to generate updated values for each working state data element of the array. In a given round of the Keccak function, the Keccak round computation circuitry updates at least one working state data element of the array based on a round constant selected based on a round constant specifying value associated with the Keccak-operation-specifying instruction.
Disclosed is a graphics processor comprising a plurality of processing elements that are configurable as different, respective “partitions” of the processing elements, each partition of processing elements including one or more processing cores and a scheduling unit. Fault detection and management can then be performed for particular, respective partitions of the processing elements within the graphics processor.
An apparatus comprises execution circuitry configured to execute a given instruction to produce a given data value. Value analysis circuitry is configured to perform an analysis of the given data value produced by the execution circuitry to determine at least one property of the given data value, and register allocation circuitry is configured to make a register allocation decision regarding storage of the given data value in a physical register file in dependence on the analysis of the given data value.
Briefly, example apparatuses, articles of manufacture, and/or techniques are disclosed that may be implemented, in whole or in part, to implement, facilitate and/or support integrated circuits comprising memory read output circuitry including a read signal input terminal, a latch, and a combinatorial gate coupled to the read signal input terminal and the latch.
G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
97.
CONSISTENCY CHECKING CIRCUIT FOR COMPONENTS WITH INTERNAL CLOCKING
A consistency checking circuit can include a dynamic input comparator structured to compare dynamic signals received at a first input and a second input to detect an inconsistency on an internal clock line of a component with respect to a signal from an external clock line, wherein the dynamic input comparator is coupled at the first input to the internal clock line and coupled at the second input to an external clock line of the component. The detected inconsistency can be a glitch on the internal clock line, a slew, or an inconsistent sequence of transitions.
H03K 5/1252 - Suppression or limitation of noise or interference
H03K 5/135 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
A graphics processor executes a graphics processing pipeline in which one or more of a sequence of one or more geometry processing stages of the graphics processing pipeline generate vertex packets for subsequent processing. When the graphics processing pipeline is being executed to render a scene from a plurality of viewpoints, at least some of the geometry processing stages of the sequence of one or more geometry processing stages are performed to generate initial vertex packets comprising vertices for assembled primitives for the scene being rendered. A respective viewpoint vertex packet for each viewpoint of the plurality of viewpoints is then generated for and using each initial vertex packet. The viewpoint vertex packets are then provided to a further stage or stages of the graphics processing pipeline for rendering the scene from the plurality of viewpoints.
There is provided a voltage feedback circuit including: a programmable voltage feedback amendment circuit configured to take an input voltage from a supply rail and generate a feedback signal to a voltage regulator (VR) so causing an output voltage of the VR to be adjusted from a VR operating setpoint, wherein the adjustment from the VR operating setpoint is programmable by the feedback amendment circuit. In addition, there is provided a system including the voltage feedback circuit and a VR. Finally, there is provided a method of adjusting a voltage in a voltage feedback circuit, the method including: taking an input voltage from a supply rail at a feedback amendment circuit; and generating a feedback signal to a VR so causing an output voltage of the VR to be adjusted from a setpoint; wherein the adjustment from the setpoint is programmable by the feedback amendment circuit.
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
G05F 1/565 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
G06F 1/3296 - Power saving characterised by the action undertaken by lowering the supply or operating voltage
An apparatus, comprises granule protection checking circuitry to obtain granule protection information associated with a target granule of physical addresses comprising a target physical address, and determine, based on the granule protection information, whether a selected physical address space associated with the target physical address is permitted to access the target granule of physical addresses. The apparatus comprises prefetch circuitry configured to initiate a prefetch operation for the target physical address enabling target data identified by the target physical address to be prefetched into a cache in advance of the granule protection checking circuitry determining whether the selected physical address space is permitted to access the target granule of physical addresses.
G06F 21/62 - Protecting access to data via a platform, e.g. using keys or access control rules
G06F 12/0862 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
G06F 12/1009 - Address translation using page tables, e.g. page table structures
