There is provided an apparatus comprising a storage hierarchy. The storage hierarchy comprises: storage circuitry configured to store a plurality of data items, and a downstream storage component. The apparatus is also provided with control circuitry responsive to receipt of a memory access request specifying an address from which content is to be retrieved, to perform a prediction of whether the content is present in the storage circuitry, and when the prediction indicates that the content is absent from the storage circuitry, to issue a storage bypass request to trigger a downstream lookup of the content in the downstream storage component. The control circuitry is configured to receive a hint from upstream of the storage circuitry, the hint indicative of whether the address belongs to a set of addresses previously observed by the processing circuitry, and to perform the prediction in dependence on the hint.
Data processing circuitry performs first second data processing operations. First data processing operations comprise a first delegation action that signals a first delegated task to be performed by second data processing operations. Performance of the first delegated task by second data processing operations comprises a second delegation action, that causes extension processing circuitry to perform a second delegated task asynchronously to the second data processing operations performed by the data processing circuitry. Completion of the first delegated task is signalled to the first data processing operations providing a data item with an associated indicator set. The set indicator causes the first data processing operations, when a delegated-task-related data processing operation that depends on the data item is to be performed, to clear the indicator and to perform a synchronization of the data processing circuitry with a result of the second delegated task before performing the delegated-task-related data processing operation.
A computer-implemented method and system are provided for controlling operation of one or more electronic devices based on detection of a meaningful context change in context data describing a human experience. Context data, including aspects such as actions and intents, is received from one or more devices and used to predict subsequent actions and intents associated with a task. A distributional representation generates latent states corresponding to the predicted aspects, and a predictor estimates next latent states. A comparison between predicted and actual latent states yields a distance metric used to identify a meaningful context change. The method distinguishes temporary variations from changes requiring adaptation of a machine learning model. In response, the system selectively updates or replaces the model and may control device operation, including switching devices on or off. This enables adaptive, context-aware control across connected devices while maintaining stability against transient changes.
A method of image processing. The method comprises obtaining a set of image data, the set being associated with one or more parameters representative of one or more image capture characteristics for the set and comprising pixel intensity values representing image pixels having respective pixel locations in an image. The method comprises, for a given pixel intensity value in the set: determining an estimated noise value based on at least: the one or more parameters associated with the set, and a representative intensity value derived from one or more pixel intensity values in the set. The method comprises associating the estimated noise value with the given pixel intensity value.
G06V 10/60 - Extraction de caractéristiques d’images ou de vidéos relative aux propriétés luminescentes, p. ex. utilisant un modèle de réflectance ou d’éclairage
A processing circuitry and method for efficient task data allocation using a command processing unit, a handling unit, execution units, and storage accessible to at least one of the execution units. The command processing unit receives a command and generates tasks for execution. The handling unit identifies storage segments and issues data for tasks to these segments by associating virtual and physical addresses. A free storage segment is detected based on task completion, and upon detection, data for a second task's execution is issued to the free segment by associating a new virtual address with the physical address of the free segment. This method ensures efficient allocation and execution of tasks by dynamically managing storage segments.
G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
A processor comprises a first processing circuitry configured to process the data in a lower-precision format and a second processing circuitry configured to process data in a higher-precision format. The first processing circuitry is configured to process a data element value using less power than the second processing circuitry processing the same data element value. The method comprises determining whether a data element value will be subject to a transpose operation. In a case that the data element value will be subject to a transpose operation, the processor converts the data element value to the higher precision format and processes the data element value using the second processing circuitry. In a case that the data element value in the lower precision format will not be subject to a transpose operation, the processor processes the data element value in the lower precision format using the first processing circuitry.
G06F 7/483 - Calculs avec des nombres représentés par une combinaison non linéaire de nombres codés, p. ex. nombres rationnels, système de numération logarithmique ou nombres à virgule flottante
G06F 7/544 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs n'établissant pas de contact, p. ex. tube, dispositif à l'état solideMéthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul
G06F 7/78 - Dispositions pour le réagencement, la permutation ou la sélection de données selon des règles prédéterminées, indépendamment du contenu des données pour changer l'ordre du flux des données, p. ex. transposition matricielle ou tampons du type pile d'assiettes [LIFO]Gestion des occurrences du dépassement de la capacité du système ou de sa sous-alimentation à cet effet
When performing tile-based rendering, packets comprising primitives to be processed for a render output are generated, together with bounding boxes to be used to identify whether the packets should be processed for respective regions of the render output. Bounding boxes to be used to identify whether primitives in the packet should be processed for a region of the render output are encoded in packet, with one or more of the bounding boxes encoded in the packet being encoded relative to a reference bounding box.
Packets comprising primitives to be processed for a render output and bounding boxes to be used to identify primitives in the packets for respective regions of the render output are generated. Each packet comprises a set of higher level data to process a set of primitives, and sets of lower level data to process sub-sets of primitives in the set of primitives that the higher level data is for. Bounding boxes associated with the sub-sets of one or more primitives identify whether the sub-sets of primitives should be processed for a respective region of a render output. When the bounding boxes identify that a sub-set of primitives should be processed for a respective region of a render output, the set of higher level data and the set of lower level data to be used for processing the sub-set of primitives is identifiable from the packet.
A method for scan operations includes performing, by a circuit, a first scan operation in a scan-shift operation mode using a first port clock signal; and performing, by the circuit, a second scan operation in a scan-capture operation mode using a second port clock signal independent from the first port clock signal. Another method for scan operations includes providing, by a scan chain architecture circuitry, a clock signal to an input latch and one or more output latches of a scan operation circuitry; and performing a scan operation using the clock signal. A circuit for scan operations includes scan operation circuitry comprising at least: an input latch and one or more output latches; and control circuitry, where the control circuitry is configured to transmit a respective first or second clock signal to control the scan operation circuitry in a first or second scan operation mode.
A circuit for column redundancy includes: one or more memory sub-arrays comprising: a plurality of bitcell columns; and a redundant input-output (I/O) circuitry comprising at least four redundant bitcell columns, where the circuit is configured to logically replace a subset of at least four bitcell columns of the plurality of bitcell columns with the at least four redundant bitcell columns. A method for column redundancy includes: detecting at least one faulty bitcell column in a memory sub-array; identifying a subset of at least four bitcell columns comprising the at least one faulty bitcell column; logically replacing the subset of at least four bitcell columns with at least four redundant bitcell columns from a redundant input-output (I/O) circuitry; and routing operational data through the at least four redundant bitcell columns.
Apparatuses, methods, systems, chip-containing products and computer-readable storage media are disclosed. Data processing circuitry performs first data processing operations and second data processing operations. The first data processing operations comprise a first delegation action that signals a first delegated task to be performed by the second data processing operations. Performance of the first delegated task by the second data processing operations comprises a second delegation action, that causes extension processing circuitry to perform a second delegated task asynchronously to the second data processing operations performed by the data processing circuitry. Completion of the first delegated task by the second data processing operations is signalled to the first data processing operations providing a data item with an associated indicator set. The set indicator causes the first data processing operations, when a delegated-task-related data processing operation that depends on the data item is to be performed, to clear the indicator and to perform a synchronization of the data processing circuitry with a result of the second delegated task before performing the delegated-task-related data processing operation.
A processing circuitry and method for efficient task data allocation using a command processing unit, a handling unit, execution units, and storage accessible to at least one of the execution units. The command processing unit receives a command and generates tasks for execution. The handling unit identifies storage segments and issues data for tasks to these segments by associating virtual and physical addresses. A free storage segment is detected based on task completion, and upon detection, data for a second task's execution is issued to the free segment by associating a new virtual address with the physical address of the free segment. This method ensures efficient allocation and execution of tasks by dynamically managing storage segments.
There is provided a data processing apparatus in which prediction circuitry stores a plurality of mappings from instructions to payloads. Query circuitry responds to a reference to one of the instructions provided as at least part of an input by outputting one of the payloads that maps to the one of the instructions. The payloads include one of a plurality of predictions and a prediction type that indicates which of a plurality of data speculation techniques the one of a plurality of predictions relates. The prediction circuitry stores, for each of the instructions, the prediction type as one of a plurality of different prediction types.
An apparatus comprises fetch circuitry and prediction circuitry. A prediction storage structure provides prediction entries providing prediction information for a corresponding block of one or more instructions. The prediction circuitry performs a lookup for a given instruction in the prediction storage structure to identify instructions to fetch after the given instruction. Allocation control circuitry is configured to support internal allocation operations for prediction entries already stored in the prediction storage structure, wherein for a given prediction entry an internal allocation operation comprises, responsive to an internal allocation trigger event, allocating a new prediction entry at a different location in the prediction storage structure than the given prediction entry and populated with given prediction information provided by the given prediction entry. The allocation control circuitry selects, in dependence on a performance metric, a level of throttling to apply to the internal allocation operations.
A target network includes a home node, a subordinate node, gateway transmitter and a gateway receiver. The home node is associated with an address in a set of system addresses. The gateway receiver, in response to receiving a read request for data associated with the address from the gateway transmitter of a source network, generates a prefetch message for the address, sends the generated prefetch message to the subordinate node, and forwards the read request to the home node, of the target network. Responsive to receiving the generated prefetch message, the subordinate node retrieves data associated with the address and stores the data in a buffer of the subordinate node. Responsive to receiving a request from the home node, the subordinate node sends the data to the home node. The read request may contain a field indicating that a prefetch message should be generated.
A processor comprises a first processing circuitry configured to process the data in a lower-precision format and a second processing circuitry configured to process data in a higher-precision format. The first processing circuitry is configured to process a data element value using less power than the second processing circuitry processing the same data element value. The method comprises determining whether a data element value will be subject to a transpose operation. In a case that the data element value will be subject to a transpose operation, the processor converts the data element value to the higher precision format and processes the data element value using the second processing circuitry. In a case that the data element value in the lower precision format will not be subject to a transpose operation, the processor processes the data element value in the lower precision format using the first processing circuitry.
G06F 7/544 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs n'établissant pas de contact, p. ex. tube, dispositif à l'état solideMéthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul
G06F 7/556 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs n'établissant pas de contact, p. ex. tube, dispositif à l'état solideMéthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul de fonctions logarithmiques ou exponentielles
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
A graphics processor is operable to execute a processing pipeline comprising a sequence of pipeline stages using one or more shared processing circuits. The execution of the processing pipeline is controlled by a pipeline manager that is operable to select respective sets of work for processing from respective work queues associated with the different pipeline stages, and to provide the selected sets of work to an iterator circuit that will then perform the desired processing. The iterator circuit is controlled to perform different processing for different pipeline stages.
Example methods, apparatuses, or articles of manufacture are disclosed herein that may be utilized, in whole or in part, to facilitate or support one or more operations or techniques for affecting control signals to a display device to selectively reduce power to at least some individually controllable emissive elements in the display device. In one implementation, some of the individually controllable emissive elements of a display device may be configured to not emit visible light while a remaining portion continues presentation of the visible image according to one or more conditions local to the display device.
G09G 3/32 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice utilisant des sources lumineuses commandées utilisant des panneaux électroluminescents semi-conducteurs, p. ex. utilisant des diodes électroluminescentes [LED]
When encoding a data array in a lossless manner, the data array is encoded using a lossless encoding scheme, and using an auxiliary encoding scheme that can encode at least some data arrays in a lossless manner such that the original array of data elements can be reconstructed from the encoded data. The result of encoding the data array using the auxiliary encoding scheme is then used to determine whether to use a result of the encoding of the data array using the auxiliary encoding scheme for the output encoded data array or whether to use a result of the encoding of the data array using the lossless encoding scheme for the output encoded data array.
H04N 19/146 - Débit ou quantité de données codées à la sortie du codeur
H04N 19/176 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage adaptatif caractérisés par l’unité de codage, c.-à-d. la partie structurelle ou sémantique du signal vidéo étant l’objet ou le sujet du codage adaptatif l’unité étant une zone de l'image, p. ex. un objet la zone étant un bloc, p. ex. un macrobloc
A data processing apparatus is provided. A processing pipeline transfers one or more control signals corresponding to an instruction through a plurality of stages, at least one of the stages is configured to write data to storage circuitry. A data prediction pipeline receives an indication of a load instruction that loads data from memory to a register in the register file, based on the indication performs a determination of whether the load instruction is eligible for predicted data, and based on the determination provides the predicted data as a prediction of the data. Switching circuitry responds to at least part of the processing pipeline being unused to cause the at least one of the stages to write the predicted data to the storage circuitry.
A data processing apparatus is provided that includes a plurality of storage circuits, each storing data items in association with tags. Indication circuitry indicates, for a partial tag that is provided as an input, a subset of the storage circuits where the partial tag is part of the tags stored in that storage circuit, and causes the subset of the storage circuits to be powered to a power level at which the subset of the storage circuits can be accessed. Access circuitry searches the subset of the storage circuits for a tag comprising the partial tag once the indication circuitry has caused the subset of storage circuits to be powered.
A controller and a method of operating a controller for a shared space air treatment apparatus configured to control air treatment in one or more zones comprises a recognition system operable to identify the presence of a person at a location associated with an air treatment zone of the shared space air treatment apparatus; a comparator operable to compare a stored air characteristic value associated with the person and a sensed air characteristic value associated with the zone; and a transceiver operable to send at least one adjustment instruction to adjust a target air characteristic value for the associated zone based on the comparison of the stored air characteristic value and the sensed air characteristic value.
A graphics accelerator is disclosed that comprises a set of plural data transfer channels operable to transfer data. Two or more of the data transfer channels are associated with each other, and caused to transfer data at respective data transfer rates in accordance with a particular data transfer rate ratio.
G06T 1/20 - Architectures de processeursConfiguration de processeurs p. ex. configuration en pipeline
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p. ex. acces direct à la mémoire, vol de cycle
In a graphics processor that is configured to execute a tile-based graphics processing pipeline a geometry buffer is provided that is operable to store ‘temporary’ geometry items that are produced by and then consumed during the initial, geometry processing pass of the tile-based graphics processing pipeline. Allocations to the geometry buffer are controlled to keep the active size of the geometry below a certain threshold.
Example methods, apparatuses, or articles of manufacture are disclosed herein that may be utilized, in whole or in part, to facilitate or support one or more operations or techniques for affecting control signals to a display device to selectively reduce power to at least some individually controllable emissive elements in the display device. In one implementation, some of the individually controllable emissive elements of a display device may be configured to not emit visible light while a remaining portion continues presentation of the visible image according to one or more conditions local to the display device.
G09G 3/32 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice utilisant des sources lumineuses commandées utilisant des panneaux électroluminescents semi-conducteurs, p. ex. utilisant des diodes électroluminescentes [LED]
An apparatus comprises requester interface circuitry which receives response flits from a memory system interconnect. A given response flit specifies a status indication indicative of a status of a memory system node associated with the given response flit, and is associated with at least one further response flit property other than the status indication. Status aggregation circuitry combines respective status indications from received response flits to generate an aggregate status indication. Control circuitry controls, based on the aggregate status indication generated by the status aggregation circuitry, a rate of memory system transactions initiated to the memory system interconnect by the requester interface circuitry. The status aggregation circuitry selects, depending on said at least one further response flit property of the given response flit, a weighting with which the status indication of the given response flit influences the aggregate status indication.
Briefly, example apparatuses, articles of manufacture, and/or techniques are disclosed that may be implemented, in whole or in part, to implement, facilitate and/or support code retrieval from a shared storage element by integrated circuits comprising co-packaged chiplets.
40 - Traitement de matériaux; recyclage, purification de l'air et traitement de l'eau
Produits et services
Custom manufacturing of chips [integrated circuits] for
others; custom manufacture of semiconductor wafers; custom
manufacture of semiconductor circuits; custom manufacture of
semiconductor components; encapsulation of semiconductors.
29.
PERFORMANCE MONITORING CIRCUITRY, METHOD AND COMPUTER PROGRAM
Performance monitoring circuitry (40) has event counters (42) each to maintain a respective event count value based on monitoring of events during processing of the software by the processing circuitry. Control circuitry (44) configures the event counters based on counter configuration information. For at least a subset of the event counters, a given event counter (42) in the subset supports a chained-counter operation comprising incrementing a given event count value by an increment value determined based on a logical combination of a first event status indication indicative of status of a first event type assigned by the counter configuration information to be monitored by the given event counter and a second event status indication indicative of status of a second event type assigned by the counter configuration information to be monitored by a further event counter.
An apparatus comprises processing circuitry to perform data processing and instruction decoding circuitry to decode instructions to control the processing circuitry. The processing circuitry imposes an ordering requirement on one or more memory access instructions to prevent said one or more memory access instructions being reordered with respect to an ordering instruction. In response to an ordering limit hint instruction associated with a given ordering instruction, the processing circuitry relaxes the ordering requirement for a memory access instruction for which the ordering limit hint instruction appears in program order between the memory access instruction and the given ordering instruction.
An apparatus comprises interface circuitry to exchange signals with one or more requesters. A to-be-translated memory access request specifies a target address to be translated to identify a location in a memory system to be accessed. In response to a to-be-translated memory access request received at the interface circuitry from a given requester, the interface circuitry issues a request acknowledgement to the given requester acknowledging the to-be-translated memory access request independent of whether the to-be-translated memory access request satisfies an observability condition.
An apparatus comprises processing circuitry and decoding circuitry to decode instructions and generate control signals for controlling the processing circuitry. In response to a bitmap-index conversion instruction indicating an input bitmap, the decoding circuitry generates control signals to control the processing circuitry to generate an index vector comprising a plurality of elements indicative of a plurality of indices of set bits in the input bitmap. In response to an index-bitmap conversion instruction indicating an index vector comprising a plurality of indices, the decoding circuitry generates control signals to control the processing circuitry to generate a plurality of partial bitmaps, each partial bitmap comprising a set bit corresponding to a respective one of the plurality of indices, and to combine the plurality of partial bitmaps to generate an output bitmap comprising set bits at each of the plurality of indices.
G06F 7/74 - Sélection ou codage, à l'intérieur d'un mot, de la position d'un ou de plusieurs chiffres binaires ayant une valeur spécifiée, p. ex. détection du un ou du zéro le plus ou le moins significatif, codeurs de priorité
G06F 5/01 - Procédés ou dispositions pour la conversion de données, sans modification de l'ordre ou du contenu des données maniées pour le décalage, p. ex. la justification, le changement d'échelle, la normalisation
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
An apparatus comprises processing circuitry configured to perform data processing in response to instructions, and at least one functional unit configured to issue one or more configuration state table access requests to access a configuration state table in memory, wherein a configuration state table access request specifies a target physical address identifying a memory location associated with target configuration state. A control register, accessible to the processing circuitry, is configured to indicate a constraint on allocation of a portion of an address space for storing the configuration state table.
G06F 12/1009 - Traduction d'adresses avec tables de pages, p. ex. structures de table de page
G06F 9/455 - ÉmulationInterprétationSimulation de logiciel, p. ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
G06F 12/1036 - Traduction d'adresses utilisant des moyens de traduction d’adresse associatifs ou pseudo-associatifs, p. ex. un répertoire de pages actives [TLB] pour espaces adresse virtuels multiples, p. ex. segmentation
G06F 12/109 - Traduction d'adresses pour espaces adresse virtuels multiples, p. ex. segmentation
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 9/50 - Allocation de ressources, p. ex. de l'unité centrale de traitement [UCT]
34.
TECHNIQUE FOR CONTROLLING USE OF ADDRESS TRANSLATION INFORMATION
An address translation provider apparatus has interface circuitry to couple it to an address translation consumer apparatus, and epoch maintenance circuitry to control transitions of epochs from amongst N possible epochs. Generation circuitry generates and outputs an item of address translation information for a translation request, with an associated epoch identifier. Tracking circuitry tracks receipt of completion signals for each item of address translation information. When an invalidation procedure is required to invalidate address translations, the epoch maintenance circuitry changes the epoch by selecting a new epoch from an available epoch amongst the N epochs, and determines the epoch identifier associated with an item of address translation information to be invalidated because of the invalidation procedure. The address translation provider apparatus completes the invalidation procedure once completion signals have been received for each item of address translation information previously issued whose associated epoch identifier is other than the new epoch.
G06F 12/1027 - Traduction d'adresses utilisant des moyens de traduction d’adresse associatifs ou pseudo-associatifs, p. ex. un répertoire de pages actives [TLB]
There is provided an apparatus comprising a fetch queue to identify instructions to be fetched for execution, and entry storage to store prediction entries comprising a multi-taken entry identifying: a first branch instruction configured to divert control flow to a first target address identifying a second instruction block, and a second branch instruction comprised in the second instruction block and configured to divert control flow to a second target address. The apparatus comprises control circuitry responsive to a prediction identifying an outcome of both of the first and second branch instructions, to populate the fetch queue based on the prediction, and in response to a subsequent identification of a change in an outcome of the second branch instruction, to flush instruction addresses subsequent to a second branch instruction address and to retain instruction addresses up to and including the second branch instruction address in the fetch queue.
An apparatus comprises processing circuitry to perform data processing and instruction decoding circuitry to decode instructions to control the processing circuitry. The processing circuitry imposes an ordering requirement on one or more memory access instructions to prevent said one or more memory access instructions being reordered with respect to an ordering instruction. In response to an ordering limit hint instruction associated with a given ordering instruction, the processing circuitry relaxes the ordering requirement for a memory access instruction for which the ordering limit hint instruction appears in program order between the memory access instruction and the given ordering instruction.
An apparatus is provided in which upper comparison circuitry compares an address to an end of a region to produce a first intermediate result and lower comparison circuitry compares an adjacent address to the address to a start of the region to produce a second intermediate result. Output circuitry uses the first intermediate result and the second intermediate result to output an extent to which the address and the adjacent address are covered by the region without the lower comparison circuitry comparing the address or without the upper comparison circuitry comparing the adjacent address.
Briefly, example apparatuses, articles of manufacture, and/or techniques are disclosed that may be implemented, in whole or in part, to implement, facilitate and/or support code retrieval from a shared storage element by integrated circuits comprising co-packaged chiplets.
A system and computer-implemented method to train and use a neural network is disclosed. For each group of elements of a feature map in a layer in the neural network, a record is accessed to determine if at least one element of the group is active. When at least one element of the group is active, a gradient is determined for each active element of the group, copied to a 5 group element position indicated by the entry for the group in record, and the group is sent to a dot product unit to update weights in the layer based on the group. When no element of the group is active, the dot product unit is signaled to prevent update of weights based on the group. The record is set during the forward path of the feature map through the network.
A method of operating a network-reachable initiator computing entity, comprising: determining a requirement, at the initiator computing entity, for offloading data processing; initiating a message, to be sent on a network to a destination, requesting a response from network-reachable recipient computing entities along the network, from the network-reachable initiator computing entity to the destination, indicating a capacity to perform offloaded data processing; and receiving a response from a first network-reachable recipient computing entity indicating a capacity to perform offloaded data processing.
H04L 67/1012 - Sélection du serveur pour la répartition de charge basée sur la conformité des exigences ou des conditions avec les ressources de serveur disponibles
H04L 67/1023 - Sélection du serveur pour la répartition de charge basée sur un hachage appliqué aux adresses IP ou aux coûts
An apparatus comprises processing circuitry configured to perform data processing, and instruction decoding circuitry configured to decode instructions to control the processing circuitry to perform the data processing. The instruction decoding circuitry is responsive to one or more types of memory access instruction associated with a target address to control the processing circuitry to perform an access to a location associated with the target address. The instruction decoding circuitry is responsive to an interrupt management instruction identifying an interrupt management operation to control the processing circuitry to perform the interrupt management operation. The interrupt management instruction has a different instruction encoding from the one or more types of memory access instruction.
An address translation consumer apparatus interface circuitry coupling the address translation consumer apparatus to an address translation provider apparatus. Processing circuitry issues a translation request to the address translation provider apparatus. In response to receiving the item of address translation information for the translation request the processing circuitry determines the epoch indicated. In the absence of an epoch indicating caching control signal inhibiting caching of items of address translation information for the determined epoch, the item of address translation information and the epoch identifier for the determined epoch is cached in a cache entry and used for the transaction. A completion signal is issued on invalidation of that cache entry. In the presence of the epoch indicating caching control signal, inhibiting caching of the item of address translation information, and using it for the transaction. A completion signal is issued once the transaction has been processed by the processing circuitry.
G06F 12/0888 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache utilisant la mémorisation cache sélective, p. ex. la purge du cache
G06F 12/0891 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache utilisant des moyens d’effacement, d’invalidation ou de réinitialisation
G06F 12/1027 - Traduction d'adresses utilisant des moyens de traduction d’adresse associatifs ou pseudo-associatifs, p. ex. un répertoire de pages actives [TLB]
43.
SELECTION OF TARGET VIRTUAL PROCESSOR FOR SERVICING VIRTUAL INTERRUPT
An apparatus comprises interrupt delivery circuitry to deliver, to a virtual interrupt interface of a given physical processor, a given virtual interrupt associated with a target virtual machine, where the given virtual interrupt is to be serviced by a target virtual processor of the target virtual machine. Virtual processor selection circuitry determines whether the given virtual interrupt is a targeted virtual interrupt (for which a pre-assigned virtual processor is constrained to be selected as the target virtual processor) or a 1-of-N virtual interrupt (for which the virtual processor selection circuitry is allowed to select the target virtual processor). For a 1-of-N virtual interrupt, the target virtual processor is selected depending on virtual processor status information indicative of a status of a plurality of virtual processors of the target virtual machine.
G06F 9/455 - ÉmulationInterprétationSimulation de logiciel, p. ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
An apparatus comprises base address registers, each corresponding to a respective one of a plurality of interrupt domains. Interrupt translation circuitry detects a given incoming event received from an interrupt source, indicative of a source interrupt domain associated with the interrupt source and a target interrupt domain for which an interrupt event is to be signalled to a target processor. When the source interrupt domain is different to the target interrupt domain, the interrupt translation circuitry determines, based on cross-domain interrupt permission information associated with the target interrupt domain, whether the given incoming event is permitted to be translated for the target interrupt domain when associated with the source interrupt domain, and if so translates the given incoming event into the interrupt event based on mapping information specified in a target domain interrupt translation control structure accessed using a base address from the base address register corresponding to the target interrupt domain.
Apparatuses, systems, chip-containing products, non-transitory computer-readable media and methods are disclosed. Load/store circuitry initiates a memory system transaction to access a shared memory location, wherein the shared memory location is accessible to multiple concurrent program threads. In response to an indication of concurrent access to the shared memory location by another program thread, the load/store circuitry causes a delay of reissuance of the memory system transaction by a delay period, wherein delay circuitry is configured to set the delay period in dependence on at least one factor determined at runtime.
A method for functional verification of a circuit design under test (DUT), comprises: generating stimulus inputs for first and second DUT instances instantiated for testing using a functional verification test bench, where the first and second DUT instances are each based on a same functional design for the circuit DUT comprising at least one clock gate configured to control, based on a clock gating control input, whether a clock signal is enabled or disabled for downstream circuitry, and the stimulus inputs comprise at least one clock gating control input being set differently for the first and second DUT instances and non-clock-gating control inputs set identically for the first and second DUT instances; using the functional verification test bench, stimulating a response of the first and second DUT instances to the stimulus inputs, to obtain test outputs for the first and second DUT instances; and using at least one output checker, comparing at least one pair of corresponding test outputs for the first and second DUT instances, to detect whether there is divergence between behaviour of the first and second DUT instances.
A data processing apparatus includes mode circuitry for indicating a first format of a first floating-point parameter and separately indicating a second format of a second floating-point parameter. Floating-point circuitry performs a two-parameter floating-point operation using the first floating-point parameter in the first format and the second floating-point parameter in the second format. At least one of the first format and the second format is dynamically changeable at runtime.
G06F 7/483 - Calculs avec des nombres représentés par une combinaison non linéaire de nombres codés, p. ex. nombres rationnels, système de numération logarithmique ou nombres à virgule flottante
A storage circuit, a method, a device and a non-transitory computer-readable medium. The storage circuit includes a first storage circuit instance having a first physical storage circuit, a second storage circuit instance having one or more pairs of second physical storage circuits; and a selection circuit to select, for a given output of the storage circuit system, an output from the first storage circuit instance or an output from the second storage circuit instance.
Apparatuses, systems, methods, computer-readable media, and computer code are disclosed. An apparatus comprises processing circuitry and decoding circuitry to decode instructions and generate control signals for controlling the processing circuitry. In response to a bitmap-index conversion instruction indicating an input bitmap, the decoding circuitry generates control signals to control the processing circuitry to generate an index vector comprising a plurality of elements indicative of a plurality of indices of set bits in the input bitmap. In response to an index-bitmap conversion instruction indicating an index vector comprising a plurality of indices, the decoding circuitry generates control signals to control the processing circuitry to generate a plurality of partial bitmaps, each partial bitmap comprising a set bit corresponding to a respective one of the plurality of indices, and to combine the plurality of partial bitmaps to generate an output bitmap comprising set bits at each of the plurality of indices.
An apparatus comprises interface circuitry to exchange signals with one or more requesters. A to-be-translated memory access request specifies a target address to be translated to identify a location in a memory system to be accessed. In response to a to-be-translated memory access request received at the interface circuitry from a given requester, the interface circuitry issues a request acknowledgement to the given requester acknowledging the to-be-translated memory access request independent of whether the to-be-translated memory access request satisfies an observability condition.
Software Testing Library (STL) runtimes are optimized by: detecting a plurality of insertion points within binary code of an application, wherein a segment interval to execute a code segment between adjacent insertion points is at most a fault tolerant time interval; segmenting the binary code into a set of code segments, each beginning with one of the insertion points; for each of the code segments, analyzing code instructions of that code segment to determine a set of functional blocks of a processor needed to process the code instructions; determining a set of segment-specific STL tests for the set of functional blocks; and injecting STL calls into the binary code at each of the insertion points, wherein each of the STL calls are restricted to a corresponding one of the set of segment-specific STL tests.
An integrated circuit assembly comprises a substrate and a grid array of electrical connections such as solder bumps formed on the surface of the substrate. An electromagnetically permeable material is formed in a closed path and disposed on the surface of the substrate, disposed at least partially within the grid array of electrical connections and encircling at least one electrical connection of the grid array of electrical connections. The electromagnetically permeable material may comprise an inductor, and may be a paramagnetic material, a ferrite material, a metal wire material, or other such material. The electromagnetically permeable material may encircle at least one solder bump of the grid array of solder bumps carrying a power signal between the substrate and the integrated circuit. The electromagnetically permeable material may be disposed on a portion of the substrate over which the solder bumps are absent from the grid array of solder bumps.
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides
H10D 80/30 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif couvert par la présente sous-classe l’au moins un dispositif étant couvert par les groupes , p. ex. des ensembles comprenant des puces de processeur à circuit intégré
53.
CONTENTION AVOIDANCE DELAYS FOR ACCESSES TO SHARED MEMORY LOCATIONS
Apparatuses, systems, chip-containing products, non-transitory computer-readable media and methods are disclosed. Load/store circuitry initiates a memory system transaction to access a shared memory location, wherein the shared memory location is accessible to multiple concurrent program threads. In response to an indication of concurrent access to the shared memory location by another program thread, the load/store circuitry causes a delay of reissuance of the memory system transaction by a delay period, wherein delay circuitry is configured to set the delay period in dependence on at least one factor determined at runtime.
In a variable-length instruction set mode, front end circuitry decodes instructions according to an encoding scheme based on an architectural encoding constraint requiring that a given instruction is encoded fully within a G-bit fetch granule, where G is a fixed power-of-2 integer, and no valid instruction is allowed to cross a boundary between G-bit fetch granules. A predetermined subset of bit positions within a given G-bit fetch granule is used to determine whether the granule is encoded according to a first subset of valid encodings encoding instructions corresponding to instructions of a fixed-length legacy instruction set, or a second subset of valid encodings encoding, according to a layout identified by a layout descriptor in the predetermined subset of bit positions, one or more instructions including at least one instruction of different length to the instructions encoded in the first subset of valid encodings. [Figure 3]
An apparatus comprises value prediction storage providing value prediction entries, each providing a data value prediction associated with a corresponding instruction. Allocation circuitry is provided to control allocation of value prediction entries in the value prediction storage using a value prediction allocation filter comprising a plurality of allocation filter entries, each providing a counter value. The allocation circuitry identifies a target allocation filter entry based on an identifier of a given instruction and an observed data value outcome of the given instruction, and suppresses allocation of a value prediction entry corresponding to the given instruction in the value prediction storage when a target counter value in the target allocation filter entry does not meet an allocation threshold.
An apparatus comprises prediction circuitry to generate a predicted outcome for each of a plurality of candidate control flow instructions and provide a confidence value associated with each predicted outcome. Reduced-latency recovery circuitry is provided to implement a reduced-latency recovery mechanism for a selected subset of candidate control flow instructions, reducing a performance impact caused by predicted outcomes of the selected subset of control flow instructions being incorrect. Selection circuitry is provided to select the selected subset of the plurality of candidate control flow instructions in dependence on the confidence values associated with the predicted outcomes for the plurality of candidate control flow instructions and at least one further attribute of the plurality of candidate control flow instructions.
An apparatus includes no-op-compatible instruction tracking circuitry configured to store tracking information indicative of program counter addresses corresponding to no-op-compatible instructions architecturally permitted to be treated as a no-op instruction; and fetch skipping circuitry configured to determine, depending on whether a given fetch target address is identified as corresponding to a no-op-compatible instruction by the tracking information stored by the no-op-compatible instruction tracking circuitry, whether to skip fetching of a given instruction corresponding to the given fetch target address.
Access control circuitry (15), responsive to a memory access request, compares a tag value determined based on a tag portion (40) of an address pointer (42) with an allocation tag (32) associated with the memory location identified by a memory address determined from the address pointer. In response to the comparison indicating a given result, a tag error response is performed. Processing circuitry (4), executing a tag protecting instruction, detects whether an operation involves an attempt to set a bit in an identified portion (74) of an output value to a value other than that in a corresponding bit in an input operand. The processing circuitry sets, when it detects said attempt, a given portion of the output value to an error-indicating value. The identified portion is a portion of the output value which would be used as the tag portion if the output operand was used as the address pointer for a memory access instruction.
G06F 12/14 - Protection contre l'utilisation non autorisée de mémoire
G06F 11/07 - Réaction à l'apparition d'un défaut, p. ex. tolérance de certains défauts
G06F 21/54 - Contrôle des utilisateurs, des programmes ou des dispositifs de préservation de l’intégrité des plates-formes, p. ex. des processeurs, des micrologiciels ou des systèmes d’exploitation au stade de l’exécution du programme, p. ex. intégrité de la pile, débordement de tampon ou prévention d'effacement involontaire de données par ajout de routines ou d’objets de sécurité aux programmes
An apparatus comprises instruction decoding circuitry configured to decode instructions of a program thread executed by a given processor core; and load/store control circuitry configured to select a target point of a memory system hierarchy at which to allocate data for a target cache line specified by a load/store instruction decoded by the instruction decoding circuitry. The load/store control circuitry is configured to select the target point of the memory system hierarchy depending on whether the load/store instruction is associated with a memory contention hint provided by a contention hint instruction decoded by the instruction decoding circuitry, the memory contention hint indicating that the target cache line is likely to be subject to contention for access from multiple threads of processing.
There is provided an apparatus comprising decoder circuitry, responsive to a mixed- element-combination instruction specifying one or more first registers and a one or more second registers, to trigger the processing circuitry to perform at least one arithmetic 5 operation to combine each first element of a set of first elements from contiguous positions in the first registers with a corresponding second element of a set of second elements selected from the second registers according to the element information to generate a set of intermediate result elements, and to combine the intermediate result elements to generate a result element. A first element size of each first element is 10 different to a second element size of each second element.
An apparatus comprises front end circuitry configured to fetch and decode instructions; and processing circuitry to perform data processing operations in response to instructions decoded by the front end circuitry. In an expandable instruction set mode, the front end circuitry decodes the instructions according to an instruction encoding scheme in which each instruction is required to meet an architectural encoding constraint requiring that, for a given instruction processed in the expandable instruction set mode: the given instruction comprises a set of functional bits representing functionality of the given instruction, and a set of one or more expansion bits; and the set of one or more expansion bits is constrained to specify a predetermined value.
In a container-based instruction set mode for processing instructions from a fixed-length instruction set, front end circuitry decodes the instructions according to an encoding scheme in which each instruction is required to meet an architectural encoding constraint requiring that, for a given instruction processed in the container-based instruction set mode: the given instruction is one of a plurality of instructions encoded fully within a C-bit container, where C is a fixed power- of-2 integer; each instruction has W functional bits, where W is a fixed non-power-of-2 integer; and no valid instruction is allowed to cross a boundary between C-bit containers. The front end circuitry supports a branch operation specifying as a branch target any one of the plurality of instructions encoded within a given C-bit container.
There is provided an apparatus, a system, a chip-containing product, a method, and a computer-readable medium. The apparatus comprises a requestor element configured to issue a memory access request, and control circuitry configured to receive the memory access request and to determine a request order in which to forward the received memory access request to a memory component relative to one or more further memory access requests. The control circuitry is configured, when determining the request order, to identify whether the memory access request is associated with a priority hint, and when the memory access request is associated with the priority hint, to prioritise the memory access request ahead of the at least one of the one or more further memory access requests in the request order.
An integrated circuit assembly comprises an integrated circuit die comprising a first mounting surface, and a substrate having a first mounting surface and a second mounting surface opposite the first mounting surface. The first mounting surface of the substrate is electrically and physically coupled to the first mounting surface of the integrated circuit die, and the substrate further comprises a first plurality of electrical contact pads on the second mounting surface of the substrate. A vertically integrated voltage regulator has a first mounting surface and a second mounting surface opposite the first mounting surface, and is electrically and physically coupled to the substrate on the second mounting surface of the substrate and the first mounting surface of the vertically integrated voltage regulator. The voltage regulator further comprises a second plurality of electrical contact pads on the second mounting surface of the voltage regulator.
There is provided an apparatus comprising processing circuitry to perform data processing in response to a sequence of instructions. The apparatus comprises occurrence count circuitry to store an occurrence count indicative of a number of repeated occurrences of portions of the sequence of instructions. The apparatus comprises pattern storage circuitry to store a plurality of pattern entries, each pattern entry of the plurality of pattern entries associated with an instruction of the sequence of instructions and comprising a parameter for parameterising a relationship correlating the occurrence count with a value associated with the instruction. The apparatus comprises prediction circuitry responsive to receipt of a given occurrence of the instruction associated with a particular pattern entry, to predict the value associated with the given occurrence based on the relationship parameterised using the at least one parameter comprised in the particular pattern entry and the occurrence count for the given occurrence.
G06F 9/38 - Exécution simultanée d'instructions, p. ex. pipeline ou lecture en mémoire
G06F 9/345 - Adressage de l'opérande d'instruction ou du résultat ou accès à l'opérande d'instruction ou au résultat d'opérandes ou de résultats multiples
An apparatus comprises instruction decoding circuitry configured to decode instructions of a program thread executed by a given processor core; and load/store control circuitry configured to select a target point of a memory system hierarchy at which to allocate data for a target cache line specified by a load/store instruction decoded by the instruction decoding circuitry. The load/store control circuitry is configured to select the target point of the memory system hierarchy depending on whether the load/store instruction is associated with a memory contention hint provided by a contention hint instruction decoded by the instruction decoding circuitry, the memory contention hint indicating that the target cache line is likely to be subject to contention for access from multiple threads of processing.
An apparatus comprises front end circuitry configured to fetch and decode instructions; and processing circuitry to perform data processing operations in response to instructions decoded by the front end circuitry. In an expandable instruction set mode, the front end circuitry decodes the instructions according to an instruction encoding scheme in which each instruction is required to meet an architectural encoding constraint requiring that, for a given instruction processed in the expandable instruction set mode: the given instruction comprises a set of functional bits representing functionality of the given instruction, and a set of one or more expansion bits; and the set of one or more expansion bits is constrained to specify a predetermined value.
In a variable-length instruction set mode, front end circuitry decodes instructions according to an encoding scheme based on an architectural encoding constraint requiring that a given instruction is encoded fully within a G-bit fetch granule, where G is a fixed power-of-2 integer, and no valid instruction is allowed to cross a boundary between G-bit fetch granules. A predetermined subset of bit positions within a given G-bit fetch granule is used to determine whether the granule is encoded according to a first subset of valid encodings encoding instructions corresponding to instructions of a fixed-length legacy instruction set, or a second subset of valid encodings encoding, according to a layout identified by a layout descriptor in the predetermined subset of bit positions, one or more instructions including at least one instruction of different length to the instructions encoded in the first subset of valid encodings.
An apparatus comprises: front end circuitry configured to fetch and decode instructions; and processing circuitry configured to perform data processing operations in response to instructions fetched and decoded by the front end circuitry. In a container-based instruction set mode for processing instructions from a fixed-length instruction set for which each instruction of the fixed-length instruction set is encoded using the same number of functional bits representing functionality of the instruction, the front end circuitry is configured to decode the instructions according to an encoding scheme in which each instruction is required to meet an architectural encoding constraint requiring that, for a given instruction processed in the container-based instruction set mode: the given instruction is one of a plurality of instructions encoded fully within a C-bit container, where C is a fixed power-of-2 integer; each instruction has W functional bits, where W is a fixed non-power-of-2 integer; and no valid instruction is allowed to cross a boundary between C-bit containers. The front end circuitry supports a branch operation specifying as a branch target any one of the plurality of instructions encoded within a given C-bit container.
There is provided an apparatus comprising decoder circuitry, responsive to a mixed-element-combination instruction specifying one or more first registers and a one or more second registers, to trigger the processing circuitry to perform at least one arithmetic operation to combine each first element of a set of first elements from contiguous positions in the first registers with a corresponding second element of a set of second elements selected from the second registers according to the element information to generate a set of intermediate result elements, and to combine the intermediate result elements to generate a result element. A first element size of each first element is different to a second element size of each second element.
Power multiplexer circuitry, systems, and methods. Power multiplexer circuitry includes interface control logic including first SR latch circuitry to generate first and second interface control signals responsive to first and second latch control signals, a PMUX control circuit to provide a first selection control signal responsive to the first interface control signal and to provide a second selection control signal responsive to the second interface control signal, a power output circuit to output a selected voltage at a PMUX output, the power output circuit including first switch circuitry arranged between a first voltage rail and the PMUX output to provide an electrical path therebetween responsive to the first selection control signal, and second switch circuitry arranged between a second voltage rail and the PMUX output to provide an electrical path therebetween responsive to the second selection control signal.
H03K 19/20 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion caractérisés par la fonction logique, p. ex. circuits ET, OU, NI, NON
Systems and methods for determining whether a region of storage has associated meta data. A storage controller can receive, from a requestor, a request for meta data associated with a region of storage, determine whether the region of storage has associated meta data, and when region of storage has associated meta data, obtain, the meta data associated with the region of storage, and send, from the storage controller to the requestor, a response based at least in part on the associated meta data.
A data processing system is disclosed that includes storage storing an array of data elements. In response to a request to process an item, a hash function is implemented to map an identifier identifying the item to a data element of the array of data elements. A data value of the data element of the array of data elements is used to determine whether the request to process the item can be granted, and the item is allowed to be processed when it is determined that the request to process the item can be granted.
An apparatus comprises value prediction storage storing value prediction entries, each value prediction entry providing a data value prediction associated with a corresponding instruction. A value prediction blocklist identifies one or more blocked instructions, and value prediction allocation circuitry is configured to control whether to allocate a given value prediction entry associated with a given instruction to the value prediction storage in dependence on whether the given instruction is identified as a blocked instruction by the value prediction blocklist. Blocklist allocation circuitry determines whether to add a target instruction to the value prediction blocklist in dependence on an allocation count indicating a number of times a value prediction entry associated with the target instruction has been allocated to the value prediction storage.
A method of data processing in a data processing system comprising a computer vision system. The method comprises obtaining image data representative of a plurality of pixels of an image, the image data comprising a plurality of pixel intensity values respectively representing said pixels. The method comprises identifying one or more compromised pixel intensity values in the plurality of pixel intensity values. The method comprises generating sensor defect state data relating to the identified compromised pixel intensity values. The method comprises performing, using the computer vision system, a feature recognition process on the image data. The method comprises performing an action based on the sensor defect state data.
G06V 10/98 - Détection ou correction d’erreurs, p. ex. en effectuant une deuxième exploration du motif ou par intervention humaineÉvaluation de la qualité des motifs acquis
G06V 20/56 - Contexte ou environnement de l’image à l’extérieur d’un véhicule à partir de capteurs embarqués
An integrated circuit assembly comprises an integrated circuit die comprising a first mounting surface, and a substrate having a first mounting surface and a second mounting surface opposite the first mounting surface. The first mounting surface of the substrate is electrically and physically coupled to the first mounting surface of the integrated circuit die, and the substrate further comprises a first plurality of electrical contact pads on the second mounting surface of the substrate. A vertically integrated voltage regulator has a first mounting surface and a second mounting surface opposite the first mounting surface, and is electrically and physically coupled to the substrate on the second mounting surface of the substrate and the first mounting surface of the vertically integrated voltage regulator. The voltage regulator further comprises a second plurality of electrical contact pads on the second mounting surface of the voltage regulator.
H10D 80/30 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif couvert par la présente sous-classe l’au moins un dispositif étant couvert par les groupes , p. ex. des ensembles comprenant des puces de processeur à circuit intégré
When generating a graphics processing output by assembling a sequence of one or more of primitives to be processed from a set of vertex indices provided for the output based on primitive configuration information provided for the output, one or more vertex packets are generated using the vertex indices for the assembled primitives, each vertex packet comprising a plurality of vertices of the assembled primitives. After a threshold number of vertices have been allocated to a vertex packet, vertex attribute processing for the vertices of the vertex packet is triggered, to thereby generate a vertex packet comprising processed vertex attributes for the vertices of the vertex packet. The assembled primitives and the generated vertex packets are then provided to later stages of the graphics processing pipeline for processing.
There is provided an apparatus comprising history storage circuitry to store history records. Each history record is configured to support a multi-taken encoding identifying: first and second address identifiers of first and second control flow altering instructions, and a local history of changes in control flow resulting from the second control flow altering instruction. The apparatus is provided with pointer storage circuitry to store a global pointer. The apparatus is provided with prediction circuitry responsive to receipt of an address to identify a local history record for which the address corresponds to the second address identifier, and to provide a prediction based on the global pointer. The prediction circuitry is responsive to receipt of the address to identify a further local history record for which the address corresponds to the first address identifier, and to provide a further prediction based on the global pointer.
A method of operating a data processing system, a data processing system, and a computer program product. The data processing system includes processors operable to process a job, wherein the job is divided into tasks, and each processor of the plurality of processors is operable to process one or more tasks of the job. The data processing system defines a volume having two or more predetermined dimensions, wherein the volume includes at least part of the job, and divides the volume into regions based on one or more predetermined dimensions of the volume, one or more corresponding dimensions of a task and the number of processors, each region having an initial region size and each region includes spatially proximate tasks. Each of the regions are initially allocated to a processor, and a task within a region is allocated to the processor that is allocated to the region.
Interconnect circuitry comprises: receiving interface circuitry configured to receive, from a metadata-transmitting caching agent, discard control metadata for a given cache line previously held in a private cache of the data-transmitting caching agent; and transmitting interface circuitry configured to transmit the discard control metadata for the given cache line to a metadata-receiving caching agent for caching in a private cache of the metadata-receiving caching agent. The discard control metadata indicating whether the given cache line is, or is eligible for becoming, a discardable cache line allowed to be discarded without data writeback even if the discardable cache line is dirty.
G06F 12/126 - Commande de remplacement utilisant des algorithmes de remplacement avec maniement spécial des données, p. ex. priorité des données ou des instructions, erreurs de maniement ou repérage
An apparatus comprises cache control circuitry to allocate, to a cache hierarchy comprising a plurality of levels of cache, one or more materialised cache lines corresponding to a region of address space indicated by software-provided information, each materialised cache line specifying a predetermined value as cached data; and cache level selection circuitry to select, based on a size of the region of address space indicated by the software-provided information, at least one target level of the plurality of levels of cache to which the one or more materialised cache lines are to be allocated.
An apparatus for data processing comprises a data processing pipeline to perform data processing operations, and extension processing circuitry to perform a delegated task asynchronously to the data processing pipeline in response to the decoding circuitry decoding an extension start instruction. The apparatus also comprises hazard detection circuitry to detect data hazards associated with processing operations performed by the data processing pipeline. When the data processing pipeline is in an extension hazard checking state, the presence of a hazard condition can be determined in dependence on whether a given memory access, to be performed in response a given memory access instruction following the extension start instruction in program order, is for accessing an address which falls within a group of addresses anticipated to be accessed by the extension processing circuitry during performance of the delegated task.
Interconnect circuitry comprises: receiving interface circuitry configured to receive, from a metadata-transmitting caching agent, discard control metadata for a given cache line previously held in a private cache of the data-transmitting caching agent; and transmitting interface circuitry configured to transmit the discard control metadata for the given cache line to a metadata-receiving caching agent for caching in a private cache of the metadata-receiving caching agent. The discard control metadata indicating whether the given cache line is, or is eligible for becoming, a discardable cache line allowed to be discarded without data writeback even if the discardable cache line is dirty.
G06F 12/00 - Accès à, adressage ou affectation dans des systèmes ou des architectures de mémoires
G06F 12/0802 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache
An apparatus comprises instruction decoding circuitry to decode instructions; processing circuitry to perform data processing in response to instructions decoded by the instruction decoding circuitry; and cache control circuitry to: set, in response to the instruction decoding circuitry decoding a mark-dead instruction specifying mark-dead target address information, one or more target cache lines selected based on the mark-dead target address information as a discardable cache line, wherein the discardable cache line is allowed to be discarded without data writeback even if the discardable cache line is dirty.
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
G06F 12/0891 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache utilisant des moyens d’effacement, d’invalidation ou de réinitialisation
An apparatus comprises cache control circuitry to allocate, to a cache hierarchy comprising a plurality of levels of cache, one or more materialised cache lines corresponding to a region of address space indicated by software-provided information, each materialised cache line specifying a predetermined value as cached data; and cache level selection circuitry to select, based on a size of the region of address space indicated by the software-provided information, at least one target level of the plurality of levels of cache to which the one or more materialised cache lines are to be allocated.
G06F 12/0802 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache
86.
Mark-live instruction that sets discard-eligibility metadata in cache lines for use by mark-dead events
An apparatus comprises instruction decoding circuitry configured to decode instructions; and processing circuitry configured to perform data processing in response to the instructions decoded by the instruction decoding circuitry. Cache control circuitry is configured to set, in response to the instruction decoding circuitry decoding a mark-live instruction specifying mark-live target address information, discard-eligibility metadata associated with one or more target cache lines selected based on the mark-live target address information, to identify the one or more target cache lines as being eligible for being treated as a discardable cache line which is allowed to be discarded without data writeback even if the discardable cache line is dirty. In response to a mark-dead event associated with a given cache line, the cache control circuitry determines depending on the discard-eligibility metadata for the given cache line whether the given cache line is eligible for becoming a discardable cache line.
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
G06F 12/08 - Adressage ou affectationRéadressage dans des systèmes de mémoires hiérarchiques, p. ex. des systèmes de mémoire virtuelle
G06F 12/0875 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache avec mémoire cache dédiée, p. ex. instruction ou pile
87.
ACCELERATOR HAVING PORT TO VIRTUAL MEMORY ADDRESS ASSOCIATION LOGIC
Briefly, example apparatuses, articles of manufacture, and/or techniques are disclosed that may be implemented, in whole or in part, to implement, facilitate and/or support integrated circuitry comprising a cache to associate a plurality of ports to virtual memory addresses, cache control circuitry to update the cache to associate the first port with the virtual memory address responsive to a transaction latency meeting a threshold latency condition.
G06F 12/0802 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache
A circuit for selective write pulse extension including: a first circuit path comprising: a delay element; a second circuit path; and a multiplexer configured to select between respective first and second global timing pulse (GTP) signals of the first circuit path and the second circuit path based on a control signal. A method for selective write pulse extension including detecting, by a circuit, one GTP pulse of a first operation mode or two GTP pulses of a second operation mode per unit cycle, where: the one GTP pulse corresponds to either a read operation or a write operation, and the two GTP pulses correspond to both the read operation and the write operation. Also, in response to the detection of the write operation as the one GTP pulse, at a reset edge of a self-timed path signal, extending a reset pulse width of the self-timed path signal.
G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
An apparatus comprises instruction decoding circuitry configured to decode instructions; and processing circuitry configured to perform data processing in response to the instructions decoded by the instruction decoding circuitry. Cache control circuitry is configured to set, in response to the instruction decoding circuitry decoding a mark-live instruction specifying mark-live target address information, discard-eligibility metadata associated with one or more target cache lines selected based on the mark-live target address information, to identify the one or more target cache lines as being eligible for being treated as a discardable cache line which is allowed to be discarded without data writeback even if the discardable cache line is dirty. In response to a mark-dead event associated with a given cache line, the cache control circuitry determines depending on the discard-eligibility metadata for the given cache line whether the given cache line is eligible for becoming a discardable cache line.
G06F 12/126 - Commande de remplacement utilisant des algorithmes de remplacement avec maniement spécial des données, p. ex. priorité des données ou des instructions, erreurs de maniement ou repérage
An apparatus comprises instruction decoding circuitry to decode instructions; processing circuitry to perform data processing in response to instructions decoded by the instruction decoding circuitry; and cache control circuitry to: set, in response to the instruction decoding circuitry decoding a mark-dead instruction specifying mark-dead target address information, one or more target cache lines selected based on the mark-dead target address information as a discardable cache line, wherein the discardable cache line is allowed to be discarded without data writeback even if the discardable cache line is dirty.
G06F 12/126 - Commande de remplacement utilisant des algorithmes de remplacement avec maniement spécial des données, p. ex. priorité des données ou des instructions, erreurs de maniement ou repérage
09 - Appareils et instruments scientifiques et électriques
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Integrated circuits; semiconductors; system-on-chip devices;
microprocessors; processors [central processing units];
microprocessors in the field of artificial intelligence;
neural network processors; electronic chips;
application-specific integrated circuits; graphics
processing units; semiconductor intellectual property cores;
computer interfaces, namely instruction set architectures;
printed circuit boards; computer software for integrated
circuits; semiconductors for handheld and mobile devices;
downloadable computer operating software; computer hardware
and recorded computer software, namely, computer subsystems
featuring standardized and optimized hardware and software
components for providing specific levels of computing
performance and functionality sold as a unit; electronic
downloadable materials, namely, electronic downloadable
instruction and development manuals, datasheets and
brochures, all in the area of design and development of
integrated circuits, microprocessors, microprocessor cores,
macro cells, microcontrollers, bus interfaces, and printed
circuit boards; none of the aforementioned in relation to
optoelectronic products, pushbutton switches, capacitive
touch switches, micro switches and rocker switches. Design of semiconductors, microprocessors, system-on-chip
devices, processors [central processing units], chips
[integrated circuits], application-specific integrated
circuits, graphics processing units, machine learning
processors and semiconductor cores; research, development,
and design relating to computer hardware for semiconductor
intellectual property, instruction set architectures,
microprocessors; research, development and design, all
relating to computer software used in, and for use in the
design, verification and construction of microprocessors,
processors, microcontrollers, microprocessor design files,
semiconductor intellectual property cores, computer hardware
accelerators, neural network processors and machine learning
processors; none of the aforementioned in relation to
optoelectronic products, pushbutton switches, capacitive
touch switches, micro switches and rocker switches.
92.
DEBUGGING INSTRUCTION EXECUTION ERRORS IN A SIMULATED COMPUTER SYSTEM
A computing system and associated methods are described for validating behavioral equivalence between different builds of a simulator codebase. Two simulator builds, generated using different build configurations and expected to behave identically for a workload, are selected and used to execute the workload. Trace operations are performed during execution, and checksum values are accumulated and reported at a defined reporting frequency. The checksum values from the executions are compared to detect a mismatch indicative of divergent simulator behavior. When a mismatch is detected, an instruction execution deviation is localized based on an instruction count and the reporting frequency. The techniques support comparison of simulator builds executing on different host operating systems, processor architectures, or translation and code generation configurations, and are applicable to workloads including operating system boot code.
40 - Traitement de matériaux; recyclage, purification de l'air et traitement de l'eau
Produits et services
Custom manufacturing of chips [integrated circuits] for
others; custom manufacture of semiconductor wafers; custom
manufacture of semiconductor circuits; custom manufacture of
semiconductor components; encapsulation of semiconductors.
A graphics processing system that comprises a graphics processor operable to perform ray tracing is disclosed. Instructions of set of ray tracing shader programs that define different elements of a ray tracing pipeline are combined to generate a combined ray tracing shader program, and the combined ray tracing shader program is provided for execution by a graphics processor.
An apparatus (10) and a method are provided, wherein the apparatus comprises interrupt detection circuitry (40) which detects interrupts raised by at least one interrupt source (14), and interrupt tracking circuitry (44) which manages one or more hard-ware-managed linked list data structures to track pending interrupts detected by the interrupt detection circuitry. A computer program comprising computer-readable code for fabrication of the apparatus, and a computer-readable storage medium are also provided.
When performing tile-based rendering a first, pre-pass operation in which primitives in a sequence of primitives for a tile are processed to determine visibility information for the sequence of primitives, the visibility information being usable to determine whether or not fragments for a primitive in the sequence of primitives should subsequently be processed further for the render output, is performed. Thereafter a second, main pass operation is performed in which the further processing of fragments for primitives that were processed during the first, pre-pass operation is controlled based on the determined visibility information for the sequence of primitives, such that for fragments for which the visibility information indicates that the fragments should not be processed further for the render output some or all of the processing during the second, main pass is omitted.
There is provided a control apparatus in which assertion circuitry asserts a request for usage devices to change their usage of a resource from an original usage. Receive circuitry receives a response to the request from the usage devices and hint circuitry asserts a hint to those of the plurality of usage devices for which the response has not been received, that a refusal in response to the request is preferred over an acceptance. There is also provided a usage device in which receive circuitry receives a request from a control apparatus to change the usage device's usage of a resource from an original usage, and receives a hint from the control apparatus that a refusal in response to the request is optional and preferred. Determination circuitry makes a determination of whether the request is to be met based on at least one of: the request and the hint and response circuitry provides a response to the request based on the determination.
An integrated circuit assembly comprises a substrate, and an integrated circuit die (202) physically and electrically attached to the substrate (204). A stiffener is attached to the substrate, the stiffener comprising a planar portion (212) and a protruding portion (216), the planar portion to be attached to the substrate and to be positioned approximately parallel to a planar surface of the substrate, the protruding portion to extend away from the planar portion of the stiffener.
09 - Appareils et instruments scientifiques et électriques
35 - Publicité; Affaires commerciales
41 - Éducation, divertissements, activités sportives et culturelles
Produits et services
Electronic publications, downloadable, in the nature of instruction manuals, user manuals, technical manuals, development manuals, datasheets, brochures, articles, newsletters, blogs, books, magazines, journals, research papers and white papers in the field of semiconductor and computer hardware design, development and manufacture, artificial intelligence, and software design and development; visual and audio recordings featuring educational videos and podcasts in the field of semiconductor and computer hardware design, development and manufacture, artificial intelligence, and software design and development Arranging and conducting live, virtual or hybrid business exhibitions in the field of technology, semiconductor and computer hardware design, development and manufacture, artificial intelligence, and software design and development; business networking; organizing business networking events in the field of technology, semiconductor and computer hardware design, development and manufacture, artificial intelligence, and software design and development; general business networking referral services, namely, promoting the goods and services of others by passing business leads and referrals among group members; advertising, marketing and promotional services related to technology, semiconductor and computer hardware design, development and manufacture, artificial intelligence, and software design and development for the purpose of facilitating networking and socializing opportunities for business purposes Providing online non-downloadable publications in the nature of educational and training materials in the field of technology, semiconductor and computer hardware design, development and manufacture, artificial intelligence, and software design and development; providing online non-downloadable visual and audio recordings featuring educational videos and podcasts in the field of technology, semiconductor and computer hardware design, development and manufacture, artificial intelligence, and software design and development; arranging and conducting live, virtual or hybrid conferences and exhibitions in the field of technology, semiconductor and computer hardware design, development and manufacture, artificial intelligence, and software design and development; educational and training services, namely, conducting classes, seminars, technical sessions, workshops, presentations, educational panels, hosting speakers all in the field of technology, semiconductor and computer hardware design, development and manufacture, artificial intelligence, and software design and development; arranging and conducting competitions, quizzes and lotteries in the area of testing knowledge about technology, semiconductor and computer hardware design, development and manufacture, artificial intelligence, and software design and development
A monitoring system for high-integrity monitoring of a safety-critical target system comprises an interface for receiving messages from a target system according to a publish-subscribe communication protocol, and one or more processors. The monitoring system is configured to access configuration data representing one or more expected timing characteristics for a succession of messages that are to be published by the target system in accordance with the publish-subscribe communication protocol and to subscribe, using the publish-subscribe communication protocol, to receive the succession of messages. The monitoring system receives the succession of messages, each comprising a respective publication timestamp, at the interface, and uses the configuration data to determine whether the publication timestamps of the received succession of messages are consistent with the expected timing characteristics. If the publication timestamps of the received succession of messages are not consistent with the expected timing characteristics, the monitoring system signals an inconsistency.
H04L 67/12 - Protocoles spécialement adaptés aux environnements propriétaires ou de mise en réseau pour un usage spécial, p. ex. les réseaux médicaux, les réseaux de capteurs, les réseaux dans les véhicules ou les réseaux de mesure à distance
