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2026
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G/S
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Electronic publications, downloadable, in the nature of instruction manuals, user manuals, techni... |
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G/S
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Custom manufacturing of chips [integrated circuits] for
others; custom manufacture of semiconduc... |
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G/S
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Integrated circuits; semiconductors; system-on-chip devices; microprocessors; processors [central... |
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G/S
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Integrated circuits; semiconductors; system-on-chip devices;
microprocessors; processors [centra... |
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G/S
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Custom manufacturing of chips [integrated circuits] for others; Custom manufacture of semiconduct... |
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G/S
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Custom manufacturing of computer chips being integrated circuits for others; Custom manufacture o... |
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Invention
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Graphics processing systems.
When generating a graphics processing output by assembling a sequen... |
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Invention
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Method, system and program for data processing.
A method of data processing in a data processing... |
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Invention
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Debugging instruction execution errors in a simulated computer system.
A computing system and as... |
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G/S
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Downloadable computer software for computer system and application development, deployment and ma... |
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G/S
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Computer software; computer software development tools; computer software development tools in th... |
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Invention
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Memory access request. There is provided an apparatus, a system, a chip-containing product, a met... |
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G/S
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Development of voluntary standards for the interoperability and security of computer instruction ... |
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Invention
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Dual-sided vertical integrated voltage regulator. An integrated circuit assembly comprises an int... |
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Invention
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Variable-length instruction set mode. In a variable-length instruction set mode, front end circui... |
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Invention
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Expandable instruction set. An apparatus comprises front end circuitry configured to fetch and de... |
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Invention
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Container-based instruction set. In a container-based instruction set mode for processing instruc... |
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Invention
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Arithmetic combination operation. There is provided an apparatus comprising decoder circuitry, re... |
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Invention
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Contention hint instruction. An apparatus comprises instruction decoding circuitry configured to ... |
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Invention
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Graphics processing.
A graphics processing system that comprises a graphics processor operable t... |
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2025
|
Invention
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Discard control metadata. Interconnect circuitry comprises: receiving interface circuitry configu... |
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Invention
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Cache level selection. An apparatus comprises cache control circuitry to allocate, to a cache hie... |
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Invention
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Mark-live instruction. An apparatus comprises instruction decoding circuitry configured to decode... |
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Invention
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Mark-dead instruction. An apparatus comprises instruction decoding circuitry to decode instructio... |
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Invention
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Integrated circuit substrate stiffener. An integrated circuit assembly comprises a substrate, and... |
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G/S
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Integrated circuits; semiconductors; system-on-chip devices; microprocessors; processors, namely,... |
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G/S
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Integrated circuits; semiconductors; system-on-chip devices; microprocessors; processors [ centra... |
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Invention
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Using throttler for droop mitigation. A clock throttler circuit for droop mitigation and disclose... |
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Invention
|
Dual-sided vertical integrated voltage regulator.
An integrated circuit assembly comprises an in... |
|
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Invention
|
Throttler based mitigator. A throttler based mitigator including circuitry, related methods and s... |
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G/S
|
Integrated circuits; Semiconductors; System-on-chips; Microprocessors; Computer central processin... |
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G/S
|
Integrated circuits; semiconductors; electronic circuits for system- on-chip devices; microproces... |
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G/S
|
Integrated circuits; semiconductors; electronic circuits for
system- on-chip devices; microproce... |
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G/S
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Computer hardware and recorded computer software, namely, computer subsystems featuring standardi... |
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G/S
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Computer hardware and recorded computer software, namely, computer subsystems comprised of standa... |
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G/S
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Computer software development tools in the field of artificial intelligence; computer software an... |
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Invention
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Fetch skipping.
An apparatus includes no-op-compatible instruction tracking circuitry configured... |
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Invention
|
Control flow prediction.
An apparatus comprises prediction circuitry to generate a predicted out... |
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Invention
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Value prediction.
An apparatus comprises value prediction storage providing value prediction ent... |
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Invention
|
Expandable instruction set.
An apparatus comprises front end circuitry configured to fetch and d... |
|
|
Invention
|
Variable-length instruction set mode.
In a variable-length instruction set mode, front end circu... |
|
|
Invention
|
Container-based instruction set.
An apparatus comprises: front end circuitry configured to fetch... |
|
|
Invention
|
Arithmetic combination operation.
There is provided an apparatus comprising decoder circuitry, r... |
|
|
Invention
|
Power management systems and circuitry.
Power multiplexer circuitry, systems, and methods. Power... |
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Invention
|
Contention hint instruction.
An apparatus comprises instruction decoding circuitry configured to... |
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|
Invention
|
Prediction circuitry.
There is provided an apparatus comprising processing circuitry to perform ... |
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|
Invention
|
Value prediction.
An apparatus comprises value prediction storage storing value prediction entri... |
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Invention
|
Prediction of a change in control flow.
There is provided an apparatus comprising history storag... |
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Invention
|
Storage meta data interrogation.
Systems and methods for determining whether a region of storage... |
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Invention
|
Processing control of data elements in data processing systems.
A data processing system is disc... |
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Invention
|
Accelerator having port to virtual memory address association logic.
Briefly, example apparatuse... |
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Invention
|
Gtp reset circuitry and methods.
A circuit for selective write pulse extension including: a firs... |
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Invention
|
Data processing system.
A method of operating a data processing system, a data processing system... |
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Invention
|
Mark-dead instruction.
An apparatus comprises instruction decoding circuitry to decode instructi... |
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|
Invention
|
Cache level selection.
An apparatus comprises cache control circuitry to allocate, to a cache hi... |
|
|
Invention
|
Mark-live instruction that sets discard-eligibility metadata in cache lines for use by mark-dead ... |
|
2024
|
Invention
|
Integrated circuit substrate stiffener.
An integrated circuit assembly comprises a substrate, an... |
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Invention
|
Opacity micromap rounding.
Systems and methods of graphics processing in which property values f... |
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Invention
|
Agentic ai systems and methods of context disambiguation.
The present disclosure relates to a sy... |
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Invention
|
Safety-critical monitoring.
A monitoring system for high-integrity monitoring of a safety-critic... |
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Invention
|
Performance queries in graphics processing.
Graphics processors and methods of operating a graph... |
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Invention
|
Hazard-checking in task delegation.
An apparatus for data processing comprises a data processing... |
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Invention
|
Tag protecting instruction.
Access control circuitry (15), responsive to a memory access request... |
|
2023
|
Invention
|
Graphics processors.
When performing tile-based rendering a first, pre-pass operation in which p... |
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Invention
|
Resource usage transition hints.
There is provided a control apparatus in which assertion circui... |
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Invention
|
Apparatus comprising interrupt tracking circuitry.
An apparatus (10) and a method are provided, ... |
