The disclosed memory sub-system controller triggers read level voltage correction for reading a second portion of a memory based on errors encountered while reading data from a first portion of the memory. The controller reads a first portion of data from a first portion of a set of memory components using a set of read threshold levels and determines a read bit error rate (RBER) associated with the data read from the first portion of the set of memory components. The controller determines that the RBER associated with the data read from the first portion transgresses a threshold RBER. The controller selects an individual read level correction process from a plurality of read level correction processes and reads a second portion of data from a second portion of the set of memory components using the set of read threshold levels adjusted based on the selected individual read level correction process.
A system and method for memory error recovery in CXL components is presented. The method includes determining that a memory component has sustained a hard failure in a Cyclic Redundancy Check-Redundant Array of Independent Devices (CRC-RAID) mechanism. The method further includes determining a location of the memory component failure, wherein the CRC-RAID mechanism comprises a plurality of memory components configured as a plurality of stripes and initiates a write operation of user data to a location within a particular stripe, wherein the particular stripe contains a failed memory component. The method includes compensating for the failed memory component, wherein the compensating comprises a plurality of read operations prior to a writing of the user data.
A variety of applications can include one or more memory devices having one or more memory cells containing a blocking dielectric separating a charge trap region from a control gate, where the blocking dielectric includes a high-k dielectric between and contacting a wide bandgap dielectric and the charge trap region. Another high-k dielectric can be positioned contacting the wide bandgap dielectric on a side of the wide bandgap dielectric opposite the side on which the first high-k dielectric is positioned, forming a sandwiched structure. Additional devices, systems, and methods are discussed.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10D 64/68 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
Methods, systems, and devices for memory system boot sequence with reduced latency are described. A host system may assert a signal (e.g., a fast boot signal) to a pin of a memory system, which may instruct the memory system to communicate data at a first data rate (e.g., a relatively lower data rate) before negotiating to a higher data rate (e.g., a highest data rate). The host system may output the fast boot signal to the memory system based on an estimated size of the data to be transferred, a dynamic measurement of the data, an application associated with the data, or any combination thereof. Based on transferring the data, the host system and the memory system may negotiate to an increased data rate (e.g., up to the highest supported data rate).
In response to determining that a representative number of program erase cycles (PECs) for a set of blocks of the memory device satisfies a condition, one or more trim values associated with the set of blocks are set according to the representative number of PECs for the set of blocks, wherein each programmed block in the set of blocks having been programmed within at least one of a specified time window or a specified temperature window. In response to receiving a write command directed to a block of the set of blocks, the write command is executed according to the one or more trim values.
Various embodiments provide for compression on a memory system controller of data generated by multiple reads performed on a set of pages of a memory device of the memory system. Such compression can be useful for storing and subsequently using data (e.g., comprising one-hard-two-soft (1H2S) information data) generated by the multiple reads to perform a management operation on the memory device, such as a read level calibration operation.
A semiconductor device assembly includes a semiconductor die, a substrate, and a spacer directly coupled to the substrate. The spacer includes a flexible main body and a support structure embedded in the flexible main body, wherein the support structure has a higher stiffness than the flexible main body. The spacer carries the semiconductor die. The flexible main body of the spacer mitigates the effects of thermomechanical stress, for example caused by a mismatch between the coefficient of thermal expansion of the semiconductor die and the substrate. The embedded support structure provides strength needed to support the semiconductor die during assembly.
A storage product manufactured as a computer component and configured to have: a secure memory region to store cryptographic keys; a network interface; a local storage device having a storage capacity accessible via the network interface; and a host interface to be connected to a local host system. The local host system can control access, made via the network interface, to the storage capacity without receiving a portion of storage access messages received in the network interface. The storage product includes an access controller configured to determine whether a message, received in the network interface from the computer network or in the host interface from the local host system, has a valid verification code according to the cryptographic keys; and if not, the message can be rejected, deleted, discarded, or ignored without further processing.
Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly includes a first substrate having first electrical traces and a second substrate having second electrical traces, where the second electrical traces are electrically coupled with the first electrical traces using at least one wire bond. The semiconductor device assembly includes an integrated circuit between the first substrate and the second substrate, where the integrated circuit is electrically coupled with the first electrical traces using at least one conductive structure.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H05K 1/14 - Structural association of two or more printed circuits
H05K 1/18 - Printed circuits structurally associated with non-printed electric components
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H10D 80/30 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising integrated circuit processor chips
10.
RADIATION MONITORING USING ACCUMULATED PARITY OF NON-PROTECTED LATCHES
Methods, systems, and devices for radiation monitoring using accumulated parity of non-protected latches are described. An array of non-protected latches store data over time and may be monitored using one or more latches to determine whether one or more errors occur. In some cases, the array may include multiple lanes of latches, where each lane may include a lane latch for parity testing and an output latch. During a parity scan, parity may be periodically generated for the data of each lane and compared to previous parity results to keep track of any soft error events that occur. The parity results for each lane may be combined to output an error flag. In some examples, the error flag may be output to a mode register, and parity testing may be performed based on one or more commands, modes, one or more counters, or with error correction operations.
G11C 29/42 - Response verification devices using error correcting codes [ECC] or parity check
G11C 29/12 - Built-in arrangements for testing, e.g. built-in self testing [BIST]
G11C 29/48 - Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
Methods, systems, and devices for caching identifiers for access commands are described. A memory sub-system can receive an access command to perform an access operation on a transfer unit of the memory sub-system. The memory sub-system can store an identifier associated with the access command in a memory component and can generate an internal command using a first core of the memory sub-system. In some embodiments, the memory sub-system can store the identifier in a shared memory that is accessible by the first core and can issue the internal command to perform the access operation on the memory sub-system.
Methods, systems, and devices for memory system power management integrated circuitry monitoring are described. A system management controller may poll registers of a power integrated management circuit (PMIC) of a memory system in response to receiving an indication of a failure at the PMIC that may trigger a shutdown condition of the memory system. For example, despite the memory system being in a shutdown condition, power to the registers of the PMIC may remain enabled, and values from the PMIC register may be polled and stored by the system management controller. The values from the PMIC register may indicate a location of the failure of the PMIC or one or more operating parameters of the PMIC during the point of failure. The system management controller may output the stored values from the PMIC registers, which may support identification of root causes of failure at the PMIC.
Systems and methods are provided for generating timing control signals for controlling the access to the memory cells of a memory device. The memory device employs a counter-based RAS chain circuit including multiple Match and Delay blocks to generate timing control signals with fine timing granularities. The Match and Delay blocks include circuits to enable area savings and improve area efficiency (AE) in the memory device as well as improve the flexibility for development chips and production parts.
A semiconductor device having monolithic conductive columns, and associated systems and methods, are disclosed herein. The semiconductor device can include a semiconductor substrate, a conductive pad, an opening, a non-conductive liner, and a plug of non-conductive material. The conductive pad may be at a surface of the semiconductor substrate. The opening may extend through the semiconductor substrate from the conductive pad to a second surface and define a side wall. The liner may coat the side wall and the plug may fill the opening. A second opening may be formed through the semiconductor device and the opening and a conductive material sintering therein.
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
Methods, systems, and devices for erase verify skip for fast cycling are described. A memory device may receive a command to perform an erase operation involving a first type of erase operation excluding an erase verify operation, and may apply a pre-programming pulse and an erase pulse to a block of memory cells while skipping an erase verify operation for one or more memory cells of the block based on the command. In some examples, the memory device may skip one or more erase verify operations based one or more internal trim settings. Additionally, or alternatively, erase verify skipping may be adaptive. For example, once a quantity of erase operations satisfies a threshold quantity, the memory device may receive a second command and may perform a second erase operation involving performing an erase verify operation for one or more memory cells of the block.
Examples of systems and methods described herein provide for accessing memory devices and, concurrently, generating access codes using an authenticated stream cipher at a memory controller. For example, a memory controller may use a memory access request to, concurrently, perform translation logic and/or error correction on data associated with the memory access request; while also utilizing the memory address as an initialization vector for an authenticated stream cipher to generate an access code. The error correction may be performed subsequent to address translation for a write operation (or prior to address translation for a read operation) to improve processing speed of memory access requests at a memory controller; while the memory controller also generates the encrypted access code.
H04L 9/06 - Arrangements for secret or secure communicationsNetwork security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
17.
VARIABLE-LENGTH LOCKED-RAID FOR CXL DEVICES WITH COMPRESSION
In a locked RAID memory system, the present method generates variable-length compressed data in a RAID stripe, which is stored along with the inclusion of a single RAID parity segment (parity strip) for the entire stripe. If any one data segment (data strip) in the RAID stripe should fail, as determined by a CRC check, the data can be recovered by XORing the single RAID parity segment with all the non-errored data segments in the stripe. However, in order to determine which data segment has failed, successive data segments must be XORed, and the CRC check reperformed, until the CRC error stands corrected. In an embodiment, the successive data segments may be tested in parallel with suitable hardware. In an embodiment, the successive data segments may be tested sequentially, or semi-in-parallel and semi-sequentially.
A transistor includes a source, a drain, a gate layer, an undoped or lightly doped channel layer, and a gate dielectric layer. The undoped or lightly doped channel layer extends between the source and the drain. The channel layer includes at least one heavily doped region to distribute channel potential along the channel layer. The gate dielectric layer is between the gate layer and the channel layer.
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
19.
HARDWARE BASED STATUS COLLECTOR ACCELERATION ENGINE FOR MEMORY SUB-SYSTEM OPERATIONS
Methods, systems, and devices for one or more acceleration engines for memory sub-system operations are described. An acceleration engine can perform one or more validation procedures on one or more codewords of a management unit. The acceleration engine can collect validation data for the management unit based on performing the validation procedures. The acceleration engine can aggregate the validation data into group validation data associated with a set of management units. The acceleration engine can transmit the group validation data to firmware of a memory sub-system or a host device.
In some implementations, an extended reality (XR) device may detect, using a camera of the XR device, a clothing item, wherein the clothing item is associated with an identifier. The XR device may transmit, to a server, a request that indicates the identifier. The XR device may receive, from the server, metadata associated with the clothing item, wherein the metadata is associated with the identifier. The XR device may retrieve, from the server, a three-dimensional model of a user associated with the XR device. The XR device may generate a three-dimensional model of the user wearing the clothing item using the three-dimensional model of the user and the metadata. The XR device may provide, via an interface of the XR device, the three-dimensional model of the user wearing the clothing item.
G06Q 50/00 - Information and communication technology [ICT] specially adapted for implementation of business processes of specific business sectors, e.g. utilities or tourism
G06V 20/20 - ScenesScene-specific elements in augmented reality scenes
An example apparatus includes a first circuit configured to activate a first control signal responsive to a second control signal and deactivate the first control signal responsive to a third control signal, a second circuit coupled to the first circuit and configured to output a clock signal when predetermined clock cycles elapsed after the first control signal is activated, and a third circuit coupled to the second circuit and configured to count the clock signal. The third circuit is configured to activate the third control signal when a count value reaches a first value and activate a fourth control signal when a count value reaches a second value greater than the first value. The difference between the second value and the first value is the predetermined clock cycles or less.
Methods, systems, and devices for section yielding in stacked memory architectures are described. A system that implements a stacked semiconductor architecture may include wafers that are divided into die units having multiple sections, and the sections may be coupled as die unit section stacks through a stack of wafers. After stacking the semiconductor wafers (e.g., before or after singulation of die stacks from the stacked wafers), functionality of the die unit section stacks may be evaluated. If a die unit section stack is found to include an error or relatively low performance, the die unit section stack may be disabled, such that other die unit section stacks of a stacked die assembly may be operated (e.g., operated in accordance with a capacity or throughput associated with the remaining memory die unit section stacks).
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
Devices and techniques are disclosed herein for providing L2P information to a host device from a storage system, the L2P information comprising a response information unit having a limited size with separate categories of information including changed L2P region and associated subregion information, to-be-loaded L2P region and associated subregion information, and invalid L2P region and associated subregion information, wherein the information in the separate categories is based on the determined changes in the different L2P regions and the subregion information in each of the separate categories identifies specific locations of changed subregions with respect to one or more corresponding regions identified in the region information of a respective category of the response information unit.
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 12/0891 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
24.
PROTRUDED BOND PADS FOR HYBRID BONDING OF SEMICONDUCTOR DEVICES
A semiconductor device assembly including a first semiconductor die having a first dielectric region and a first bond pad that are disposed on a first side of the first semiconductor die, and a second semiconductor die having a second dielectric region and a second bond pad that are disposed on a second side of the second semiconductor die, wherein a hybrid bonding interface between the first side of the first semiconductor die and the second side of the second semiconductor die includes a conductive region between the first bond pad and the second bond pad, and wherein the conductive region and at least one of the first and the second bond pads include a same conductive material element, and the conductive region has an electrical resistivity lower than the at least one of the first and the second bond pads.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H10D 80/30 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising integrated circuit processor chips
25.
MULTI-ROLE SEMICONDUCTOR DEVICE SUBSTRATES, SEMICONDUCTOR DEVICE ASSEMBLIES EMPLOYING THE SAME, AND METHODS FOR FORMING THE SAME
A semiconductor device assembly is provided. The assembly includes a substrate having an upper surface on which is disposed a first device contact, a keep-out region extending from a first side surface of the substrate to a second side surface of the substrate opposite the first, and at least one trace coupled to the first device contact and extending across the keep out region towards a third side surface of the substrate. The assembly further includes at least one semiconductor device disposed over the upper surface of the substrate and coupled to the first device contact. The keep-out region of the substrate is free from conductive structures other than the at least one trace.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/552 - Protection against radiation, e.g. light
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
A phase detector circuit may receive a reference clock signal and a clock signal and detect a phase difference between the two clock signals and output a signal indicative of the phase difference. In some examples, the reference clock signal and the clock signal may be provided to multiple inputs of the phase detector circuit. In some examples, the phase detector circuit may include one or more NOR latches. In some examples, the phase detector circuit may include one or more NAND circuits.
G06F 1/08 - Clock generators with changeable or programmable clock frequency
G06F 1/12 - Synchronisation of different clock signals
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
27.
SEMICONDUCTOR DEVICES WITH NANO-VIAS, SUCH AS NANO-THROUGH-SILICON VIAS LANDING ON MIDDLE-OF-LINE OR BACK-END-OF-LINE LAYERS
Semiconductor devices with nano-vias, such as nano-through-silicon vias landing on middle-of-line (MOL) or back-end-of-line (BEOL) layers, are disclosed herein. In one embodiment, a semiconductor die includes a first side, a bond pad at the first side, a landing pad within an intermediate layer of the semiconductor die, and a via extending from the bond pad to the landing pad. The via can have an aspect ratio of height to width of 6:1 or less. The intermediate layer can be positioned between the first side and a second side of the semiconductor die opposite the first side. In some embodiments, the intermediate layer is a MOL layer. In other embodiments, the intermediate layer is a BEOL layer. The semiconductor die can be a memory die, a logic die, a central processing unit (CPU) die, a graphics processing unit (GPU) die, a tensor processing unit (TPU) die, or another type of die.
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
28.
FIRMWARE POWER UP SEQUENCING IN MEMORY SUB-SYSTEMS
A front-end firmware component of a memory sub-system receives a first request to perform a first set of initialization operations and initiates a first set of initialization operations for the front-end component in parallel with initiating a second set of initialization operations for a back-end component. Responsive to completing the first set of initialization operations, the front-end component sends a first notification to a host computer system to indicate that the front-end component is available to respond to requests for configuration data associated with the memory sub-system, receives a second request from the host computer system for a configuration data associated with the memory sub-system, and responsive to receiving the second request from the host computer system before the back-end component has completed the second set of initialization operations, provides the configuration data to the host computer system.
Some embodiments include an integrated assembly having first conductive lines which extend along a first direction, and having second conductive lines over the first conductive lines and which extend along a second direction that crosses the first direction. Capacitors are over the second conductive lines. The second conductive lines are operatively proximate active structures to gatedly couple a first set of the capacitors to the first conductive lines through the active structures. Shield structures are between the first conductive lines and extend along the first direction. A voltage source is electrically coupled to the shield structures through a second set of the capacitors. Some embodiments include assemblies having two or more decks stacked one atop another.
H10B 12/00 - Dynamic random access memory [DRAM] devices
G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
G11C 11/4091 - Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
In some implementations, a memory device may detect that data is to be written for a set of temperature profiles. The memory device may write, at respective temperatures corresponding to the set of temperature profiles, multiple copies of the data. The memory device may receive, from a host device, a read request associated with the data. The memory device may detect, based on receiving the read request, a current temperature of the memory device. The memory device may read a copy, from the multiple copies, that is associated with a temperature profile, from the set of temperature profiles, that corresponds to the current temperature of the memory device. The memory device may provide, to the host device, the copy of the data.
A method of forming an electronic device comprises forming a stack structure comprising vertically alternating insulative structures and additional insulative structures, and forming pillars comprising a channel material and at least one dielectric material vertically extending through the stack structure. The method comprises removing the additional insulative structures to form cell openings, forming a first conductive material within a portion of the cell openings, and forming a fill material adjacent to the first conductive material and within the cell openings. The fill material comprises sacrificial portions. The method comprises removing the sacrificial portions of the fill material, and forming a second conductive material within the cell openings in locations previously occupied by the sacrificial portions of the fill material. Related electronic devices, memory devices, and systems are also described.
Disclosed in some examples, are methods, systems, and machine-readable mediums in which application state is saved using in-memory versioning in a shared memory pool of disaggregated memory. By utilizing a disaggregated memory pool, the processing resources may be on separate devices than the memory those resources are using. As a result of this architecture, a failure of hardware of processing resources or an application does not necessarily also cause the hardware resources of the memory devices to fail. This allows a standby application executing on standby processing resources to quickly resume execution when a primary application fails by utilizing the memory pool assigned to the primary application in the memory pool.
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
G06F 9/455 - EmulationInterpretationSoftware simulation, e.g. virtualisation or emulation of application or operating system execution engines
G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
33.
FIXED RATIO MEMORY TIERING WITH VARIABLE CACHE LINE SIZE
Apparatus and methods are disclosed, including sending, by an application executing on a processor of a computing system to a dynamic random access memory (DRAM), a memory operation indicating a DRAM cache line stored in the DRAM; receiving, by the processor, DRAM metadata stored in the DRAM for the DRAM cache line; identifying, by the processor, a tiered memory region of multiple tiered memory regions storing a tiered memory cache line containing target data of the memory operation when the DRAM metadata indicates that the target data is not stored in the DRAM cache line; and loading the tiered memory cache line containing the target data into the DRAM, loading the DRAM cache line into the identified tiered memory region, and updating the DRAM metadata.
Methods, apparatuses and systems related to managing stored data in view of charge losses are described. An apparatus may include a management mechanism that scans memory cells and adjusts read voltage levels for the memory cells to account for charge losses during operation of the apparatus. The apparatus may further leverage the management mechanism to detect or estimate one or more targeted conditions by tracking an adjustment progress while implementing the management mechanism. When the adjustment progress reaches a predetermined condition, the apparatus can estimate the occurrence of the one or more targeted conditions and implement a data refresh mechanism to restore the charges to their intended levels instead of completing the management mechanism.
A microelectronic device includes a stack structure comprising a vertically alternating sequence of insulative and conductive structures arranged in tiers. At least one pillar, comprising a channel material, extends through the stack structure. A source region, below the stack structure, comprises a doped material with vertical extensions that protrude to an interface with the channel material at an elevation proximate at least one source-side GIDL region. Slit structures extend through the stack structure to divide the structure into blocks of pillar arrays. A series of spaced, discrete pedestal structures are included along a base of the slit structures. Forming the microelectronic device structure may include forming a lateral opening through cell materials of the pillar, vertically recessing the channel material, and laterally recessing other material(s) of the pillar before forming the doped material in the broadened recesses. Additional microelectronic devices, related methods, and electronic systems are also disclosed.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
The present disclosure includes apparatuses, methods, and systems for pre-decoder circuitry. An embodiment includes a memory array including a plurality of memory cells, decoder circuitry coupled to the memory array, wherein the decoder circuitry comprises a p-type transistor having a first gate, a first n-type transistor having a second gate, and a second n-type transistor having a third gate, and pre-decoder circuitry configured to provide a bias condition for the first gate, the second gate, and the third gate to provide a selection signal to one of the plurality of memory cells, wherein the bias condition comprises zero volts for the first gate, the second gate, and the third gate for a positive configuration for the memory cells and a negative voltage for the third gate and zero volts for the first gate and the second gate for a negative configuration for the memory cells.
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
A variety of applications can include one or more memory devices having one or more memory cells containing a blocking dielectric separating a charge trap region from a control gate, where the blocking dielectric includes a high-k dielectric between and contacting a wide bandgap dielectric and the charge trap region. Another high-k dielectric can be positioned contacting the wide bandgap dielectric on a side of the wide bandgap dielectric opposite the side on which the first high-k dielectric is positioned, forming a sandwiched structure. Additional devices, systems, and methods are discussed.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
38.
MEMORY DEVICE USING WORDLINE DRIVERS WITH CROSSING ROW OUTPUTS
Systems, methods, and apparatus related to memory devices. In one approach, a memory device includes wordlines connected to rows of memory cells in a memory array. Driver circuitry applies voltages to the wordlines for accessing data stored in the memory cells. A row ordering for the wordlines is implemented with non-aligned logical-to-physical addressing so that wordlines on opposite sides of individual drivers are not physically aligned in the memory array.
Methods, systems, and devices for signal delay control with inverted feedback are described. A system may include a delay circuit that is configured with a chain of delay elements along a forward path of the delay circuit and one or more feedback elements that provide electrical feedback to the forward path. Feedback elements may be or include feedback inverters, such as tri-state inverters, with one or more inputs that are operable to control a signal strength at an output of the feedback inverter. A feedback signal may contend with a signal along the forward path, which may reduce a voltage level associated with the forward signal. By controlling the strength of the feedback signal, the delay circuit may be able to dynamically adjust a delay of the forward signal.
G11C 7/22 - Read-write [R-W] timing or clocking circuitsRead-write [R-W] control signal generators or management
H03K 5/134 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active-delay devices with field-effect transistors
Methods, systems, and devices for phase error detection and correction are described. A system may implement phase detection circuits configured to receive one or more respective clock signals from one or more phase adjustor circuits. The phase detection circuits may perform a comparison between the respective clock signals. The phase detector circuits may utilize multiple sets of transistors to compare the clock signals. The multiple sets of transistors may be coupled between various current sources and outputs of the circuit. The transistors may be operable based on multiple clock signals received from the phase adjustor circuits. The phase detector circuit may compare various voltage levels at respective outputs to detect one or more phase errors and output one or more phase errors to the phase adjustor circuits.
In some implementations, a memory device may receive a read command instructing the memory device to read a first set of host data stored at a memory component that is associated with a memory component rank, of multiple memory component ranks associated with a channel. The memory device may read, via the channel based on receiving the read command, the first set of host data using a read-only interface associated with the memory component. The memory device may receive a write command instructing the memory device to write a second set of host data to the memory component. The memory device may write, via the channel and based on receiving the write command, the second set of host data to the memory component using a write-only interface associated with the memory component.
Methods, systems, and devices for endurance group for tiered storage applications are described. A memory system may implement a single memory device with different types of memory and corresponding data access categories. The memory device may implement endurance groups, which may each include a set of memory cells configurable as single-level cells, triple-level cells, or quad-level cells. The endurance groups may be configured based on a capacity identifier selected for the memory device from a set of capacity identifiers supported by the memory system. Each capacity identifier of the set of capacity identifiers may be associated with a configuration of the endurance groups. The host system may transmit a capacity identifier to indicate a configuration of the memory system. The memory system may support data movement internal to the memory system between the endurance groups, without transferring data between the host system.
A memory device includes an off-lining logging circuit. The memory device detects errors in the memory array as well as one or more addresses which identify where in the array the error was located. The off-lining logging circuit counts errors in different portions of the array, such as sections and/or column planes, based on the addresses. If the count value crosses a threshold, the portion may be identified as a candidate for off-lining. In some examples, a host device may receive off-lining candidate address information from the memory and off-line the identified portions.
An apparatus including a multi-purpose communication mechanism and associated systems and methods are disclosed herein. The apparatus may include the multi-purpose communication mechanism that enables different circuits to process corresponding/different signals communicated through a shared direct access (DA) pad.
Methods, systems, and devices for adjusted access operations for replay protected memory blocks (RPMBs) are described. A memory system may communicate one or more commands concurrently with performance of an access operation on a RPMB in response to receiving a first security protocol command. The first security protocol command may be a security protocol out (SPO) command transmitted from a host device. In combination with a ready to transfer response from the memory system and a data out UPIU from the host device, the first security protocol command may indicate a type of the access operation and corresponding data. The one or more commands may include additional SPO commands, security protocol in (SPI) commands, one or more other commands, or any combination thereof. In some cases, the memory device may transmit the data back to the host after the access operation is complete.
Methods, systems, and devices for multi-plane firmware image management are described. A memory system may store a primary firmware image across multiple planes. The memory system may read the firmware image from the planes using a multi-plane read operation. The memory system may store copies of the firmware image to separate, individual planes and the copies may be accessed (e.g., read) based on detecting an error in the primary firmware image.
Various reduced power addressing schemes in different configurations are monitored to assess the toggling characteristics of these schemes. The identified toggling characteristics, in relation to different configurations, are then analyzed in consideration of the associated costs of the reduced power addressing schemes. Among these configurations, the one found to optimize the balance between benefits and costs is selected for implementation as part of the reduced power addressing scheme.
Methods, systems, and devices for manual dynamic word line start voltage (MDWLSV) prediction and a self-adapting cache program for memory operations are described. In some examples, a memory device may receive a sequence of write commands for a memory block, and the memory device may monitor an interval between two consecutive write commands in the sequence. The memory device may compare the interval to a threshold interval. The memory device may utilize a first programming mode associated with a combination of a set feature (SF) and a get feature (GF) for MDWLSV prediction if the interval exceeds the threshold. The memory device may utilize a second programming mode associated with the SF for MDWLSV prediction if the interval is less than the threshold. The described techniques may provide for the host device to transmit commands for MDWLSV prediction in advance by transmitting the MDWLSV commands via a previous write command.
Aspects of the present disclosure configure a system component, such as memory sub-system controller, to transition a state of a memory sub-system into different panic handling modes. The controller detects failure of a memory sub-system and determines that self-recovery from the failure of the memory sub-system is unavailable. The controller, in response to determining that self-recovery from the failure of the memory sub-system is unavailable, incrementally transitions a state of the memory sub-system to different panic handling modes and returns the memory sub-system to a deployed mode from one of the different panic handling modes in response to successfully recovering the memory sub-system.
Methods, systems, and devices for sparse piers for three-dimensional memory arrays are described. A semiconductor device, such as a memory die, may include pier structures formed in contact with features formed from alternating layers of materials deposited over a substrate, which may provide mechanical support for subsequent processing. For example, a memory die may include alternating layers of a first material and a second material, which may be formed into various cross-sectional patterns. In some examples, the alternating layers may be formed into one or more pairs of interleaved comb structures. Pier structures may be formed in contact with the cross sectional patterns to provide mechanical support between instances of the cross-sectional patterns, or between layers of the cross-sectional patterns (e.g., when one or more layers are removed from the cross-sectional patterns), or both.
Methods, systems, and devices for zone write operation techniques are described. A memory system may support zone write operations directly to a multiple-level cell cursor of the memory system. For example, the memory system may close a first zone associated with storing a first type of information from being written with additional information. Based on closing the first zone, the memory system may determine a rate at which the first type of information is written to the memory system. The memory system may receive a command to write second information of the first type to a second zone of the memory system. To write the second information to the second zone, the memory system may write the second information to a cursor configured to store information written to the second zone, and the cursor may be associated with multiple-level memory cells based on the first rate.
Some embodiments include an integrated assembly having a memory array over a base. First sense-amplifier-circuitry is associated with the base and includes sense amplifiers directly under the memory array. Vertically-extending digit lines are associated with the memory array and are coupled with the first sense-amplifier-circuitry. Second sense-amplifier-circuitry is associated with the base and is offset from the first sense-amplifier-circuitry. Control circuitry is configured to selectively couple the digit lines to either a voltage supply terminal or to the second sense-amplifier-circuitry.
G11C 11/4091 - Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
G11C 11/4094 - Bit-line management or control circuits
G11C 11/4097 - Bit-line organisation, e.g. bit-line layout, folded bit lines
53.
INDICATING A STATUS OF A MEMORY BUILT-IN SELF-TEST FOR MULTIPLE MEMORY DEVICE RANKS
Implementations described herein relate to indicating a status of the memory built-in self-test for multiple memory device ranks. A memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. The memory device may identify a first data mask inversion (DMI) bit of the memory device that is associated with a first rank of the memory device and a second DMI bit of the memory device that is associated with a second rank of the memory device. The memory device may set the first DMI bit to a first value based on determining to perform the memory built-in self-test for the first rank of the memory device. The memory device may perform the memory built-in self-test for the first rank of the memory device based on setting the first DMI bit to the first value.
Methods, systems, and apparatuses include determining to apply a read retry operation to a portion of memory. The likelihood of a read retry timeout meeting a threshold is determined. A reverse trim setting is selected in response to determining the likelihood of the read retry timeout meets the threshold. The read retry operation is executed using the selected trim setting.
Methods, systems, and devices for host verification for a memory device are described. A memory device may receive a first value from a host device that is associated with an identification of the host device after an event. The memory device may transmit a second value to the host device that is based on the first value and comprises a random set of bits. The memory device may receive from the host device data or a command that comprises an encrypted third value that is based at least in part on the second value and a secret shared between the host device and the memory device. The memory device may also enable a functionality of the memory device based on the encrypted third value.
Systems, apparatuses, and methods related to an adjustable timer component are described. A memory device includes, a memory controller coupled to the memory device comprising an adjustable timer component. The adjustable timer component is configured to receive a timer generation request and, responsive to receiving the request, store in a cache an active timer entry corresponding to a particular first address, generate a timer corresponding to an active timer entry and the particular first address, and monitor the timer to determine when the timer expires. Responsive to the expiration of the timer, dequeue the timer entry and invalidate the timer entry stored in the cache. The memory device can also include command logic configured to, prior to issuing a second command, query the cache of the adjustable timer component to determine if the cache includes an active timer entry corresponding to the particular second address.
A microelectronic device package may include a microelectronic device supported on, and electrically connected to, a package substrate or a redistribution layer. A non-masking material defined (NMMD) contact may facilitate an electrical connection between the microelectronic device and the package substrate or the redistribution layer.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
The present disclosure includes apparatuses, methods, and systems for drift compensation for codewords in memory. An embodiment includes a memory device having an array of memory cells, and circuitry to sense a codeword stored in the array, determine a derivative value of a cell metric for each cell of the codeword based on a threshold voltage of that respective cell, a mean of threshold voltage values of each cell of the codeword, and a value proportional to a total quantity of the cells of the codeword and a position of the threshold voltage value of that respective cell in the threshold voltage values of each cell of the codeword, determine the cell metric for which the determined derivative value changes from a first polarity to a second polarity, input the determined cell metric to a Pearson detector, and determine originally programmed data of the codeword using the Pearson detector.
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
Methods, systems, and devices for management command microcode techniques for memory architectures are described. For example, interface circuitry of a memory system may be configured to determine that a management operation is to be performed, and may indicate a request to a controller of a host system to schedule aspects of the management operation. In response, the controller may indicate one or more commands to the interface circuitry to perform the management operation. Such techniques may involve the interface circuitry and controller being configured in accordance with a sequence of operations (e.g., a microcode), and respective management operations may each be associated with a pointer and a length of the sequence of operations. The controller may be configured to determine one or more commands for an indicated management operation by referencing the sequence of operations in accordance with the pointer and length associated with the indicated management operation.
Methods, systems, and devices for adjusted access operations for replay protected memory blocks (RPMBs) are described. A memory system may communicate one or more commands concurrently with performance of an access operation on a RPMB in response to receiving a first security protocol command. The first security protocol command may be a security protocol out (SPO) command transmitted from a host device. In combination with a ready to transfer response from the memory system and a data out UPIU from the host device, the first security protocol command may indicate a type of the access operation and corresponding data. The one or more commands may include additional SPO commands, security protocol in (SPI) commands, one or more other commands, or any combination thereof. In some cases, the memory device may transmit the data back to the host after the access operation is complete.
Methods, systems, and devices for manual dynamic word line start voltage (MDWLSV) prediction and a self-adapting cache program for memory operations are described. In some examples, a memory device may receive a sequence of write commands for a memory block, and the memory device may monitor an interval between two consecutive write commands in the sequence. The memory device may compare the interval to a threshold interval. The memory device may utilize a first programming mode associated with a combination of a set feature (SF) and a get feature (GF) for MDWLSV prediction if the interval exceeds the threshold. The memory device may utilize a second programming mode associated with the SF for MDWLSV prediction if the interval is less than the threshold. The described techniques may provide for the host device to transmit commands for MDWLSV prediction in advance by transmitting the MDWLSV commands via a previous write command.
A memory device includes a command interface configured to receive a write command from a host device. The memory device also includes an input/output interface configured to receive a data strobe. Furthermore, the memory device includes capture circuitry configured to capture the data strobe and generate an internal data strobe. The capture circuitry includes gated extend circuitry configured to extend an overlap of the data strobe with a start-to-synchronize signal that indicates that the data strobe is to be used in the memory device. Moreover, the capture circuitry includes re-gating circuitry configured to re-gate an output of the gated extend circuitry based at least in part on the start-to-synchronize signal.
The present disclosure provides techniques for using a multiple-port buffer to improve a transaction rate of a memory module. In an example, a memory module can include a circuit board having an external interface, first memory devices mounted to the circuit board, and a first multiple-port buffer circuit mounted to the circuit board. The first multiple-port buffer circuit can include a first port coupled to data lines of the external interface, the first port configured to operate at a first transaction rate, a second port coupled to data lines of a first plurality of the first memory devices, and a third port coupled to data lines of a second plurality of the first memory devices. The second and third ports can be configured to operate at a second transaction rate, wherein the second transaction rate is slower than the first transaction rate.
A memory device includes a three-dimensional (3D) memory array comprising a plurality of blocks and control logic coupled to the 3D memory array. The control logic identifies a defective portion of a block of the plurality of blocks, wherein the defective portion is located above a non-defective portion of the block and causes the defective portion to be pre-programmed before programming the non-defective portion. While pre-programming the defective portion, the control logic causes a first voltage to be applied to a top plurality of wordlines of the defective portion and causes a second voltage to be applied to a bottom plurality of wordlines of the defective portion that are located below the top plurality of wordlines, wherein the second voltage is lower than the first voltage.
Systems and devices for semiconductor die coupling with inductive coils are described. A semiconductor device may include one or more inductive coils to enhance signal quality of signals communicated over conductive lines and to support improved processing bandwidth. The semiconductor device may include multiple dies and each die may include respective circuitry. The respective circuitry may be coupled with the one or more inductive coils. In some cases, each die of the semiconductor device may respectively include one or more inductive coils that couple die circuitry with a same channel. In some cases, a redistribution layer that is shared by each die may be configured with one or more inductive coils that are coupled with each die. Each die may be coupled with the one or more inductive coils based on a conductive pillar or based on a hybrid bond.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/04 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers
66.
MICROELECTRONIC DEVICES, AND RELATED METHODS AND MEMORY DEVICES
A microelectronic device includes a first microelectronic device and a second microelectronic device structure overlying the first microelectronic device structure. The first microelectronic device structure includes a first base structure, and a first dielectric oxycarbide material overlying the first base structure. The second microelectronic device structure includes a second dielectric oxycarbide material bonded to the first dielectric oxycarbide material of the first microelectronic device structure, and a second base structure overlying the second dielectric oxycarbide material. Related methods and memory devices are also described.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
67.
APPARATUSES AND METHODS FOR ON-DEVICE TELEMETRY LOGGING
A memory device logs telemetry information using a resistive element array. A telemetry logging circuit changes a resistance of one or more resistive elements in the array responsive to one or more commands, addresses, mode signals, or combinations thereof. The change to the resistance may be cumulative with other changes. For example if the resistive element is an antifuse, the resistance may decrease each time the information is logged. In some example embodiments, the memory may read out a resistance of one or more of the resistive elements to determine a telemetry value, which may be written to storage such as a mode register or SPD.
Methods, systems, and devices for security for read commands are described. The memory system receive a read command to read data from a read protected memory block (RPMB) region. The read command may include a first message authenticated code (MAC) key. In some cases, the memory system may authenticate the read command using the first MAC key and retrieving the data from the RPMB region. The memory system may transmit the data after retrieving the data from the RPMB region. In some cases, the memory system may determine whether a read protect flag associated with a logical unit identified by the read command indicates that reading of data stored in the logical unit is permitted. The memory system may read the data based on determining that the read protect flag permits reading the data.
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
Methods, systems, and devices for write temperature recovery from a memory system are described. A memory system may receive a command to provide write temperature information associated with data written to the one or more memory devices. The memory system may read, from the one or more memory devices based on the command, a write temperature indicative of a temperature of the memory system at a time of writing a subset of the data. The memory system may read, based on transmitting the write temperature to a host system, one or more subsets of the data.
Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to debug a memory sub-system. The controller receives, from a host over a first bus, authentication information associated with unlocking the debugging component and, in response to successfully authenticating the host based on the authentication information, unlocks a debugging component. The debugging component receives one or more debug commands from the host via a second bus and transmits, to the host via the second bus, debugging information in response to receiving the one or more debug commands.
Some embodiments include integrated memory having an array of access transistors. Each access transistor includes an active region which has a first source/drain region, a second source/drain region and a channel region. The active regions of the access transistors include semiconductor material having elements selected from Groups 13 and 16 of the periodic table. First conductive structures extend along rows of the array and have gating segments adjacent the channel regions of the access transistors. Heterogenous insulative regions are between the gating segments and the channel regions. Second conductive structures extend along columns of the array, and are electrically coupled with the first source/drain regions. Storage-elements are electrically coupled with the second source/drain regions. Some embodiments include a transistor having a semiconductor oxide channel material. A conductive gate material is adjacent to the channel material. A heterogenous insulative region is between the gate material and the channel material.
H10D 64/68 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 53/10 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the top-view layout
H10B 53/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
H10B 53/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
H10B 53/40 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the peripheral circuit region
Methods, systems, and devices for parallel access in a memory array are described. A set of memory cells of a memory device may be associated with an array of conductive structures, where such structures may be coupled using a set of transistors or other switching components that are activated by a first driver. The set of memory cells may be divided into two or more subsets of memory cells, where each subset may be associated with a respective second driver for driving access currents through memory cells of the subset. Two or more of such second drivers may operate concurrently, which may support distributing current or distributing associated circuit structures across a different footprint of the memory device than other different implementations with a single such second driver.
G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
G11C 11/4091 - Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
G11C 11/4093 - Input/output [I/O] data interface arrangements, e.g. data buffers
Methods, systems, and devices for operating frequency monitoring for memory devices are described for monitoring one or more operating frequency ranges experienced by a memory device. The memory device may include monitoring circuitry or logic that may identify one or more durations of operating the memory device within the one or more operating frequency ranges. The memory device may store an indication of the one or more durations, or an indication of information associated with the one or more durations. The indication may be accessed a host device associated with the memory device or may be transmitted by the memory device to the host device. The host device may use information included in the indication to perform an operation associated with the memory device.
Methods, systems, and devices for techniques for detecting a state of a bus are described. A memory device may receive an access command transmitted to the memory device via a bus. The memory device may transmit data requested by the access command over data lines and a control signal that indicates the bus is in an active state over a control line. The control signal may be transmitted during a first unit interval of a read operation. The control signal may be configured to have a first voltage when the bus is in an idle state and a second voltage when the bus is in the active state. The control line may be configured to have or trend toward the first voltage when the bus is in the idle state.
Aspects of the present disclosure configure a memory sub-system processor to use a fin stack to improve heat dissipation to improve a data transfer rate. The processor measures temperature of at least one of the processing device or the set of memory components. The processor accesses a reference temperature for controlling data transfer rate between a host and the set of memory components. The processor compares the measured temperature with the reference temperature and, based on the comparison, adjusts the data transfer rate based on comparing the measured temperature with the reference temperature.
Some embodiments include an integrated assembly having a channel-material-pillar extending vertically through a stack of alternating conductive levels and insulative levels. The channel-material-pillar includes a first semiconductor material. A second semiconductor material is directly against an upper region of the channel-material-pillar. The second semiconductor material has a higher dopant concentration than the first semiconductor material and joins to the first semiconductor along an abrupt interfacial region such that there is little to no mixing of dopant from the second semiconductor material into the first semiconductor material. Some embodiments include methods of forming integrated assemblies.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
77.
MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND SHARED CHANNEL REGION
Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first data line located in a first level of the apparatus; a second data line located in a second level of the apparatus; a first memory cell located in a third level of the apparatus between the first and second levels, the first memory cell including a first transistor coupled to the first data line, and a second transistor coupled between the first data line and a charge storage structure of the first transistor; and a second memory cell located in a fourth level of the apparatus between the first and second levels, the second memory cell including a third transistor coupled to the second data line, and a fourth transistor coupled between the second data line and a charge storage structure of the third transistor, the first transistor coupled in series with the third transistor between the first and second data lines.
H10B 12/00 - Dynamic random access memory [DRAM] devices
G11C 11/401 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
78.
MEMORY ADDRESS TRANSLATION FOR DATA PROTECTION AND RECOVERY
Address translation of host commands to access host data stored in memory devices that provides a chip kill capability not only involves locating where the host data is stored, but also involves locating where parity data striped with the host data is stored. In locating where the parity data is stored, the address translation can be performed with logical (e.g., arithmetic) operations.
Protection for a secure boot procedure can be provided in addition to cryptographic verification of boot firmware associated with the boot procedure. While the boot firmware is being verified and executed at a secure sub-system, an open sub-system can be put into a halt state, during which the open sub-system is prevented from performing the boot procedure. The open sub-system is still prevented from performing the boot procedure even if the boot firmware is verified and/or executed unless the open sub-system is put into the resume state again.
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
Systems and devices for semiconductor die coupling with inductive coils are described. A semiconductor device may include one or more inductive coils to enhance signal quality of signals communicated over conductive lines and to support improved processing bandwidth. The semiconductor device may include multiple dies and each die may include respective circuitry. The respective circuitry may be coupled with the one or more inductive coils. In some cases, each die of the semiconductor device may respectively include one or more inductive coils that couple die circuitry with a same channel. In some cases, a redistribution layer that is shared by each die may be configured with one or more inductive coils that are coupled with each die. Each die may be coupled with the one or more inductive coils based on a conductive pillar or based on a hybrid bond.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to debug a memory sub-system. The controller receives, from a host over a first bus, authentication information associated with unlocking the debugging component and, in response to successfully authenticating the host based on the authentication information, unlocks a debugging component. The debugging component receives one or more debug commands from the host via a second bus and transmits, to the host via the second bus, debugging information in response to receiving the one or more debug commands.
Aspects of the present disclosure configure a system component, such as memory sub-system controller, to transition a state of a memory sub-system into different panic handling modes. The controller detects failure of a memory sub-system and determines that self-recovery from the failure of the memory sub-system is unavailable. The controller, in response to determining that self-recovery from the failure of the memory sub-system is unavailable, incrementally transitions a state of the memory sub-system to different panic handling modes and returns the memory sub-system to a deployed mode from one of the different panic handling modes in response to successfully recovering the memory sub-system.
Methods, systems, and devices for security for read commands are described. The memory system receive a read command to read data from a read protected memory block (RPMB) region. The read command may include a first message authenticated code (MAC) key. In some cases, the memory system may authenticate the read command using the first MAC key and retrieving the data from the RPMB region. The memory system may transmit the data after retrieving the data from the RPMB region. In some cases, the memory system may determine whether a read protect flag associated with a logical unit identified by the read command indicates that reading of data stored in the logical unit is permitted. The memory system may read the data based on determining that the read protect flag permits reading the data.
Methods, systems, and devices for write temperature recovery from a memory system are described. A memory system may receive a command to provide write temperature information associated with data written to the one or more memory devices. The memory system may read, from the one or more memory devices based on the command, a write temperature indicative of a temperature of the memory system at a time of writing a subset of the data. The memory system may read, based on transmitting the write temperature to a host system, one or more subsets of the data.
Methods, systems, and devices for endurance group for tiered storage applications are described. A memory system may implement a single memory device with different types of memory and corresponding data access categories. The memory device may implement endurance groups, which may each include a set of memory cells configurable as single-level cells, triple-level cells, or quad-level cells. The endurance groups may be configured based on a capacity identifier selected for the memory device from a set of capacity identifiers supported by the memory system. Each capacity identifier of the set of capacity identifiers may be associated with a configuration of the endurance groups. The host system may transmit a capacity identifier to indicate a configuration of the memory system. The memory system may support data movement internal to the memory system between the endurance groups, without transferring data between the host system.
Methods, systems, and devices for multi-plane firmware image management are described. A memory system may store a primary firmware image across multiple planes. The memory system may read the firmware image from the planes using a multi-plane read operation. The memory system may store copies of the firmware image to separate, individual planes and the copies may be accessed (e.g., read) based on detecting an error in the primary firmware image.
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
An apparatus including a multi-purpose communication mechanism and associated systems and methods are disclosed herein. The apparatus may include the multi-purpose communication mechanism that enables different circuits to process corresponding/different signals communicated through a shared direct access (DA) pad. The shared direct access (DA) pad connected to a vertically extending via and configured to facilitate communication of a first signal and a second signal with an external device.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
09 - Scientific and electric apparatus and instruments
Goods & Services
Computer hardware; computer chips; semi-conductors; semiconductor devices; semiconductor chips; semi-conductor memories; integrated circuits; printed circuit boards; computer memories; computer memory hardware; electronic memory integrated circuit chips for computer storage devices; integrated circuit chips; computer memory devices; memory modules; memory cards; in-storage processing systems, namely, systems comprising blank digital storage media and processing circuitry; dynamic random access memory (DRAM); graphic memory being memory for GPUs; non-volatile computer memory devices; computer storage devices, namely, solid state devices for storage of computer data and processing circuitry; solid state drives, solid state systems, namely, non-volatile memory and a controller with firmware, blank flash drives, blank flash memory devices in the nature of blank flash memory chips, blank flash memory cards, and blank flash memory drives, NOR flash memory devices in the nature of NOR flash memory chips and blank NOR flash memory cards, and NAND flash memory devices in the nature of blank NAND flash memory cards and blank NAND flash memory drives; blank flash memory cards; blank digital storage media; blank electronic storage media; data storage devices, namely, semiconductors for data storage
09 - Scientific and electric apparatus and instruments
Goods & Services
Computer hardware; computer chips; semi-conductors; semiconductor devices; semiconductor chips; semi-conductor memories; integrated circuits; printed circuit boards; computer memories; computer memory hardware; electronic memory integrated circuit chips for computer storage devices; integrated circuit chips; computer memory devices; memory modules; memory cards; in-storage processing systems, namely, systems comprising blank digital storage media and processing circuitry; dynamic random access memory (DRAM); graphic memory being memory for GPUs; non-volatile computer memory devices; computer storage devices, namely, solid state devices for storage of computer data and processing circuitry; solid state drives, solid state systems, namely, non-volatile memory and a controller with firmware, blank flash drives, blank flash memory devices in the nature of blank flash memory chips, blank flash memory cards, and blank flash memory drives, NOR flash memory devices in the nature of NOR flash memory chips and blank NOR flash memory cards, and NAND flash memory devices in the nature of blank NAND flash memory cards and blank NAND flash memory drives; blank flash memory cards; blank digital storage media; blank electronic storage media; data storage devices, namely, semiconductors for data storage
Methods, systems, and devices for forming an indium chalcogenide film are described. Precursors that include an indium-cyclopentadienyl compound may enable formation of indium chalcogenide films at a lower temperature as compared to other precursors including indium, as the reactivity of indium-cyclopentadienyl compounds may be higher than these other precursors. Additionally, using ammonia as a reagent during the atomic layer deposition process to form the indium chalcogenide film may enable an increased rate of formation of indium chalcogenide films for a given temperature. A method may include reacting an indium-cyclopentadienyl precursor and a second precursor that includes a selenium compound or a tellurium compound to form an indium chalcogenide.
C23C 16/30 - Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
Methods, systems, and devices for dynamic voltage supply for memory circuit are described. An apparatus may adjust a supply voltage based on a process corner and a temperature of the memory system. An apparatus may include a memory array and a controller. The controller may determine a first temperature of the apparatus is less than a first temperature threshold at a first time. The controller may transition a voltage supplied to the controller from a first voltage level to a second voltage level based on determining the first temperature is less than the first temperature threshold. The controller may determine a second temperature is greater than a second temperature threshold at a second time. The controller may transition the voltage supplied to the controller from the second voltage level to the first voltage level based on determining the second temperature is greater than the second temperature threshold.
Apparatus, systems, and methods for analyzing data are described. The data can be analyzed using a hierarchical structure. One such hierarchical structure can comprise a plurality of layers, where each layer performs an analysis on input data and provides an output based on the analysis. The output from lower layers in the hierarchical structure can be provided as inputs to higher layers. In this manner, lower layers can perform a lower level of analysis (e.g., more basic/fundamental analysis), while a higher layer can perform a higher level of analysis (e.g., more complex analysis) using the outputs from one or more lower layers. In an example, the hierarchical structure performs pattern recognition.
Methods, systems, and devices for an output driver with compact inductive peaking are described. A memory system may implement a circuit for communicating signaling with a host system. The circuit may include a transmission component for transmitting signaling, and a reception component for receiving signaling, where the transmission component and the reception component are coupled with a pad. The circuit may include a current stabilization component and a drain capacitor to store charge associated with the transmission component. The circuit may include a series inductor coupled with the transmission component, the reception component, the drain capacitor, the current stabilization component, and the pad. A capacitance of the pad may be based on a resistance and an inductance of the series inductor.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/528 - Layout of the interconnection structure
94.
MEMORY DEVICE SECURITY THROUGH DISABLEMENT OF FUSE BLOWS
A memory device includes a memory array; a plurality of fuses; a disabling fuse; and control logic, operatively coupled with the plurality of fuses and the disabling fuse, to perform operations during manufacturing of the memory device, the operations including: determining whether the plurality of fuses are programmed; and responsive to determining that the plurality of fuses are programmed, blowing the disabling fuse to disable a blow functionality, wherein the blow functionality is triggered by a subsequent blow command to blow the plurality of fuses.
G06F 21/78 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
G11C 29/10 - Test algorithms, e.g. memory scan [MScan] algorithmsTest patterns, e.g. checkerboard patterns
95.
TECHNIQUES FOR TRANSFERRING DATA BETWEEN MEMORY DEVICES
Methods, systems, and devices for techniques for transferring data between memory devices are described. A memory system may pre-fetch one or more subsets of data associated with the data transfer operation from a first die of the memory system and a second die of the memory system prior to initiating a programming operation on either die. For example, to perform a data folding operation for a set of data which includes a first subset of data stored to the first die and a second subset of data stored to the second die, the memory system may retrieve both the first subset from the first die and the second subset from the second die prior to performing a programming operation on either die.
Devices and techniques that provide reconfigurable eMMC partitions are described herein. A flash memory device includes a register to store card specific data including a reconfiguration lock flag indicating whether partitions on the flash memory device are reconfigurable. The flash memory device can include an interface controller and a memory device able to be configured into one or more partitions by the interface controller.
A variety of applications can include devices implementing one or more fin field-effect transistors (FinFETs) with gate oxide thickness that address thicker gate oxide quality with minimum material loss in the fins of the FinFETs for high voltage devices. The gate oxides can be fabricated with thicker oxides than gate oxides of FinFETs used with capacitors in memory cells of memory arrays. These gate oxides can be formed as oxide liners by oxidation with use of a protective liner to maintain uniform composition of material for the fin during FinFET processing.
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
98.
MONITORING MEMORY DEVICE HEALTH ACCORDING TO DATA STORAGE METRICS
A plurality of memory device life metrics are determined, where one of the plurality of memory device life metrics comprises a read count metric that specifies a number of read operations performed on the memory device. A plurality of normalized metric values are calculated, where each of the normalized metric values is based on a ratio of a respective memory device life metric to a respective lifetime target value associated with the respective memory device life metric. A normalized metric value that satisfies a selection criterion is identified from the plurality of normalized metric values. The identified normalized metric value corresponds to an amount of used device life of the memory device. An amount of remaining device life of the memory device is determined based on the identified normalized metric value. An indication of the amount of remaining device life is provided to a host system.
Methods, systems, and devices for a memory device with an error correction memory device with fast data access are described. For example, during a read operation, a memory device may be configured to output the data indicated by the read operation concurrent with performing an error correction operation. If the memory device detects an error, the memory device may indicate the error to a host device and, in some cases, output the corrected data to the host device. During a write operation, the memory device may store error detection or correction information associated with data to be stored at the memory device. The memory device may, in some cases, store error detection or correction information generated by the host device.
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 11/20 - Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
G06F 13/00 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using ferroelectric elements
G11C 11/4093 - Input/output [I/O] data interface arrangements, e.g. data buffers
G11C 29/52 - Protection of memory contentsDetection of errors in memory contents
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
H03M 13/19 - Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes
H03M 13/45 - Soft decoding, i.e. using symbol reliability information
Methods, systems, and devices for temperature-dependent refresh operations are described. A memory system may adjust refresh operations based on a temperature of the memory system to reduce a refresh current and improve reliability of the refresh operations. For example, the memory system may include a temperature sensor configured to provide temperature information associated with a memory device. Based on the temperature information, the memory system may, in response to a refresh command, activate a set of access lines (e.g., word lines) to refresh memory cells coupled with the access lines, where a count of the set of access lines (e.g., how many access lines are included in the set) may be based on the temperature information. In some examples, the count of the set may be determined based on comparing the temperature information to one or more temperature thresholds.
