In a disclosed Schmitt trigger, an input stage includes a first p-channel field effect transistor (PFET) and a second PFET, which are connected in series to a VDD rail, and a first n-channel field effect transistor (NFET) and a second NFET, which are connected in series between ground and the second PFET. An output stage includes additional FETs for hysteresis. The first PFET and first NFET are different from the other FETs and have a higher voltage rating. For example, the first PFET and first NFET can be buried oxide field effect transistors (BOXFETs) and the other FETs can be laterally diffused metal oxide semiconductor field effect transistors (LDMOSFETs)). Gates of the first PFET and first NFET are connected to an input node. Gates of the second PFET and NFET are connected to receive reference voltages to prevent safe operating area (SOA) violations and control trigger voltage levels.
H03K 3/3565 - Bistables with hysteresis, e.g. Schmitt trigger
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
The disclosure provides a structure and method for an inductor having a winding with a first segment connected to two second segments. An inductor according to the disclosure includes a plurality of windings coupled together in series about a magnetic core. At least one of the plurality of windings includes a first segment in a first wiring layer and extending over a width of the magnetic core. A second segment is within a second wiring layer and coupled to the first segment through a vertical interconnect. The second segment includes two sub-segments separated by a gap along a length of the magnetic core.
A radio frequency (RF) switch includes a transistor stack with different sections having different configurations for achieving different parasitic capacitances. Specifically, a first section is connected to an input terminal and a second section is connected between the first section and an output terminal. The second section has over-gate gaps for reduced source-to-drain capacitance, whereas the first section does not. Additionally, gate-to-source/drain contact spacing can be larger in the second section than in the first section, transistor layout length can be longer in the second section than in the first section and/or source and drain interconnect interdigitation can be less in the second section than in the first section. Optionally, sub-sections of the series-connected transistors within the first and/or second sections also have different configurations. Thus, numbers and sizes of compensation capacitors within the switch and overall chip area consumed by the switch are reduced while maintaining a high Pmax.
H03K 17/10 - Modifications for increasing the maximum permissible switched voltage
H03K 17/041 - Modifications for accelerating switching without feedback from the output circuit to the control circuit
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
4.
SEMICONDUCTOR LAYERS FORMED BY LATERAL EPITAXIAL GROWTH
Structures that include a semiconductor layer formed by lateral epitaxial growth and methods of forming such structures. The structure comprises a first semiconductor layer that includes first and second sections, and that comprises a first single-crystal semiconductor material. The structure further comprises a second semiconductor layer that includes a section and a semiconductor region, and that comprises one or more second single-crystal semiconductor materials. The semiconductor region extends between the second section of the first semiconductor layer and the section of the second semiconductor layer. An opening penetrates at least partially through the first semiconductor layer and through the second semiconductor layer. The opening is oriented along a (100) crystal plane of the first single-crystal semiconductor material, and the semiconductor region borders the opening. A dielectric layer is positioned between the first section of the first semiconductor layer and the section of the second semiconductor layer.
G02F 1/015 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour based on semiconductor elements having potential barriers, e.g. having a PN or PIN junction
5.
STRUCTURE WITH TWO WORK FUNCTION METALS OVER CONDUCTIVE BRIDGE, AND METHOD TO FORM SAME
A structure, including an insulator within a substrate. The substrate includes a first active region adjacent a first sidewall of the insulator and a second active region adjacent a second sidewall of the insulator opposite the first sidewall. The structure further includes a conductive bridge over the insulator and coupling the first active region of the substrate to the second active region of the substrate. The structure includes a gate dielectric layer over the conductive bridge, a first work function metal over the first active region, and a second work function metal over the second active region.
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 27/085 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
6.
INTEGRATED CIRCUIT DESIGN METHOD AND SYSTEM EMPLOYING PARASITIC DIODE ANALYSIS
Disclosed are embodiments of computer-aided design (CAD) methods and systems that employ one or more electronic design automation (EDA) tools to flag parasitic diodes within a layout or netlist (depending upon the embodiments). In one embodiment, information contained in process design kit (PDK) tables (e.g., a first table with layer-specific design rules for devices in a processing technology and a second table with descriptions of parasitic diodes in the processing technology) can be used to identify any parasitic diodes within a displayed portion of an IC design layout. Once identified, parasitic diodes can be flagged within the displayed portion of the layout to provide visual cues intended to draw a user's attention to the parasitic diodes during the design process to ensure that any unintended or unwanted parasitic diodes are either accounted for when predicting IC performance or removed from the design to avoid a negative impact on performance.
Structures that include a semiconductor layer formed by lateral epitaxial growth and methods of forming such structures. The structure comprises a first semiconductor layer including a first section and a second section adjacent to the first section, a second semiconductor layer including a section and a semiconductor region that projects from the second section of the first semiconductor layer to the section of the second semiconductor layer, and a dielectric layer disposed between the first section of the first semiconductor layer and the section of the second semiconductor layer. The section and the semiconductor region of the second semiconductor layer comprise one or more single-crystal semiconductor materials.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
C30B 1/02 - Single-crystal growth directly from the solid state by thermal treatment, e.g. strain annealing
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
The present disclosure relates to semiconductor structures and, more particularly, to a device triggered silicon control rectifiers (SCR) and methods of manufacture. The structure includes: a first device comprising a first shallow diffusion region of a first conductivity type within a first well of a second conductivity type and a second shallow diffusion region of the first conductivity type within the first well of the second conductivity type.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 29/74 - Thyristor-type devices, e.g. having four-zone regenerative action
9.
EXTENDED DRAIN METAL OXIDE SEMICONDUCTOR (EDMOS) FIELD EFFECT TRANSISTOR (FET) WITH DUAL THICKNESS SEMICONDUCTOR MATERIAL
The present disclosure relates to semiconductor structures and, more particularly, to an extended drain metal oxide semiconductor (EDMOS) field effect transistor (FET) with a fully depleted region comprising a dual thicknesses semiconductor material and methods of manufacture. The structure includes: a semiconductor on insulator (SOI) material including a first portion with a first thickness and a second portion with a second thickness; a gate structure on the SOI material over the first portion with the first thickness; and sidewall spacers adjacent to the gate structure, with at least one sidewall spacer extending over both the first portion with the first thickness and the second portion with the second thickness.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
Device structures for a high-voltage semiconductor device and methods of forming such device structures. The structure comprises a layer stack including a first dielectric layer and a second dielectric layer. The first dielectric layer includes a portion between the second dielectric layer and a semiconductor substrate. The structure further comprises a field-effect transistor including a first source/drain region in the semiconductor substrate, a second source/drain region in the semiconductor substrate, and a gate electrode on the layer stack. The gate electrode is laterally between the first and second source/drain regions, and the gate electrode overlaps with the portion of the first dielectric layer and the second dielectric layer. The structure further comprises a spacer laterally between the first source/drain region and the second dielectric layer.
H10D 64/66 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
H10D 64/68 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
Structures for a photonics chip that include a photodetector and methods of forming such structures. The structure comprises a photodetector including a pad and a semiconductor layer on the pad. The pad includes a side edge and a first waveguide core that extends from the side edge adjacent to the semiconductor layer. The structure further comprises a second waveguide core including a section adjoined to the side edge of the pad adjacent to the first waveguide core.
Embodiments of the disclosure provide a crystalline semiconductor layer between a bipolar transistor structure and a field effect transistor (FET) structure. The structure includes a dielectric layer on a back-gate semiconductor layer, a bipolar transistor structure on the dielectric layer, FET structure on the dielectric layer, and a crystalline semiconductor layer on the dielectric layer between the bipolar transistor structure and the FET structure. The crystalline semiconductor layer includes a terminal of the bipolar transistor structure and a terminal of the FET structure.
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. The structure comprises a first semiconductor layer including a first portion, a second portion, and a third portion between the first portion and the second portion, a first terminal including a first semiconductor region on the first portion of the first semiconductor layer, a second terminal including a second semiconductor region on the second portion of the first semiconductor layer, an intrinsic base laterally disposed between the first terminal and the second terminal, and an extrinsic base on the intrinsic base. The intrinsic base includes a doped region in the third portion of the first semiconductor layer, and the doped region has a dopant depth profile with a dopant concentration that is asymmetrical relative to the first terminal and the second terminal.
Embodiments of the disclosure provide a structure including a first back-gate well adjacent a second back-gate well. A bipolar transistor (BT) is over the first back-gate well and includes a base structure laterally between a set of emitter/collector (E/C) terminals and extending longitudinally away from the set of E/C terminals. A field effect transistor (FET) is over the second back-gate well and includes a gate structure laterally between a set of source/drain (S/D) terminals and extending longitudinally away from the set of S/D terminals toward the BT. The gate structure is coupled to the base structure.
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
15.
PHOTODETECTORS WITH AN ADJOINED SLOTTED WAVEGUIDING STRUCTURE
Structures for a photonics chip that include a photodetector and methods of forming such structures. The structure comprises a photodetector including a pad and a semiconductor layer on the pad. The structure further comprises a waveguiding structure including a first waveguide core, a second waveguide core, a slot between the first waveguide core and the second waveguide core, and a plurality of waveguide core segments. The waveguiding structure is adjoined to a side edge of the pad adjacent to the semiconductor layer. Each of the plurality of waveguide core segments includes a portion that is disposed in the slot.
The present disclosure relates to semiconductor structures and, more particularly, to cell layouts in semiconductor structures and methods of manufacture. A structure includes: a plurality of abutting cells each of which include transistors with gate structures having diffusion regions; a contact spanning across abutting cells of the plurality of abutting cells and contacting to the diffusion regions of separate cells of the abutting cells; and a continuous active region spanning across the plurality of abutting cells, wherein the continuous active region includes a drain-source abutment with L-shape construct, a source-source abutment with U-shape construct, and a drain-drain abutment with a filler cell located between a drain-drain abutment.
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
A serpentine resistor within a back end of line (BEOL) level of a substrate includes a plurality of first sections oriented in a first horizontal direction, at least one second section oriented in a second horizontal direction, a plurality of vertical sections, and at least one lateral turn between the first horizontal direction and the second horizontal direction. The serpentine resistor may have a serpentine shape in the vertical plane and the horizontal plane, and may extend between two bonded substrates, providing higher resistance values compared to conventional BEOL resistors.
H01L 27/08 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
The present disclosure relates to semiconductor structures and, more particularly, to a transistor triggered silicon control rectifier (SCR) and methods of manufacture. The structure includes: a vertical silicon controlled rectifier; and a triggering device adjacent to the vertical silicon controlled rectifier, the triggering device and the vertical silicon controlled rectifier sharing a diffusion region within a semiconductor substrate.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
The present disclosure relates to semiconductor structures and, more particularly, to a device triggered silicon control rectifier (SCR) and methods of manufacture. The structure includes: a vertical silicon controlled rectifier; a lateral triggering device including a first diffusion region, a second diffusion region and a third diffusion region, the third diffusion region being shared with the vertical silicon controlled rectifier; and a body contact over the first diffusion region.
H01L 29/74 - Thyristor-type devices, e.g. having four-zone regenerative action
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
The present disclosure relates to semiconductor structures and, more particularly, to a differential circuit with automatic parasitic neutralization and gain boost and methods of manufacture. The structure includes a plurality of auxiliary circuit devices with back-gate controls to perform a boost gain, and a differential pair of circuit devices which are connected to the auxiliary circuit devices.
Device structures for a high-voltage semiconductor device and methods of forming such device structures. The structure comprises a semiconductor substrate including a trench, and a field-effect transistor including a first and second source/drain regions in the semiconductor substrate, a gate dielectric inside the trench, and a gate on the gate dielectric. The gate and the gate dielectric are disposed laterally between the first and second source/drain regions.
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
22.
STACKED TRENCH CAPACITORS AND METHODS OF MAKING THEREOF
Stacked trench capacitors and methods of making the same are provided. Stacked trench capacitor comprises a first conductive layer and a second conductive layer in a first dielectric layer over a first semiconductor substrate, and a third conductive layer and a fourth conductive layer in a second dielectric layer. The first and second conductive layers are spaced by a first insulator layer, and the third and fourth conductive layers are spaced by a second insulator layer, and the second conductive layer is directly contacting the third conductive layer. A second semiconductor substrate is over the fourth conductive layer.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01G 4/012 - Form of non-self-supporting electrodes
Structures for an optical component, such as an optical reflector or an Echelle grating, and methods of forming such structures. The structure comprises a first waveguide core positioned in a vertical direction over a semiconductor substrate. The first waveguide core includes a tapered section and a plurality of segments separated by a plurality of gaps. A second waveguide core, which is positioned in the vertical direction relative to the first waveguide core, includes a portion positioned adjacent to the first waveguide core.
G02B 6/122 - Basic optical elements, e.g. light-guiding paths
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
G02B 6/124 - Geodesic lenses or integrated gratings
G02B 6/13 - Integrated optical circuits characterised by the manufacturing method
Structures for a waveguide escalator, as well as methods of forming such structures. The structure comprises a first waveguide core on a substrate, a second waveguide core, and a back-end-of-line stack including a third waveguide core disposed between the first waveguide core and the second waveguide core. The third waveguide core comprises a layer stack that includes a first layer, a second layer, and a third layer between the first layer and the second layer. The first layer and the second layer comprise a first dielectric material with a first refractive index, and the third layer comprises a second dielectric material with a second refractive index that is less than the first refractive index.
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
G02B 6/122 - Basic optical elements, e.g. light-guiding paths
G02B 6/13 - Integrated optical circuits characterised by the manufacturing method
25.
HETEROJUNCTION BIPOLAR TRANSISTOR WAFERS WITH BACKSIDE SUB-COLLECTOR CONTACT
The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistor wafers with backside sub-collector contact and methods of manufacture. The structure includes: a first chiplet comprising a first device with a backside contact; and a second chiplet connected to the first chiplet, the second chiplet comprising a second device with a frontside contact.
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor and methods of manufacture. The structure includes: a collector region; an extrinsic base comprising an emitter opening with an angled sidewall; an emitter within the emitter opening; and an intrinsic base between the emitter and the collector.
A system for phase imbalance calibration, including: an in-phase (I) signal channel including an analog-to-digital converter (ADC) for sampling an I signal to provide a sampled I signal; a quadrature (Q) signal channel including an ADC for sampling a Q signal to provide a sampled Q signal; a sampling clock for controlling the sampling of the ADC on the I signal channel and the sampling of the ADC on the Q signal channel; and sampling clock delay circuitry for adjusting one of a sampling start time of the ADC on the I channel and a sampling start time of the ADC on the Q channel relative to one another such that the sampled I signal and the sampled Q signal are in phase.
A structure and method include a transistor with semiconductor nanosheets, which extend between source/drain regions and which include at least a lowermost semiconductor nanosheet and an uppermost semiconductor nanosheet above the lowermost semiconductor nanosheet. The transistor includes inner gate sections below the center portions of each semiconductor nanosheet and an outer gate section with a horizontal portion above the center portion of the uppermost semiconductor nanosheet and with vertical portions on opposing sides of the semiconductor nanosheets and inner gate sections. Inner spacers are below the end portions of each semiconductor nanosheet. Outer spacers are adjacent the sidewalls of the outer gate section (including above end portions of the uppermost semiconductor nanosheet), are wider than the inner spacers, and extend onto proximal portions of the source/drain regions. Additional outer spacers are adjacent to the outer spacers (e.g., on the proximal portions or on taller and wider distal portions).
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
A power switch, including: a PFET including a gate, a source coupled to a source voltage, and a drain for outputting a supply voltage; and a level shifter, wherein the level shifter includes: an input node for receiving an input voltage, wherein the input voltage includes first and second voltage levels; a supply node for receiving the supply voltage, wherein the supply voltage includes third and fourth voltage levels; and an output node for outputting an output voltage, wherein the output node is coupled to the gate of the PFET; wherein, when the input voltage is at the first voltage level, the output voltage is at the first voltage level and the PFET is in a conducting state; and wherein a voltage between the gate and drain of the PFET and a voltage between the gate and source of the FET do not exceed a maximum voltage of the PFET.
H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only
H03K 17/10 - Modifications for increasing the maximum permissible switched voltage
H03K 19/173 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components
30.
Shielded inductor structures and methods of forming the same
A structure including a first chip and a second chip stacked over the first chip is provided. The first chip includes a first dielectric over a substrate. The second chip includes a second dielectric over the first dielectric. An inductor is arranged at least in part in the first dielectric of the first chip. An electromagnetic shield structure is arranged around the inductor. The electromagnetic shield structure includes a lower shield portion extending at least partially through the first dielectric of the first chip and an upper shield portion extending at least partially through the second dielectric of the second chip. The electromagnetic shield structure is formed in part in the BEOL metallization structure in each of the first chip and the second chip in a heterogenous integration process.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/00 - Details of semiconductor or other solid state devices
31.
IC structure with MFMIS memory cell and CMOS transistor
An IC structure includes an MFMIS memory cell on a semiconductor substrate, and a CMOS transistor adjacent the MFMIS memory cell on the same semiconductor substrate. A method provides co-integration of the MFMIS memory cell with the CMOS transistor. The method may optionally co-integrate an MFIS memory cell. The IC structure and method provide a lower cost approach to forming MFMIS memory cells, which provide a number of advantages over MFIS memory cells.
The present disclosure relates to semiconductor structures and, more particularly, to a device triggered silicon control rectifier (SCR) and methods of manufacture. the structure includes: a vertical silicon controlled rectifier having a diffusion region in a well of a semiconductor substrate; a vertical triggering device sharing the diffusion region with the vertical silicon controlled rectifier; and a body contact adjacent to the vertical triggering device and electrically connecting to the well.
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
33.
STRUCTURE WITH BARRIER-FREE METAL VIA AND METAL WIRE INCLUDING NON-COPPER CONDUCTOR, AND METHOD TO FORM SAME
A structure including a barrier-free metal via over a substrate and in a dielectric layer. The structure further includes a barrier-free metal wire in the dielectric layer and over the barrier-free metal via and coupled to at least an exposed portion of the barrier-free metal via. The barrier-free metal via and the barrier-free metal wire each include a non-copper conductor. By using non-copper conductors in the structure, the structure is substantially without liners and has improved performance without creating or increasing parasitic capacitance.
H01B 1/02 - Conductors or conductive bodies characterised by the conductive materialsSelection of materials as conductors mainly consisting of metals or alloys
H01B 1/04 - Conductors or conductive bodies characterised by the conductive materialsSelection of materials as conductors mainly consisting of carbon-silicon compounds, carbon, or silicon
34.
PHOTONICS CHIPS INCLUDING A PHOTONIC COUPLER AND A PHOTODETECTOR
Structures for a photonics chip that include a photodetector and methods of forming such structures. The structure comprises a photodetector, a first waveguide core coupled to the photodetector, and a second waveguide core coupled to the photodetector. The structure further comprises a third waveguide core including a section disposed laterally between a section of the first waveguide core and a section of the second waveguide core.
G02B 6/122 - Basic optical elements, e.g. light-guiding paths
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
G02B 6/13 - Integrated optical circuits characterised by the manufacturing method
35.
Structures for a field-effect transistor that include a spacer structure
Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure comprises a silicon-on-insulator substrate including a semiconductor substrate, a dielectric layer on the semiconductor substrate, and a semiconductor layer on the dielectric layer. The structure further comprises a gate electrode on the semiconductor layer. The gate electrode comprises a single-crystal semiconductor material. The structure further comprises a spacer structure including a first portion that overlaps with a side surface of the dielectric layer and a second portion that overlaps with a portion of the semiconductor substrate adjacent to the side surface of the dielectric layer.
H10D 86/00 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
36.
FULLY DEPLETED SEMICONDUCTOR-ON-INSULATOR SWITCH WITH BUILT-IN ELECTROSTATIC DISCHARGE PROTECTION
A disclosed semiconductor structure includes a semiconductor layer including a switch area with side-by-side first and second portions and an RF switch with built-in ESD/power surge protection. The RF switch includes series-connected transistors, which include, within the first portion of the switch area, source/drain regions and channel regions positioned laterally between the source/drain regions; and parallel gates adjacent to the channel regions, respectively, and traversing the first portion of the switch area without extending further onto the second portion. Outer source/drain regions are silicided and contacted, whereas inner source/drain regions are unsilicided and uncontacted. The second portion of the switch area is in contact with the source/drain regions in the first area, is unsilicided, and is either undoped or low doped. Thus, the second portion makes up resistive elements connected in parallel to the series-connected transistors.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
H03K 17/081 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor integrated silicon controlled rectifier and methods of manufacture. The structure includes: a first region having a first dopant type provided in a semiconductor substrate; a second region having a second dopant type provided in the semiconductor substrate; an isolation region between the first region and the second region; a first semiconductor layer vertically contacting the first region, the first semiconductor layer having a dopant type opposite from the first dopant type; a second semiconductor layer vertically contacting the second region, the second semiconductor layer having a dopant type opposite from the second dopant type; a polysilicon material vertically contacting the first semiconductor layer; and a single crystalline semiconductor material vertically contacting the first semiconductor layer and the second semiconductor layer.
H01L 29/04 - Semiconductor bodies characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
Structures for a photonic chip that include a photodetector and methods of forming such structures. The structure comprises a photodetector including a pad, a first semiconductor layer on the pad, and a second semiconductor layer on the pad. The second semiconductor layer is laterally spaced from the first semiconductor layer. The structure further comprises a first waveguide core connected to the pad adjacent to the first semiconductor layer, and a second waveguide core connected to the pad adjacent to the second semiconductor layer.
H10F 30/223 - Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices having only one potential barrier, e.g. photodiodes the potential barrier being a PIN barrier
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
H10F 71/00 - Manufacture or treatment of devices covered by this subclass
H10F 77/122 - Active materials comprising only Group IV materials
Layout design for an electronic device may be performed by providing a representation of a first layout to a client and providing, in response to an input from the client, a collection of design information calculated according to the first layout to the client. The collection of design information may include a dimension extracted from the first layout, and may further include parasitics information related to the dimension, margin information related to a ground rule applicable to the dimension, or both. The collection of design information may be provided to the client as a real-time response to inputs received from the client. By providing the parasitics information, the margin information, or both to the client, the design of sub-ground-rule layouts may be performed in less time and using fewer resources than would otherwise be the case.
Structures for a photonics chip that enable external communication and methods of forming such structures. The structure comprises a spot-size converter, a body on a semiconductor substrate, and a dielectric layer on the semiconductor substrate. The body includes a surface adjacent to the spot-size converter and a reflector on the surface. The dielectric layer includes a recess disposed above the spot-size converter and the reflector.
The present disclosure relates to semiconductor structures and, more particularly, to vertical heterojunction bipolar transistors and methods of manufacture. The structure includes: a sub-collector region; a collector region above the sub-collector region; an intrinsic base above the collector region; an emitter above the intrinsic base region; and an extrinsic base on the intrinsic base and adjacent to the emitter, wherein the collector region includes an undercut profile comprising lower inwardly tapered sidewalls and upper inwardly tapered sidewalls which extend to a narrow section between the sub-collector region and the base region.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/165 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group in different semiconductor regions
The disclosure provides a structure and method for an inductor with windings having different widths. A structure may include an inductor including a plurality of windings about a magnetic core. Each winding has a first segment within a first wiring layer coupled to a second segment within a second wiring layer. The plurality of windings includes a first winding having a first width along a same direction as a length of the magnetic core and a second winding having a second width along the same direction as the length of the magnetic core. The second width is larger than the first width.
H01F 1/14 - Magnets or magnetic bodies characterised by the magnetic materials thereforSelection of materials for their magnetic properties of inorganic materials characterised by their coercivity of soft-magnetic materials metals or alloys
43.
SINGLE ENDED SENSE AMPLIFIER WITH CURRENT PULSE CIRCUIT
Embodiments of the disclosure provide memory circuit, a sense amplifier and associated method for reading a resistive state in a memory device. The sense amplifier includes a bit cell configurable to a high or low resistance state; a sensing circuit that detects a voltage drop across the bit cell in response to an applied read current during a read operation and generates a high or low logic output at an output node; and a pulse generation circuit that increases the applied read current with an injected current pulse when a low to high transition of the resistive state of the bit cell is detected.
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
44.
SILICON CONTROL RECTIFIER INTEGRATED WITH A TRANSISTOR
The present disclosure relates to semiconductor structures and, more particularly, to a silicon control rectifier (SCR) and methods of manufacture. The structure includes: a doped region in a semiconductor substrate; at least two regions of semiconductor material comprising opposite doping types over the doped region; and polysilicon regions over respective ones of the least two regions of semiconductor material.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
45.
BIPOLAR TRANSISTOR STRUCTURE WITH BOUNDING STRUCTURE AT HORIZONTAL END AND METHODS TO FORM SAME
Embodiments of the disclosure provide a structure including a first emitter/collector (E/C) layer over a substrate. A base structure is over the substrate and adjacent a first horizontal end of the first E/C layer. A bounding structure is over the substrate and adjacent a second horizontal end of the first E/C layer. The bounding structure, in some implementations, may include a gate conductor or a base material. A spacer is between the first E/C layer and the bounding structure.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A disclosed memory structure includes memory cells connected to first and second cell supply voltage lines. A programming circuit enables programming of a low cell supply voltage (Vcsl) on the first cell supply voltage line and includes transistors with different threshold voltages connected to ground and further connectable, via switches, to the first cell supply voltage line. The programming circuit can further include an additional switch connected between ground and the first cell supply voltage line. In an operational mode, the first cell supply voltage line is discharged to ground via the additional switch. In the retention mode, one of the transistors of the programming circuit is connected by a corresponding switch to the first cell supply voltage line for programming of Vcsl. Optionally, the memory structure can be implemented in FDSOI and the transistors of the programming circuit can also be back biased for fine tuning of Vcsl.
Structures that include a switching memory element and methods of forming a structure including a switching memory element. The structure comprises a switching memory element, and a two-terminal access device including a first terminal coupled to the switching memory element, a second terminal, and a semiconductor layer between the first terminal and the second terminal. The semiconductor layer is electrically floating in the structure.
Structures for an integrated circuit having a watermark and related methods. The structure comprises a first semiconductor structure including at least one feature with a variation relative to a second semiconductor structure including the at least one feature without the variation. The variation provides a watermark for identifying a Process Design Kit used to form the first semiconductor structure.
H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
Structures for a photonics chip that include an integrated semiconductor laser and methods of forming such structures. The structure comprises a waveguide core, a multi-layer quantum-well stack, and an optical coupler on a portion of the waveguide core. The optical coupler, which comprises a semiconductor material, is disposed between the portion of the waveguide core and the multi-layer quantum-well stack.
G02B 6/122 - Basic optical elements, e.g. light-guiding paths
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
G02B 6/13 - Integrated optical circuits characterised by the manufacturing method
50.
PHOTODETECTORS WITH A NOTCHED LIGHT-ABSORBING LAYER
Structures for a photonics chip that include a photodetector and methods of forming such structures. The structure comprises a photodetector that is disposed on a substrate and that includes a light-absorbing layer. The light-absorbing layer includes a sidewall and a notch in the sidewall. The structure further comprises a waveguide core including a section adjacent to the notch in the sidewall of the light-absorbing layer.
Disclosed are a photonic integrated circuit (PIC) design system and method including optical signal propagation simulation with coupling awareness to account for transition loss due to a difference between at least one specific physical parameter (e.g., curvature radius, material composition, etc.) in optically coupled photonic devices. Coupling awareness can be achieved by including, within a bus of a netlist between the photonic devices, at least one pair of physical data pins: one associated with a specific physical parameter in the light emitting photonic device and the other associated with the specific physical parameter in the light receiving photonic device. Alternatively, coupling awareness can be achieved by running a utility to identify a parameter mismatch between the light emitting and receiving photonic devices, developing a custom coupling cell to account for the mismatch, and inserting the custom coupling cell into a design layout for the PIC.
A method for hybrid bonding a first semiconductor substrate to a second semiconductor substrate includes forming a first plurality of metal pads on a face of the first substrate, forming a second plurality of metal pads on a face of the second substrate, selectively forming a first dielectric layer over a first insulating material of the first substrate, selectively forming a second dielectric layer over a second insulating material of the second substrate, placing the face of the first substrate against the face of the second substrate so that the first dielectric layer contacts the second dielectric layer, and heating the first substrate and the second substrate to bond the first plurality of metal pads to the second plurality of metal pads. The first and second dielectric layers may be formed by an area selective deposition process.
The present disclosure relates to semiconductor structures and, more particularly, to high electron mobility transistors and methods of manufacture. The structure includes: a gate structure; a first barrier layer under and adjacent to the gate structure; and a second barrier layer over the first barrier layer and which is adjacent to the gate structure.
The present disclosure relates to semiconductor structures and, more particularly, to buried interconnect structures and methods of manufacture. The structure includes: a semiconductor substrate; a trench isolation structure extending into the semiconductor substrate; and at least one buried interconnect structure in the semiconductor substrate and crossing the trench isolation structure.
The present disclosure relates to semiconductor structures and, more particularly, to devices with isolation structures and methods of manufacture. The structure includes: a stack of semiconductor materials; a semiconductor substrate under the stack of semiconductor materials; a trench filled with in insulator material; and a damaged region of the stack of semiconductor materials extending from at least a bottom of the insulator material to the semiconductor substrate.
H01L 29/04 - Semiconductor bodies characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
56.
NONVOLATILE MEMORY WITH ISOLATION STRUCTURE AND METHOD OF FORMING THE SAME
A non-volatile memory structure includes a semiconductor substrate and first and second memory devices on the semiconductor substrate. Each of the first and second memory devices includes a floating gate, a tunnelling insulator under the floating gate, an isolation layer over the floating gate, and at least one of a select gate and a control gate over the isolation layer. The non-volatile memory structure further includes an erase gate shared by the first and second memory devices, a source region under the erase gate, and a shallow trench isolation structure between the erase gate and the source region. The shallow trench isolation structure increases the number of write/erase cycles that can be performed by the non-volatile memory structure.
The present disclosure relates to semiconductor structures and, more particularly, to silicon controlled rectifiers and methods of manufacture. The structure includes: a plurality of wells of a first conductivity type; a well of a second conductivity type which is different than the first conductivity type; an intrinsic semiconductor region between the well and the plurality of wells; and contacts within the plurality of wells.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
58.
INTEGRATED CIRCUIT STRUCTURE WITH DIFFUSION BREAK IN P-TYPE FIELD EFFECT TRANSISTOR REGION AND METHOD
A semiconductor device includes an insulating layer, a first semiconductor layer over the insulating layer, a diffusion break structure between a first active region and a second active region and including a first insulating pattern over the insulating layer and an opening over the first insulating pattern, and a conductive gate material over the opening.
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
A temperature-adaptive gate driver for a GaN switch includes a gate-to-source voltage adjustment unit and a driver for outputting an on-state gate-to-source voltage to a gate terminal of the switch. The on-state gate-to-source voltage is adjusted based, in part, on temperature of the switch. The amount of adjustment of the on-state gate-to-source voltage with rise in temperature is based, in part, on high-temperature gate-bias reliability data of the switch and is chosen for a favorable trade-off between performance and life-time. The gate-to-source voltage adjustment unit includes a temperature sense element for sensing temperature of the switch and outputs to the driver an output signal based, in part, on temperature. The gate-to-source voltage adjustment unit includes a regulator for receiving a feedback signal based in part, on resistance of the temperature sense element, and for causing a value of the output signal to be responsive to a value of the feedback signal.
The present disclosure relates to semiconductor structures and, more particularly, to a high-electron-mobility transistor and methods of manufacture. The structure includes: a semiconductor substrate; at least one insulator film over the semiconductor substrate, the at least one insulator film including a recess; and a field plate extending into the at least one recess and over the at least one insulator film.
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
The disclosure provides bipolar transistor structures with a cavity below an extrinsic base, and methods to form the same. A structure of the disclosure provides a bipolar transistor structure including an extrinsic base protruding from an intrinsic base of a bipolar transistor. The extrinsic base extends over a cavity. An insulator is horizontally adjacent the cavity and below a portion of the extrinsic base. A collector extension region of the bipolar transistor structure extends laterally below the insulator and the cavity.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
Disclosed is a fully depleted semiconductor-on-insulator structure including a buried Nwell in a substrate below P-type and N-type well regions, an insulator layer on the substrate, and mixed threshold voltage transistors on the insulator layer above at least one of the well regions. An Nwell can be connected to receive a positive bias voltage with any NFET and any PFET above being a FBB LVT/SLVT NFET and a RBB RVT/HVT PFET, respectively. A Pwell can be connected to receive another positive bias voltage less than the positive bias voltage on the Nwell with any NFET and any PFET above being a FBB RVT/HVT NFET and a RBB LVT/SLVT PFET, respectively. Additionally, or alternatively, a Pwell can be connected to receive a negative bias voltage with any NFET and any PFET above being a RBB RVT/HVT NFET and a FBB LVT/SLVT PFET, respectively.
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
Structures for an optical switch and methods of forming such structures. The structure comprises a first waveguide core including a first portion and a second portion, a second waveguide core including a first portion and a second portion, a ring resonator having a first portion adjacent to the first portion of the first waveguide core and a second portion adjacent to the first portion of the second waveguide core, and an optical coupler coupled to the second portion of first waveguide core and the second portion of the second waveguide core. The first portion of the ring resonator is spaced from the first portion of the first waveguide core by a first gap over a first light coupling region, and the second portion of the ring resonator is spaced from the first portion of the second waveguide core by a second gap over a second light coupling region.
The present disclosure relates to semiconductor structures and, more particularly, to high electron mobility transistors and methods of manufacture. The structure includes: a semiconductor substrate; a gate structure on the semiconductor substrate; a gate metal connecting to the gate structure; and a field plate connected to a source region of the gate structure. The gate metal and the field plate include a same material.
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
Disclosed are a pixel and a compact memory-in-pixel display (e.g., implemented in a fully-depleted semiconductor-on-insulator processing technology platform). A block of electronic components for a pixel includes a memory cell array, a driving circuit for an LED, and a logic circuit connected between the memory cell array and driving circuit. The memory cell array is above a Pwell, the driving circuit is above an adjacent Nwell, and the logic circuit includes P-type transistors on the Nwell and N-type transistors on the Pwell. A pixel array is above alternating P and N wells with a single buried Nwell below. Specifically, each column of pixels is above adjacent elongated P and N wells and, within each column, adjacent pixels have mirrored layouts. Furthermore, adjacent columns of pixels are above two elongated wells of one type and a shared elongated well of the opposite type therebetween and the adjacent columns have mirrored layouts.
G09G 3/32 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
A disclosed structure includes a power amplifier and circuitry for implementing a biasing scheme that enables high power operation. The power amplifier includes parallel transistor chains connected to input and output transformers. Each chain includes series-connected first, second, and third n-type field effect transistors (NFETs) having front and back gates. The output transformer receives a variable positive power supply voltage generated using average power tracking. Front and back gates of each third NFET receive a positive bias voltage greater than or equal to the variable positive power supply voltage and a negative bias voltage, respectively. By negative back biasing the third NFETs, threshold voltages thereof are raised so a high positive bias voltage can be applied to the front gates to increase power output without violating reliability specifications. Optionally, by making the negative bias voltage temperature dependent, voltages at source regions of the third NFETs are held constant.
The present disclosure relates to semiconductor structures and, more particularly, to quantum dot structures and methods of manufacture. The structure includes: a plurality of barrier gates; a plurality of spin qubit gates interdigitated with the plurality of barrier gates; and access gates on opposing sides of the plurality of barrier gates.
The disclosure provides a structure including a silicon carbide (SiC) channel horizontally between a source and a drain drift region. The SiC channel has opposite doping from the source and the drain drift region. A capping semiconductor is on the SiC channel and is horizontally between the source and the drain drift region. The capping semiconductor includes a semiconductor having a higher charge carrier mobility than the SiC channel. A gate structure is on the capping semiconductor.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
A differential power amplifier circuit, including: a first differential power amplifier including first and second cross-coupled neutralization capacitors; and a second differential power amplifier, coupled in parallel with the first differential power amplifier, including a plurality of multi-gate transistors.
H03F 1/22 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
H03F 3/21 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
70.
POWER SPLITTERS INCLUDING A TUNABLE MULTIMODE INTERFERENCE COUPLER
Khalifa University of Science and Technology (United Arab Emirates)
Inventor
Rakowski, Michal
Bian, Yusheng
Augur, Roderick A.
Taha, Ayat M.
Papadovasilakis, Marios
Gebregiorgis, Yonas Hadush
Viegas, Jaime
Abstract
Structures for a power splitter that include a multimode interference coupler and methods of forming such structures. The structure comprises a multimode interference coupler including a grating having a plurality of grating lines, an input waveguide core, and an output waveguide core. The grating lines are disposed between the input waveguide core and the output waveguide core. The structure further comprises a resistive heating element adjacent to the grating lines.
G02F 1/21 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour by interference
G02F 1/01 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour
G02F 1/225 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour by interference in an optical waveguide structure
71.
Hierarchical memory architecture including on-chip multi-bank non-volatile memory with low leakage and low latency
A disclosed non-volatile memory (NVM) structure is implemented in a fully depleted semiconductor-on-insulator technology processing platform and includes multiple NVM banks with NVM cells including transistors. NVM banks have well regions in a substrate. Transistors of NVM cells of each NVM bank are on an insulator layer above a corresponding well region for that bank. A bias control circuit causes well regions for NVM banks in a standby state to be biased with a reverse back biasing voltage and causes a well region for an NVM bank in an operational state to be biased with a forward back biasing voltage. The bias control circuit can initiate forward back biasing during a cache data retrieval process (before NVM bank access) to ensure that the corresponding well region of an NVM bank at issue is fully biased when, following the cache data retrieval process, access to the NVM bank is still required.
G11C 11/00 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor
G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
72.
ELECTRO-OPTIC BRIDGE CHIPS FOR CHIP-TO-CHIP COMMUNICATION
Structures including an electro-optic bridge chip and methods of forming such structures. The structure comprises a photonics chip and an electro-optic bridge chip on a package substrate. The electro-optic bridge chip includes a waveguide core and an electrical trace line. A portion of the waveguide core is coupled to an optical coupler of the photonics chip.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
G02B 6/122 - Basic optical elements, e.g. light-guiding paths
G02B 6/43 - Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
The present disclosure relates to semiconductor structures and, more particularly, to bipolar transistors and methods of manufacture. The structure includes: a collector; a base region above the collector; an emitter laterally connecting to the base region; and an extrinsic base connecting to the base region.
H01L 29/201 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds
Photonic structures including multiple input/output optical couplers and methods of forming such photonic structures. The photonic structure comprises a light source and a photonics chip including a semiconductor substrate. The photonic structure further comprises a first mirror disposed at a first height relative to a top surface of the semiconductor substrate and a second mirror disposed at a second height relative to the top surface of the semiconductor substrate. The first mirror is configured to reflect first light from the light source to the photonics chip, and the second mirror is configured to reflect second light from the light source to the photonics chip. The first mirror is disposed between the second mirror and the light source, and the second height is different from the first height.
A structure according to the disclosure includes a dielectric layer over a substrate and horizontally between a gate terminal and a source/drain (S/D) terminal. The dielectric layer has a first surface proximal to the substrate and a second surface opposite the first surface. The dielectric layer has a plurality of recesses in the second surface. At least some of the plurality of recesses have different depths. A conductive field plate includes a metal layer on the second surface and within the plurality of recesses. The conductive field plate is electrically isolated from the gate terminal and the S/D terminal.
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
A system and computerized method verify product custody along a product manufacturing chain. The method may include verifying a first machine-readable (MR) code for a product level N is valid by comparing the first MR code to a database of valid MR codes. Where the first MR code for the product level N is verified as valid, a second, valid MR code is generated for a next product level N+1 in the database of valid MR codes. In addition, the first MR code for the product level N in the database of valid MR codes is invalidated, so it cannot be used again. The second MR code is formed for use with the next product level N+1, e.g., by the downstream product manufacturer. Custody of product levels along a manufacturing chain can be verified and secured, avoiding bad actors from inserting and profiting from fake parts into the manufacturing chain.
G06K 7/14 - Methods or arrangements for sensing record carriers by electromagnetic radiation, e.g. optical sensingMethods or arrangements for sensing record carriers by corpuscular radiation using light without selection of wavelength, e.g. sensing reflected white light
77.
ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT AND METHODS OF FORMING THE SAME
An electrostatic discharge (ESD) protection circuit includes a silicon controlled rectifier. The silicon controlled rectifier includes a first well of a first conductivity type in a substrate, and a first doped region of a second conductivity type and a first tap region of the first conductivity type in the first well. The second conductivity type has an opposite polarity to the first conductivity type. The first doped region is coupled to a first pad. The first tap region is coupled to a second pad through a resistor external to the silicon controlled rectifier.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 29/87 - Thyristor diodes, e.g. Shockley diodes, break-over diodes
78.
NANOSHEET STRUCTURES WITH BOTTOM SEMICONDUCTOR MATERIAL
The present disclosure relates to semiconductor structures and, more particularly, to nanosheet transistor structures with a bottom epitaxial semiconductor material and methods of manufacture. The structure includes: a plurality of stacked semiconductor nanosheets; a plurality of gate structures surrounding individual semiconductor nanosheets of the plurality of semiconductor nanosheets; a first semiconductor material of a first conductivity type at source/drain regions of the plurality of gate structures; and a second semiconductor material of a second conductivity type above the first semiconductor material, the first conductivity type being different than the second conductivity type.
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H03B 5/12 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
H03B 5/04 - Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
H03B 5/36 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator active element in amplifier being semiconductor device
80.
STRUCTURE WITH GATE OVER NON-ALIGNED SEMICONDUCTOR REGIONS
Embodiments of the disclosure provide a structure and related method for a gate over semiconductor regions that are not aligned. Structures according to the disclosure include a first semiconductor region extending from a first widthwise end to a second widthwise end within a substrate. A second semiconductor region is adjacent the first semiconductor region and extends from a first widthwise end to a second widthwise end within the substrate. The second widthwise end of the second semiconductor region is non-aligned with the second widthwise end of the first semiconductor region. A gate structure is over the substrate and extends widthwise over the first semiconductor region and the second semiconductor region.
Structures for a co-packaged photonics chip and electronic chip, and associated methods. The structure comprises a layer comprising a molding compound, an electronic chip and a photonics chip affixed in the layer, and a waveguiding structure including a waveguide core adjacent to the photonics chip. The photonics chip includes an optical coupler, the waveguide core includes a portion that overlaps with the optical coupler, and the waveguide core comprises a polymer.
G02B 6/122 - Basic optical elements, e.g. light-guiding paths
G02B 6/13 - Integrated optical circuits characterised by the manufacturing method
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
Photonics chip structures including a reflector and methods of forming such structures. The photonics chip structure comprises a first waveguide core, a second waveguide core adjacent to the first waveguide core, and a reflector including a plurality of metal contacts over a portion of the first waveguide core. The second waveguide core is configured to couple light to the first waveguide core, and the metal contacts are configured to reflect the light.
A disclosed flip-flop includes primary and secondary sections connected to switchable and continuous power supplies, respectively. The primary section includes logic outputting first control signals, a primary latch controlled by the first control signals, and a data output device connected to an output terminal of the primary latch. The secondary section includes logic outputting second control signals and a secondary latch. A first transmission gate controlled by the second control signals is connected between the output terminal of the primary latch and an input terminal of the secondary latch. A second transmission gate controlled by the first and second control signals is connected between output and input terminals of the secondary latch. In a normal mode, both sections receive power and the first transmission gate is conductive. In a retention mode, the primary section is powered down, the first transmission gate is non-conductive and the second transmission gate is conductive.
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
84.
STATIC RANDOM ACCESS MEMORY (SRAM) CELL WITH VARIABLE TOGGLE THRESHOLD VOLTAGE AND MEMORY CIRCUIT INCLUDING SRAM CELLS
A static random access memory (SRAM) cell includes P-type and N-type transistors having secondary gates. A node connected to all secondary gates receives a write enable signal (WEN). A low WEN forward biases the P-type transistors and increases the toggle threshold voltage (Vtth) of the SRAM cell to avoid data switching during a read. A high WEN forward biases the N-type transistors and decreases Vtth during a write. The SRAM cell can be implemented using a fully depleted semiconductor-on-insulator technology, where the secondary gates include corresponding portions of a well region below. In this case, an array of SRAM cells can be above a single well region. Alternatively, the array can be sectioned into sub-arrays above different well regions and a decoder can output sub-array-specific WENs to the different well regions (e.g., with only one WEN being high at a given time to reduce capacitance).
G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
Structures including a wide band-gap semiconductor layer stack and methods of forming such structures. The structure comprises a layer stack on a substrate and a first dielectric layer on the layer stack. The layer stack includes semiconductor layers that comprise a wide band-gap semiconductor material. A seal ring includes a trench that penetrates through the first dielectric layer and the layer stack to the substrate, a second dielectric layer that lines the trench, and a conductor layer including first and second portions inside the trench. The trench surrounds portions of the layer stack and the first dielectric layer. The second dielectric layer includes a first portion disposed between the first portion of the conductor layer and the portion of the layer stack, and the second dielectric layer includes a second portion disposed between the second portion of the conductor layer and the portion of the first dielectric layer.
The present disclosure relates to semiconductor structures and, more particularly, to a transistor with a thermal plug and methods of manufacture. The structure includes: a semiconductor substrate; a gate structure over the semiconductor substrate; a source region on a first side of the gate structure; a drain region on a second side of the gate structure; and a thermal plug extending from a top side of the semiconductor substrate into an active region of the semiconductor substrate.
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
A circuit structure includes an enhancement mode transistor and a turn-off slew rate controller for automatically adding drain-source capacitance to the transistor when the transistor is transitioning to an off state. The added drain-source capacitance slows the turn-off slew rate (dV/dt_off) of the transistor without also increasing the turn-off energy loss (E_off). The slew rate controller can include: sensors connected to the drain region for sensing both the drain voltage and the slew rate, respectively; a logic circuit for generating and outputting an enable signal based on output voltages from the sensors; and a capacitance adder for adding to the drain-source capacitance only when the logic value of the enable signal indicates that the drain voltage is at or above a predetermined positive drain voltage level and the slew rate is positive.
H03K 19/003 - Modifications for increasing the reliability
H03K 17/0412 - Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the control circuit
H03K 17/06 - Modifications for ensuring a fully conducting state
88.
PHOTONICS CHIP PACKAGE STRUCTURES INCLUDING A CONTROLLED UNDERFILL FILLET
Structures for a packaged photonics chip and associated methods. The structure comprises a photonics chip, a packaging substrate, a plurality of electrical connections disposed in a gap between the photonics chip and the packaging substrate, and a fillet comprising an underfill material. The fillet is disposed to overlap with a portion of the photonics chip adjacent to the gap, the fillet has a width dimension and a height dimension transverse to the width dimension, and a ratio of the width dimension to the height dimension is greater than or equal to 1.5.
Structures for an insulated-gate bipolar transistor and methods of forming a structure for an insulated-gate bipolar transistor. The structure comprises a semiconductor substrate having a front surface and a back surface opposite from the front surface. The semiconductor substrate comprises a wide bandgap semiconductor material. The structure further comprises a gate electrode at the front surface of the semiconductor substrate, and a diode at the back surface of the semiconductor substrate.
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
Disclosed semiconductor structures include semiconductor fin(s), each extending from a semiconductor substrate and having opposing sidewalls. Each fin has a lower portion and an upper portion above the lower portion. The lower portion has a base proximal to the semiconductor substrate and divots within the opposing sidewalls at the base. An isolation region is on the semiconductor substrate adjacent to the opposing sidewalls of each fin (e.g., including within the divots). The upper portion of each fin extends above the level of the top surface of the isolation region and can be incorporated into a single-fin or multi-fin fin-type device (e.g., a fin-type field effect transistor (FINFET)). In some embodiments, multiple single-fin and/or multi-fin FINFETs incorporating the upper portions of such fins can be incorporated into a memory cell, such as a static random access memory (SRAM) cell. Also disclosed herein are associated method embodiments.
H10B 10/00 - Static random access memory [SRAM] devices
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
Structures including a compound semiconductor layer stack and methods of forming such structures. The structure comprises a device region on a substrate. The device region includes a first section of a layer stack that has a plurality of semiconductor layers, and each semiconductor layer comprises a compound semiconductor material. The structure further comprises an isolation structure disposed about the section of the layer stack, and a device in the device region. The isolation structure penetrates through the layer stack to the substrate.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
92.
INDUCTOR STRUCTURES INTEGRATED IN SEMICONDUCTOR DEVICES
The disclosed subject matter relates generally to inductor structures integrated in semiconductor devices. More particularly, the present disclosure relates to a semiconductor device having a semiconductor chip, a redistribution layer on the semiconductor chip, and an inductor structure having an upper section in the redistribution layer and a lower section in the semiconductor chip. The upper section and the lower section are concentric about a center region of the inductor structure. The lower section is connected to the upper section.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
A test tray system for electronics, like photonics integrated circuit (PIC) structures, and a related method are disclosed. The test tray system includes at least one test tray. Each test tray includes a first section exposing a first electrical component to a high temperature, and a second section covered by a thermal protection element configured to prevent a second component from being exposed to the high temperature at the same time that the first electrical component is being exposed to the high temperature. The test tray system allows testing of the first component at a high temperature, e.g., 125° C., while protecting the second component from the high temperatures.
An integrated circuit includes a fin having a height and a width under a gate of a selected fin-type field effect transistor (FinFET) that is less than the height and width along a remainder of the fin including under gates and for source/drain regions of other FinFETs. The IC includes a first FinFET having a first gate over a fin having a first height and a first width under the first gate, and a second FinFET in the fin adjacent to the first FinFET. The second FinFET has a second gate over the fin, and the fin has, under the second gate only, a second height less than the first height and a second width less than the first width. The resulting reduced channel height and width for the second FinFET increases gate control and reduces gate leakage, which is beneficial for ultra-low current leakage (ULL) devices.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A semiconductor device including a semiconductor substrate. A first transistor and a second transistor are formed on the semiconductor substrate. Each transistor comprises a source, a drain, and a gate. A CA layer forms a local interconnect layer electrically connected to one of the source and the drain of the first transistor. A CB layer forms a local interconnect layer electrically connected to the gate of one of the first transistor and the second transistor. An end of the CB layer is disposed at a center of the CA layer
H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
Structures for a photonics chip that include a photonic component and methods of forming such structures. The structure may comprise a photodetector on a substrate and a waveguide core. The photodetector includes a light-absorbing layer having a longitudinal axis, a first sidewall, and a second sidewall adjoined to the first sidewall at an interior angle. The first sidewall is slanted relative to the longitudinal axis, and the second sidewall is oriented transverse to the longitudinal axis. The waveguide core includes a tapered section adjacent to the first sidewall and the second sidewall of the light-absorbing layer.
The present disclosure relates to semiconductor structures and, more particularly, to gate-all-around field effect transistors and methods of manufacture. The structure includes: a plurality of stacked semiconductor nanosheets over a semiconductor substrate; a plurality of gate structures surrounding the plurality of semiconductor nanosheets; a conductive material between the plurality of semiconductor nanosheets and the plurality of gate structures; an inner sidewall spacer adjacent to each of the plurality of gate structures and conductive material; and source/drain regions on opposing sides of the plurality of gate structures, separated therefrom by the inner sidewall spacer.
H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
The present disclosure relates to semiconductor structures and, more particularly, to a high-electron-mobility transistor and methods of manufacture. The structure includes: a gate structure; a first field plate on a first side of the gate structure; and a second field plate on a second side of the gate structure, independent from the first field plate.
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
Structures including an inductor and methods of forming such structures. The structure comprises a semiconductor substrate including a first plurality of sealed cavities and a back-end-of-line stack on the semiconductor substrate. Each sealed cavity includes an air gap, and the back-end-of-line stack includes an inductor having a winding that overlaps with the scaled cavities.
Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. The structure comprises an intrinsic base including a first semiconductor layer, a collector including a second semiconductor layer, and an emitter including a third semiconductor layer. The first semiconductor layer, which comprises silicon-germanium, includes a first portion and a second portion adjacent to the first portion. The second semiconductor layer includes a portion on the first portion of the first semiconductor layer, and the third semiconductor layer includes a portion on the second portion of the first semiconductor layer. The structure further comprises a dielectric spacer laterally between the portion of the second semiconductor layer and the portion of the third semiconductor layer.
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/165 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group in different semiconductor regions
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
