A laminate transformer includes a multilayer substrate having at least first, second, third, and fourth metal layers. The second metal layer and the third metal layer are separated by a voltage barrier having a thickness. A first multiloop coil has at least a first loop on the first metal layer and at least a second loop on the second metal layer. A second multiloop coil has at least a third loop on the third metal layer and at least a fourth loop on the fourth metal layer. A partial EMI shield for the first multiloop coil is on the second metal layer. A partial EMI shield for the second multiloop coil is on the third metal layer.
An example apparatus having a first and second data terminal and including a first transistor having a first terminal, a second terminal, and a control terminal; a second transistor having a first terminal and a control terminal, the first terminal of the second transistor coupled to the first terminal of the first transistor; a third transistor having a first terminal, a second terminal, and a control terminal; a fourth transistor having a first terminal and a control terminal, the first terminal of the fourth transistor coupled to the first terminal of the third transistor; and gate driver circuitry having a first terminal, and a second terminal, the first terminal of the gate driver circuitry coupled to the first data terminal, and the second terminal of the first transistor, the second terminal of the gate driver circuitry coupled to the second data terminal and the second terminal of third transistor.
In a described example, a circuit includes a switching system and a reference controller. The reference controller includes an output voltage sampler and a variable reference generator. The switching system is configured to activate a primary switch to provide an input current through a flyback inductor in response to an instantaneous amplitude of an output current falling below a predetermined threshold. Additionally, the switching system is configured to deactivate the primary switch in response to the input current increasing greater than a variable peak current amplitude. The output voltage sampler is configured to sample an output voltage of the flyback inductor in response to the deactivation of the primary switch. The variable reference generator is configured to generate the variable peak current amplitude based on the output voltage of the flyback inductor.
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
Methods, apparatus, systems and articles of manufacture are described for a wireless battery system. An example apparatus includes at least one memory, instructions, and processor circuitry to at least one of instantiate or execute the instructions to identify a first battery node to transmit an uplink command during a first superframe interval, transmit a downlink command to the first battery node and a second battery node, the first battery node to switch in the first superframe interval from a receive state to a transmit state in response to the downlink command, the first battery node to transmit the uplink command in the transmit state, and receive the uplink command from the first battery node in the first superframe interval.
A method includes rolling a roller with a protrusion across a lead frame to create an indent in a feature of the lead frame, attaching a die to a die attach pad of the lead frame, coupling the die with a lead, and enclosing portions of the die, the die attach pad, and portions of the lead frame feature with a molding compound. A system includes a roller with a cylindrical body and a protrusion, a chuck to engage a lead frame, and a controller to roll the roller across the lead frame to create an indent in a feature of the lead frame. An integrated circuit includes a package structure enclosing a first portion of a lead and a first portion of a die attach pad, and a rolled indent in the first portion of the lead or the die attach pad.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
An example circuit includes a multiphase loop controller having phase current inputs, a feedback input, and a control loop output. A first phase loop controller includes a first phase current input, a first feedback input, and a first phase loop output, in which the first feedback input is coupled to the feedback input. A second phase loop controller includes a second phase current input, a second feedback input, and a second phase loop output. Pulse generator circuitry includes first, second, and third pulse control inputs, and first and second pulse outputs, in which the first pulse control input is coupled to the control loop output, the second pulse control input is coupled to the first phase loop output, and the third pulse control input is coupled to the second phase loop output.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
A multi-layer package substrate includes a first build-up layer including a first dielectric layer and at least a second build-up layer including a second dielectric layer on the first build-up layer. The second build-up layer includes a top metal layer with a surface configured for attaching at least one integrated circuit (IC) die. The first build-up layer includes a bottom metal layer and a first microvia extending through the first dielectric layer, and the second build-up layer includes at least a second microvia extending through the second dielectric layer that is coupled to the first microvia. A barrier ring that has a coefficient of thermal expansion (CTE) matching material relative to a CTE of a metal of the second microvia positioned along only a portion of a height of at least the second microvia including at least around a top portion of the second microvia.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
An analog-to-digital converter including a voltage-to-delay circuit, a plurality of residue stages coupled in a sequence, and select logic. A first residue stage generates a bit output and a residue delay signal, a second residue stage generates a bit output and a residue delay signal responsive to the residue delay signal from the first residue stage, and a third residue stage generates a bit output and a residue delay signal responsive to the residue delay signal from the second residue stage. The third residue stage includes a plurality of trim circuits, the selection of which is controlled by the bit output of two or more preceding residue stages in the sequence.
H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
In examples, an electronic device includes a semiconductor die including circuitry, a microelectromechanical systems (MEMS) element on the semiconductor die and coupled to the circuitry, a bond pad on the semiconductor die and coupled to the circuitry, and a bondline on the semiconductor die between the MEMS element and the bond pad, with the bondline circumscribing the MEMS element. The electronic device includes a semiconductor interposer coupled to the bondline and having a striated exterior surface facing away from the MEMS element.
Techniques for determining an angle-of-arrival of a wireless transmission are provided, including receiving, with a first antenna, at least a first portion of a wireless transmission, determining when a second portion of the wireless transmission will be received, switching to the second antenna to receive the second portion of the wireless transmission, determining an angle of arrival of the wireless transmission based on the first portion and the second portion of the wireless transmission, and outputting the angle of arrival of the wireless transmission.
G01S 3/46 - Systems for determining direction or deviation from predetermined direction using antennas spaced apart and measuring phase or time difference between signals therefrom, i.e. path-difference systems
G01S 3/48 - Systems for determining direction or deviation from predetermined direction using antennas spaced apart and measuring phase or time difference between signals therefrom, i.e. path-difference systems the waves arriving at the antennas being continuous or intermittent and the phase difference of signals derived therefrom being measured
G01S 3/50 - Systems for determining direction or deviation from predetermined direction using antennas spaced apart and measuring phase or time difference between signals therefrom, i.e. path-difference systems the waves arriving at the antennas being pulse modulated and the time difference of their arrival being measured
G01S 3/72 - Diversity systems specially adapted for direction-finding
An integrated circuit (IC) includes first and second memory devices and a bridge. The IC also includes a first interconnect segment coupled between the first memory device and the bridge. The IC further includes a second interconnect segment coupled between the first and second memory devices, and a third interconnect segment coupled between the bridge and the second memory device. The IC includes a first DMA circuit coupled to the first interconnect segment, and a second DMA circuit coupled to the second interconnect segment. A fourth interconnect segment is coupled between the first and second DMA circuits.
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
An apparatus includes a two-level converter circuit (120), a higher-level converter circuit (130) (having switches), and a controller (140). The controller receives a feedback signal (112) associated with the two-level/higher-level converter circuits and generates a control signal (142) based on the feedback signal. The apparatus operates in one of three modes (first/second/third modes) based on the control signal (142). In the first mode, the apparatus operates as a two-level converter to generate a two-level output voltage from an input voltage. In a second mode, the apparatus operates as a higher-level converter to increase a number of levels to more than two-levels for the output voltage. In a third mode, the apparatus transitions between the first/second modes where the apparatus operates as the two-level converter and where the switches of the higher-level converter circuit are activated for a period of time to generate a zero voltage at a switching connection point of the apparatus.
H02M 7/483 - Converters with outputs that each can have more than two voltage levels
H02M 7/5387 - Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
H02M 7/5395 - Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency by pulse-width modulation
A device includes a semiconductor substrate having a surface. The device includes a first region in the substrate having a first dopant, a second region in the substrate having a second dopant, and a third region in the substrate having the first dopant. A first light absorption layer is on the surface and over a fourth region of the substrate between the first and second regions. The first light absorption layer is configured to absorb light of a particular wavelength. A second light absorption layer is on the surface and over a fifth region of the substrate between the second and third regions. The second light absorption layer is configured to absorb the light of the particular wavelength. At least one of lateral dimensions of the first and second light absorption layers or a lateral separation between the first and second light absorption layers is based on the particular wavelength.
H01L 31/107 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode
H01L 31/02 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof - Details
An example includes: a system board having a surface; bond fingers on a surface of the system board; a semiconductor device on the surface of the system board, the semiconductor device comprising a semiconductor die having a surface, the semiconductor die comprising bond pads on the surface; conductors coupling the bond pads to the bond fingers; and a datum structure on the surface of the system board, the datum structure having openings that form wells with sides around the bond fingers.
G02B 26/08 - Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light
In some examples, a circuit includes a first transistor having first and second terminals; a first current source having first and second terminals, the first terminal of the first current source coupled to the first terminal of the first transistor, and the second terminal of the first current source coupled to the second terminal of the first transistor; a second transistor having a control terminal and first and second terminals, the control terminal of the second transistor coupled to the second terminal of the first current source, and the first terminal of the second transistor coupled to the second terminal of the first current source; a third transistor having first and second terminals, the first terminal of the third transistor coupled to the second terminal of the second transistor; and a fourth transistor having first and second terminals, the first terminal of the fourth transistor coupled to the second terminal of the first current source, and the second terminal of the fourth transistor coupled to the second terminal of the third transistor.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
An apparatus includes a two-level converter circuit, a higher-level converter circuit (having switches), and a controller. The controller receives a feedback signal associated with the two-level/higher-level converter circuits and generates a control signal based on the feedback signal. The apparatus operates in one of three modes (first/second/third modes) based on the control signal. In the first mode, the apparatus operates as a two-level converter to generate a two-level output voltage from an input voltage. In a second mode, the apparatus operates as a higher-level converter to increase a number of levels to more than two-levels for the output voltage. In a third mode, the apparatus transitions between the first/second modes where the apparatus operates as the two-level converter and where the switches of the higher-level converter circuit are activated for a period of time to generate a zero voltage at a switching connection point of the apparatus.
H02M 7/497 - Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode sinusoidal output voltages being obtained by combination of several voltages being out of phase
17.
LAYER NORMALIZATION TECHNIQUES FOR NEURAL NETWORKS
Various embodiments of the present disclosure relate to performing layer normalization within the context of neural networks, and in particular, to optimizing the operations required to perform layer normalization. In one example embodiment a technique for performing layer normalization is provided. The technique first includes generating a first input matrix and a second input matrix using a plurality of values stored by a feature vector. Next, the technique includes matrix multiplying the first input matrix with the second input matrix to generate an output matrix, such that the output matrix stores a plurality of result values. Finally, the technique includes performing layer normalization for the feature vector using the plurality of result values stored by the output matrix.
An example system includes processing circuitry including n transmission paths; and a memory to store data specifying m of the n transmission paths that are operable for a first operation, m≤n. In operation, the processing circuitry starts performing the first operation on the m transmission paths; receives a signal for a second operation to be performed on p transmission paths, p≠m, and in response, preserves the data stored in the memory and stops performance of the first operation. Thereafter, the second operation is performed on the p transmission paths to completion, after which the data is restored to the memory, and performance of the first operation on the m of transmission paths is resumed.
A molded inductor includes a winding having leads configured for attaching leads of the winding to pads on a package substrate, having a magnetic core with a body disposed within the winding, wherein the magnetic core has at least one mold flow enhancing feature that enhances a filling of a magnetic mold material as compared to a filling provided by a uniform cylindrical body. The magnetic mold material encases the winding and the magnetic core to form either a standalone discrete inductor component, or the magnetic component of an output filter of an integrated switching power converter module.
H01F 27/36 - Electric or magnetic shields or screens
H01F 41/00 - Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformersApparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
H01F 41/061 - Winding flat conductive wires or sheets
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/552 - Protection against radiation, e.g. light
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
20.
VERTICAL DEEP TRENCH AND DEEP TRENCH ISLAND BASED DEEP N-TYPE WELL DIODE AND DIODE TRIGGERED PROTECTION DEVICE
A semiconductor device which includes two or more integrated deep trench features configured as a Zener diode. The Zener diode includes a plurality of deep trenches extending into semiconductor material of the substrate and a dielectric deep trench liner that includes a dielectric material. The deep trench further includes a doped sheath contacting the deep trench liner and an electrically conductive deep trench filler material within the deep trench. The doped sheath of adjacent deep trenches overlap and form a region of higher doping concentration which sets the breakdown voltage of the Zener diode. The Zener diode can be used as a triggering diode to limit the voltage on other components in a semiconductor device.
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
21.
DYNAMIC POWER NEGOTIATION OUTSIDE ENHANCED BEACON EXCHANGE IN A WIRELESS NETWORK VIA ACKNOWLEDGMENT FRAMES
An end device in a ZIGBEE communication protocol wireless network includes a memory configured to store computer-executable instructions and a processor coupled to the memory and configured to execute the instructions. The processor sends a first data frame to a first network device using a first network transmission power level and receives a first acknowledgment frame from the first network device. The first acknowledgement frame includes a first transmission power information element, and the first transmission power information element includes a second transmission power level. The processor updates a power control information table entry with the second transmission power level and sends a second data frame to the first network device using the second transmission power level.
H04W 52/22 - TPC being performed according to specific parameters taking into account previous information or commands
H04W 4/80 - Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
An example method of producing a microelectromechanical system (MEMS) package, the method comprising: applying first epoxy layers to a first substrate, at least one of the first epoxy layers coupled to a second substrate; applying a first post gel heat treatment to the first epoxy layers; after applying the first post gel heat treatment to the first epoxy layers, applying second epoxy layers to the second substrate and to the first epoxy layers; and applying a second post gel heat treatment to the first epoxy layers and the second epoxy layers.
A system, method, and device are shown that are operable to transform and align a plurality of fields from an input to an output data stream using a multilayer butterfly or inverse butterfly network by selectably switching bit positions of the input data stream. In some examples, a device includes a first circuit configured to selectably switch bit positions of a first subset of the data stream with a second subset of the data stream and a second circuit configured to: selectably switch bit positions of a first subset of the first subset of the data stream with a second subset of the first subset of the data stream, and selectably switch bit positions of a first subset of the second subset of the data stream with a second subset of the second subset of the data stream.
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
H03M 13/27 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes using interleaving techniques
24.
STREAMING ENGINE WITH SEPARATELY SELECTABLE ELEMENT AND GROUP DUPLICATION
A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. An element duplication unit optionally duplicates data element an instruction specified number of times. A vector masking unit limits data elements received from the element duplication unit to least significant bits within an instruction specified vector length. If the vector length is less than a stream head register size, the vector masking unit stores all 0's in excess lanes of the stream head register (group duplication disabled) or stores duplicate copies of the least significant bits in excess lanes of the stream head register.
G06F 12/0875 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
G06F 9/32 - Address formation of the next instruction, e.g. by incrementing the instruction counter
G06F 9/345 - Addressing or accessing the instruction operand or the result of multiple operands or results
G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G06F 12/0846 - Cache with multiple tag or data arrays being simultaneously accessible
G06F 12/0897 - Caches characterised by their organisation or structure with two or more cache hierarchy levels
An integrated filter optical package including an ambient light sensor that incorporates an infrared (IR) filter in an integrated circuit (IC) stacked-die configuration is provided. The integrated filter optical package incorporates an infrared (IR) coated glass layer to filter out or block IR light while allowing visible (ambient) light to pass through to a light sensitive die having a light sensor. The ambient light sensor detects an amount of visible light that passes through the IR coated glass layer and adjusts a brightness or intensity of a display screen on an electronic device accordingly so that the display screen is readable.
An example apparatus includes: an integrated circuit including a first surface and terminals; a package including: a housing around the integrated circuit, the housing exposing the first surface; and an electrical interconnect including a second surface and an opening, the second surface electrically coupled to the terminals, the second surface mechanically coupled to the housing, the opening configured to expose the first surface.
A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to determine a first destination device connected to the data path and associated with the first memory access request and a first credit threshold corresponding to the first memory access request. The arbiter circuit is further configured to determine a second destination device connected to the data path and associated with the second memory access request and a second credit threshold corresponding to the second memory access request. The arbiter circuit is configured to arbitrate access to the data path by the first memory access request and the second memory access request based on the first credit threshold and the second credit threshold.
G06F 12/0817 - Cache consistency protocols using directory methods
G06F 12/0831 - Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
G06F 12/084 - Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
G06F 12/0846 - Cache with multiple tag or data arrays being simultaneously accessible
G06F 12/0855 - Overlapped cache accessing, e.g. pipeline
G06F 12/0862 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
G06F 12/0875 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
G06F 12/0891 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
H03M 13/01 - Coding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
H03M 13/09 - Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
H03M 13/27 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes using interleaving techniques
Methods, apparatus, and systems are described to facilitate phase detection for data clock synchronization. An example phase detection circuitry includes an oscillator having an output; frequency adjuster circuitry having an input, a first output, and a second output, the input of the frequency adjuster circuitry coupled to the output of the oscillator; a clock buffer circuitry including: a first resistor having a first terminal and a second terminal; and a second resistor having a first terminal and a second terminal, the second terminal of the second resistor coupled to the first terminal of the first resistor; and a feedback amplifier having a first input, a second input, and an output, the first input of the feedback amplifier coupled to a second terminal of the first resistor and a first terminal of the second resistor.
H03K 5/22 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
29.
ETCH STOP ARCHITECTURES FOR POWER DEVICE AND PASSIVE COMPONENTS
A semiconductor device includes a semiconductor substrate; a source electrode, a gate electrode, and a drain electrode on the semiconductor substrate; a staircase dielectric structure on the semiconductor substrate and laterally between the gate electrode and the drain electrode; and a metal layer on the staircase dielectric structure. The staircase dielectric structure includes a first dielectric layer on the semiconductor substrate, a first etch-stop layer on the first dielectric layer, and a second dielectric layer on the first etch-stop layer, where the first dielectric layer has a first lateral dimension greater than a second lateral dimension of the second dielectric layer. The metal layer includes a first field plate on at least a first region of the first dielectric layer and a second field plate on at least a second region of the second dielectric layer.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
Described embodiments include a circuit for overcurrent protection includes an amplifier having first and second amplifier inputs and an amplifier output. A reference voltage source has first and second reference voltage terminals and is configured to provide a reference voltage. The first reference voltage terminal is adapted to be coupled to a first transistor current terminal, and the second reference voltage terminal is coupled to the first amplifier input. A negative temperature coefficient (NTC) resistor has first and second NTC terminals. The first NTC terminal is adapted to be coupled to a second transistor current terminal, and the second NTC terminal is coupled to the second amplifier input. A transistor shutoff signal is provided at the amplifier output responsive to a voltage at the second amplifier input being greater than a voltage at the first amplifier input.
H02H 3/08 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess current
In an example, a Hall sensor can include an IC die formed on a lead frame that is configured to conduct a current, the IC die being configured to sense a magnetic field resulting from the current. The Hall sensor can include at least one magnetic permeability material film formed on the IC die. The Hall sensor can include at least one permalloy material layer formed on the respective at least one magnetic permeability material film, the at least one magnetic permeability material film and the at least one permalloy material layer combining to provide a magnetic concentrator providing concentration of the magnetic field.
An example apparatus includes: voltage buffer circuitry including: source follower circuitry having a terminal; and a resistor having a first terminal and a second terminal, the first terminal of the resistor coupled to the terminal of the source follower circuitry; and driver circuitry including: a first transistor having a first terminal and a second terminal, the first terminal of the first transistor coupled to the second terminal of the resistor; and a second transistor having a terminal coupled to the second terminal of the first transistor.
A circuit includes a first ground terminal, a second ground terminal, an output terminal, a transistor, a controller, and a resistor. The output terminal is configured to provide an output voltage. The transistor has a first terminal coupled to the output terminal, a second terminal coupled to the first ground terminal, and a control terminal. The controller has an output coupled to the control terminal, and a reference terminal coupled to the second ground terminal. The resistor has a first terminal coupled to the second terminal of the transistor, and a second terminal coupled to the reference terminal.
H02M 3/155 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
An apparatus includes: a substrate having a first set of bond pads; an integrated circuit (IC) having a second set of bond pads; bond wires between bond pads of the first set of bond pads and respective bond pads of the second set of bond pads; a first encapsulant layer in contact with the substrate and spaced away from the IC; a second encapsulant layer in contact with the IC and spaced away from the substrate, the second encapsulant layer separated from the first encapsulant layer by a gap; and a third encapsulant layer in contact with at least one of the first encapsulant layer and the second encapsulant layer, the third encapsulant layer at least partially covering the gap.
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/10 - ContainersSeals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
The present disclosure introduces semiconductor devices that include a first doped region having a first dopant type, a second doped region having a second dopant type different from the first dopant type, and third and fourth doped regions. The third and fourth doped regions have the first dopant type, contact corresponding opposite sides of the second doped region, and are electrically connected to the second doped region. The present disclosure also introduces diode implementations of such semiconductor devices, as well as methods of manufacturing such semiconductor devices.
Semiconductor devices and fabrication methods thereof are described. For example, a semiconductor device includes a semiconductor layer, a drain region disposed in the semiconductor layer, a source region disposed in the semiconductor layer, a channel region disposed between the drain region and the source region, a gate disposed over the channel region, and first and second insulating layers disposed between the gate and the semiconductor layer. Sections of the first insulating layer and sections of the second insulating layer alternate along a first direction perpendicular to a second direction defined between the drain region and the source region, each of the sections of the first insulating layer having a first thickness and each of the sections of the second insulating layer having a second thickness greater than the first thickness.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
Systems, apparatus, articles of manufacture, and methods are described to manage debugging interfaces of computing device. An example apparatus includes first memory configured to store a debug authentication status; a processor; second memory storing instructions that, when executed, cause the processor to: check the debug authentication status in the first memory; perform an authentication procedure in response to determining that the debug authentication status stored in the first memory does not indicate that debug is allowed; and set the debug authentication status in the first memory to indicate that debug is allowed in response to a successful performance of the authentication procedure.
A circuit comprises a clock, a counter, and a controller. The counter is connected to the clock. The controller is connected to the counter. The controller is configured to control a display brightness according to a brightness value and a count of the counter. The controller is further configured to perform, upon receiving the brightness value at an input, a digital display brightness update at a temporally proximate PWM segment in a clock frame. A positive integer number of PWM segments occur within the clock frame. The clock frame corresponds to a counted duration corresponding to a counting range of the counter. Contiguous counting is performed over an entirety of the clock frame. The controller causes uninterrupted illumination to be maintained from a first display frame to a second display frame, the second display frame being immediately subsequent to the first display frame.
Semiconductor devices with guard ring structures are described. In some examples, a semiconductor device includes a semiconductor substrate, a III-N layer over the semiconductor substrate. The III-N layer extends past a device region of the semiconductor substrate. The semiconductor device further includes a guard ring surrounding the device region. The guard ring includes a discontinuity formed through the III-N layer and extending into the semiconductor substrate.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
40.
PROTECTIVE DIELECTRIC LAYER CRACK MITIGATION THROUGH STRESS SINGULARITY FIELD REDUCTION
A microelectronic device may have a protective dielectric layer over the top metal layer of the microelectronic device which provides a portion of a hermetic seal between the microelectronic device and the environment. The protective dielectric layer may also improve resistance to physical damage of the microelectronic device before packaging. The protective dielectric layer may have bond pad openings to allow electrical contact between the microelectronic device to a microelectronic package. The protective dielectric layer may overlap the bond pads to ensure the hermetic seal of the microelectronic device. Cracking of the protective dielectric layer in the region where the protective dielectric layer overlaps the bond pad may lead to failure of the microelectronic device. Stress analysis using finite element methods (FEM) and experimental data show that increasing the overlap of the protective dielectric layer over the bond pad may reduce protective dielectric layer cracking.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/10 - ContainersSeals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
41.
SEMICONDUCTOR DIE SINGULATION USING DIE ATTACH FILM AND PLASMA DICING
An example semiconductor device package includes: a semiconductor die having a backside surface mounted to a die pad of a leadframe using a die attach film that includes polymer particles, the leadframe having leads spaced from the die pad; wire bonds coupling bond pads on a device side surface of the semiconductor die that is opposite the backside surface to the leads of the leadframe; and mold compound covering the semiconductor die, the wire bonds, and portions of the leads of the leadframe, with additional portions of the leads of the leadframe exposed from the mold compound to form terminals; wherein the semiconductor die has vertical sides extending from the backside surface to the device side surface that have a scalloped pattern.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 23/00 - Details of semiconductor or other solid state devices
A circuit can include a first switch and a second switch. The first switch has first and second current terminals and a first control terminal, in which the first or second current terminal is coupled to a switch output. The second switch has third and fourth current terminals and a second control terminal, in which the second control terminal is coupled to the first control terminal, and the fourth current terminal is coupled to the switch output. A switch network is coupled between the first switch and the second switch.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
43.
METHODS AND APPARATUS TO DETECT AN ELECTRICAL ARC USING MACHINE LEARNING
Systems, apparatus, articles of manufacture, and methods for detection of an electrical arc using machine learning are described. Example instructions, when executed, cause at least one processor circuit to at least access data representing at least one of a voltage or a current of a monitored circuit, execute a machine learning model using the data to generate a classification representative of whether an arc has occurred within the monitored circuit, cause output of the result of the classification of whether the arc has occurred within the monitored circuit, record the data from the monitored circuit, and perform additional training of the machine learning model based on the recorded data.
In described examples, a circuit includes a first current source, a second current source, a first bipolar junction transistor (BJT), a second BJT, a third BJT, a fourth BJT, and a fifth BJT. A base of the second BJT is coupled to a first terminal of the first current source. A base of the third BJT is coupled to a first terminal of the second current source, and an emitter of the third BJT is coupled to an emitter of the second BJT and a collector of the first BJT. A base of the fifth BJT is coupled to a base and an emitter of the fourth BJT and to a collector of the third BJT, and a collector of the fifth BJT is coupled to an emitter of the first BJT.
H03F 1/08 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
H03F 1/32 - Modifications of amplifiers to reduce non-linear distortion
H03F 3/50 - Amplifiers in which input is applied to, or output is derived from, an impedance common to input and output circuits of the amplifying element, e.g. cathode follower
A system includes a battery powered domain, which may be powered by a voltage regulator, such as a low dropout (LDO) regulator. The components of the system may, as a default, maintain a lower-power state to preserve battery charge but may periodically go to a higher-power state to facilitate memory reads and writes and interrupts. The system may include hardware to change a power state of the regulator based on control signals that are also used for clock gating, thereby achieving quick transitions between the power states.
G05F 1/59 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices including plural semiconductor devices as final control devices for a single load
46.
NOISE ESTIMATION USING USER-CONFIGURABLE INFORMATION
An example system includes a memory to store correlation information that specifies a noise correlation value for each channel, of a set of channels, of image data; filter circuitry to determine a respective local intensity for each channel of the set of channels; and threshold calculation circuitry to sum the respective local intensities of a subset of the set of channels based on the correlation information to produce a sum of local intensities; and determine a noise threshold based on the sum of local intensities. Suppression circuitry of the system is to apply a noise suppression function to each channel of the subset of the set of channels of the image data based on the noise threshold.
H04N 23/81 - Camera processing pipelinesComponents thereof for suppressing or minimising disturbance in the image signal generation
H04N 23/84 - Camera processing pipelinesComponents thereof for processing colour signals
H04N 25/61 - Noise processing, e.g. detecting, correcting, reducing or removing noise the noise originating only from the lens unit, e.g. flare, shading, vignetting or "cos4"
An integrated circuit, with an error amplifier having a first input, a second input, and an output, a voltage controlled oscillator having an input coupled to the output of the error amplifier, a feedback controlled voltage stage having at least one control coupled to the output of the error amplifier and an output coupled to the first input of the error amplifier, and an adaptive-reference voltage stage coupled to the second input of the error amplifier.
H03B 5/04 - Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
H03B 5/24 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising resistance and either capacitance or inductance, e.g. phase-shift oscillator active element in amplifier being semiconductor device
An integrated circuit (IC) package includes a molding having a first surface and a second surface, the first surface opposing the second surface. An interconnect is encased in the molding. The interconnect includes pads situated at a periphery of a side of the IC package. A portion of the pads are exposed at the first surface of the molding. A die pad is situated proximal to the second surface of the molding. The die pad has a first surface and a second surface, the first surface opposing the second surface, and the second surface is circumscribed by the second surface of the molding. A die is mounted on the first surface of the die pad. A heat spreader is mounted on the second surface of the molding and the second surface of the die pad. The heat spreader extends between edges of the second surface of the molding.
H01L 23/367 - Cooling facilitated by shape of device
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
49.
METHODS AND APPARATUS TO CORRECT NON-LINEARITY IN TRANSMITTERS
Methods, apparatus, systems, and articles of manufacture are described to correct non-linearity in transmitters. An example system includes an input stage, a driver, an input terminal of the driver coupled to an output terminal of the input stage; an output buffer, an input terminal of the output buffer coupled to an output terminal of the driver, an output terminal of the output terminal coupled to a first input terminal of the input stage via a resistor; and non-linear correction circuitry having an input terminal and an output terminal, the input terminal of the non-linear correction circuitry coupled to the output terminal of the output buffer and the first input terminal of the input stage via the resistor, the output terminal of the non-linear correction circuitry coupled to the output terminal of the input stage and the input terminal of the driver.
A61B 8/00 - Diagnosis using ultrasonic, sonic or infrasonic waves
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
50.
SHORT CIRCUIT PROTECTION WITH TEMPERATURE COMPENSATION
THRTHR). The first reference voltage terminal is adapted to be coupled to a first transistor current terminal (402 drain), and the second reference voltage terminal is coupled to the first amplifier input (408). A negative temperature coefficient (NTC) resistor (422) has first and second NTC terminals. The first NTC terminal is adapted to be coupled to a second transistor current terminal (402 source), and the second NTC terminal is coupled to the second amplifier input (410). A transistor shutoff signal is provided at the amplifier output (412) responsive to a voltage at the second amplifier input (410) being greater than a voltage at the first amplifier input (408).
H02H 1/00 - Details of emergency protective circuit arrangements
H02H 3/087 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess current for DC applications
An example method includes: computing a difference metric 655 between first sensed data 635A and second sensed data 635B, wherein the first sensed data is associated with a first region in a field of view of a sensor, and wherein second sensed data is associated with a second region in the field of view; determining that the first sensed data is distinguishable from the second sensed data using the difference metric; and detecting occupancy 665 in the first region in response to determining that the first sensed data is distinguishable from the second sensed data.
G01S 7/41 - Details of systems according to groups , , of systems according to group using analysis of echo signal for target characterisationTarget signatureTarget cross-section
G01S 13/04 - Systems determining presence of a target
G01S 13/536 - Discriminating between fixed and moving objects or between objects moving at different speeds using transmission of continuous unmodulated waves, amplitude-, frequency-, or phase-modulated waves
G01S 13/56 - Discriminating between fixed and moving objects or between objects moving at different speeds for presence detection
G01S 13/931 - Radar or analogous systems, specially adapted for specific applications for anti-collision purposes of land vehicles
52.
LINEARIZATION OF DELAY DOMAIN ANALOG-TO-DIGITAL CONVERTERS
A delay-domain analog-to-digital converter (ADC) including first and second ADCs and corresponding look-up table (LUT) memories. Control logic controls the first ADC to convert a first analog level plus a first offset to a first digital value; controls the second ADC to convert the first analog level plus a second offset to a second digital value; and computes a first difference value between the first and second digital values. The control logic further controls the first ADC to convert the first analog level minus the first offset to a third digital value; controls the second ADC to convert the first analog level plus the second offset to a fourth digital value; computes a second difference value between the third and fourth digital values; and adjusts a correction value for the first analog level in the LUT memory based on a third difference between the first and second difference values.
H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
H03M 1/06 - Continuously compensating for, or preventing, undesired influence of physical parameters
53.
POWER AMPLIFIER CASCODE BIAS GENERATION USING OUTPUT BIAS VOLTAGE
Embodiments disclosed herein relate to power amplifiers and topology design thereof. In an example, a circuit includes a power amplifier (PA), a voltage divider, and a bias voltage generator circuit. The PA includes a first transistor coupled to receive a first input signal, a second transistor coupled to receive a second input signal, a third transistor coupled to the first transistor and coupled to the bias voltage generator circuit, and a fourth transistor coupled to the second transistor, the bias voltage generator circuit, and the third transistor. The voltage divider includes a first resistor and a second resistor. The first resistor is coupled to the third transistor of the PA. The second resistor is coupled to the fourth transistor of the PA. The first resistor and the second resistor are coupled to each other and coupled to the bias voltage generator circuit.
A semiconductor device comprising a semiconductor substrate having a first cut side and an opposite second cut side, a circuit formed in or over the semiconductor substrate between the first and second cut sides, and a first scribelane portion between the circuit and the first cut side and a second scribelane portion between the circuit and the second cut side, the first scribelane portion including conductive scribelane structures, and the second scribelane portion being devoid of conductive scribelane structures.
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 23/00 - Details of semiconductor or other solid state devices
A test system includes a test instrument with a signal terminal, a splitter having a splitter input connected to the signal terminal and multiple splitter outputs, multiple test channels, each including a socket with a socket terminal connected to a respective one of the splitter outputs to couple a transceiver terminal of an installed electronic device under test (DUT) to the respective splitter output, and a controller configured to operate the test instrument to concurrently test transceiver circuits of the installed DUTs at respective unique subcarriers of an OFDM signal at the signal terminal.
In a described example, an apparatus can include a multi-layer substrate and a capacitor device. The multi-layer substrate has a first surface and a second surface. The capacitor device is on the second surface of the multi-layer substrate. The capacitor device can include a conductive substrate layer, a dielectric layer, a first capacitor terminal, and a second capacitor terminal. The conductive substrate layer can include a first set of fingers and a second set of fingers. The first set of fingers is interdigitated with the second set of fingers. The dielectric layer is between the first and second set of fingers. The first capacitor terminal is coupled to the first set of fingers. The second capacitor terminal is coupled to the second set of fingers.
Methods, apparatus, systems, and articles of manufacture are described to correct non-linearity in transmitters. An example system includes an input stage, a driver, an input terminal of the driver coupled to an output terminal of the input stage; an output buffer, an input terminal of the output buffer coupled to an output terminal of the driver, an output terminal of the output terminal coupled to a first input terminal of the input stage via a resistor; and non-linear correction circuitry having an input terminal and an output terminal, the input terminal of the non-linear correction circuitry coupled to the output terminal of the output buffer and the first input terminal of the input stage via the resistor, the output terminal of the non-linear correction circuitry coupled to the output terminal of the input stage and the input terminal of the driver.
H03K 3/01 - Circuits for generating electric pulsesMonostable, bistable or multistable circuits Details
A61B 8/00 - Diagnosis using ultrasonic, sonic or infrasonic waves
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
58.
METHODS AND APPARATUS TO REDUCE INTERFERENCE ASSOCIATED WITH A CHARGE PUMP
Methods, apparatus, and systems are described to facilitate phase detection for data clock synchronization. An example apparatus includes a charge pump having a first capacitor, a second capacitor, and a terminal; and clamping circuitry having a terminal, the terminal of the clamping circuitry coupled to the first capacitor via the terminal and the second capacitor via the terminal.
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
H02M 1/32 - Means for protecting converters other than by automatic disconnection
H02M 1/44 - Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
The first example is related to a device including a die attach pad and a die. The die attach pad has a surface region. The die includes a base surface that fits within the surface region of the die attach pad. The die also includes a top surface opposite the base surface. The top surface is larger than the base surface.
In examples, a semiconductor package includes a copper lead having top and bottom surfaces, an end surface, and first and second lateral surfaces orthogonal to the top, bottom, and end surfaces. The end surface, the top surface, and the bottom surface are plated with another metal, a first portion of the first lateral surface distal to a mold compound and proximal to the end surface is plated with the another metal, a second portion of the first lateral surface distal to the mold compound and proximal to the first portion of the first lateral surface is not plated with the another metal, a first portion of the second lateral surface distal to the mold compound and proximal to the end surface is plated with the another metal, and a second portion of the second lateral surface distal to the mold compound and proximal to the first portion of the second lateral surface is not plated with the another metal.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
Integrated devices having a coaxial structure are described. In one example, an integrated device includes a package substrate and a first coaxial structure. The package substrate includes an integrated die and a signal launch configured to emit or receive a signal. The first coaxial structure is arranged partially on a surface of the package substrate. The first coaxial structure includes an inner coaxial conductor electrically coupled to the signal launch and an outer coaxial conductor comprising an array of grounded conductors arranged to at least partially surround the inner coaxial conductor. The first coaxial structure is adapted to be coupled to a second coaxial structure of a PCB via the surface of the package substrate.
A semiconductor package includes a lead having an exterior surface portion, at an exterior of the semiconductor package, and an encapsulated surface portion contacting an encapsulation material. A solderable metal layer is on the exterior surface portion. The lead has a higher surface roughness at the encapsulated surface portion than at the exterior surface portion. Before the solderable metal layer is formed, polymer material of the encapsulation material may extend onto the exterior surface portion. A first portion of the polymer material on the exterior surface portion is removed, exposing areas of the lead. Metal from the lead, where exposed by a remaining portion of the polymer material, is removed by an electrolytic process. The lead is biased to a positive potential with respect to an electrolytic solution. Subsequently, the remaining portion of the polymer material is removed. The solderable metal layer is formed on the exterior surface portion.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
Various embodiments of the present disclosure relate to optimizing the execution of a transformer network, and in particular, to optimizing the execution of non-linear operations within the transformer network. In one example embodiment, a technique for executing a transformer network within the context of an encoder is provided. The technique first includes generating embedding data based on sensor data, and generating key data, query data, and value data based on the embedding data. Next the technique includes producing a first result by performing a first matrix multiplication operation with respect to the key data and transpose-read query data. Next, the technique includes performing a SoftMax operation on the first result to produce a second result, and transpose-writing the second result to memory. Finally, the technique includes producing a third result by performing a second matrix multiplication operation with respect to the value data and transpose-written second result.
Various embodiments of the present disclosure relate to converting sensor data from a first perspective to a second perspective, and in particular, to improving the efficiency of mapping feature data from a first perspective to a second perspective within the context of a neural network. In one example embodiment, a technique for mapping sensor data from a first perspective to a second perspective is provided. The technique first includes processing sensor data to produce a first set of feature maps associated with a first perspective. Next, the technique includes transposing the first set of feature maps to produce a first set of transposed feature maps. Once transposed, the technique includes transforming the first set of transposed feature maps into a second set of feature maps associated with a second perspective. Finally, the technique includes transposing the second set of feature maps to produce a second set of transposed feature maps.
An example method includes: computing a difference metric between first sensed data and second sensed data, wherein the first sensed data is associated with a first region in a field of view of a sensor, and wherein second sensed data is associated with a second region in the field of view; determining that the first sensed data is distinguishable from the second sensed data using the difference metric; and detecting occupancy in the first region in response to determining that the first sensed data is distinguishable from the second sensed data.
G01S 13/56 - Discriminating between fixed and moving objects or between objects moving at different speeds for presence detection
B60N 2/00 - Seats specially adapted for vehiclesArrangement or mounting of seats in vehicles
G01S 7/41 - Details of systems according to groups , , of systems according to group using analysis of echo signal for target characterisationTarget signatureTarget cross-section
An integrated circuit includes a memory cell that includes a first and second cross-coupled inverters, an output of the first inverter connected to an input of the second inverter, and an output of the second inverter connected to an input of the first inverter. A resistor and a first switch are between a power rail and a power terminal of the first inverter, a fuse and a second switch are between the power rail and a power terminal of the second inverter. The first and second switches are configured to conduct during a first phase of a control signal. A third switch is between the output of the first inverter and a reference rail and a fourth switch is between the output of the second inverter and the reference rail. The third and fourth switches are configured to conduct during a second phase of the control signal.
G11C 17/18 - Auxiliary circuits, e.g. for writing into memory
G11C 17/16 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
H10B 20/25 - One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
67.
Analytics-Driven Summary Views for Surveillance Networks
A method of displaying surveillance video streams is provided that includes receiving surveillance video streams generated by a plurality of video cameras, and displaying a selected subset of the surveillance video streams in a summary view on at least one display device, wherein, for each surveillance video stream in the summary view, only a relevant portion of each frame in the surveillance video stream is displayed, and wherein a relevant portion is a subset of a frame for at least some of the surveillance video streams in the summary view.
H04N 21/218 - Source of audio or video content, e.g. local disk arrays
H04N 21/44 - Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream or rendering scenes according to encoded video stream scene graphs
H04N 21/8549 - Creating video summaries, e.g. movie trailer
A method for compiling and executing a nested loop includes initializing a nested loop controller with an outer loop count value and an inner loop count value. The nested loop controller includes a predicate FIFO. The method also includes coalescing the nested loop and, during execution of the coalesced nested loop, causing the nested loop controller to populate the predicate FIFO and executing a get predicate instruction having an offset value, where the get predicate returns a value from the predicate FIFO specified by the offset value. The method further includes predicating an outer loop instruction on the returned value from the predicate FIFO.
G06F 5/06 - Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
69.
METHOD OF REDUCING INTEGRATED DEEP TRENCH OPTICALLY SENSITIVE DEFECTIVITY
A microelectronic device includes an integrated deep trench in a substrate, with a field oxide layer on the substrate. The integrated deep trench includes a of deep trench extending into semiconductor material of the substrate, a deep trench sidewall dielectric layer contacting the substrate and an electrically conductive trench-fill material contacting the deep trench sidewall dielectric layer. The conductive trench-fill material is covered during the formation of the field oxide layer to minimize the trench-fill seam void volume. Minimizing the trench-fill seam void volume minimizes optical defectivity observed in subsequent yield enhancement. The integrated deep trench may be configured as a capacitor or may be configured as a contact to the underlying substrate.
An electronic device and method are provided. The method includes providing an array of electronic devices having leadframes where the leadframes include at least one depopulated lead and external leads interconnected by a first dambar, a second dambar, and a connection assembly. The connection assembly connects the first dambar to a first external lead of a first leadframe and to a second external lead of a second adjacent leadframe. A first punch process is performed to remove the first dambar and the second dambar from the leadframes. A second punch process is performed to create a cut in the connection assembly proximate the first external lead adjacent to the at least one depopulated lead to disconnect the connection assembly from the first external lead. A trimming process is performed to trim external leads of the leadframes to their required length while simultaneously removing the connection assembly.
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
A circuit (100) can include a first switch (102) and a second switch (104). The first switch (122) has first and second current terminals and a first control terminal (112), in which the first or second current terminal is coupled to a switch output (114). The second switch (104) has third and fourth current terminals and a second control terminal (120), in which the second control terminal (120) is coupled to the first control terminal (112), and the fourth current terminal is coupled to the switch output (114). A switch network (106) is coupled between the first switch (102) and the second switch (104).
A delay-domain anal og-to-digi tai converter (ADC) (200) including first and second ADCs (240, 241) and corresponding look-up table (LUT) memories (250, 251), and calibration method for the same. Control logic controls the first ADC (240) to convert (402) a first analog level plus a first offset to a first digital value; controls the second ADC (241) to convert the first analog level plus a second offset to a second digital value; and computes a first difference value between the first and second digital values. The control logic is further controls the first ADC to convert the first analog level minus the first offset to a third digital value; controls the second ADC to convert the first analog level plus the second offset to a fourth digital value; computes a second difference value between the third and fourth digital values; and adjusts a correction value associated with the first analog level in the LUT memory (250) based on a third difference between the first and second difference values.
The present disclosure generally relates to semiconductor devices in an integrated circuit (IC) that have different threshold voltages. In an example, an IC includes a semiconductor substrate, a channel layer, a barrier layer, a first semiconductor device, and a second semiconductor device. The channel layer is on the semiconductor substrate, and the channel layer includes a gallium nitride (GaN) material. The barrier layer is on the channel layer. The first semiconductor device is on the semiconductor substrate. The first semiconductor device includes a first terminal over the barrier layer, and the first semiconductor device has a first threshold voltage. The second semiconductor device is on the semiconductor substrate. The second semiconductor device includes a second terminal over the barrier layer, and the second semiconductor device has a second threshold voltage different from the first threshold voltage. The first and second threshold voltages are both positive or negative voltages.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
The present disclosure generally relates to semiconductor devices in an integrated circuit (IC) that have different threshold voltages. In an example, a channel layer is formed on a semiconductor substrate. The channel layer includes a gallium nitride (GaN) material. A barrier layer is formed on the channel layer. A first semiconductor device is formed on the semiconductor substrate. The first semiconductor device includes a first terminal over the barrier layer, and the first semiconductor device has a first threshold voltage. A second semiconductor device is formed on the semiconductor substrate. The second semiconductor device includes a second terminal over the barrier layer, and the second semiconductor device has a second threshold voltage different from the first threshold voltage. The first and second threshold voltages are both positive or negative voltages.
H01L 27/085 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
An example apparatus includes a substrate having opposing first and second surfaces. The apparatus also includes an on-substrate device on the first surface of the substrate and a wafer cap on the first surface of the substrate over the on-substrate device. A peripheral ring layer of a fusible alloy is configured to hermetically seal the wafer cap to the first surface of the substrate around the on-substrate device.
H01L 23/10 - ContainersSeals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
A method includes receiving a feedback signal associated with a multi-level converter circuit. The multi-level converter circuit includes a two-level converter circuit and a higher-level converter circuit. The higher-level converter circuit increases a number of levels associated with the multi-level converter circuit to more than two levels provided by the two-level converter circuit. The method also includes generating at least one control signal for controlling at least one switch of the two-level converter circuit based on the feedback signal. The method further includes generating at least another control signal for controlling at least another switch of the higher-level converter circuit based on the feedback signal.
H02M 7/483 - Converters with outputs that each can have more than two voltage levels
H02M 7/5395 - Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency by pulse-width modulation
77.
PHOTOLITHOGRAPHIC MASKS AND DEVICES FABRICATED THEREFROM
Mask devices for photolithography used in semiconductor and other device fabrication are described. For example, a mask device includes a light-passing substrate and a patterned opaque layer disposed on the light-passing substrate. The patterned opaque layer includes a light-modulating region with elongate features consecutively disposed at increasing distances from one another.
An apparatus includes a transmitter, a voltage regulator, an isolator, and a test controller. The transmitter has an input, an output, and a first supply voltage terminal. The input couples to the apparatus' input terminal. The voltage regulator's input couples to a second supply voltage terminal. The voltage regulator's output couples to the first supply terminal. The first terminal of the isolator couples to the output of the transmitter. A first test controller terminal couples to the second supply voltage terminal. A second test controller terminal couples to the input terminal of the apparatus. The first control output couples to the control input of the voltage regulator. The test controller changes a logic state of a control signal at the first control output from a first logic state to a second logic state.
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
79.
INTEGRATED MAGNETIC COMPONENT IN ELECTRONIC APPARATUS
An apparatus includes a packaged electronic device having a first terminal, a coil having a second terminal that is spaced apart from the first terminal, and a magnetic structure that encloses portions of the packaged electronic device and the coil and exposes respective portions of the first and second terminals. A method of manufacturing an electronic apparatus includes attaching a first terminal of a packaged electronic device to a carrier, attaching a second terminal of a coil to the carrier, performing a molding process using a magnetic molding compound to form a molded magnetic structure that encloses portions of the packaged electronic device and the coil, and removing the carrier to expose portions of the first and second terminals.
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H02M 3/00 - Conversion of DC power input into DC power output
H02M 3/155 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
An example circuit includes an input divider network, a threshold generator, and a comparator. The input divider network has a first divider input, a second divider input, a first threshold input, a second threshold input, a first divider output, and a second divider output, in which the second divider input is coupled to a signal ground terminal. The threshold generator has first and second threshold outputs and a selection input, in which the first threshold output is coupled to the first threshold input and the second threshold output is coupled to the second threshold input. The comparator has first and second comparator inputs and a comparator output, in which the first comparator input is coupled to first divider output, the second comparator input is coupled to the second divider output, and the comparator output is coupled to the selection input.
In an example embodiment, a device includes an address protocol controller configured to receive an access request that includes an address associated with an external memory, and an external memory interface controller coupled to the address protocol controller and configured to couple to the external memory. The address protocol controller is configured to determine, based on a type of the external memory device, whether to generate a modified address associated with the address in the access request. Based on the external memory device being a first type, the address protocol controller is configured to provide the address to the external memory. Based on the external memory being a second type, the address protocol controller is configured to generate the modified address and provide the modified address to the external memory interface controller to access the external memory.
An apparatus includes an integrated circuit comprising a power stage having a control input and a voltage output terminal, and a controller that has a feedback voltage input, an error signal input, and a control output. The control output is coupled to the control input of the power stage. The controller is configurable to provide a modulated signal at the control output responsive to a first signal at the feedback voltage input and a second signal at the error signal input. The second signal includes an integral of a difference between the first signal and a reference signal. In some examples, the second signal is generated by an integral controller and is used by multiple integrated circuits to control multiple power stages in a multiphase power converter.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
Described examples include a process that includes illuminating a spatial light modulator at a first illumination level during a first bit-plane and stopping illumination at a beginning of a second bit-plane subsequent to the first bit-plane. The process also includes resuming illumination after a settling period of the spatial light modulator at a second illumination level for a time period such that a total illumination energy during the second bit-plane is equivalent to an intended illumination energy for the second bit-plane at the first illumination level and stopping illumination at the second illumination level before a subsequent third bit-plane.
G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
G09G 3/34 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source
84.
MULTICHANNEL MEMORY ARBITRATION AND INTERLEAVING SCHEME
Arbitration and interleaving are performed with respect to requests received through input ports, from respective requestors. An example controller is caused to determine, for each request, a pathway to a channel, among a set of channels. Such determination includes to: place each request in a channel queue of a set of channel queues associated with the requestor from which the request was received, the channel queue in which the request is placed being associated with a specific channel of the set of channels; for each request for presentation to an interface, select an arbitration algorithm among multiple arbitration algorithms to determine which channel queues participate in a first arbitration, and obtain the request from a participating channel queue; and present each request obtained through the first arbitration to an interface coupled to the set of channels for participation in a second arbitration.
A system and method for enhanced channel hopping sequence is described. A pseudo random channel hopping sequence is redistributed using certain system specific parameters for separating adjacent transmission channels within a predetermined number of consecutive transmission channel numbers in the random channel hopping sequence to improve inter-channel interference between adjacent transmission channels.
Described examples include a method having steps of laying out at least two conductors and modeling conductor current through the at least two conductors to determine a current density in the at least two conductors. The method also has steps of revising the at least two conductors as adjusted conductors to add conductive material to areas of the conductor where the modeling conductor current shows above average current density; fabricating the adjusted conductors; and mounting a die to the adjusted conductors.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
An apparatus (800 or 804 only) includes an integrated circuit comprising a power stage (834) having a control input (input to power stage 834) and a voltage output terminal (output of power stage 834), and a controller (830 and 832) that has a feedback voltage input, an error signal input, and a control output of PWM signal generator (32). The control output is coupled to the control input of the power stage. The controller is configurable to provide a modulated signal at the control output responsive to a first signal (VFB) at the feedback voltage input and a second signal (DC loop control signal Verror) at the error signal input. The second signal includes an integral of a difference between the first signal and a reference signal (VREF). In some examples, the second signal is generated by an integral controller (814) and is used by multiple integrated circuits (804, 806, and 808) to control multiple power stages in a multiphase power converter (800).
H02M 3/157 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
88.
DIRECT MEMORY ACCESS CONTROLLER FOR DETECTING TRANSIENT FAULTS
Various embodiments of the present disclosure relate to managing transient faults within storage elements, and in particular, to maintaining the integrity of data stored in memory (109). In one example embodiment, a technique for performing a data integrity process (200) is provided. The technique first includes accessing address data stored in a first location (111) in memory (109) such that the address data is indicative of a second location (113) in memory (109). The technique then includes accessing data stored in the second location (113) in memory (109) and generating a data integrity value based on the accessed data. Once generated, the technique includes performing a comparison between the data integrity value and a reference value associated with the accessed data. If the comparison shows the data integrity value matches the reference value, then the technique includes outputting a positive indication. Else, the technique includes outputting a negative indication.
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
89.
METHODS, SYSTEMS, AND APPARATUS TO IMPROVE SIMULATIONS OF GATE LEVEL NETLISTS
Systems, apparatus, articles of manufacture, and methods are disclosed to improve simulations of gate level netlists. An example apparatus includes interface circuitry to obtain register transfer level code indicative of an operation of an integrated circuit, machine-readable instructions, and programmable circuitry to at least one of instantiate or execute the machine-readable instructions to obtain a gate level netlist corresponding to the integrated circuit, the gate level netlist including modules in the integrated circuit and connections between the modules, obtain a first probe, the first probe representing a first location within the gate level netlist at which to monitor behavior, identify a root module that includes an output configured to determine a signal at the first location, and generate a second probe to replace the first probe representing a second location within the gate level netlist closer to the output of the root module than the first probe.
The present disclosure generally relates to semiconductor processing for a bipolar junction transistor (BJT). In an example, a semiconductor device includes a semiconductor substrate and a bipolar junction transistor on the semiconductor substrate. The bipolar junction transistor includes a collector layer on the semiconductor substrate, a base layer on the collector layer, a raised base layer on the base layer, a dielectric spacer on the base layer and along a sidewall of the raised base layer, and an emitter layer on the base layer. The dielectric spacer is laterally between the raised base layer and the emitter layer. The emitter layer extends over the dielectric spacer and at least partially over the raised base layer. The raised base layer has a substantially continuous upper surface from a distance away from the emitter layer to the dielectric spacer underlying the emitter layer.
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
An example apparatus includes: buffer circuitry including: a first transistor having a first terminal, a second terminal, and a control terminal; and a second transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the second transistor coupled to the first terminal of the first transistor, the control terminal of the second transistor coupled to the control terminal of the first transistor; output stage circuitry including: gate biasing circuitry having a terminal; a third transistor having a first terminal and a control terminal, the control terminal of the third transistor coupled to the second terminal of the second transistor and the terminal of the gate biasing circuitry; current mirror circuitry having an input and an output, the input of the current mirror circuitry coupled to the second terminal of the first transistor.
A method is described herein. The method generally includes fetching a set of data from a memory coupled to a memory controller. The method generally includes determining a first subset of data from the set of data. The method generally includes determining a second subset of data from the set of data. The method generally includes determining a first element from the set of data. The method generally includes providing a vector including the first subset, the first element, and the second subset, wherein each element of the first subset is disposed in one portion of the vector and each element of the second subset is disposed in another portion of the vector. The method generally includes storing the vector into a register of the memory controller.
A controller for a voltage converter, such as a buck converter, includes: a switching regulator circuit having high side and low side switches; comparators configured to compare a voltage of an output circuit to reference voltages; and a control circuit coupled to the current comparators, configured to receive outputs from the comparators, and configured to generate a control signal for alternatingly switching the high side and low side switches off and on, such that the low side switch is off when the high side switch is on, and the high side switch is off when the low side switch is on, and wherein the control circuit includes a latching circuit configured to latch a signal corresponding to at least one of the outputs from the comparators. A method of operating a buck converter in connection with a fixed high-frequency automotive radar system, with reliable over-current detection, is also disclosed.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
Described embodiments include a circuit with a first amplifier having first and second amplifier inputs and a first amplifier output. The first amplifier input is coupled to a reference voltage terminal. The second amplifier input is coupled to a voltage feedback terminal. A second amplifier has third and fourth amplifier inputs and second and third amplifier outputs. The third amplifier input is coupled to the first amplifier output. A first switch has first and second switch terminals. The second switch terminal is coupled to the fourth amplifier input. A third amplifier has fifth and sixth amplifier inputs and a fourth amplifier output. The fifth amplifier input is coupled to the second amplifier output. The sixth amplifier input is coupled to the third amplifier output. A second switch has a third switch terminal coupled to the fourth amplifier output, and a fourth switch terminal coupled to the first amplifier output.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
95.
METHODS AND APPARATUS TO DETECT AND DIAGNOSE FAULTS IN BUCK REGULATORS
An example apparatus includes: a phase circuit configured to receive a pulse of a pulse width module (PWM) signal; provide, after receiving the pulse, an output voltage to a load; exhibit a fault; in response to the fault corresponding to a first category, transmit a first code voltage in a current sense (CS) signal; in response to the fault corresponding to a second category, transmit a reference voltage in the CS signal; receive, after transmission of the reference voltage, a tristate voltage in the PWM signal; and transmit, after receiving the tristate voltage, a second code voltage in the CS signal based on a type of the fault and the second category.
The techniques and circuits, described herein, include solutions for pass-through operation including overcurrent protection in buck-boost converters. In some aspects, first and second switches selectively couple inputs of a peak current comparator to inputs of an error amplifier during pass-through operation. As part of peak current control scheme, one of the peak current comparator inputs is coupled to a current sensor that senses a current through an inductor of the buck-boost converter. As a result, an output of the error amplifier tracks the inductor current during pass-through mode, which may be utilized to implement inductor overcurrent protection in the pass-through mode.
H02M 3/157 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
97.
TEMPERATURE ESTIMATION USING ELECTROCHEMICAL IMPEDANCE SPECTROSCOPY
A temperature estimation apparatus includes a measurement circuit and a temperature estimation circuit. The measurement circuit is configured to acquire a voltage measurement and a current measurement. The voltage measurement and the current measurement include a frequency component. The temperature estimation circuit is coupled to the measurement circuit. The temperature estimation circuit is configured to estimate an impedance based on the voltage measurement and the current measurement, and estimate a temperature based on a feature vector including at least two features of the impedance.
G01R 31/3842 - Arrangements for monitoring battery or accumulator variables, e.g. SoC combining voltage and current measurements
G01R 31/367 - Software therefor, e.g. for battery testing using modelling or look-up tables
H01M 10/48 - Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte
98.
METHODS AND APPARATUS TO ENABLE STATUS CHANGE DETECTION IN A LOW POWER MODE OF A MICROCONTROLLER UNIT
Methods, apparatus, systems, and articles of manufacture to enable status change detection in a low power mode of a microcontroller unit are disclosed herein. An example integrated circuit (IC) includes a controller to determine that the IC is to enter a low power mode. The example IC includes a universal serial bus (USB) physical layer integrated circuit including a transceiver and a detector circuit. The transceiver is disabled while in the low power mode. The detector circuit is enabled while in the low power mode. The detector circuit is to determine whether a pinout of a USB receptacle is shorted to ground. The example IC includes a power control module (PCM) to disable the controller when entering the low power mode. Upon receipt of an indication that the ID pinout of the USB receptacle is shorted to the ground, the PCM initiates a boot sequence.
A method of forming an integrated circuit on a substrate is described herein. The method includes forming a first doped region of a detection structure on the substrate, the first doped region comprises a first doped conductivity type. The method forming a capacitor of the detection structure, which includes forming a second doped region of a second conductivity type opposite the first doped conductivity type, the second doped region surrounded by the first doped region. The second doped well comprises a top surface area smaller than a top surface area of the first doped region. The method includes performing parametric testing on the capacitor over a plurality of breakdown voltages. The method includes determining the gate oxide integrity of the capacitor based on the parametric testing over the plurality of breakdown voltages.
A semiconductor package includes a semiconductor die including terminals, a plurality of leads, at least some of the leads being electrically coupled to the terminals within the semiconductor package, a sensor on a surface of the semiconductor die, a set of metal columns on the surface of the semiconductor die, the set of metal columns forming a perimeter around the sensor on the surface of the semiconductor die, and a mold compound surrounding the semiconductor die except for an area inside the perimeter on the surface of the semiconductor die such that the sensor is exposed to ambient air.
B81C 1/00 - Manufacture or treatment of devices or systems in or on a substrate
G01N 27/22 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating capacitance
