Several systems, methods and integrated circuits capable of reducing blocking artifacts in video data are disclosed. In an embodiment, a system for reducing blocking artifacts in video data includes a processing module and a deblocking module. The deblocking module comprises a luma deblocking filter and a chroma deblocking filter configured to filter an edge between adjacent blocks associated with the video data, where a block of the adjacent blocks corresponds to one of a prediction block and a transform block. The processing module is communicatively associated with the deblocking module and is operable to configure at least one filter coefficient corresponding to the chroma deblocking filter based on one or more filter coefficients corresponding to the luma deblocking filter. The processing module is further configured to cause the chroma deblocking filter to filter the edge between the adjacent blocks based on the configured at least one filter coefficient.
H04N 19/86 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression involving reduction of coding artifacts, e.g. of blockiness
H04N 19/117 - Filters, e.g. for pre-processing or post-processing
H04N 19/134 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or criterion affecting or controlling the adaptive coding
H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
H04N 19/186 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a colour or a chrominance component
2.
IN-LINE CHROMATIC ABERRATION CORRECTION IN WIDE DYNAMIC RANGE (WDR) IMAGE PROCESSING PIPELINE
In an advanced driver-assistance system (ADAS), RAW sensor image processing for a machine vision (MV) application is important. Due to different color, e.g., red/green/blue (RGB), color components, being focused by the lens at different locations in image plane, the lateral chromatic aberration phenomenon may sometimes be observed, which causes false color around edges in the final image output, especially for high contrast edges, which can impede MV applications. Disclosed herein are low-latency, efficient, optimized designs for chromatic aberration correction (CAC) components. An in-pipeline CAC design may be used to perform on-the-fly CAC without any out-of-pipeline memory traffic; enable use of wide dynamic range (WDR) sensors; uses bicubic interpolation; support vertical and horizontal chromatic aberration color channel offsets, reduce CAC line memory requirements, and support flexible look-up table (LUT) down-sampling factors to improve the spatial precision of correction and accommodate popular image sensor resolutions.
A circuit includes a first processor core, a second processor core, and a video processing circuit. The first processor core is configured to program the video processing circuit to: provide a rear view image processing path, and to transfer a rear view image from the rear view image processing path to a surround view image processing path. The second processor core is configured to program the video processing circuit to provide the surround view image processing path, to receive the rear view image from the rear view image processing path, and to provide a surround view image based on the rear view image.
An electronic device with a non-volatile memory includes a non-volatile memory (NVM) cell selectively programmable to change a program state from a first state to a second state or to a third state, and may also include a write circuit configured to selectively program the NVM cell to change the program state from the first state to the second state by applying a programming voltage signal to a first source/drain region and to change the program state from the first state to the third state by applying the programming voltage signal to a second source/drain region. A read circuit is configured to identify the program state of the NVM memory cell as one of the first state, the second state, and the third state based on a cell voltage of the non-volatile memory cell.
H10B 20/25 - One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
G11C 17/16 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
G11C 17/18 - Auxiliary circuits, e.g. for writing into memory
5.
OSCILLATOR FREQUENCY BASED ON MOBILITY AND PTAT TEMPERATURE COMPENSATION
In an example, a system includes a first transistor having a first terminal coupled to a current mirror and a control terminal coupled to a first current source and a resistor. The system includes a second transistor having a first terminal coupled to the current mirror, a second terminal coupled to a second terminal of the first transistor, and a control terminal coupled to the resistor and a second current source. The system includes a third transistor having a first terminal coupled to a voltage terminal, a second terminal coupled to the control terminal of the second transistor, and a control terminal coupled to the first terminal of the second transistor. The system includes a fourth transistor having a control terminal coupled to the current mirror, first and second terminals coupled to one another and to the second terminal of the first transistor.
An electronic circuit includes an oscillator circuit, a first divider circuit, a synchronization control circuit, and a peripheral circuit. The oscillator circuit is configured to generate a base frequency clock. The first divider circuit is configured to divide the base frequency clock by a first selectable divisor to generate a divided clock. The synchronization control circuit is configured to generate a synchronization pulse that controls a change of the first selectable divisor in the first divider circuit from a first value to a second value. A pulse width of the synchronization pulse is based on the first value of the first selectable divisor. The peripheral circuit is coupled to the first divider circuit and the synchronization control circuit. The peripheral circuit includes a second divider circuit. The second divider circuit divides the divided clock by a second selectable divisor, and change the second selectable divisor responsive to the synchronization pulse.
An apparatus includes a first transistor having a first transistor control terminal and coupled between a power terminal and a switching terminal. The apparatus further includes a second transistor having a second transistor control terminal and coupled between the switching terminal and a ground terminal. The apparatus further includes a first switch coupled between the power terminal and the second transistor control terminal, the first switch having a first switch control terminal; The apparatus further includes a second switch coupled between the second control terminal and the ground terminal, the second switch having a second switch control terminal. The apparatus also includes a controller having a control input, a first control output, and a second control output, the control input coupled to the second transistor control terminal, the first control output coupled to the first switch control terminal, and the second control output coupled to the second switch control terminal.
A circuit includes an anisotropic magnetoresistance (AMR) sensor; an operational amplifier; and a calibration circuit. The AMR sensor has a first terminal, a second terminal, a third terminal, and a fourth terminal. The operational amplifier has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first terminal of the operational amplifier is coupled to the second terminal of the AMR sensor. The second terminal of the operational amplifier is coupled to the third terminal of the AMR sensor. The calibration circuit is coupled to the first terminal of the operational amplifier. The calibration circuit is configured to provide an adjustable offset trim voltage at the first terminal of the operational amplifier to cancel out an offset voltage generated by the AMR sensor.
G01R 35/00 - Testing or calibrating of apparatus covered by the other groups of this subclass
G01D 5/244 - Mechanical means for transferring the output of a sensing memberMeans for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for convertingTransducers not specially adapted for a specific variable using electric or magnetic means influencing characteristics of pulses or pulse trainsMechanical means for transferring the output of a sensing memberMeans for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for convertingTransducers not specially adapted for a specific variable using electric or magnetic means generating pulses or pulse trains
G01D 5/245 - Mechanical means for transferring the output of a sensing memberMeans for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for convertingTransducers not specially adapted for a specific variable using electric or magnetic means influencing characteristics of pulses or pulse trainsMechanical means for transferring the output of a sensing memberMeans for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for convertingTransducers not specially adapted for a specific variable using electric or magnetic means generating pulses or pulse trains using a variable number of pulses in a train
In examples, a sensing device comprises a semiconductor die including a device side and a fluid sensor in the device side. The device comprises a metal ring forming an opening over the fluid sensor, the metal ring having a top surface, a bottom surface, and an inner surface extending between the top surface and the bottom surface, and the bottom surface being on the device side. At least a portion of the inner surface abuts the device side being plated with a noble metal. The device includes a mold compound covering the semiconductor die and a first portion of the metal ring, in which a second portion of the metal ring having the top surface protrudes out of the mold compound and provides at least one of a cartridge interface or a tube interface.
G01F 1/64 - Measuring the volume flow or mass flow of fluid or fluent solid material wherein the fluid passes through a meter in a continuous flow by using electric or magnetic effects by measuring electrical currents passing through the fluid flowMeasuring the volume flow or mass flow of fluid or fluent solid material wherein the fluid passes through a meter in a continuous flow by using electric or magnetic effects by measuring electrical potential generated by the fluid flow, e.g. by electrochemical, contact, or friction effects
G01F 1/002 - Measuring the volume flow or mass flow of fluid or fluent solid material wherein the fluid passes through a meter in a continuous flow wherein the flow is in an open channel
10.
INTEGRATED CIRCUIT WITH INDUCTOR IN MAGNETIC PACKAGE
A packaged integrated circuit (IC) includes a package substrate, an electronic device on the package substrate, and metal interconnects coupled between the electronic device and the package substrate. The packaged IC also includes an insulation material on the package substrate and encapsulating the electronic device. The insulation material surrounds the metal interconnects. An inductor is over the electronic device and is coupled to the package substrate. A magnetic material is on the insulation material and encapsulates the inductor. The magnetic material is different from the insulation material.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
Described embodiments include a voltage clamping circuit having a threshold-setting circuit with a threshold input and a threshold output. A switch has a first terminal coupled to the threshold input, a second switch terminal, and a switch control terminal. A first transistor is coupled between the threshold output and the switch control terminal, and has a first control terminal. A second transistor is coupled between the first control terminal and ground, and has a second control terminal. A first driver circuit has a first driver input and a first driver output. A second driver circuit has a second driver input coupled to the first driver input, and a second driver output. A third transistor is coupled between the threshold input and ground, and has a third control terminal that is coupled to the second control terminal and the second switch terminal.
H03K 17/082 - Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
H02M 1/14 - Arrangements for reducing ripples from DC input or output
H02M 3/156 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
12.
WAFER-LEVEL FABRICATION OF ELECTROSTATIC DISCHARGE DEVICES
In examples, a package comprises first and second dies including first and second diodes, respectively. The package comprises first and second metal contacts coupled to bottom surfaces of the first and second dies, respectively, with the first and second metal contacts exposed to a bottom surface of the package. The package also comprises an isolation layer between the first and second dies and between the first and second metal contacts and a metal layer coupled to top surfaces of the first and second dies. The package also comprises a mold compound covering the first and second dies and the metal layer.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/60 - Protection against electrostatic charges or discharges, e.g. Faraday shields
13.
CONCURRENT USE OF MULTIPLE PROTOCOLS ON A SINGLE RADIO
A method for concurrent execution of multiple protocols using a single radio of a wireless communication device is provided that includes receiving, in a radio command scheduler, a first radio command from a first protocol stack of a plurality of protocol states executing on the wireless communication device, determining a scheduling policy for the first radio command based on a current state of each protocol stack of the plurality of protocol stacks, and scheduling the first radio command in a radio command queue for the radio based on the scheduling policy, wherein the radio command scheduler uses the radio command queue to schedule radio commands received from the plurality of protocol stacks.
H04L 47/6275 - Queue scheduling characterised by scheduling criteria for service slots or service orders based on priority
H04L 69/18 - Multiprotocol handlers, e.g. single devices capable of handling multiple protocols
H04W 4/80 - Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
H04W 72/0446 - Resources in time domain, e.g. slots or frames
H04W 72/1263 - Mapping of traffic onto schedule, e.g. scheduled allocation or multiplexing of flows
H04W 72/566 - Allocation or scheduling criteria for wireless resources based on priority criteria of the information or information source or recipient
In one example, an audio device includes a substrate, a first piezoelectric flap, a second piezoelectric flap, a transmit circuit, a first receive circuit, a switch circuit, and a second receive circuit. The substrate has an opening. The first piezoelectric flap has a first end on the substrate and extending over the opening, the first piezoelectric flap having first and second terminals. The second piezoelectric flap has a second end on the substrate and extending over the opening, the second piezoelectric flap spaced from the first piezoelectric flap, the second piezoelectric flap having third and fourth terminals. The transmit circuit has driver outputs. The first receive circuit has first receiver inputs. The switch circuit coupled to the driver outputs and the first receiver inputs, and the first and second terminals. The second receive circuit has second receiver inputs coupled to the third and fourth terminals.
Embodiments disclosed herein relate to impedance matching for outputting wide-band signals in radio frequency applications. In an example, a circuit including a low-noise amplifier (LNA) sub-circuit and a tuning sub-circuit is provided. The LNA sub-circuit is configured to couple to an antenna and includes a transistor that includes a gate, a source, and a drain, a first inductor that includes a first terminal configured to couple to the antenna and includes a second terminal, a second inductor that includes a first terminal coupled to the first terminal of the first inductor and includes a second terminal coupled to the gate of the transistor, and a third inductor that includes a first terminal coupled to the source of the transistor and includes a second terminal. The tuning sub-circuit is coupled to the source of the transistor.
A circuit includes a sense circuit and a comparator having a first input and a second input, the first input coupled to the sense circuit. The circuit also includes a first transistor having a control terminal and a current terminal, the current terminal coupled to the second input of the comparator and an amplifier having an input and an output, the input coupled too the control terminal of the first transistor. Additionally, the circuit includes a second transistor having a control terminal and a current terminal, the control terminal coupled to the output of the amplifier and a capacitor having a terminal coupled to the current terminal of the second transistor and to the input of the amplifier.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
In some examples, a semiconductor device comprises a substrate, a trench, and a layer of a dielectric material. The substrate includes a semiconductor material and has opposing first and second surfaces. The trench extends between the first surface and the second surface, the trench having the dielectric material. The layer of the dielectric material is on the second surface of the substrate and is contiguous with the dielectric material in the trench.
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
Described embodiments include a power driver circuit having a first transistor coupled between an input voltage terminal and an intermediate terminal, and having a first control terminal. A second transistor is coupled between the intermediate terminal and a switching terminal, and has a second control terminal coupled to an output of a gate drive circuit. A first diode has a first anode coupled to the input voltage terminal, and a first cathode coupled to the first control terminal through a resistor. A first voltage clamp circuit is coupled between the first control terminal and the intermediate terminal. A second voltage clamp circuit is coupled between the first control terminal and the switching terminal. A second diode is coupled between the first control terminal and a voltage supply terminal.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H03K 17/22 - Modifications for ensuring a predetermined initial state when the supply voltage has been applied
An electronic device includes a first semiconductor die attached to a first conductive die attach pad and having a first electronic component, a second semiconductor die attached to a second conductive die attach pad and having a second electronic component, a first package structure that encloses the first semiconductor die and a portion of the first die attach pad, a second package structure that encloses the second semiconductor die and a portion of the second die attach pad, and a conductive metal structure that is electrically connected to the first and second electronic components and extends between the first and second package structures, the conductive metal structure exposed outside the first and second package structures.
In examples, a package comprises a semiconductor die having a device side including circuitry formed therein. The package comprises a substrate facing and coupled to the device side. The substrate includes first and second metal layers. The first metal layer is positioned closer to the device side than the second metal layer and is coupled to the second metal layer by way of a via. At least one of the first and second metal layers has a top surface facing the semiconductor die. The top surface includes a notch etched therein. The substrate also includes a dielectric contacting the notch and at least part of the first and second metal layers and the via. The package includes a mold compound covering the semiconductor die and the substrate. The package includes a lateral surface approximately perpendicular to the first and second metal layers of the substrate. The mold compound, the dielectric, and the second metal layer are exposed to the lateral surface. A segment of the dielectric is positioned between the first metal layer and the lateral surface. The segment of the dielectric contacts the mold compound at the lateral surface.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
Disclosed herein are improvements to instructions and hardware for performing neural network operations. In an embodiment, a processing device includes instruction fetch circuitry, decoder circuitry, and neural network operation circuitry. The instruction fetch circuitry is configured to fetch a neural network instruction from memory that specifies an operation and a set of values that enable sub-circuits of the neural network operation circuitry for use with one or more of the operations of the group of operations and provide the neural network instruction to the decoder circuitry. The decoder circuitry is configured to cause the neural network operation circuitry to perform, based on the operation, a convolution operation using a first sub-circuit of the neural network operation circuitry and a first subset of the set of values or a batch normalization operation using a second sub-circuit of the neural network operation circuitry and a second subset of the set of values.
In examples, a semiconductor package comprises a semiconductor die having a device side in which circuitry is formed, and a conductive terminal coupled to the device side of the semiconductor die. The package also comprises a mold compound covering the semiconductor die and at least part of the conductive terminal, where the conductive terminal is exposed to an exterior of the mold compound. The mold compound has top and bottom surfaces and a lateral side extending between the top and bottom surfaces. The lateral side includes a first surface contacting the top surface and extending vertically from the top surface toward the bottom surface. The lateral side also includes a second surface contacting the first surface and extending horizontally away from the semiconductor die. The lateral side also includes a third surface contacting the second surface and extending from the second surface to contact the bottom surface. The third surface has physical marks resulting from a singulation process. The first and second surfaces lack physical marks resulting from the singulation process.
An apparatus includes an integrated circuit that includes a microprocessor and a microcontroller unit circuit (MCU) coupled to the microprocessor. The MCU includes a central processing unit (CPU) core and a network processor that implements a wireless interface. The MCU is configured to execute a location application that facilitates a determination of a physical location of the apparatus. The MCU may also be configured to support one or more management functions. The microprocessor sends data to the MCU for wireless transmission by the MCU's wireless interface.
An example apparatus includes: first through eighth gated inverters each having inputs and outputs; a first and second inverter each having an input and an output, the output of the first inverter coupled to the input of the second gated inverter, the output of the second inverter coupled to the input of the third gated inverter; the fifth gated inverter coupled to the input of the first gated inverter and the input of the first inverter; the sixth gated inverter coupled to the input of the second inverter and the input of the fourth gated inverter; the seventh gated inverter coupled to the output of the first gated inverter and the output of the third gated inverter; the eighth gated inverter coupled to the output of the second gated inverter and the output of the fourth gated inverter; and a bus-holder circuit between the seventh and eighth gated inverter inputs.
H03K 21/00 - Details of pulse counters or frequency dividers
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
25.
POWER CONVERTER CONTROLLER WITH FREQUENCY MONITORING
A circuit (130) includes a microcontroller (140) having a first terminal (142) and a second terminal (144). The microcontroller (140) is configured to: receive a signal (current/voltages) associated with operation of a power converter at the first terminal (142); adjust a switch control signal (SWITCH_CSs) at the second terminal 144 responsive to the signal; measure a frequency of the switch control signal; compare the measured frequency responsive to at least one envelope of a set of envelopes (346, 348) to obtain monitoring results; and perform control operations responsive to the monitoring results.
H02M 3/00 - Conversion of DC power input into DC power output
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
26.
BACK SIDE MOLD COMPOUND FLASH SUPRESSION TRENCH FOR EXPOSED DIE PACKAGING
A back side exposed semiconductor die package (100) with a plurality of leads (146) around a perimeter of the semiconductor die package (100), a semiconductor die (104) electrically coupled to a plurality of the leads (146), a plurality of mold compound flash suppression trenches (120) on the back side (114) of the semiconductor die (104) and a back side mold compound free zone (110) are described. The plurality of mold compound flash suppression trenches (120) on the back side (114) of the semiconductor die (104) act as a reservoir to prevent mold compound (150) from encroaching on the mold compound free zone (110) on the back side (104) of the semiconductor die (104). After formation of the semiconductor die package (100) on the lead frame, individual semiconductor die (104) are singulated, and components such as a head sink (168) may subsequently be attached to the mold compound free zone (110) of the semiconductor die (104).
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
An electronic device includes first and second semiconductor dies, the first semiconductor die having: a side extending in a first plane of orthogonal first and second directions; a sensor circuit along the side; and a conductive terminal extending outward from the side along an orthogonal third direction, and the second semiconductor die bonded to the first semiconductor die and having: a bottom side; a lateral side; and an insulation layer, the bottom side spaced apart from and facing the side of the first semiconductor die to form a protected chamber for the sensor circuit, the lateral side of the second semiconductor die spaced apart from the conductive terminal along the first direction, the insulation layer extending along the lateral side of the second semiconductor die, and the insulation layer spaced apart from and facing the conductive terminal along the first direction.
Embodiments disclosed herein relate to synchronizing signals across multiple independent clock domains. In an example, a synchronizer flip-flop circuit is provided. The synchronizer flip-flop circuit includes a first latch sub-circuit coupled to receive an input and a second latch sub-circuit coupled to the first latch sub-circuit. The first latch sub-circuit includes a first group of inverters, a first diode-connected transistor coupled in parallel to each inverter of the first group of inverters and configured to provide a first bias voltage to each inverter of the first group of inverters, and a second diode-connected transistor coupled in parallel to each inverter of the first group of inverters and configured to provide a second bias voltage to each inverter of the first group of inverters.
In described examples, a circuit includes a current mirror circuit. A first stage is coupled to the current mirror circuit. A second stage is coupled to the current mirror circuit and to the first stage. A voltage divider network is coupled to the second stage. The circuit includes an output transistor having first and second terminals, in which the first terminal of the output transistor is coupled to the first stage, and the second terminal of the output transistor is coupled to the voltage divider network.
An electronic device includes a substrate and a die having an active surface disposed on the substrate. Bond pads are disposed on the active surface of the die and includes a recess defined in a top surface of the bond pads. Ball bonds are disposed in the recess of the bond pads and wire bonds are attached to the ball bonds and to the substrate. A mold compound encapsulates the die, the bond pads, the ball bonds, and the wire bonds. The mold compound covers all but one surface of the substrate, where the one surface not covered faces away from the die.
In some examples, an apparatus comprises a chopper, a first microelectromechanical system (MEMS) device, a second MEMS device, and a processing circuit. The chopper configured is to repeatedly switch states to enable and disable provision of a light signal. The first MEMS device is configured to provide first and second irradiance signals when the chopper is in, respectively, first and second states The second MEMS device is configured to provide first and second reference signals when the chopper is in, respectively, the first and second states. The processing circuit is configured to generate a first signal based on the first irradiance signal and the first reference signal, generate a second signal based on the second irradiance signal and the second reference signal, and provide a third signal at the processing output representing an irradiance measurement of the light source based on a difference between the first and second signals.
G01N 21/3504 - Investigating relative effect of material at wavelengths characteristic of specific elements or molecules, e.g. atomic absorption spectrometry using infrared light for analysing gases, e.g. multi-gas analysis
B81B 3/00 - Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes
G01N 21/27 - ColourSpectral properties, i.e. comparison of effect of material on the light at two or more different wavelengths or wavelength bands using photo-electric detection
A load current sensing circuit includes a sense leg including a sense transistor with a gate coupled to the output of a high-side gate driver, a feedback transistor, and a sense resistor coupled in series between a power supply and ground. An amplifier has differential inputs coupled to the sense leg and to an output, and an output coupled to the feedback transistor gate. A bias circuit has a first transistor coupled between the power supply voltage and the first bias voltage terminal, and a gate receiving, from a first leg, a first differential from the output voltage. A second leg in the amplifier bias circuit generates a gate voltage, for a second transistor coupled between ground and a second bias voltage terminal, that is at a second differential from a voltage at the first bias voltage terminal. The amplifier is biased between the first and second bias voltages.
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
H03K 17/082 - Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
H03K 17/10 - Modifications for increasing the maximum permissible switched voltage
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
33.
INTEGRATED CIRCUIT INCLUDING FLASH MEMORY AND CMOS LOGIC CIRCUITRY
An integrated circuit (IC) including Flash memory and CMOS logic circuitry and a method of fabrication thereof is disclosed. The IC comprises a substrate including a first region and a second region, where a Flash memory cell gate stack is formed in the first region, a first transistor is formed in the first region and operable at a first voltage level, the first transistor including a gate formed over a first gate oxide layer exclusive of nitridation, and one or more sets of second transistors are formed in the second region, each set operable at a corresponding second voltage level different than the first voltage level and including a corresponding second gate oxide layer having nitridation.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
G11C 16/08 - Address circuitsDecodersWord-line control circuits
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
An example apparatus includes programmable circuitry configured to: provide a sample signal, a time amplification (TA) signal, and a kick signal to sample and conversion circuitry; sample a differential signal for a first amount of time-based on the sample signal; charge a first capacitor for a second amount of time-based on the first kick signal; after the first amount of time and the second amount of time, charge a second capacitor, the charging based on the first TA signal, the charging to cause a falling edge in a first delay signal; and generating, a rising edge in the delay signal based on the falling edge of O_RST signal.
An opto-emulator transmitter includes: a current controller; an oscillator circuit; and receiver replica circuitry. The current controller has a first terminal, a second terminal, and a third terminal. The oscillator circuit has a first terminal, a second terminal, and a third terminal. The first terminal of the oscillator circuit is coupled to the second terminal of the current controller. The receiver replica circuitry has a first terminal, a second terminal, and a third terminal. The first terminal of the receiver replica circuitry is coupled to the second terminal of the oscillator circuit. The second terminal of the receiver replica circuitry is coupled to the third terminal of the oscillator circuit. The third terminal of the receiver replica circuitry is coupled to the third terminal of the current controller.
In one example, an apparatus comprises a substrate, a first piezoelectric flap, and a second piezoelectric flap. The substrate has an opening. The first piezoelectric flap has a first end on the substrate and has a first portion extending over a first part of the opening, the first piezoelectric flap including first electrodes, in which the first electrodes extend no more than half of a first length of the first portion. The second piezoelectric flap has a second end on the substrate and has a second portion extending over a second part of the opening, the second piezoelectric flap including second electrodes, in which the second electrodes extend no more than half of a second length of the second portion.
A back side exposed semiconductor die package with a plurality of leads around a perimeter of the semiconductor die package, a semiconductor die electrically coupled to a plurality of the leads, a plurality of mold compound flash suppression trenches on the back side of the semiconductor die and a back side mold compound free zone are described. The plurality of mold compound flash suppression trenches on the back side of the semiconductor die act as a reservoir to prevent mold compound from encroaching on the mold compound free zone on the back side of the semiconductor die. After formation of the semiconductor die package on the lead frame, individual semiconductor die are singulated, and components such as a head sink may subsequently be attached to the mold compound free zone of the semiconductor die.
In described examples, an R2R digital-to-analog converter includes multiple arms and a voltage regulator. Respective arms include an arm switch with a p-channel MOSFET (PFET) switch and an n-channel MOSFET (NFET) switch. The voltage regulator includes a differential amplifier, a p-ladder that includes N cascade-coupled PFETS and has first and second ends, an n-ladder that includes y×N cascade-coupled NFETS and has first and second ends, a first resistor (resistance R), and a second resistor (resistance y×R). The first p-ladder end is coupled to a first terminal of the first resistor. The second terminal of the first resistor is coupled to an input of the differential amplifier and a first terminal of the second resistor. A second terminal of the second resistor is coupled to the first n-ladder end. An output of the differential amplifier is coupled to the second n-ladder end and provides a gate voltage of the NFET switch.
A circuit includes an amplifier having a first input, a reference input, and an output. A pulse width modulator (PWM) controller has an input coupled to the output of the amplifier. A first switch has a control terminal coupled to an output of the PWM controller. A second switch has a second terminal coupled to the second terminal of the first switch, and has a control terminal coupled to the output of the PWM controller. An input of a current sensor is coupled to the second terminal of the first switch and is coupled to a second terminal of the second switch. An output of the current sensor is coupled to the first input of the amplifier. A duty cycle monitoring and reference signal adjustment circuit has an input coupled to the output of the PWM controller and has an output coupled to the reference input of the amplifier.
A circuit includes a microcontroller having a first terminal and a second terminal. The microcontroller is configured to: receive a signal associated with operation of a power converter at the first terminal; adjust a switch control signal at the second terminal responsive to the signal; measure a frequency of the switch control signal; compare the measured frequency responsive to at least one envelope of a set of envelopes to obtain monitoring results; and perform control operations responsive to the monitoring results.
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
H02M 3/00 - Conversion of DC power input into DC power output
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
Embodiments disclosed herein relate to split rail architecture for power supplies in a system, and more particularly, to providing isolation and control of a power supply. In an example, an integrated circuit device is provided that includes a device voltage supply, an input/output (I/O) voltage supply coupled to the device voltage supply, and a level shifter circuit coupled to the I/O voltage supply. The level shifter circuit includes a pair of cross-coupled p-type metal-oxide semiconductor field effect transistors (PMOS transistors), a pair of n-type transistors (NMOS transistors) coupled between the pair of cross-coupled PMOS transistors and a ground connection, and an inverter circuit coupled to the device voltage supply and the level shifter circuit. The level shifter circuit further includes a capacitor coupled to the pair of cross-coupled PMOS transistors and the ground connection and is in parallel with respect to a first one of the pair of NMOS transistors.
In described examples, an electronic circuit for determining a phase difference between a first clock signal and a second clock signal includes a timer circuit, circuitry for generating a selectively delayed transition of the second clock signal, and phase determination circuitry. The timer circuit produces an elapsed time between a transition of the first clock signal and the selectively delayed transition of the second clock signal. The circuitry for generating the selectively delayed transition of the second clock signal generates the selectively delayed transition in response to a random selection of a respective output from a plurality of second clock signal delay stages. The phase determination circuitry provides the phase difference in response to the elapsed time and the random selection of a respective output from a plurality of second clock signal delay stages.
H03L 7/085 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
G04F 10/00 - Apparatus for measuring unknown time intervals by electric means
H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass
H03K 5/14 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of delay lines
H03L 7/081 - Details of the phase-locked loop provided with an additional controlled phase shifter
43.
SEMICONDUCTOR DEVICE HAVING A REDUCED HEIGHT GATE ELECTRODE LAYER
The present disclosure generally relates to a semiconductor device having a reduced height gate electrode layer. In an example, a semiconductor device includes a substrate, a gate dielectric layer, a gate electrode layer, a doped source/drain region, and a dielectric layer. The gate dielectric layer is on a surface of the substrate. The gate electrode layer is on the gate dielectric layer. The doped source/drain region is in the substrate and has a metallurgical junction parallel to a plane coplanar with the surface of the substrate. The metallurgical junction extends to a first vertical distance from the surface of the substrate. The gate electrode layer has a top surface that is a second vertical distance away from the surface of the substrate. The second vertical distance is equal to or less than half of the first vertical distance. The dielectric layer is over the substrate and the gate electrode layer.
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
A device for a grinding table includes a shim with a cross section shaped to mirror a cross section of a step gap formed at an edge of grinding tape adhered to a first side of a wafer that covers solder balls, such that the shim and the grinding tape form a planer surface on a grinding table for the wafer.
B24B 41/06 - Work supports, e.g. adjustable steadies
B24B 7/22 - Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfacesAccessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain
H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
In examples, a package comprises a substrate including a conductive member coupled to a conductive terminal, with the conductive terminal exposed to an exterior of the package. The package also includes a first semiconductor die having first device and first non-device sides, with the first device side coupled to the substrate and the first non-device side opposing the first device side, and with the first device side having circuitry formed therein. The package also includes a second semiconductor die having second device and second non-device sides, with the second device side coupled to the substrate and the second non-device side opposing the second device side, and with the second device side having circuitry formed therein. The package also includes first and second adhesive layers contacting the first and second non-device sides, respectively. The package also includes a passivation overcoat (PO) layer contacting the first and second adhesive layers, and a semiconductor layer contacting the PO layer and exposed to an exterior of the package.
H01L 23/373 - Cooling facilitated by selection of materials for the device
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
46.
SYSTEM ARCHITECTURE TO SELECTABLY SYNCHRONIZE TIME-BASES
A system timer bus used by the processor elements in systems, such as an ARM-based system on a chip (SoC), is driven using a Precision Time Measurement (PTM) value. This allows the processor elements to be synchronized to the PCIe ports that use PTM. When two SoCs are connected using PCIe links, this example allows the processor elements in both SoCs to be synchronized. As the processor elements are synchronized, associated tasks on the two SoCs are synchronized, so that overall operations are synchronized.
An integrated circuit (IC) (400) including Flash memory and CMOS logic circuitry and a method of fabrication thereof is disclosed. The IC (400) comprises a substrate including a first region (403 A/C) and a second region (403B), where a Flash memory cell gate stack (485-1) is formed in the first region (403 A/C), a first transistor (491 ) is formed in the first region (403 A/C) and operable at a first voltage level, the first transistor (491) including a gate (489) formed over a first gate oxide layer (486) exclusive of nitridation, and one or more sets of second transistors (471A/B) are formed in the second region (403B), each set (471A/B) operable at a corresponding second voltage level different than the first voltage level and including a corresponding second gate oxide layer (450) having nitridation.
A packaged integrated circuit (IC) (100) includes a package substrate (316), an electronic device (104) on the package substrate (316), and metal interconnects (301-305) coupled between the electronic device (104) and the package substrate (316). The packaged IC (100) also includes an insulation material (150) on the package substrate (316) and encapsulating the electronic device (104). The insulation material (104) surrounds the metal interconnects (301-305). An inductor (108) is over the electronic device (104) and is coupled to the package substrate (316). A magnetic material (160) is on the insulation material (150) and encapsulates the inductor (108). The magnetic material (160) is different from the insulation material (150).
Embodiments disclosed herein relate to synchronizing signals across multiple independent clock domains. In an example, a synchronizer flip-flop circuit is provided. Synchronizer flip-flop circuit (100) includes a first latch sub-circuit (112) coupled to receive input data (101) and a second latch sub-circuit (117) coupled to the first latch sub-circuit (112). The first latch subcircuit (112) includes a first group of inverters, a first diode-connected transistor (113) coupled in parallel to each inverter of the first group of inverters and configured to provide a first bias voltage to each inverter of the first group of inverters, and a second diode-connected transistor (114) coupled in parallel to each inverter of the first group of inverters and configured to provide a second bias voltage to each inverter of the first group of inverters.
An opto-emulator transmitter (102A) includes: a current controller (222); an oscillator circuit (238); and receiver replica circuitry (258). The current controller (222) has a first terminal (224), a second terminal (228), and a third terminal (230). The oscillator circuit (238) has a first terminal (240), a second terminal (242), and a third terminal (244). The first terminal (240) of the oscillator circuit (238) is coupled to the second terminal (228) of the current controller (222). The receiver replica circuitry (258) has a first terminal (260), a second terminal (262), and a third terminal (264). The first terminal (260) of the receiver replica circuitry (258) is coupled to the second terminal (242) of the oscillator circuit (238). The second terminal (262) of the receiver replica circuitry (258) is coupled to the third terminal (244) of the oscillator circuit (238). The third terminal (264) of the receiver replica circuitry (258) is coupled to the third terminal (230) of the current controller (222).
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H03K 17/689 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors with galvanic isolation between the control circuit and the output circuit
An apparatus includes a first prism and a second prism coupled to the first prism, where the first prism faces a first side of the second prism. The apparatus also includes a spatial light modulator (SLM) facing a second side of the second prism and reflective focusing optics facing a third side of the second prism.
From a bit stream, at least the following are decoded: a stereoscopic image of first and second views; a maximum positive disparity between the first and second views; and a minimum negative disparity between the first and second views. In response to the maximum positive disparity violating a limit on positive disparity, a convergence plane of the stereoscopic image is adjusted to comply with the limit on positive disparity. In response to the minimum negative disparity violating a limit on negative disparity, the convergence plane is adjusted to comply with the limit on negative disparity.
H04N 19/597 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding specially adapted for multi-view video sequence encoding
H04N 19/70 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by syntax aspects related to video coding, e.g. related to compression standards
53.
ACCESSING ERROR STATISTICS FROM A CIRCUIT HAVING INTEGRATED ERROR CORRECTION
In described examples, a memory module includes a memory array with a primary access port coupled to the memory array. Error correction logic is coupled to the memory array. A statistics register is coupled to the error correction logic. A secondary access port is coupled to the statistics register to allow access to the statistics register by an external device without using the primary interface.
A circuit includes a high-side driver having a high-side slew control input, a high-side drive input and a high-side drive output. A low-side driver has a low-side slew control input, a low-side drive input and a low-side drive output. Drive control circuitry has a high-side drive control output, a low-side drive control output, and a slew control output. The high-side drive control output is coupled to the high-side drive input, the low-side drive control output is coupled to the low-side drive input. The slew control output is coupled to at least one of the high-side slew control input and the low-side slew control input, and the drive control circuitry is configured to provide a slew control signal at the slew control output. The high-side and/or low-side driver is configured to modulate a slew rate of a drive signal at a respective drive output thereof based on the slew control signal.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H03K 19/003 - Modifications for increasing the reliability
55.
DYNAMIC PLATED METAL THICKNESS FOR SEMICONDUCTOR PACKAGE
A semiconductor package includes a semiconductor component and a plurality of leads electrically connected to the semiconductor component. Each of the leads has a first surface, and has a second surface opposite from the first surface, with a solderable metal on the first surface and the second surface. The solderable metal has a first average thickness on the first surfaces, and has a second average thickness on the second surfaces. The second average thickness is 10 percent to 80 percent of the first average thickness. The semiconductor package is formed by concurrently electroplating the solderable metal on the first surfaces and on the second surfaces. The solderable metal is electroplated on the first surfaces with a first average current, and is electroplated on the second surfaces with a second average current. The second average current is 10 percent to 80 percent of the first average current.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
In some examples, a battery management system (BMS) includes a set of battery cells and a secondary network node coupled to the set of battery cells. The secondary network node is configured to, responsive to determination by the secondary network node of an exception event, wirelessly transmit a series of periodically repeating reverse wake up data frames to a primary network node. The secondary network node is also configured to, responsive to receipt of a synchronization frame from the primary network node after transmitting the series of reverse wake up data frames, transmit an uplink data frame to the primary network node.
H01M 10/42 - Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
H01M 10/48 - Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte
H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
An electronic device includes a package structure, conductive leads, first and second semiconductor dies, and a metal clip, The package structure has opposite longitudinal ends, opposite lateral sides, a middle portion midway between the longitudinal ends, a first portion that extends between the middle portion and one longitudinal end, and a second portion that extends between the middle portion and the other longitudinal end. The metal clip extends in the package structure from the first portion to the second portion through the middle portion and electrically couples the first electronic component of the first semiconductor die to the second electronic component of the second semiconductor die.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H01L 23/00 - Details of semiconductor or other solid state devices
In an example, a method includes receiving, in a first super frame (502B), a first downlink (522B) on a first channel from a wireless master node (504) at a wireless device (506.5) in a WBMS, where the first downlink (522B) indicates a second channel assigned to the wireless device (506.5). The method includes transmitting, in the first super frame (502B), a synchronization frame (530) from the wireless device (506.5) to an unsynchronized wireless device (506.3) on the second channel, where the synchronization frame (530) indicates a third channel. The method also includes receiving, in the first super frame (502B), the synchronization frame (530) at the unsynchronized wireless device (506.3) on the second channel. The method includes transmitting, on the third channel in a second super frame after the first super frame (502B), an uplink from the unsynchronized wireless device (506.3) to the wireless master node (504).
A method of forming a composite material includes photo-initiating a polymerization of a monomer in a pattern of interconnected units to form a polymer microlattice. Unpolymerized monomer is removed from the polymer microlattice. The polymer microlattice is coated with a metal. The metal-coated polymer microlattice is dispersed in a polymer matrix.
A video encoder including a first buffer containing a plurality of data values defining a macroblock of pixels of a video frame. The video encoder also includes a second buffer and an entropy encoder coupled to the first and second buffers and configured to encode a macroblock based on another macroblock. The entropy encoder identifies a subset of the data values from the first buffer defining a given macroblock and copies the identified subset to the second buffer, the subset of data values being just those data values used by the entropy encoder when subsequently encoding another macroblock.
An apparatus includes a resonant converter controller having a converter voltage sensing terminal, a reference voltage terminal, a converter current sensing terminal, first and second converter capacitor terminals, and first and second control outputs. The resonant converter controller is configured to: receive a current sensing signal at the converter current sensing terminal; generate a first signal based on the current sensing signal; generate a second signal representing a difference between a first voltage at the converter voltage sensing terminal and a reference voltage at the reference voltage terminal; and generate first and second switching signals at, respectively, the first and second control outputs responsive to the first signal, the second signal, and a capacitor voltage between the first and second converter capacitor terminals to regulate the first voltage based on the reference voltage.
H02M 1/38 - Means for preventing simultaneous conduction of switches
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
An electronic device includes a substrate and a die having an active surface disposed on the substrate. A sensor is in communication with the active surface of the die and a ring is disposed on the die and encircles the sensor. The ring includes a cylindrical wall and a cap, where the cylindrical wall has an open top and the cap has a partial circular shape that extends beyond each side of the cylindrical wall, A cover is disposed on the cap such that the cover closes off the open top of the ring to form a cavity inside the ring to prevent foreign substance from entering the cavity. A mold compound covers the die and the cover, and abuts an outer surface of the cylindrical wall.
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
G01N 27/22 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating capacitance
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/24 - Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel, at the normal operating temperature of the device
63.
NODE RESYNCHRONIZATION MECHANISM FOR WIRELESS BATTERY MANAGEMENT SYSTEM
In an example, a method includes receiving, in a first super frame, a first downlink on a first channel from a wireless master node at a wireless device in a WBMS, where the first downlink indicates a second channel assigned to the wireless device. The method includes transmitting, in the first super frame, a synchronization frame from the wireless device to an unsynchronized wireless device on the second channel, where the synchronization frame indicates a third channel. The method also includes receiving, in the first super frame, the synchronization frame at the unsynchronized wireless device on the second channel. The method includes transmitting, on the third channel in a second super frame after the first super frame, an uplink from the unsynchronized wireless device to the wireless master node.
In some examples, a battery management system (BMS) (200) includes a set of battery cells (208) and a secondary network node (206) coupled to the set of battery cells. The secondary network node is configured to, responsive to determination by the secondary network node of an exception event, wirelessly transmit a series of periodically repeating reverse wake up data frames to a primary network node (102). The secondary network node is also configured to, responsive to receipt of a synchronization frame from the primary network node after transmitting the series of reverse wake up data frames, transmit an uplink data frame to the primary network node.
B60L 53/20 - Methods of charging batteries, specially adapted for electric vehiclesCharging stations or on-board charging equipment thereforExchange of energy storage elements in electric vehicles characterised by converters located in the vehicle
A driver includes a current generator having an input and first and second outputs. The current generator generates a first current at the first output while a signal at the input is at a first logic state and generates a second current at the second output while the signal at the input is at a second logic state. A comparator has a first comparator input, a second comparator input, and a first comparator output, and a second comparator output. The first comparator input is coupled to the first output, and the second comparator input is coupled to the second output. A latch has a first latch input, a second latch input, and a latch output. The first latch input is coupled to the first comparator output, and the second latch input is coupled to the second comparator output. A gate control circuit has an input coupled to the latch output.
H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only
H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
66.
OPTIMIZED REGENERATIVE BRAKING CONTROL OF ELECTRIC MOTORS USING LOOK-UP TABLES
A regenerative braking controller for an AC motor. To determine an electromagnetic torque for slowing or stopping the motor, the regenerative braking controller accesses a lookup table to retrieve a braking torque value corresponding to a current estimate of rotor velocity. The retrieved braking torque may correspond to a maximum or minimum torque level at which regenerative braking will occur at the current rotor velocity, or to a torque level at which charging current during regenerative braking will be maximized. If an external mechanical brake is present, the regenerative braking controller can forward an external braking torque signal to a controller so that the mechanical brake can apply the remainder of the braking force beyond that indicated by the regenerative braking torque. A method for establishing the braking torques to be stored in the lookup table is also disclosed.
B60L 15/02 - Methods, circuits or devices for controlling the propulsion of electrically-propelled vehicles, e.g. their traction-motor speed, to achieve a desired performanceAdaptation of control equipment on electrically-propelled vehicles for remote actuation from a stationary place, from alternative parts of the vehicle or from alternative vehicles of the same vehicle train characterised by the form of the current used in the control circuit
B60L 15/20 - Methods, circuits or devices for controlling the propulsion of electrically-propelled vehicles, e.g. their traction-motor speed, to achieve a desired performanceAdaptation of control equipment on electrically-propelled vehicles for remote actuation from a stationary place, from alternative parts of the vehicle or from alternative vehicles of the same vehicle train for control of the vehicle or its driving motor to achieve a desired performance, e.g. speed, torque, programmed variation of speed
H02P 3/16 - Arrangements for stopping or slowing electric motors, generators, or dynamo-electric converters for stopping or slowing an individual dynamo-electric motor or dynamo-electric converter for stopping or slowing a DC motor by combined electrical and mechanical braking
H02P 21/22 - Current control, e.g. using a current control loop
H02P 21/36 - Arrangements for braking or slowingFour quadrant control
H02P 27/08 - Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using DC to AC converters or inverters with pulse width modulation
Radar systems, radar-implementation methods, and non-transitory processor-readable mediums storing processor-executable instructions for implementing radar chirp generation and processing are provided. An example set of processor-executable instructions includes instructions for configuring each of a plurality of transmitters to transmit each chirp of a set of chirps with a specific spin frequency that is different for each transmitter, in which the specific spin frequency is a function of an index value identifying the corresponding transmitter, and a number of the plurality of transmitters; and determining, in a frequency domain, a Doppler representation based on reflected signals that are reflected from one or more objects contacted by one or more chirps of the transmitted sets of chirps, in which the Doppler representation includes multiple spectrum bands including one or more empty spectrum bands determined by the specific spin frequency function, wherein none of the object(s) appear(s) in any of the empty spectrum band(s).
A method for sample adaptive offset (SAO) filtering and SAO parameter signaling in a video encoder is provided that includes determining SAO parameters for largest coding units (LCUs) of a reconstructed picture, wherein the SAO parameters include an indicator of an SAO filter type and a plurality of SAO offsets, applying SAO filtering to the reconstructed picture according to the SAO parameters, and entropy encoding LCU specific SAO information for each LCU of the reconstructed picture in an encoded video bit stream, wherein the entropy encoded LCU specific SAO information for the LCUs is interleaved with entropy encoded data for the LCUs in the encoded video bit stream. Determining SAO parameters may include determining the LCU specific SAO information to be entropy encoded for each LCU according to an SAO prediction protocol.
H04N 19/86 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression involving reduction of coding artifacts, e.g. of blockiness
H04N 19/117 - Filters, e.g. for pre-processing or post-processing
H04N 19/463 - Embedding additional information in the video signal during the compression process by compressing encoding parameters before transmission
H04N 19/70 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by syntax aspects related to video coding, e.g. related to compression standards
H04N 19/80 - Details of filtering operations specially adapted for video compression, e.g. for pixel interpolation
H04N 19/82 - Details of filtering operations specially adapted for video compression, e.g. for pixel interpolation involving filtering within a prediction loop
H04N 19/91 - Entropy coding, e.g. variable length coding [VLC] or arithmetic coding
A device includes a memory bank. The memory bank includes data portions of a first way group. The data portions of the first way group include a data portion of a first way of the first way group and a data portion of a second way of the first way group. The memory bank further includes data portions of a second way group. The device further includes a configuration register and a controller configured to individually allocate, based on one or more settings in the configuration register, the first way and the second way to one of an addressable memory space and a data cache.
G06F 12/0817 - Cache consistency protocols using directory methods
G06F 12/0831 - Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
G06F 12/084 - Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
G06F 12/0846 - Cache with multiple tag or data arrays being simultaneously accessible
G06F 12/0855 - Overlapped cache accessing, e.g. pipeline
G06F 12/0862 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
G06F 12/0875 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
G06F 12/0891 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
H03M 13/01 - Coding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
H03M 13/09 - Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
H03M 13/27 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes using interleaving techniques
70.
METHODS, SYSTEMS, AND APPARATUS FOR COUPLING POWER AMPLIFIER INPUT SIGNALS
Methods, systems, and apparatus are disclosed for coupling a power amplifier input signal. An example system a first amplifier including a signal input, a feedback input, and a differential output that includes a first output and a second output, a first resistor including a first resistor terminal and a second resistor terminal, wherein the first resistor terminal is coupled to the first output, a second resistor including a third resistor terminal and a fourth resistor terminal, wherein the third resistor terminal is coupled to the second resistor terminal at an output common mode node and the fourth resistor terminal coupled to the second output, and a second amplifier including a first input and a third output, wherein the first input is coupled to the second resistor terminal and third resistor terminal, and the third output is coupled to the feedback input of the first amplifier.
Described embodiments include a control circuit with a first comparator having a first comparator input receiving a first threshold voltage, and a second comparator input coupled to an output voltage terminal. A second comparator has a third comparator input receiving a second threshold voltage, and a fourth comparator input coupled to a current output terminal. A first logic circuit provides a true signal at its output responsive to a particular number of its inputs receiving a true input. A second logic circuit has inputs coupled to the first comparator output, and to the first logic output. A variable resistance circuit has an output coupled to a mode detection output. An amplifier has inputs coupled to the variable resistance circuit output, and a third reference voltage source. A duty cycle generation circuit provides a respective pulse width modulation (PWM) signal at each of its respective duty cycle outputs.
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
Various embodiments of the present disclosure relate to conditional branch instructions to support software pipelining techniques. In an example embodiment, a system including instruction fetch circuitry, decoder circuitry, and conditional branch circuitry is provided. The instruction fetch circuitry is configured to fetch a conditional branch instruction from memory and provide the instruction to the decoder circuitry. The instruction includes an iteration count and multiple branch destinations. The branch destinations include two or more branch destinations corresponding to conditions against which the conditional branch circuitry evaluates the iteration count. The decoder circuitry is configured to cause the conditional branch circuitry to select a branch destination, of the two or more branch destinations, based on a comparison of the iteration count to each of the conditions and cause the instruction fetch circuitry to fetch an indication of an instruction from a memory location stored at the selected branch destination.
A power controller comprises a control loop configured to control timing of pulsed signals that activate phases of a coupled inductor voltage regulator based on current demand of a load circuit and comprises a transient detection circuit configured to determine a projected current through a compensation inductor of the coupled inductor voltage regulator based on a state of the phases and operating parameters of the coupled inductor voltage regulator. The transient detection circuit is configured to detect a transient in the current demand of the load circuit based on a variability in phase-to-phase overlap of the pulsed signals. Responsive to detecting the transient, the transient detection circuit is configured to apply a correction to the control loop that alters the timing of the pulsed signals based on the projected current through the compensation inductor.
H02M 7/537 - Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
74.
FREQUENCY-BASED COMPENSATION FOR POWER CONTROLLERS AND CONVERTERS
A circuit includes an error amplifier including a reference input, a feedback input, and an error output. A compensation network has a frequency input and a compensation output, in which the compensation output is coupled to the error output. The compensation network configured to provide a variable capacitance between the compensation output and a ground terminal based on a frequency signal at the frequency input having a value representative of a frequency of a clock signal.
H03B 5/12 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
A driver (140) includes a current generator (202) having an input and first and second outputs. The current generator (202) generates a first current at the first output while a signal at the input is at a first logic state and generates a second current at the second output while the signal at the input is at a second logic state. A comparator (220) has a first comparator input, a second comparator input, and a first comparator output, and a second comparator output. The first comparator input is coupled to the first output, and the second comparator input is coupled to the second output. A latch (241) has a first latch input, a second latch input, and a latch output. The first latch input is coupled to the first comparator output, and the second latch input is coupled to the second comparator output. A gate control circuit (151) has an input coupled to the latch output.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
76.
TECHNIQUES TO DETECT AN INDUCTOR-OPEN CONDITION IN VOLTAGE REGULATORS
Some examples relate to a circuit including a plurality of input pins, a plurality of output pins, a pulse width modulated (PWM) controller, and an inductor-open detection circuit. The PWM controller has a plurality of inputs and a plurality of outputs. The plurality of inputs of the PWM controller are coupled to the plurality of input pins, and the plurality of outputs of the PWM controller are coupled to the plurality of output pins. The inductor-open detection circuit has an input coupled to a pin of the plurality of input pins, and has an output coupled to the PWM controller.
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
G01R 19/165 - Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
77.
METHODS AND APPARATUS TO FACILITATE ACCESS CONTROL IN MEMORY
Methods, apparatus, systems, and articles of manufacture are described to facilitate access control in memory. An example method includes accessing state values stored in non-volatile memory, the state values corresponding to a state of the non-volatile memory; responsive to obtaining a request to enter a diagnostic mode, authenticating credentials corresponding to the request; determining the state of the non-volatile memory based on the state values; and determining whether to permit or prohibit access to the non-volatile memory based on the determined state.
In some examples, a transistor comprises a gallium nitride (GaN) layer; a GaN-based alloy layer having a top side and disposed on the GaN layer, wherein source, drain, and gate contact structures are supported by the GaN layer, and a first doped region positioned in a drain access region and extending from the top side into the GaN layer.
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
A semiconductor device includes a GaN FET on a silicon substrate and a buffer layer of III-N semiconductor material, with a columnar region, a transition region surrounding the columnar region, and an inter-columnar region around the transition region. The columnar region is higher than the inter-columnar region. The GaN FET includes a gate of III-N semiconductor material with a thickness greater than twice the vertical range of the top surface of the buffer layer in the columnar region. A difference between the gate thickness over the columnar region and over the transition region is less than half of the vertical range of the top surface of the buffer layer in the columnar surface. The semiconductor device may be formed by forming a gate layer of III-N semiconductor material over the barrier layer by a gate MOVPE process using a carrier gas that includes zero to 40 percent hydrogen gas.
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 29/04 - Semiconductor bodies characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/205 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds in different semiconductor regions
A charge pump circuit includes first and second capacitors, first, second, third and fourth switches, and a transistor. The first switch is coupled between a top plate of the first capacitor and a first voltage input terminal. The second switch is coupled between a bottom plate of the first capacitor and a reference voltage terminal. The third switch is coupled between the top plate of the first capacitor and a top plate of the second capacitor. The transistor and the fourth switch are coupled in series between the bottom plate of the first capacitor and a second voltage input terminal.
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only
81.
METHODS, SYSTEMS, AND APPARATUS FOR COUPLING POWER AMPLIFIER INPUT SIGNALS
Methods, systems, and apparatus are disclosed for coupling a power amplifier input signal. An example system a first amplifier (204) including a signal input (234a, 234b), feedback input (246), and a differential output that includes a first output (236a) and a second output (236b), a first resistor (218a) including a first resistor terminal and a second resistor terminal, wherein the first resistor terminal is coupled to the first output (236a), a second resistor (218b) including a third resistor terminal and a fourth resistor terminal, wherein the third resistor terminal is coupled to the second resistor terminal at an output common mode node (242) and the fourth resistor terminal coupled to the second output (236b), and a second amplifier (208) including a first input (242) and a third output (240), wherein the first input (242) is coupled to the second resistor terminal and third resistor terminal, and the third output (240) is coupled to the feedback input (246) of the first amplifier (204).
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 1/32 - Means for protecting converters other than by automatic disconnection
83.
Identifying a Source of a Function Call and Inheriting Access Permission
Systems and methods provide for inherited access permissions, thereby facilitating read and write access by called contexts. Hardware logic may enforce access permissions in the system. When a processor core executes code associated with a first context, the processor core generates a first hardware signal identifying the first context. The processor core may then switch from the first context to the second context due to the first context calling the second context. The processor core may then generate a second hardware signal identifying the calling (first) context, and then the first hardware signal identifies the called (second) context. The hardware logic that enforces the access permissions may then determine that the second context is being called and that the second context includes either direct access permissions or inherited access permissions associated with the calling (first) context.
Channel state information (CSI) feedback in a wireless communication system is disclosed. A precoding matrix is generated for multi-antenna transmission based on precoding matrix indicator (PMI) feedback, wherein the PMI indicates a choice of precoding matrix derived from a matrix multiplication of two matrices from a first codebook and a second codebook. In one embodiment, the first codebook comprises at least a first precoding matrix constructed with a first group of adjacent Discrete-Fourier-Transform (DFT) vectors. In another embodiment, the first codebook comprises at least a second precoding matrix constructed with a second group of uniformly distributed non-adjacent DFT vectors. In yet another embodiment, the first codebook comprises at least a first precoding matrix and a second precoding matrix, where said first precoding matrix is constructed with a first group of adjacent DFT vectors, and said second precoding matrix is constructed with a second group of uniformly distributed non-adjacent DFT vectors.
H04B 7/06 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
85.
SEMICONDUCTOR STRUCTURE AND METHOD FOR WAFER SCALE CHIP PACKAGE
An embodiment semiconductor structure includes a metal layer. The semiconductor structure also includes a redistribution layer (RDL) structure including an RDL platform and a plurality of RDL pillars disposed between the RDL platform and the metal layer. Additionally, the semiconductor structure includes an under-bump metal (UBM) layer disposed on the RDL platform and a solder bump disposed on the UBM layer, where the UBM layer, the RDL platform, and the RDL pillars form an electrical connection between the solder bump and the metal layer.
Systems and methods enable the classification of each value of multiple floating-point values stored in a first vector register, and storage in a second vector register multiple elements that each indicate a respective classification of a respective value of the multiple floating-point values. A system includes a functional unit, first and second vector registers coupled to the functional unit, and processing circuitry. The processing circuitry is configurable, e.g., via an instruction, to cause the functional unit to perform the classification and storage operations.
An example apparatus includes: a low-pass filter and a high-pass filter coupled to a first current terminal of the first transistor; an input of a first amplifier coupled to the output of the high-pass filter; an input of a negative gain amplifier coupled to an output of the first amplifier; inputs of an adder coupled to an output of the negative gain amplifier and an output of the low-pass filter; a first input of a second amplifier coupled to the output of the adder; a control terminal of a second transistor coupled to the output of the second amplifier, a second current terminal of the second transistor coupled to the first input of the second amplifier; and a control terminal of a third transistor coupled to the output of the second amplifier, a second current terminal of the third transistor coupled to an output terminal.
Methods, apparatus, systems, and articles of manufacture are described corresponding to immutable configuration of memory devices. An example memory includes a memory bank including a first portion and a second portion, the second portion configured to store configuration information that specifies whether the first portion is immutable; and a controller coupled to the memory bank, the controller configured to determine whether to prevent data from being written to the first portion based on the configuration information.
An example apparatus includes: level shifter circuitry having a first input terminal, a second input terminal, and an output terminal; latch circuitry having an input terminal and an output terminal, the input terminal of the latch circuitry coupled to the output terminal of the level shifter circuitry; a first transistor having a first terminal and a control terminal, the first terminal of the first transistor coupled to the first input terminal of the level shifter circuitry; a second transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the second transistor coupled to the control terminal of the first transistor, the control terminal of the second transistor coupled to the first input terminal of the level shifter circuitry; and a third transistor having a terminal coupled to the second terminal of the second transistor.
The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502) between the substrate (408) and a JTAG controller (404). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.
Techniques for image processing including receiving input image data, wherein the input image data includes data associated with a clear color channel, receiving a color offset value associated with a color channel, wherein color values for the color channel are not provided in the input image data, based on the color offset value, generating intermediate estimated color values for the color channel, wherein generating the intermediate estimated color values includes: clipping color values that have a magnitude greater than the color offset value, and adjusting color values that have a magnitude less than the color offset value based on the color offset value, applying a color correction function to the intermediate estimated color values based on the color offset value to determine color corrected estimated color values, and outputting the color corrected estimated color values.
An example apparatus includes a buffer configured to, when enabled: obtain an input voltage; and provide the input voltage to a first boundary cell; and a second boundary cell configured to, when the apparatus is used in analog mode and a boundary scan occurs disable the buffer.
In an example, a system includes an input channel and a voltage to delay converter (V2D) coupled to the input channel. The system also includes a first multiplexer coupled to the V2D and an analog-to-digital converter (ADC) coupled to the first multiplexer. The system includes a second multiplexer coupled to the input channel and an auxiliary ADC coupled to the second multiplexer. The system includes calibration circuitry coupled to an output of the auxiliary ADC, where the calibration circuitry is configured to correct a non-linearity in a signal provided by the input channel. The calibration circuitry is also configured to determine the non-linearity of the signal provided to the ADC relative to the signal provided to the auxiliary ADC.
According to an embodiment, a system and method is disclosed for efficient wake up in a wireless communication device for receiving beacons without significantly affecting the battery power and data throughput. Wireless device receives beacons from network elements such as access points. If beacons are not received as scheduled within defined intervals, then the wireless device determines a pattern of beacon reception timings and uses a weighted score process to select the best possible reception timing pattern and uses it as the schedule for receiving beacons on going forward basis, thus avoiding staying awake at all time to receive misaligned beacons.
A non-transitory machine-readable medium having machine-readable instructions including a firmware generator, the machine-readable instructions for the firmware generator being executable by a processor core to perform operations including signing a firmware image for a hardware security module (HSM) with a private key of a public private key pair to provide a first signature and augmenting the firmware image with a header that includes the first signature to provide an augmented firmware image. The operations further include encrypting the augmented firmware image with a symmetric key to provide an encrypted augmented firmware image. Furthermore, the operations include signing the encrypted augmented firmware image with the private key to provide a second signature and augmenting the encrypted augmented firmware image with the second signature to provide a firmware package for the HSM.
H04L 9/30 - Public key, i.e. encryption algorithm being computationally infeasible to invert and users' encryption keys not requiring secrecy
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
An example apparatus (300) includes: switch control circuitry (306); and mode control circuitry (104) configured to: in response to a determination that the switch control circuitry (306) is to be operated in a fixed frequency mode, signal a switch control circuitry transition to the switch control circuitry (306) configured to transition the switch control circuitry (306) to an on-time control mode to transmit an on-time control pulse signal to a switch (112); and in response to the switch control circuity transition to the on-time control mode, signal the switch control circuitry (306) configured to transmit a fixed frequency mode clock signal to the switch (112).
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 3/157 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
An example apparatus includes: switch control circuitry; and mode control circuitry configured to: in response to a determination that the switch control circuitry is to be operated in a fixed frequency mode, signal a switch control circuitry transition to the switch control circuitry configured to transition the switch control circuitry to an on-time control mode to transmit an on-time control pulse signal to a switch; and in response to the switch control circuitry transition to the on-time control mode, signal the switch control circuitry configured to transmit a fixed frequency mode clock signal to the switch.
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
98.
SEMICONDUCTOR DEVICE WITH DIFFUSION SUPPRESSION AND LDD IMPLANTS AND AN EMBEDDED NON-LDD SEMICONDUCTOR DEVICE
The present disclosure provides a method for forming a semiconductor device containing MOS transistors both with and without source/drain extension regions in a semiconductor substrate having a semiconductor material on either side of a gate structure including a gate electrode on a gate dielectric formed in a semiconductor material. In devices with source/drain extensions, a diffusion suppression species of one or more of indium, carbon and a halogen are used. The diffusion suppression implant can be selectively provided only to the semiconductor devices with drain extensions while devices without drain extensions remain diffusion suppression implant free.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 21/225 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regionsRedistribution of impurity materials, e.g. without introduction or removal of further dopant using diffusion into, or out of, a solid from or into a solid phase, e.g. a doped oxide layer
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 21/266 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation using masks
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
In some examples, a gallium-based device comprises a substrate layer; a first group-III nitride layer supported by the substrate layer; a second group-III nitride layer supported by the first group-III nitride layer; a tunnel barrier layer supported by the second group-III nitride layer; a passivation layer supported by the tunnel barrier layer; and source, gate, and drain contact structures supported by the first group-III nitride layer.
In accordance with at least one example of the description, a microelectromechanical systems (MEMS) device includes a hinge. The MEMS device also includes a spring tip. Additionally, the MEMS device includes a top layer including a recessed shelf and a top surface, where the recessed shelf is coupled to the hinge.
G02B 26/08 - Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light
G02B 6/35 - Optical coupling means having switching means
