Processing chambers having a chamber body with a wafer cassette assembly and at least one lift pin assembly are described. The wafer cassette assembly has at least two support columns configured to hold a plurality of wafer supports spaced along a height of the support columns. The lift pin assemblies have a plurality of lift pins arranged so that each of the plurality of wafer supports comprises at least three lift pins.
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C23C 16/52 - Controlling or regulating the coating process
Exemplary semiconductor processing methods may include providing one or more first etchant precursors to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region. A plurality of pairs of silicon oxide material and polysilicon material may be disposed on the substrate. The methods may include forming plasma effluents of the one or more first etchant precursors and contacting the substrate with the plasma effluents of the one or more first etchant precursors to selectively etch silicon oxide material. The methods may include providing one or more second etchant precursors to the processing region, forming plasma effluents of the one or more second etchant precursors, and contacting the substrate with the plasma effluents of the one or more second etchant precursors to selectively etch polysilicon material. A temperature within the processing region may be greater than or about 0° C.
Embodiments described herein relate to an apparatus that includes a microwave power generator, and a rectangular waveguide coupled to the microwave power generator. In an embodiment, the apparatus may also include an impedance tuner that is coupled to the rectangular waveguide, and a coaxial waveguide that is coupled to the rectangular waveguide. In an embodiment, the coaxial waveguide includes a conductive pin with a first end and a second end. In an embodiment, the apparatus further includes a circular waveguide cavity around the second end of the conductive pin, and a slotted antenna in the circular waveguide cavity.
A method for calibrating an edge ring height is described herein. The method includes measuring first thicknesses at a plurality of locations of a substrate using a substrate measurement system of a substrate processing system, and performing a process on the substrate in a process chamber including an edge ring that surrounds the substrate. The method also includes measuring second thicknesses the plurality of locations and estimating a rate and edge ring height of the edge ring and calibrating the edge ring height based on the estimated edge ring height.
H01L 21/66 - Testing or measuring during manufacture or treatment
G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM]
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
5.
UNDERCUT-ASSISTED LONG RANGE EVANESCENT COUPLING BETWEEN WAVEGUIDES
An optical device includes a substrate, cladding material on the substrate, a first inner core within the cladding material, and a trench in the substrate that assists with evanescent coupling of an optical signal between the first inner core and a second inner core that is positioned farther from the substrate than the first inner core.
G02B 6/293 - Optical coupling means having data bus means, i.e. plural waveguides interconnected and providing an inherently bidirectional system by mixing and splitting signals with wavelength selective means
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
G02B 6/122 - Basic optical elements, e.g. light-guiding paths
G02B 6/136 - Integrated optical circuits characterised by the manufacturing method by etching
G02B 6/38 - Mechanical coupling means having fibre to fibre mating means
Precursor delivery systems that can achieve increased dose profile control compared to current precursor delivery systems are described. Processing methods that include using the precursor delivery system to deposit a film are also described. The precursor delivery system comprises a first precursor outlet line and a second precursor outlet line, each of the first precursor outlet line and the second precursor outlet line configured to allow the precursor to be delivered from a pressure-controlled precursor reservoir to a processing chamber, wherein the first precursor outlet line is configured to deliver the precursor at a first flow rate and the second precursor outlet line is configured to deliver the precursor at a second flow rate.
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C23C 16/14 - Deposition of only one other metal element
C23C 16/52 - Controlling or regulating the coating process
7.
PLASMA GENERATOR AND INJECTOR ASSEMBLY FOR LAYER INSERTION, AND RELATED METHODS, PROCESSING CHAMBERS, AND SYSTEMS
Embodiments of the present disclosure generally relate to an injector assembly for use in a processing chamber, and related components and methods. In one or more embodiments, a method of substrate processing includes performing an ignition process including flowing a plasma gas into a plasma volume and igniting the plasma gas into a plasma. The method further includes performing a deposition process including flowing a processing gas into an internal volume of a process chamber and across a substrate in the internal volume and depositing a deposition structure over the substrate. The method further includes performing an insertion process including flowing an insertion gas for a time of less than 5 seconds into the plasma within the plasma volume to form effluents from the insertion gas, flowing the effluents into the internal volume and across the substrate in the internal volume, and inserting the effluents into the deposition structure.
Embodiments described herein relate to a method of developing a resist layer on a substrate that has been selectively exposed with a lithography process. In an embodiment the method includes exposing the resist layer to a gas including one or both of an organic acid or a ketone in a chamber with an exposure time that is at least ten minutes, where the gas selectively removes an unexposed portion of the resist layer to form a pattern in the resist layer, and where the resist layer includes a metal. The method may further include purging the chamber.
Methods of manufacturing interconnect structures as part of a microelectronic device fabrication process are described. Methods of selectively depositing iridium-containing films are also described. The methods include exposing a substrate including a metallic material and a dielectric material to an iridium-containing precursor and a reactant to form the iridium-containing film. The iridium-containing film selectively grows on the metallic material relative to the dielectric material.
A plasma coil assembly including a ring-shaped body, an RF electrode positioned within the ring-shaped body, and a dielectric top plate positioned within the ring-shaped body. A semiconductor manufacturing processing chamber including a processing chamber body, a gas distribution assembly, a substrate support, and the plasma coil assembly. A method of selectively etching a substrate surface including forming a process gas, exposing the substrate surface to the process gas to form activated fluorine-containing species, and sublimating the activated fluorine-containing species. A method of etching a substrate surface including exposing the substrate surface to a fluorine-containing plasma and applying a bias voltage to the substrate surface, the fluorine-containing plasma generated by the plasma coil assembly. A method of etching a substrate surface including exposing the substrate surface to an inductively coupled plasma and applying a bias voltage to the substrate surface, the inductively coupled plasma generated by the plasma coil assembly.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
In one embodiment, a physical vapor deposition (PVD) target is provided. The PVD target includes a body having a target region and a backing region. The backing region includes a diameter greater than the diameter of the target region. The target region and backing region have the same coefficient of thermal expansion and the same material.
A showerhead for a semiconductor processing system is provided. In one aspect, a showerhead includes a body that defines a first gas channel formed, at least in part, by injection holes in fluid communication with a distribution cavity in which a plurality of radially-extending ribs of the body define a plurality of radially-extending passages. A first gas is flowable along the first gas channel so that the first gas injected through the injection holes and into the distribution cavity flows radially along the radially-extending passages and so that at least a portion of the first gas flowing along such passages flows through distribution holes extending to a bottom surface of the body. The body also defines a second gas channel formed by a plurality of through holes so that a second gas is flowable therethrough. The first and second gas channels are fluidly isolated from one another within the showerhead.
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C23C 16/50 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
13.
MODELING APPROACH FOR DEVELOPMENT OF GAS INJECTION UNIT WITHIN PROCESSING CHAMBER
A model of a processing chamber with a gas injection unit is used to perform simulated process conditions based on different combinations of parameter values. The simulated process conditions correspond to different measurements of a process variable, such as a etch byproduct removal rate. Based on the simulations, an optimal set of parameter values is determined that optimizes the variable. The gas injection unit is designed in accordance with this optimal set of parameter values.
Methods of manufacturing interconnect structures as part of a microelectronic device fabrication process are described. Methods of selectively depositing iridium-containing films are also described. The methods include exposing a substrate including a metallic material and a dielectric material to an iridium-containing precursor and a reactant to form the iridium-containing film. The iridium-containing film selectively grows on the metallic material relative to the dielectric material.
C23C 16/04 - Coating on selected surface areas, e.g. using masks
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C23C 16/16 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metal carbonyl compounds
C23C 16/18 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metallo-organic compounds
Metal stacks and methods of depositing a metal stack on a semiconductor substrate are disclosed. The metal stack is formed by depositing a molybdenum (Mo) layer on a semiconductor substrate. The molybdenum (Mo) layer is treated with a silane, followed by formation of a nitride layer on the molybdenum (Mo) layer. A metal stack having low resistivity is formed.
iiiiiiiii) a damping circuit coupled to the first node, wherein the damping circuit includes one or more resistive elements. The one or more resistive elements are generally implemented by at least one resistive element with a resistance between 0.1 ohms and 100 ohms.
Embodiments of the disclosure describe a method that includes disposing an electrical insulator material over a layer of a ceramic-based material having vias and solid portions between the vias. The vias are filled with an electrically conductive metal that forms electrical paths through the layer of the ceramic-based material. A composite structure is formed that includes portions of the electrical insulator material that are fixed to the solid portions of the layer of the ceramic-based material. The composite structure further includes regions positioned between the portions of the electrical insulator material. The electrical insulator material has a first coefficient of thermal expansion (CTE), the electrically conductive metal has a second CTE, and the ceramic-based material has a third CTE that is greater than the first CTE and less than the second CTE.
H01B 5/16 - Non-insulated conductors or conductive bodies characterised by their form comprising conductive material in insulating or poorly conductive material, e.g. conductive rubber
H01B 1/02 - Conductors or conductive bodies characterised by the conductive materialsSelection of materials as conductors mainly consisting of metals or alloys
H01B 3/02 - Insulators or insulating bodies characterised by the insulating materialsSelection of materials for their insulating or dielectric properties mainly consisting of inorganic substances
H01B 3/08 - Insulators or insulating bodies characterised by the insulating materialsSelection of materials for their insulating or dielectric properties mainly consisting of inorganic substances quartzInsulators or insulating bodies characterised by the insulating materialsSelection of materials for their insulating or dielectric properties mainly consisting of inorganic substances glassInsulators or insulating bodies characterised by the insulating materialsSelection of materials for their insulating or dielectric properties mainly consisting of inorganic substances glass woolInsulators or insulating bodies characterised by the insulating materialsSelection of materials for their insulating or dielectric properties mainly consisting of inorganic substances slag woolInsulators or insulating bodies characterised by the insulating materialsSelection of materials for their insulating or dielectric properties mainly consisting of inorganic substances vitreous enamels
H01B 19/04 - Treating the surfaces, e.g. applying coatings
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
In one or more embodiments, a sub-pixel circuit includes at least two isolation structures disposed over a substrate, wherein adjacent isolation structures define a well. Anodes are disposed over an upper surface of the isolation structures. The sub-pixel circuit further includes overhang structures. The overhang structures have a layer including an upper portion having a bottom surface disposed on an outer portion of the anodes. The layer further includes a lower portion with a lowermost surface disposed on the isolation structures and extending past a sidewall of the isolation structures and over the well. The layer further includes an upper sidewall, adjacent upper sidewalls defining an opening of the well. The sub-pixel circuit further includes an organic light emitting diode (OLED) material, a cathode, and an encapsulation layer.
Metal stacks and methods of depositing a metal stack on a semiconductor substrate are disclosed. The metal stack is formed by depositing a molybdenum (Mo) layer on a semiconductor substrate. The molybdenum (Mo) layer is treated with a silane, followed by formation of a nitride layer on the molybdenum (Mo) layer. A metal stack having low resistivity is formed.
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
A substate gripper includes a first plate, a second plate, and a plurality of arms coupled with the first plate and the second plate. Each of the plurality of arms includes at least one flexure member configured to flex responsive to movement of the second plate with respect to the first plate. Flexure of the flexure members of the plurality of arms causes respective ends of the plurality of arms to perform a gripping action to grip a substrate.
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
21.
MICROWAVE PLASMA SOURCE WITH NON-CYLINDRICAL CAVITY ANTENNAS
Embodiments described herein relate to an apparatus that includes a plate, where the plate includes a first dielectric material, and a resonator coupled to the plate. In an embodiment, the resonator includes a second dielectric material, and the resonator has a cross-sectional shape with a first end with a first width and a second end with a second width that is smaller than the first width. In an embodiment, the first end faces the plate.
Embodiments described herein generally relate to processes for back end of line advanced packaging assembly. More particularly, embodiments described herein relate to processes for activating silicon surfaces for hydrophilic silicon direct bonding applications. In at least one embodiment, a method for activating a substrate is provided. The method includes providing a substrate into a process chamber, the substrate including a plurality of patterned structures, at least one metal layer and a silicon surface, and curing the silicon surface of the substrate. The curing process includes flowing one or more gases into the process chamber, the one or more gases including ozone, and providing UV light while operating the process chamber at a temperature of about 25° C. to about 300° C. A plurality of oxygen radicals are formed from the ozone and reacted with the silicon surface of the substrate to form an activated surface.
An ophthalmic lens is provided. The ophthalmic lens includes a lens stack having an eye-side (ES) lens, a world-side (WS) lens, a waveguide disposed between the ES lens and the WS lens, and one or more adhesive layers securing at least the ES lens to the waveguide and at least the WS lens to the waveguide. Further, the ophthalmic lens includes a retainer engaging the ES lens and the WS lens and being arranged to mechanically hold the lens stack together and resist delamination forces of the lens stack.
Embodiments of substrate supports are provided herein. In some embodiments, a substrate support includes: a ceramic plate having a first side configured to support a substrate and a second side, wherein the ceramic plate includes an electrode embedded in the ceramic plate; a first cooling plate coupled to the second side of the ceramic plate; a ceramic ring disposed about the ceramic plate and having a first side and a second side, wherein the ceramic ring includes one or more chucking electrodes and a heating element disposed in the ceramic ring, wherein the ceramic ring is spaced apart from the ceramic plate and the first cooling plate; a second cooling plate coupled to the second side of the ceramic ring, wherein the second cooling plate is thermally isolated from the first cooling plate; and a sealing element disposed adjacent to the ceramic ring and the ceramic plate.
A method of forming a bonded device. The method may include providing a carrier substrate, forming, on a first surface of the carrier substrate, a first bonding layer for bonding to a device substrate, and annealing the first bonding layer at a temperature of greater than 600° C.
A model of a processing chamber with a gas injection unit is used to perform simulated process conditions based on different combinations of parameter values. The simulated process conditions correspond to different measurements of a process variable, such as a etch byproduct removal rate. Based on the simulations, an optimal set of parameter values is determined that optimizes the variable. The gas injection unit is designed in accordance with this optimal set of parameter values.
Embodiments of slit door assemblies for use in a process chamber are provided herein. In some embodiments, a slit door assembly comprises: a slit door having an arcuate profile and a first surface comprising a plasma facing surface and a second surface opposite the first surface, and wherein at least one of: the first surface or the second surface includes a recessed portion along a peripheral edge thereof; or the slit door has an annular shape; and an actuator assembly coupled to the slit door and configured to move the slit door in a vertical direction, wherein the actuator assembly includes a plurality of rods coupled to the slit door, wherein one or more of the plurality of rods include a cooling channel extending to the slit door or a heater.
In some embodiments, a method includes positioning a semiconductor structure within a processing chamber. The semiconductor structure includes a first layer disposed over a substrate surface. The semiconductor structure further includes a second layer disposed over the first layer. The second layer has a hardmask layer. The semiconductor structure further includes one or more second dielectric layers disposed over the second layer. The one or more second dielectric layers have a gap formed over a portion of the second layer. The semiconductor structure further includes a metal material disposed within the gap formed over the second layer. The metal material has a molybdenum oxide (MoOx) layer. The method further includes flowing a process gas into the processing chamber, and performing a redox operation on a portion of the semiconductor structure to reduce the MoOx to molybdenum (Mo). The redox operation includes applying a microwave energy to the process gas.
Embodiments described herein relate to a method that includes obtaining a set of spectral data and a set of critical dimension (CD) data from a plurality of substrates, and extracting a spectral feature from the set of spectral data and a CD feature from the set of CD data with a feature extraction process. In an embodiment, the method further comprises implementing a first radial basis decomposition process on the spectral feature and a second radial basis decomposition process on the CD feature to develop a spectral radial basis decomposition coefficient and CD radial basis decomposition coefficient, and identifying a causal relationship between the spectral radial basis decomposition coefficient and the CD radial basis decomposition coefficient based on a temporal trend.
An ophthalmic lens is provided. The ophthalmic lens includes a lens stack having an eye-side (ES) lens, a world-side (WS) lens, a waveguide disposed between the ES lens and the WS lens, and one or more adhesive layers securing at least the ES lens to the waveguide and at least the WS lens to the waveguide. Further, the ophthalmic lens includes a retainer engaging the ES lens and the WS lens and being arranged to mechanically hold the lens stack together and resist delamination forces of the lens stack.
Embodiments of the present disclosure generally relate to an injector assembly for use in a processing chamber, and related components and methods. In one or more embodiments, a method of substrate processing includes performing an ignition process including flowing a plasma gas into a plasma volume and igniting the plasma gas into a plasma. The method further includes performing a deposition process including flowing a processing gas into an internal volume of a process chamber and across a substrate in the internal volume and depositing a deposition structure over the substrate. The method further includes performing an insertion process including flowing an insertion gas for a time of less than 5 seconds into the plasma within the plasma volume to form effluents from the insertion gas, flowing the effluents into the internal volume and across the substrate in the internal volume, and inserting the effluents into the deposition structure.
Embodiments of slit door assemblies for use in a process chamber are provided herein. In some embodiments, a slit door assembly comprises: a slit door having an arcuate profile and a first surface comprising a plasma facing surface and a second surface opposite the first surface, and wherein at least one of: the first surface or the second surface includes a recessed portion along a peripheral edge thereof; or the slit door has an annular shape; and an actuator assembly coupled to the slit door and configured to move the slit door in a vertical direction, wherein the actuator assembly includes a plurality of rods coupled to the slit door, wherein one or more of the plurality of rods include a cooling channel extending to the slit door or a heater.
A model of a processing chamber with a gas injection unit is used to perform simulated process conditions based on different combinations of parameter values. The simulated process conditions correspond to different measurements of a process variable, such as a etch byproduct removal rate. Based on the simulations, an optimal set of parameter values is determined that optimizes the variable. The gas injection unit is designed in accordance with this optimal set of parameter values.
Exemplary semiconductor processing methods may include providing one or more first etchant precursors to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region. A plurality of pairs of silicon oxide material and polysilicon material may be disposed on the substrate. The methods may include forming plasma effluents of the one or more first etchant precursors and contacting the substrate with the plasma effluents of the one or more first etchant precursors to selectively etch silicon oxide material. The methods may include providing one or more second etchant precursors to the processing region, forming plasma effluents of the one or more second etchant precursors, and contacting the substrate with the plasma effluents of the one or more second etchant precursors to selectively etch polysilicon material. A temperature within the processing region may be greater than or about 0 °C.
The present disclosure generally relates to modulating pressure within an inner chamber of a processing chamber and/or modulating velocity of a processing gas. The processing chamber comprises a chamber, a gas inlet configured to flow processing gas into the chamber, an exhaust configured to remove processing gas from the chamber, a substrate holder disposed between the gas inlet and the exhaust, and a first injector configured to pulse inert or process gas into the chamber. In one embodiment, the processing chamber further comprises a second injector configured to pulse the inert gas into the chamber, where the first injector pulses inert gas before the substrate holder and the second injector pulses inert gas after the substrate holder. In another embodiment, the processing chamber comprises a pressure control valve configured to close or partially close being processing of a substrate to constrict the exhaust.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C23C 16/46 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for heating the substrate
36.
SUBSTRATE DEFECT TROUBLESHOOTING ANALYSIS USING MACHINE LEARNING
A method includes obtaining, by a processing device, defect data for a substrate processed in a substrate processing system. The method further includes obtaining, by the processing device, context data associated with the substrate. The method further includes determining a troubleshooting guide associated with the defect data. The troubleshooting guide includes a sequence of troubleshooting operations, each associated with one or more probably root causes for the defect data. The method further includes determining a subset of context data based on the troubleshooting guide. The method further includes processing the defect data and the subset of context data using one or more trained machine learning models that output a predicted corrective action associated with a troubleshooting operation in the sequence of troubleshooting operations. The method further includes initiating the corrective action.
Embodiments of the disclosure describe a method that includes disposing an electrical insulator material over a layer of a ceramic-based material having vias and solid portions between the vias. The vias are filled with an electrically conductive metal that forms electrical paths through the layer of the ceramic-based material. A composite structure is formed that includes portions of the electrical insulator material that are fixed to the solid portions of the layer of the ceramic-based material. The composite structure further includes regions positioned between the portions of the electrical insulator material. The electrical insulator material has a first coefficient of thermal expansion (CTE), the electrically conductive metal has a second CTE, and the ceramic-based material has a third CTE that is greater than the first CTE and less than the second CTE.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
Exemplary modular gas blocks may include a body having an inlet end and an outlet end. The body may define a first fluid channel extending along a length and may define a second fluid channel extending along a width. The inlet end may define a fluid inlet that is coupled with the first fluid channel. The outlet end may define a first fluid outlet that is coupled with the first fluid channel. An upper surface of the body may define a first fluid port that is coupled with the fluid inlet via the first fluid channel. The upper surface of the body may define a second fluid port that is coupled with the second fluid channel. The body may define a third fluid port that is coupled with the second fluid port via the second fluid channel.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
40.
GREYSCALE LITHOGRAPHY FOR SUBSTRATE TOPOGRAPHY CORRECTION
A method of substrate topography correction. The method may include receiving a thickness map of a substrate, the thickness map defining a total thickness variation across the substrate, and providing a greyscale photoresist layer on a first surface of the substrate. The method may further include performing a greyscale lithography operation on the greyscale photoresist layer, based upon the thickness map, wherein the greyscale lithography operation is to reduce the total thickness variation.
G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor
G03F 7/213 - Exposing with the same light pattern different positions of the same surface at the same time
41.
CHEMICAL PROCESS ENHANCEMENT THROUGH MODULATION OF GAS OR PRESSURE CONTROL
The present disclosure generally relates to modulating pressure within an inner chamber of a processing chamber and/or modulating velocity of a processing gas. The processing chamber comprises a chamber, a gas inlet configured to flow processing gas into the chamber, an exhaust configured to remove processing gas from the chamber, a substrate holder disposed between the gas inlet and the exhaust, and a first injector configured to pulse inert or process gas into the chamber. In one embodiment, the processing chamber further comprises a second injector configured to pulse the inert gas into the chamber, where the first injector pulses inert gas before the substrate holder and the second injector pulses inert gas after the substrate holder. In another embodiment, the processing chamber comprises a pressure control valve configured to close or partially close being processing of a substrate to constrict the exhaust.
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
A system for transferring a substrate from a high pressure area to a low pressure area is provided. The system includes a load lock chamber that includes: a chamber body disposed around an interior volume; a first substrate support; a first exhaust inlet; and a first baffle positioned between the first substrate support and the first exhaust inlet. The system further includes a first exhaust line fluidly coupled to the interior volume through the first exhaust inlet.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
43.
HYBRID INDUCTIVELY COUPLED PLASMA SOURCE FOR ION AND RADICAL ETCHING
An apparatus for an inductively coupled plasma (ICP) chamber provides both high power and low power etching capabilities in a single chamber. In some embodiments, the apparatus may comprise a dielectric tube positioned vertically along a central axis of at least one planar coil perpendicular to and surrounding the dielectric tube and has a first end with a first opening with a first diameter and a second end with a second opening with a second diameter smaller than the first opening and is configured to contain inductively coupled plasma, at least one electromagnetic coil surrounding the dielectric tube that is configured to control ions or plasma internally in the dielectric tube, and at least one coil surrounding the dielectric tube above the planar coil where the at least one coil is configured to generate inductively coupled plasma internally in the dielectric tube.
A system for transferring a substrate from a high pressure area to a low pressure area is provided. The system includes a load lock chamber that includes: a chamber body disposed around an interior volume; a first substrate support; a first exhaust inlet; and a first baffle positioned between the first substrate support and the first exhaust inlet. The system further includes a first exhaust line fluidly coupled to the interior volume through the first exhaust inlet.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
Systems, methods, and apparatus including designs embodied in machine-readable media for exhaust control. One of the methods includes measuring an airflow through an exhaust path of a gas panel of a semiconductor processing system; determining whether the measured airflow is within a defined range; in response to determining that the measured airflow is outside of the defined range, selectively opening or closing the exhaust gate by an incremental amount.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
F16K 31/02 - Operating meansReleasing devices electricOperating meansReleasing devices magnetic
F16K 3/00 - Gate valves or sliding valves, i.e. cut-off apparatus with closing members having a sliding movement along the seat for opening and closing
F16K 37/00 - Special means in or on valves or other cut-off apparatus for indicating or recording operation thereof, or for enabling an alarm to be given
Gas distribution inserts configured to deliver a gas in semiconductor manufacturing processing chambers are described. The gas distribution insert comprises a plurality of randomly oriented gas openings extending through the thickness of the inlet end wall. An inner gas channel extends from the outlet end wall face to the insert outlet end, and the inner gas channel is bounded by an inner gas channel sidewall. The gas distribution inserts include at least two gas inlets extending through the inner gas channel sidewall.
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
47.
PULSED VOLTAGE WAVEFORM WITH BINARY PULSES FOR BIASING OF PLASMA
Methods and apparatus for forming a discrete multimodal ion energy distribution function (lEDF)-containing plasma. One example method generally includes generating a first burst of a first plurality of pulses by delivering, in a first pulsing state, a first pulse of the first plurality of pulses within a first burst of pulses, and delivering, in the first pulsing state, a second pulse of the first plurality of pulses within the first burst of pulses. The example method also generally incudes generating a second burst of a second plurality of pulses by delivering, in a second pulsing state, a third pulse of the second plurality of pulses within a second burst of pulses, and delivering, in the second pulsing state, a fourth pulse of the second plurality of pulses within the second burst of pulses, where the first voltage, the second voltage, the third voltage, and the fourth voltage are each different.
Methods and structure for gate-all-around (GAA) semiconductor device that can support multiple threshold voltages. The semiconductor device can include a first channel. The first channel can overlaid by a first dielectric layer. The first dielectric layer can be overlaid by a second dielectric layer. The semiconductor device can include a second channel. The second channel can be overlaid by a third dielectric layer. The first dielectric layer can be a doped dielectric layer. The third dielectric layer can be overlaid by a fourth dielectric layer. The semiconductor device can include a work-function metal layer overlaying the second dielectric layer and the fourth dielectric layer. The work-function metal layer can have a uniform thickness.
Embodiments described herein include a device and method of for depositing a film. The method includes receiving a substrate in a process volume. The substrate includes structures thereon having varying critical dimensions. A plasma is formed in the process volume using a process gas. The plasma is formed by pulsing a combination of high frequency (HF) power and low frequency (LF) power. The film is deposited over a surface of the substrate. The film is deposited in a trench between adjacent structures, and wherein the film is formed from a precursor gas.
C23C 16/50 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
C23C 16/04 - Coating on selected surface areas, e.g. using masks
C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
C23C 16/52 - Controlling or regulating the coating process
Exemplary modular gas blocks may include a body having an inlet end and an outlet end. The body may define a first fluid channel extending along a length and may define a second fluid channel extending along a width. The inlet end may define a fluid inlet that is coupled with the first fluid channel. The outlet end may define a first fluid outlet that is coupled with the first fluid channel. An upper surface of the body may define a first fluid port that is coupled with the fluid inlet via the first fluid channel. The upper surface of the body may define a second fluid port that is coupled with the second fluid channel. The body may define a third fluid port that is coupled with the second fluid port via the second fluid channel.
Methods and systems for input/output (IO) handling during an update process for a manufacturing system controller are provided. A detection is made that process control instructions corresponding to a process recipe are to be updated. A set of notifications is transmitted between component(s) of the manufacturing system and a system update IO handler of the system controller. The notifications include commands which, upon execution, cause the manufacturing system component(s) to maintain an environment of the manufacturing system at a target condition while the process control instructions are updated. Following a completion of the update and upon determining that the condition of the environment satisfies one or more criteria associated with the target condition, additional notifications are transmitted between the component(s) and a system process IO handler to initiate performance of a process at the manufacturing system.
G05B 19/042 - Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
52.
IN-SITU REFLECTOMETRY FOR REAL-TIME PROCESS CONTROL
In one implementation, a method of monitoring film thickness on a substrate, comprises: generating light from a light source; collimating the light from the light source to form a collimated beam; reflecting the collimated beam off of a surface to be measured to produce a reflected beam; splitting the reflected beam with a dichroic mirror, wherein the reflected beam splits into a first beam and a second beam; receiving, by a pyrometer, the first beam from the dichroic mirror; receiving, by a spectrometer, the second beam from the dichroic mirror; and analyzing data derived from the pyrometer and the spectrometer to determine one or more characteristics of the surface to be measured.
Methods and structure for gate-all-around (GAA) semiconductor device that can support multiple threshold voltages. The semiconductor device can include a first channel. The first channel can overlaid by a first dielectric layer. The first dielectric layer can be overlaid by a second dielectric layer. The semiconductor device can include a second channel. The second channel can be overlaid by a third dielectric layer. The first dielectric layer can be a doped dielectric layer. The the third dielectric layer can be overlaid by a fourth dielectric layer. The semiconductor device can include a work-function metal layer overlaying the second dielectric layer and the fourth dielectric layer. The work-function metal layer can have a uniform thickness
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
Methods and apparatus for forming a discrete multimodal ion energy distribution function (IEDF)-containing plasma. One example method generally includes generating a first burst of a first plurality of pulses by delivering, in a first pulsing state, a first pulse of the first plurality of pulses within a first burst of pulses, and delivering, in the first pulsing state, a second pulse of the first plurality of pulses within the first burst of pulses. The example method also generally incudes generating a second burst of a second plurality of pulses by delivering, in a second pulsing state, a third pulse of the second plurality of pulses within a second burst of pulses, and delivering, in the second pulsing state, a fourth pulse of the second plurality of pulses within the second burst of pulses, where the first voltage, the second voltage, the third voltage, and the fourth voltage are each different.
Described herein is a method for detecting contaminations in a process chamber is provided. The method includes flowing a gas into a process chamber, and igniting a flame in the process chamber at a contact region between the gas a surface in the process chamber. The method may also include measuring one or more properties of the flame using an optical sensor, and identifying a contamination on the surface based on the one or more properties of the flame.
Methods and apparatus for processing a substrate are provided herein. In some embodiments, a method of processing a substrate includes: forming a first patterned mask on a substrate made of glass; etching exposed portions of the substrate to form a plurality of blind vias; removing the first patterned mask; forming a second patterned mask on the substrate after removing the first patterned mask; etching exposed second portions of the substrate to form a redistribution layer (RDL) pattern at an upper portion of at least one of the plurality of blind vias; depositing a seed layer in the plurality of blind vias and the RDL pattern; and filling the plurality of blind vias and the RDL pattern with a metal material to form a plurality of filled vias and a redistribution layer (RDL).
In one embodiment, a physical vapor deposition (PVD) target is provided. The PVD target includes a body having a target region and a backing region. The backing region includes a diameter greater than the diameter of the target region. The target region and backing region have the same coefficient of thermal expansion and the same material.
A method includes obtaining, by a processing device, defect data for a substrate processed in a substrate processing system. The method further includes obtaining, by the processing device, context data associated with the substrate. The method further includes determining a troubleshooting guide associated with the defect data. The troubleshooting guide includes a sequence of troubleshooting operations, each associated with one or more probably root causes for the defect data. The method further includes determining a subset of context data based on the troubleshooting guide. The method further includes processing the defect data and the subset of context data using one or more trained machine learning models that output a predicted corrective action associated with a troubleshooting operation in the sequence of troubleshooting operations. The method further includes initiating the corrective action.
A system includes a factory interface, a load port, and a controller. The controller detects when a container is received at the load port, where the container stores one or more parts. The controller directs a detection system, via one or more robot arms, to move according to one or more mapping patterns to obtain a mapping of the container, indicating regions and positions of detected parts. This mapping is recorded in a storage medium. Based on the mapping, the controller identifies any misalignment or misorientation of detected parts within the container. If such an issue is detected, the controller transmits an error message to a system controller associated with the manufacturing system, specifying the misalignment or misorientation of the affected part.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/673 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components using specially adapted carriers
A showerhead for a semiconductor processing system is provided. In one aspect, a showerhead includes a body that defines a first gas channel formed, at least in part, by injection holes in fluid communication with a distribution cavity in which a plurality of radially-extending ribs of the body define a plurality of radially-extending passages. A first gas is flowable along the first gas channel so that the first gas injected through the injection holes and into the distribution cavity flows radially along the radially-extending passages and so that at least a portion of the first gas flowing along such passages flows through distribution holes extending to a bottom surface of the body. The body also defines a second gas channel formed by a plurality of through holes so that a second gas is flowable therethrough. The first and second gas channels are fluidly isolated from one another within the showerhead.
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
61.
GENERATION OF SYNTHETIC FAULT IMAGES OF SEMICONDUCTOR SPECIMENS
The presently disclosed subject matter includes a computer system and a computer-implemented method of generating synthetic examination output images, including synthetic fault images and synthetic fault-free images. The synthetic fault images comprise artificially generated 3D defects. The proposed technique enables fast, accurate, and efficient generation of a large and diverse collection of synthetic fault images and fault-free images, which can be implemented in runtime, as part of the examination process of semiconductor specimens.
Methods and systems for cleaning for a chemical mechanical polishing system, including moving a carrier head of the chemical mechanical polishing system over a treatment station of the chemical mechanical polishing system; pressurizing a first pressurizable chamber of the carrier head, the first pressurizable chamber arranged between a membrane assembly and a lower carrier body of the carrier head, such that a membrane assembly arranged beneath the lower carrier body is displaced from a home position; and directing a gas from an orifice of the treatment station onto a component of the carrier head to clean polishing by-product off the component.
B24B 55/06 - Dust extraction equipment on grinding or polishing machines
B24B 57/02 - Devices for feeding, applying, grading or recovering grinding, polishing or lapping agents for feeding of fluid, sprayed, pulverised, or liquefied grinding, polishing or lapping agents
B24B 37/30 - Work carriers for single side lapping of plane surfaces
A carrier head for positioning a substrate on a polishing surface includes a housing, a support comprising multiple channels therethrough, and a plurality of pressure control elements secured within the multiple channels of the support. Each pressure control element includes an electromagnetic actuator, a first flexible membrane secured to the support such that portions of the first flexible membrane extending from each channel to define a balloon at each channel with each balloon defining a chamber such that actuation of the electromagnetic actuator adjusts a gas pressure in the respective chamber, and a pressure sensor arranged within the chamber.
B24B 37/30 - Work carriers for single side lapping of plane surfaces
B24B 37/005 - Control means for lapping machines or devices
B24B 37/10 - Lapping machines or devicesAccessories designed for working plane surfaces characterised by the movement of the work or lapping tool for single side lapping
H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
An apparatus includes a body configured to support a substrate, a first coating, conformal on a surface of the body, that is corrosion resistant to at least one of: boron trichloride, nitrogen trifluoride, hafnium tetrachloride, aluminum trichloride, oxygen gas, chlorine gas, fluorine gas, chlorine trifluoride, hydrogen fluoride, hydrogen gas, ammonia, tungsten hexafluoride, tetrafluoromethane, titanium tetrachloride, molybdenum pentachloride, ozone, tetrafluorosilane, or hexafluoroethane, and a second coating, on the first coating, having a hardness that greater than or equal to about 8 gigapascals.
C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
C23C 14/06 - Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
65.
ION IMPLANTER, CONTROL SYSTEM, AND TECHNIQUES FOR TUNING BUNCHER OF ION IMPLANTER
An ion implanter. The ion implanter may include an ion source to generate an ion beam, and a linear accelerator, downstream to the ion source. The linear accelerator may include a buncher system to receive the ion beam and output a bunched ion beam, and a plurality of acceleration stages, to accelerate the bunched ion beam. The buncher system may include at least one RF buncher, a controller to adjust at least one control parameter of the at least one RF buncher over a plurality of instances; and a beam monitor, disposed downstream of at least one RF buncher, and arranged to perform a plurality of beam measurements of the bunched ion beam over the plurality of instances. As such, the controller may be further arranged to determine a focal length of the buncher based upon the plurality of beam measurements.
H01J 37/317 - Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. ion implantation
H01J 37/04 - Arrangements of electrodes and associated parts for generating or controlling the discharge, e.g. electron-optical arrangement, ion-optical arrangement
A method of substrate topography correction. The method may include receiving a thickness map of a substrate, the thickness map defining a total thickness variation across the substrate, and providing a greyscale photoresist layer on a first surface of the substrate. The method may further include performing a greyscale lithography operation on the greyscale photoresist layer, based upon the thickness map, wherein the greyscale lithography operation is to reduce the total thickness variation.
H01L 21/308 - Chemical or electrical treatment, e.g. electrolytic etching using masks
H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor
The present disclosure describes a filter assembly for a heater line of a processing chamber. The filter assembly includes a first impedance producing element, a first air core inductor, and a second air core inductor. The first impedance producing element includes a first conductive lead and a second conductive lead wound around a first toroid shaped core. A first end of the first conductive lead and a first end of the second conductive lead are coupled to an output of an electric device. The first air core inductor is electrically connected with the first conductive lead. The second air core inductor is electrically connected with the second conductive lead.
Embodiments of the present disclosure generally relate to semiconductor processing equipment. In one or more embodiments, a flow adapter for mounting to a processing chamber includes a first flange, a second flange, and a conduit extending at least partially between the first flange and the second flange. The conduit includes an outer face, an inner flow opening, and one or more angled flow openings extending between the outer face and the inner flow opening. The one or more angled flow openings are oriented at an oblique angle relative to the inner flow opening.
Exemplary modular gas blocks may include a dual gas block that includes a block body having an inlet, a first outlet, and a second outlet. The block body may define a fluid channel extending along a length of the block body. The inlet end of the block body may define a fluid inlet that is fluidly coupled with the fluid channel. The first outlet of the block body may define a first fluid outlet that is fluidly coupled with the fluid channel. The second outlet of the block body may define a second fluid outlet that is fluidly coupled with the fluid channel.
Methods and apparatus for processing a substrate are provided herein. In some embodiments, a method of processing a substrate includes: forming a first patterned mask on a substrate made of glass; etching exposed portions of the substrate to form a plurality of blind vias; removing the first patterned mask; forming a second patterned mask on the substrate after removing the first patterned mask; etching exposed second portions of the substrate to form a redistribution layer (RDL) pattern at an upper portion of at least one of the plurality of blind vias; depositing a seed layer in the plurality of blind vias and the RDL pattern; and filling the plurality of blind vias and the RDL pattern with a metal material to form a plurality of filled vias and a redistribution layer (RDL).
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/528 - Layout of the interconnection structure
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
09 - Scientific and electric apparatus and instruments
Goods & Services
Semiconductor wafer processing equipment, namely,
semiconductor processing chambers used to deposit chemical
elements on wafer substrates. Recorded software for use in connection with deposition of
chemical elements on wafer substrates.
09 - Scientific and electric apparatus and instruments
Goods & Services
Semiconductor wafer processing equipment, namely,
semiconductor processing chambers used to deposit chemical
elements on wafer substrates. Recorded software for use in connection with deposition of
chemical elements on wafer substrates.
73.
PREVENTION OF CONTAMINATION OF SUBSTRATES DURING PRESSURE CHANGES IN PROCESSING SYSTEMS
Disclosed are implementations for minimizing substrate contamination during pressure changes in substrate processing systems. Over a duration of a pressure change (increase or decrease) in a chamber of a substrate processing system, a flow rate is adjusted multiple times to reduce occurrence of contaminant particles in an environment of the chamber. In some instances, the flow rate is changed continuously using at least one dynamic valve that enable continuous control over the pressure dynamics of the chamber.
F24F 11/49 - Control or safety arrangements for purposes related to the operation of the system, e.g. for safety or monitoring ensuring correct operation, e.g. by trial operation or configuration checks
F24F 11/74 - Control systems characterised by their outputsConstructional details thereof for controlling the supply of treated air, e.g. its pressure for controlling air flow rate or air velocity
The present disclosure relates to flow guide arrangements for gas activation and gas distribution, and related chamber kits, methods, and processing chambers. In one or more embodiments, a processing chamber includes a chamber body at least partially defining an internal volume, one or more heat sources operable to heat the internal volume, a substrate support disposed in the internal volume, and one or more inlet openings configured to direct a gas across a gas flow path over the substrate support and to one or more exhaust outlets. The processing chamber includes a flow guide disposed in the internal volume. The flow guide includes a first guide block, a second guide block disposed opposite the first guide block with respect to the gas flow path, and a flange connecting the first guide block and the second guide block.
C30B 25/14 - Feed and outlet means for the gasesModifying the flow of the reactive gases
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C23C 16/46 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for heating the substrate
C30B 25/08 - Reaction chambersSelection of materials therefor
C30B 25/10 - Heating of the reaction chamber or the substrate
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
Systems, methods, and apparatus including designs embodied in machine-readable media for exhaust control. One of the methods includes measuring an airflow through an exhaust path of a gas panel of a semiconductor processing system; determining whether the measured airflow is within a defined range; in response to determining that the measured airflow is outside of the defined range, selectively opening or closing the exhaust gate by an incremental amount.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
Gas distribution inserts configured to deliver a gas in semiconductor manufacturing processing chambers are described. The gas distribution insert comprises a plurality of randomly oriented gas openings extending through the thickness of the inlet end wall. An inner gas channel extends from the outlet end wall face to the insert outlet end, and the inner gas channel is bounded by an inner gas channel sidewall. The gas distribution inserts include at least two gas inlets extending through the inner gas channel sidewall.
Embodiments described herein include a device and method of for depositing a film. The method includes receiving a substrate in a process volume. The substrate includes structures thereon having varying critical dimensions. A plasma is formed in the process volume using a process gas. The plasma is formed by pulsing a combination of high frequency (HF) power and low frequency (LF) power. The film is deposited over a surface of the substrate. The film is deposited in a trench between adjacent structures, and wherein the film is formed from a precursor gas.
Embodiments described herein relate to a method for transferring a pattern in a resist layer into a patterning stack under the resist layer. In an embodiment, the method includes treating the resist layer with a treatment that incorporates sulfur into a surface of the resist layer after the pattern is formed in the resist layer, and transferring the pattern in the resist layer into the patterning stack.
The presently disclosed subject matter includes a computer system and a computer-implemented method of generating synthetic examination output images, including synthetic fault images and synthetic fault-free images. The synthetic images comprise artificially generated 3D defects. A machine learning model is trained for transforming examination output images to height maps. The height maps are modified to include certain 3D features, and a second machine learning model is used for transforming the height maps to modified examination output images to exhibit the 3D features.
A circuit includes a switching thin film transistor (TFT), the switching TFT having a threshold voltage that is based on a value of a direct current (DC) voltage, a driving TFT coupled to the switching TFT, a storage capacitor disposed between the switching TFT and the driving TFT, and an organic light-emitting diode (OLED) having an anode coupled to the driving TFT.
G09G 3/3233 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
H10K 59/121 - Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
81.
VARIABLE CONDUCTANCE EDGE RING FOR VAPOR DEPOSITION CHAMBER
Substrate processing chamber gas distribution assemblies and methods utilizing of processing substrates using the same are described. The gas distribution assembly includes an edge ring having a lower surface configured to be supported on a substrate processing chamber pedestal and an upper surface, the lower surface and the upper surface defining an edge ring thickness, the substrate processing chamber edge ring having a first edge ring thickness at a first edge of the ring-shaped body that is greater than a second edge ring thickness at a second edge opposite the first edge of the substrate processing chamber edge ring.
C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
82.
LASER HEATING ARRANGEMENTS FOR INJECTION GAS ACTIVATION, AND RELATED PROCESSING CHAMBERS, APPARATUS, AND METHODS
The present disclosure relates to pre-heating process gases for activation, such as for low-temperature processing, and related chamber kits, methods, and processing chambers. In one or more embodiments, a substrate processing chamber includes a chamber body at least partially defining an internal volume, a substrate support disposed in the internal volume, and a flow inlet assembly operable to flow a gas into the internal volume. The flow inlet assembly includes an injector, an opening formed in the injector, and a flow guide disposed in the opening. The flow guide includes an inner surface and an outer surface, and the flow guide is in fluid communication with the internal volume. The flow inlet assembly includes one or more heating elements disposed within the opening, and an absorptive mass disposed within the flow guide.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
83.
LINE EDGE ROUGHNESS REDUCTION THROUGH APPLICATION OF TENSILE STRESS
Embodiments described herein relate to a method, that obtaining a substrate with a patterned resist layer positioned over a patterning stack, wherein the patterned resist layer comprises a first low frequency roughness. In an embodiment, the method further includes forming a capping layer on the patterned resist layer. In an embodiment, a bottom of the patterned resist layer is exposed, and the patterned resist layer has a second low frequency line edge roughness that is lower than the first low frequency line edge roughness after the capping layer is formed.
Embodiments of the present disclosure relate to devices and methods related to gas reservoirs for fast delivery of gases to a processing chamber for processing of a substrate. The gas reservoir includes a first surface and a second surface, the first surface defining a length of the gas reservoir, and the second surface defining a height of the gas reservoir; a plurality of compartments, each compartment operable to hold a gas, and at least two compartments include heating capabilities, a splitter where the splitter is disposed below the plurality of compartments and the splitter is coupled to a gas panel and a valve block, a plurality of gas panel gas lines, and a plurality of gas reservoir gas lines.
C23C 16/448 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for generating reactive gas streams, e.g. by evaporation or sublimation of precursor materials
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
C23C 16/52 - Controlling or regulating the coating process
Embodiments described herein relate to a method for transferring a pattern in a resist layer into a patterning stack under the resist layer. In an embodiment, the method includes treating the resist layer with a treatment that incorporates sulfur into a surface of the resist layer after the pattern is formed in the resist layer, and transferring the pattern in the resist layer into the patterning stack.
G03F 7/40 - Treatment after imagewise removal, e.g. baking
H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
86.
MACHINE LEARNING BASED VIRTUAL SENSING OF WAFER TEMPERATURES DURING REFLOW PROCESS IN A PHYSICAL VAPOR DEPOSITION CHAMBER WITH UNCERTAIN CHAMBER PHYSICAL PROPERTIES AND VARYING OPERATING CONDITIONS
Methods and devices for determining a temperature of a substrate during processing are provided herein. Embodiments include extracting modes from a virtual model of thermal conditions within a processing chamber. Embodiments further include receiving thermal sensor data associated with a target substrate. Embodiments further include using compressed sensing to generate a thermal map for the target substrate based on the thermal sensor data and the extracted modes.
G05B 13/02 - Adaptive control systems, i.e. systems automatically adjusting themselves to have a performance which is optimum according to some preassigned criterion electric
Embodiments of the disclosure include a method of forming a device package, comprising forming a device containing layer over a supporting surface of a first substrate, wherein forming the device containing layer comprises: forming a plurality of first openings in a first dielectric layer that is formed over a first conductive layer; forming a second conductive layer on first portions of the first conductive layer to form a pillar in each of the first openings; removing the first dielectric layer, wherein a second portion of the first conductive layer is exposed after removing the first dielectric layer, and the second portion of the first conductive layer is disposed over a first portion of the first substrate; removing the second portion of the first conductive layer; positioning one or more electronic devices over the first portion of the first substrate and adjacent to a pillar; depositing a molding material over the pillars and the one or more electronic devices; and forming, by use of a material removal process, a planar surface that comprises a portion of the molding material, a portion of the one or more electronic devices, and a portion of the pillars.
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 23/528 - Layout of the interconnection structure
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/00 - Details of semiconductor or other solid state devices
88.
MOVABLE CENTRAL REFLECTORS OF SEMICONDUCTOR PROCESSING EQUIPMENT, AND RELATED SYSTEMS AND METHODS
The present disclosure relates to a radiation reflector assembly for use with a semiconductor processing chamber and a substrate processing system having the radiation reflector assembly. The radiation reflector assembly includes a shell body that includes an interior cylindrical wall; and a reflector disk that includes a center hole, a bottom reflective surface, and a top surface. The reflector disk is disposed within and spaced from the interior cylindrical wall in a manner that permits fluid to flow therebetween. The radiation reflector assembly includes an actuator coupled to the reflector disk, and the actuator is operable to axially displace the reflector disk relative to the shell body. The radiation reflector assembly includes an elongated tube extending through the center hole of the reflector disk. A method of processing a substrate with the radiation reflector assembly is also described.
C30B 25/10 - Heating of the reaction chamber or the substrate
C23C 16/46 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for heating the substrate
89.
GATE-ALL-AROUND TRANSISTORS AND METHODS OF FORMING
Approaches herein provide devices and methods for forming optimized gate-all-around transistors. One method may include forming a plurality of nanosheets each comprising a plurality of alternating first layers and second layers, and etching the plurality of nanosheets to laterally recess the second layers relative to the first layers. The method may further include forming an inner spacer over the recessed second layers by forming a spacer material along an exposed portion of each of the plurality of nanosheets, etching the spacer material to remove the spacer material from the first layers of each of the plurality of nanosheets, and performing a sidewall treatment to the plurality of nanosheets after the spacer material is removed from the first layers of each of the plurality of nanosheets.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
H01L 21/66 - Testing or measuring during manufacture or treatment
H10D 30/43 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 1D charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
Embodiments described herein relate to electronic and photonic integrated circuits and methods for fabricating integrated interconnect between electrical, opto-electrical and photonic devices. One or more optical silicon photonic devices described herein may be used in connection with one or more opto-electrical integrated circuits (opto-electrical chip) on a single package substrate to from a co-packaged optical and electrical device. The methods described herein enable high volume manufacturing of electrical, opto-electrical and the optical silicon photonic devices having a plurality of optical structures, such as waveguides, formed on or integral with a photonic glass layer substrate.
G02B 6/42 - Coupling light guides with opto-electronic elements
91.
MACHINE LEARNING BASED VIRTUAL SENSING OF WAFER TEMPERATURES DURING REFLOW PROCESS IN A PHYSICAL VAPOR DEPOSITION CHAMBER WITH UNCERTAIN CHAMBER PHYSICAL PROPERTIES AND VARYING OPERATING CONDITIONS
Methods and devices for determining a temperature of a substrate during processing are provided herein. Embodiments include extracting modes from a virtual model of thermal conditions within a processing chamber. Embodiments further include receiving thermal sensor data associated with a target substrate. Embodiments further include using compressed sensing to generate a thermal map for the target substrate based on the thermal sensor data and the extracted modes.
H01L 21/66 - Testing or measuring during manufacture or treatment
G01K 3/10 - Thermometers giving results other than momentary value of temperature giving differences of valuesThermometers giving results other than momentary value of temperature giving differentiated values in respect of time, e.g. reacting only to a quick change of temperature
G01K 3/14 - Thermometers giving results other than momentary value of temperature giving differences of valuesThermometers giving results other than momentary value of temperature giving differentiated values in respect of space
G05B 13/02 - Adaptive control systems, i.e. systems automatically adjusting themselves to have a performance which is optimum according to some preassigned criterion electric
92.
LASER HEATING ARRANGEMENTS FOR INJECTION GAS ACTIVATION, AND RELATED PROCESSING CHAMBERS, APPARATUS, AND METHODS
The present disclosure relates to pre-heating process gases for activation, such as for low-temperature processing, and related chamber kits, methods, and processing chambers. In one or more embodiments, a substrate processing chamber includes a chamber body at least partially defining an internal volume, a substrate support disposed in the internal volume, and a flow inlet assembly operable to flow a gas into the internal volume. The flow inlet assembly includes an injector, an opening formed in the injector, and a flow guide disposed in the opening. The flow guide includes an inner surface and an outer surface, and the flow guide is in fluid communication with the internal volume. The flow inlet assembly includes one or more heating elements disposed within the opening, and an absorptive mass disposed within the flow guide.
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
93.
FLOW ADAPTORS FOR GAS FLOWS, AND RELATED PROCESSING CHAMBERS, PROCESSING SYSTEMS, APPARATUS, AND METHODS
Embodiments of the present disclosure generally relate to semiconductor processing equipment. In one or more embodiments, a flow adapter for mounting to a processing chamber includes a first flange, a second flange, and a conduit extending at least partially between the first flange and the second flange. The conduit includes an outer face, an inner flow opening, and one or more angled flow openings extending between the outer face and the inner flow opening. The one or more angled flow openings are oriented at an oblique angle relative to the inner flow opening.
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
The present disclosure describes a filter assembly for a heater line of a processing chamber. The filter assembly includes a first impedance producing element, a first air core inductor, and a second air core inductor. The first impedance producing element includes a first conductive lead and a second conductive lead wound around a first toroid shaped core. A first end of the first conductive lead and a first end of the second conductive lead are coupled to an output of an electric device. The first air core inductor is electrically connected with the first conductive lead. The second air core inductor is electrically connected with the second conductive lead.
An ion implanter. The ion implanter may include an ion source to generate an ion beam, and a linear accelerator, downstream to the ion source. The linear accelerator may include a buncher system to receive the ion beam and output a bunched ion beam, and a plurality of acceleration stages, to accelerate the bunched ion beam. The buncher system may include at least one RF buncher, a controller to adjust at least one control parameter of the at least one RF buncher over a plurality of instances; and a beam monitor, disposed downstream of the at least one RF buncher, and arranged to perform a plurality of beam measurements of the bunched ion beam over the plurality of instances. As such, the controller may be further arranged to determine a focal length of the buncher based upon the plurality of beam measurements.
H01J 37/317 - Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. ion implantation
H05H 11/00 - Magnetic induction accelerators, e.g. betatrons
96.
THIN-FILM TRANSISTOR (TFT) AND CAPACITOR STRUCTURES WITH HIGH DIELECTRIC CONSTANT LAYERS FOR ORGANIC LIGHT-EMITTING DIODE (OLED) DISPLAY BACKPLANE PANELS
Embodiments disclosed herein generally relate to thin-film transistor (TFT) and capacitor structures. The structures include one or more layers having a dielectric constant greater than five. The layer(s) having the dielectric constant greater than five may be implemented in a second buffer layer, a first bottom gate insulator (GI) layer, a first top GI layer, a second top GI layer, a first low temperature polycrystalline silicon (LTPS) interlayer dielectric (ILD) layer, and/or a first ILD layer. The first top GI layer may also have a dielectric constant less than five. Implementing the layer(s) with different dielectric constants results in various functional improvements of TFT and capacitor structures.
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
97.
MINIMIZING CORROSION IN PRE-PLASMA ABATEMENT SYSTEMS
Embodiments include a method for reducing corrosion in a pump exhaust foreline of a processing system. The method begins with the operation of a plasma processing system and evacuating a fluorine or chlorine containing gas into a processing chamber exhaust foreline as effluent. The effluent is abated in a plasma abatement system with a hydrogen containing reagent in a vacuum environment. The abated effluent contains one or more of HF or HCl at vacuum pressure. A controller runs a program to determine if a condition for condensation of HCl or HF exist based on a characteristic, flow rate and pressure of the effluent. A non-condensable gas is injected into the effluent. The abated effluent is pumped to a pump exhaust foreline coupled to an outlet of the pump, wherein the pump exhaust foreline is at atmospheric pressure.
B01D 53/32 - Separation of gases or vapoursRecovering vapours of volatile solvents from gasesChemical or biological purification of waste gases, e.g. engine exhaust gases, smoke, fumes, flue gases or aerosols by electrical effects other than those provided for in group
B01D 53/34 - Chemical or biological purification of waste gases
Embodiments described herein relate to a method, that obtaining a substrate with a patterned resist layer positioned over a patterning stack, wherein the patterned resist layer comprises a first low frequency roughness. In an embodiment, the method further includes forming a capping layer on the patterned resist layer. In an embodiment, a bottom of the patterned resist layer is exposed, and the patterned resist layer has a second low frequency line edge roughness that is lower than the first low frequency line edge roughness after the capping layer is formed.
A system includes an interposer device including an interposer, and at least a first photonic interconnect and a second photonic interconnect on the interposer. The first photonic interconnect includes at least one turning element within a first dielectric layer, at least one microscopic light-emitting component within a second dielectric layer and above the turning element, and at least one waveguide within the first dielectric layer. The at least one turning element is to direct at least one optical signal generated by the at least one microscopic light-emitting component to the at least one waveguide for transmission to the second photonic interconnect. The system further includes a plurality of components connected to the interposer device. The plurality of components includes a first component connected to the first photonic interconnect and a second component connected to the second photonic interconnect.
There are provided systems and methods comprising obtaining design data of each of a plurality of given overlay targets comprising a plurality of stacked layers, using at least part of the design data to simulate image data of the given overlay target that would have been acquired by an electron beam examination system, using the image data to predict, before actual manufacturing of each given overlay target, one or more given attributes informative of quality of one or more images of the given overlay target after being manufactured according to the design data, and using the one or more given attributes determined for each given overlay target to select at least one optimal overlay target among the plurality of different overlay targets, wherein the at least one optimal overlay target is usable to be actually manufactured on the semiconductor specimen.
