09 - Scientific and electric apparatus and instruments
Goods & Services
Semiconductor wafer processing equipment, namely,
semiconductor processing chambers used to deposit chemical
elements on wafer substrates. Recorded software for use in connection with deposition of
chemical elements on wafer substrates.
09 - Scientific and electric apparatus and instruments
Goods & Services
Semiconductor wafer processing equipment, namely,
semiconductor processing chambers used to deposit chemical
elements on wafer substrates. Recorded software for use in connection with deposition of
chemical elements on wafer substrates.
3.
CHEMICAL PASSIVATION OF MOLYBDENUM PLUG OR TRENCH'S OUTER SURFACE TO PREVENT MO NITRIDATION OR OXIDATION AND MAINTAIN LOW CONTACT RESISTANCE
A method includes forming a metal fill material on at least one electrical connection formed in a feature formed within a dielectric layer of a semiconductor device structure. The metal fill material partially fills the feature, the partially filled feature comprises the metal fill material and an exposed first portion of a sidewall of the feature that comprises the material of the dielectric layer, and a gap region formed between a second portion of the sidewall and a sidewall of the metal fill material, and performing a soaking process on the semiconductor device structure to form a passivation layer over a surface of the metal fill material and including a portion of the metal fill material disposed within the gap.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
C23C 8/08 - Solid state diffusion of only non-metal elements into metallic material surfacesChemical surface treatment of metallic material by reaction of the surface with a reactive gas, leaving reaction products of surface material in the coating, e.g. conversion coatings, passivation of metals using gases only one element being applied
C23C 16/04 - Coating on selected surface areas, e.g. using masks
C23C 16/06 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
C23C 28/00 - Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of main groups , or by combinations of methods provided for in subclasses and
C23C 28/02 - Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of main groups , or by combinations of methods provided for in subclasses and only coatings of metallic material
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
Methods of manufacturing semiconductor devices are described. A film stack on a substrate is exposed to a mixture of chlorine (Cl2), hydrogen bromide (HBr), oxygen (O2), and a fluorine-containing hydrocarbon to etch an opening in the film stack. The fluorine-containing hydrocarbon may have a general formula (I) CxHyFz wherein x is an integer in a range of from 1 to 4, y is an integer in a range of from 0 to 8, and z is an integer in a range of from 1 to 8. The film stack may additionally be exposed to etch cycles of a plasma where the plasma can be turned off periodically.
A brush cleaning system for cleaning a substrate includes a tank, and a first cylindrical roller, a second cylindrical roller, and a third cylindrical roller disposed in the tank. The brush cleaning system also includes a first cleaning position defined between the first cylindrical roller and the second cylindrical roller, and a second cleaning position defined between the second cylindrical roller and the third cylindrical roller. When the substrate is disposed in the first cleaning position, the first cylindrical roller is configured to clean a first side of the substrate and the second cylindrical roller is configured to clean a second side of the substrate. When the substrate is disposed in the second cleaning position, the second cylindrical roller is configured to clean the second side of the substrate and the third cylindrical roller is configured to clean a first side of the substrate.
A46B 13/02 - Brushes with driven brush bodies power-driven
B08B 1/20 - Cleaning of moving articles, e.g. of moving webs or of objects on a conveyor
B08B 1/34 - Cleaning by methods involving the use of tools by movement of cleaning members over a surface using rotary cleaning members rotating about an axis parallel to the surface
B08B 3/02 - Cleaning by the force of jets or sprays
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
A method includes determining durations of a plurality of processes in a sequence of processes to be performed by a substrate processing system. Each process is performed by a subsystem of the substrate processing system. The method further includes determining a duration for a process of the plurality of processes that is a longest duration among the durations. The method further includes calculating a pace for the substrate processing system based at least in part on the determined first duration. The method further includes causing multiple substrates to be introduced sequentially into the substrate processing system at the calculated pace for execution of the first sequence of processes with respect to each of the multiple substrates.
Exemplary gas flow components for a semiconductor processing system may include a 3D printed component that defines an outer body of the gas flow component. The 3D printed component may include an outer surface. The components may include a prefabricated component that is at least partially encapsulated within the 3D printed component. The prefabricated component may define a non-linear fluid flow lumen having an inlet and an outlet. The inlet and the outlet may each extend through the outer surface of the 3D printed component.
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
Multiple station substrate processing chambers and methods are provided comprising four spatially separated substrate processing stations within a chamber wall are described. Independently controlled heating zones to the each of four spatially separated substrate processing stations and independently heated supply lines improve deposition uniformity of substrates simultaneously processed in each of the each of four spatially separated substrate processing stations.
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
C23C 16/52 - Controlling or regulating the coating process
A method of processing a metal layer for a semiconductor structure includes performing a metal surface recovery process to remove an oxidized or nitridized layer from a surface of the metal layer and recover a metal surface of the metal layer, performing a metal passivation process to passivate the metal surface of the metal layer and form a passivation layer, and performing an encapsulation layer deposition process to deposit an encapsulation layer on the passivation layer.
H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
Systems and methods disclosed herein relate to a digital lithography system and method for alignment resolution with the digital lithography system. The digital lithography system includes a metrology system configured to improve overlay alignment for different layers of the lithography process. The metrology system allows for decreased size of alignment marks. Based on determining the positions of alignment marks with the metrology system, correction data is obtained to achieve accurate overlay of layers on subsequent patterning processes.
G03F 9/00 - Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
G01B 11/27 - Measuring arrangements characterised by the use of optical techniques for measuring angles or tapersMeasuring arrangements characterised by the use of optical techniques for testing the alignment of axes for testing the alignment of axes
G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor
11.
WAVEGUIDES CO-OPTIMIZATIONS WITH LIGHT ENGINES IN AR GLASS MODULE
Embodiments of the present disclosure generally relate to augmented reality systems. More specifically, embodiments described herein provide for augmented reality systems, methods of correcting an image projected into a waveguide, and related components. In one or more embodiments, an augmented reality system includes a light engine configured to emit an image and a waveguide including a substrate. The waveguide further includes an input coupler disposed over the substrate and configured to receive the image from the light engine. An output coupler is disposed over the substrate and configured to emit an outcoupled image. A controller is configured to generate corrective data based on one or more characteristics of the outcoupled image and adjust one or more components of the augmented reality system based on the corrective data.
A system includes a process chamber, a substrate support assembly to support a substrate, and a shower head assembly. The shower head assembly includes a gas distribution plate including an inner region having a first radius and a first thickness and an outer region, that is concentric with the inner region, having a f second radius that is greater than the first radius. The outer region further having a second thickness that is less than the first thickness causing the inner region to have a first distance from the substrate and the outer region to have a second distance from the substrate. The first distance is less than the second distance. The gas distribution plate is configured to deposit a coating on an outer region of the substrate without depositing the coating on an inner region of the substrate.
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
13.
REFLECTIVE SILVER FOR CHAMBER COMPONENTS IN SUBSTRATE PROCESSING, AND RELATED PROCESSING CHAMBERS AND METHODS
Embodiments of the present disclosure relate to reflective silver for chamber components in substrate processing, and related processing chambers and methods. The reflective silver can be used for a variety of processing operations. As an example, the reflective silver can be used in RTP chambers and/or epitaxial deposition chambers. In one or more embodiments, a processing chamber includes one or more walls at least partially defining a chamber volume, one or more substrate supports disposed in the chamber volume, and one or more heat sources operable to heat the chamber volume. The processing chamber includes a reflector oriented to reflect energy toward the chamber volume. At least a section of the reflector includes an opaque material at least partially coated with a reflective material. The opaque material includes silicon carbide (SiC).
H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
Methods used in electronic device manufacturing and, more particularly, to methods used for forming metal containing interconnect features in a semiconductor device. In one aspect, a method of forming a boron nitride layer on a metal surface is provided. The method includes exposing a surface of a metal layer to a nitrogen-containing plasma to form a metal nitride layer on the surface. The method further includes performing a chemical vapor deposition (CVD) soak process in which the metal nitride layer is exposed to a boron (B)-containing precursor gas, form a boron nitride monolayer.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
Exemplary semiconductor processing methods may include providing a fluorine-containing precursor, a chlorine-containing precursor, and a hydrogen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region. A silicon-containing material and a silicon-and-germanium-containing material may be disposed on the substrate. The methods may include contacting the substrate with the fluorine-containing precursor, the chlorine-containing precursor, and the hydrogen-containing precursor. The methods may include selectively removing at least a portion of the silicon-containing material from the substrate.
The present disclosure generally relates to a processing system comprising a flow assembly for processing thin substrates using low flow rates. The flow assembly comprises at least one compression part configured to compress a volume occupied by gas radicals flowing at a rate of about 0.1 slm to 5 slm from a plasma source to a chamber in two dimensions. The at least one compression part compresses the volume occupied by the gas radicals about 50% to about 90% from an initial cross-sectional area of the port of the process chamber. In some embodiments, the at least one compression part is a two compression parts, where a first compression part coupled to the port of the process chamber is larger in volume than a second compression part coupled to the first compression part and the chamber. In such an embodiment, the first and second compression parts are removable.
Described are semiconductor devices, e.g., GAA, FinFET, CFET, having a bilayer dielectric wall. Methods of forming a semiconductor device form a bilayer dielectric wall during the formation of the shallow trench isolation (STI). The first or liner dielectric layer of the bilayer dielectric wall is designed to allow the second or core dielectric layer to withstand downstream etching and to be removed prior to formation of the source/drain epitaxial regions. In some embodiments, the core dielectric layer is removed to form an airgap, mitigating the performance penalty associated with the bilayer dielectric wall.
A method for bonding wafers is provided. More specifically, the method provides for forming a hybrid bond between wafers that compensates for warpage and offset on each of the wafers being bonded.
A device includes a substrate comprising a plurality of structures and a dielectric layer. A first structure of the plurality of structures is separated from a second structure of the plurality of structures by a first distance. Each structure of the plurality of structures has an aspect ratio of about 5:1 to about 15:1. The dielectric layer is disposed on an upper surface of the substrate, a first sidewall and a second sidewall of the plurality of structures, and an upper surface of the plurality of structures. The dielectric layer has a thickness of about 1 nm to about 5 nm on the sidewalls of the plurality of structures. A method of forming a device includes depositing the dielectric layer over the substrate. A portion of the dielectric layer is modified to form a modified dielectric layer. An atomic layer etch is performed to remove the modified dielectric layer.
A system, controller, and method of automatically changing a polishing pad of a chemical mechanical polishing (CMP) system are provided. In one aspect, a CMP system includes a platen having a pad mounting surface upon which a pad, or replacement pad, can be disposed. The platen forms a plurality of apertures that extend to the pad mounting surface. The CMP system also includes a pad handler arranged to selectively move a pad onto the pad mounting surface during a pad installation process, and to selectively move the pad from the pad mounting surface during a pad removal process. The CMP system further includes a vacuum pump arranged to selectively apply a vacuum within the plurality of apertures so as to hold the pad to the pad mounting surface, such as during CMP processing of a substrate. The vacuum pump can cease applying the vacuum during an automated pad change process.
Embodiments of the present disclosure generally relate to epitaxial film stacks and vapor deposition processes for preparing the epitaxial film stacks. In one or more embodiments, a multi-layered epitaxial stack is disposed on a substrate, and the multilayered epitaxial stack contains a plurality of doped silicon-germanium and silicon mini-stacks. Each of the doped silicon germanium stack contains a doped-silicon- germanium layer disposed between a first silicon-germanium layer and a second silicon-germanium layer. Each of the doped-silicon-germanium layers independently contains a concentration of a dopant which may vary or be the same between each of the doped-silicon-germanium layers. The multi-layered epitaxial stack has a dopant gradient based on the concentration of the dopant within each of the doped-silicon- germanium layers such that the multi-layered epitaxial stack has a wafer bow value at a predetermined threshold. The multi-layered epitaxial stack may be used throughout the microelectronics industry.
A device includes a substrate comprising a plurality of structures and a dielectric layer. A first structure of the plurality of structures is separated from a second structure of the plurality of structures by a first distance. Each structure of the plurality of structures has an aspect ratio of about 5:1 to about 15:1. The dielectric layer is disposed on an upper surface of the substrate, a first sidewall and a second sidewall of the plurality of structures, and an upper surface of the plurality of structures. The dielectric layer has a thickness of about 1 nm to about 5 nm on the sidewalls of the plurality of structures. A method of forming a device includes depositing the dielectric layer over the substrate. A portion of the dielectric layer is modified to form a modified dielectric layer. An atomic layer etch is performed to remove the modified dielectric layer.
C23C 16/04 - Coating on selected surface areas, e.g. using masks
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
Technologies related to database architecture designed for computationally expensive workloads are described. A device includes multiple optical interfaces each configured to couple to different set of processing resources. Optical-to-electrical blocks of the device are each coupled to at least one of the multiple optical interfaces. Memory blocks of the device are each coupled to at least one of the multiple optical-to-electrical blocks.
G02B 6/42 - Coupling light guides with opto-electronic elements
G06F 16/27 - Replication, distribution or synchronisation of data between databases or within a distributed database systemDistributed database system architectures therefor
G02B 6/43 - Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
A system, controller, and method of automatically changing a polishing pad of a chemical mechanical polishing (CMP) system are provided. In one aspect, a CMP system includes a platen having a pad mounting surface upon which a pad, or replacement pad, can be disposed. The platen forms a plurality of apertures that extend to the pad mounting surface. The CMP system also includes a pad handler arranged to selectively move a pad onto the pad mounting surface during a pad installation process, and to selectively move the pad from the pad mounting surface during a pad removal process. The CMP system further includes a vacuum pump arranged to selectively apply a vacuum within the plurality of apertures so as to hold the pad to the pad mounting surface, such as during CMP processing of a substrate. The vacuum pump can cease applying the vacuum during an automated pad change process.
Disclosed embodiments include systems and techniques that deploy a gas showerhead having a first surface, a second surface, and a side surface. The gas showerhead includes one or more delivery channels, each delivery channel including one or more inlet ports through at least one of the first surface or the side surface, and a plurality of outlet ports through the second surface. The gas showerhead further includes an exhaust channel having a plurality of exhaust inlet ports through the second surface, and one or more exhaust outlet ports through at least one of the first surface, the second surface, or the side surface.
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
C23C 16/50 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
C23C 16/448 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for generating reactive gas streams, e.g. by evaporation or sublimation of precursor materials
B33Y 80/00 - Products made by additive manufacturing
A semiconductor device may include a substrate. The semiconductor device may include a backside metal layer disposed on a backside of the substrate and may include a first track and a second track. The semiconductor device may include a device layer may include a dummy source, a dummy gate, an active source, and an active gate. The semiconductor device may include a frontside metal pathway electrically connecting the dummy gate and the active gate. The device may include a first metal through substrate via (TSV) connecting the first track and the active source. The device may include a second metal TSV connecting the second track and the dummy source.
H01L 23/528 - Layout of the interconnection structure
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
A shield for use with a rotatable platen is disclosed. The shield includes a frame, which is mounted to the base of the platen. The electrostatic chuck is then mounted to the frame. The frame includes a plurality of ribs that extend radially outward from a center portion. The ribs terminate in one or more arc shaped support members, which hold a protective cover. This protective cover surrounds the entirety of the circumference of the electrostatic chuck, protecting it from the incoming ion beam at high tilt angles.
H01J 37/09 - DiaphragmsShields associated with electron- or ion-optical arrangementsCompensation of disturbing fields
H01J 37/317 - Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. ion implantation
28.
CHEMICAL PASSIVATION OF MOLYBDENUM PLUG OR TRENCH'S OUTER SURFACE TO PREVENT MO NITRIDATION OR OXIDATION AND MAINTAIN LOW CONTACT RESISTANCE
A method includes forming a metal fill material on at least one electrical connection formed in a feature formed within a dielectric layer of a semiconductor device structure. The metal fill material partially fills the feature, the partially filled feature comprises the metal fill material and an exposed first portion of a sidewall of the feature that comprises the material of the dielectric layer, and a gap region formed between a second portion of the sidewall and a sidewall of the metal fill material, and performing a soaking process on the semiconductor device structure to form a passivation layer over a surface of the metal fill material and including a portion of the metal fill material disposed within the gap.
Methods and apparatus for polishing a semiconductor substrate are provided. In one embodiment a polishing system for polishing a semiconductor substrate is provided. The polishing system includes a polishing pad assembly and a carrier head assembly. The is carrier head assembly disposed over the polishing pad assembly and includes a body having a lower surface facing the polishing pad assembly, a shaft coupling a carrier to the body, the shaft disposed through the lower surface, the lower surface facing the carrier and the polishing pad assembly, and a droplet reduction system disposed on the lower surface.
B24B 37/10 - Lapping machines or devicesAccessories designed for working plane surfaces characterised by the movement of the work or lapping tool for single side lapping
30.
SEMICONDUCTOR DEVICES HAVING REDUCED CONTACT RESISTIVITY
The present technology includes semiconductor devices and methods with improved contact resistivity. Semiconductor devices include a substrate base, a contact including a silicide overlying at least a portion of the substrate in the one or more features, which has a contact length of less than 40 Angstroms. The methods for generating a reduced contact length silicide layer includes depositing a first metal, and performing at least one thermal anneal to generate a silicide having a reduced contact length.
The present technology includes semiconductor devices and methods with improved contact resistivity. Semiconductor devices include a substrate base, a silicon oxide disposed on the base defining one or more features, a non-magnetic transition-metal doped contact silicide layer disposed on the substrate in the one or more features, and at least a first metal layer. The non-magnetic transition-metal doped contact silicide layer includes a non-magnetic transition-metal, a first metal, and a silicon containing compound, and includes greater than or about 8.0 E+13 per cm2 non-magnetic transition-metal atoms. The first metal layer includes the first metal and overlies the non-magnetic transition-metal doped contact silicide layer.
Methods used in electronic device manufacturing and, more particularly, to methods used for forming metal containing interconnect features in a semiconductor device. In one aspect, a method of forming a boron nitride layer on a metal surface is provided. The method includes exposing a surface of a metal layer to a nitrogen- containing plasma to form a metal nitride layer on the surface. The method further includes performing a chemical vapor deposition (CVD) soak process in which the metal nitride layer is exposed to a boron (B)-containing precursor gas, form a boron nitride monolayer.
Aspects of the present disclosure includes methods of forming a waveguide. The method of forming a waveguide includes depositing a mandrel disposed over a substrate. Portions of the mandrel are etched to form a trench. A spacer material is deposited over the mandrel and the substrate. The spacer material is etched to form a spacer in the trench. The mandrel is etched using ion beam etching (IBE). The mandrel and the substrate are etched to form a blazed grating. The spacer is removed.
An ophthalmic lens assembly includes a first ophthalmic lens and a second ophthalmic lens. The first ophthalmic lens comprises one or more first mechanical fiducials. The one or more first mechanical fiducials comprise a first mechanical fiducial formed at a first location on the first ophthalmic lens. The second ophthalmic lens comprises one or more second mechanical fiducials. The one or more second mechanical fiducials comprise a second mechanical fiducial formed at a second location on the second ophthalmic lens. The first mechanical fiducial and the second mechanical fiducial are aligned with one another.
Technologies related to database architecture designed for computationally expensive workloads are described. A device includes multiple optical interfaces each configured to couple to different set of processing resources. Optical-to-electrical blocks of the device are each coupled to at least one of the multiple optical interfaces. Memory blocks of the device are each coupled to at least one of the multiple optical-to-electrical blocks.
Embodiments of the present disclosure generally relate to augmented reality waveguides for augmented, virtual, and mixed reality. More specifically, embodiments described herein provide waveguides with a large field-of-view and a method of forming the same. In one embodiment, a waveguide is provided. The waveguide includes an incoupler (IC) grating. The incoupler (IC) grating includes a plurality of blazed structures disposed over a substrate. The plurality of blazed structures having a blazed surface with a slant angle relative to a plane parallel to the substrate. The waveguide further includes a metal material disposed over the plurality of blazed structures. An intermediate grating and an outcoupler (OC) grating each including a plurality of device structures. The plurality of device structures having a variable depth.
A method for forming waveguide structures is provided. More specifically, embodiments described herein provide techniques for forming staircase gratings with reduced top and bottom critical dimensions.
G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor
Embodiments of the disclosure describe an apparatus including a first electrostatic chuck (ESC) disposed in a processing region includes one or more segments and a surface of each of the one or more segments of the first ESC defines a first chucking surface that is oriented in a first direction. A first chucking force causes a first substrate to be urged against the first chucking surface. A second ESC disposed in the processing region includes one or more segments and a surface of each of the one or more segments of the second ESC defines a second chucking surface that is oriented in a second direction that is opposite the first direction. A second chucking force causes a second substrate to be urged against the second chucking surface. An actuator is configured to position the first ESC relative to the second ESC.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 23/00 - Details of semiconductor or other solid state devices
39.
SEMICONDUCTOR DEVICES HAVING REDUCED CONTACT RESISTIVITY
The present technology includes semiconductor devices and methods with improved contact resistivity. Semiconductor devices include a substrate base, a contact including a silicide overlying at least a portion of the substrate in the one or more features, which has a contact length of less than 40 Angstroms. The methods for generating a reduced contact length silicide layer includes depositing a first metal, and performing at least one thermal anneal to generate a silicide having a reduced contact length.
The present technology includes semiconductor devices and methods with improved contact resistivity. Semiconductor devices include a substrate base, a silicon oxide disposed on the base defining one or more features, a non-magnetic transition-metal doped contact silicide layer disposed on the substrate in the one or more features, and at least a first metal layer. The non-magnetic transition-metal doped contact silicide layer includes a non-magnetic transition-metal, a first metal, and a silicon containing compound, and includes greater than or about 8.0 E+13 per cm2 non-magnetic transition-metal atoms. The first metal layer includes the first metal and overlies the non-magnetic transition-metal doped contact silicide layer.
H01L 29/43 - Electrodes characterised by the materials of which they are formed
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
A semiconductor device may include a substrate. The semiconductor device may include a backside metal layer disposed on a backside of the substrate and may include a first track and a second track. The semiconductor device may include a device layer may include a dummy source, a dummy gate, an active source, and an active gate. The semiconductor device may include a frontside metal pathway electrically connecting the dummy gate and the active gate. The device may include a first metal through substrate via (TSV) connecting the first track and the active source. The device may include a second metal TSV connecting the second track and the dummy source.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
Exemplary semiconductor processing methods may include providing a fluorine-containing precursor and a secondary precursor to a processing region of a semiconductor processing chamber. The secondary precursor may be or include a carbon-containing precursor, a hydrogen-containing precursor, a nitrogen-containing precursor, or an oxygen-containing precursor. A substrate may be housed within the processing region. A silicon-containing material and a silicon-and-germanium-containing material may be disposed on the substrate. The methods may include contacting the substrate with the fluorine-containing precursor and the secondary precursor. The methods may include selectively removing at least a portion of the silicon-and-germanium-containing material from the substrate. The processing region may be maintained at a temperature of greater than or about 200° C.
Embodiments described herein relate to a method of forming a sub-pixel. The method includes depositing an intermediate layer material over a substrate and an anode. The anode is disposed over the substrate. A separation structure material is disposed over the intermediate layer material. A portion of the separation structure material is removed to form separation structures. A first structure material and second structure material are deposited over the substrate. A portion of the first structure material and the second structure material are removed to form a first structure and a second structure. A portion of the intermediate layer material is removed to form an intermediate layer. An OLED material, a cathode, and an encapsulation layer are deposited over the intermediate layer. A resist is patterned in a first sub-pixel. A portion of the OLED material, the cathode, and the encapsulation layer exposed by the second resist are removed.
A method includes determining durations of a plurality of processes in a sequence of processes to be performed by a substrate processing system. Each process is performed by a subsystem of the substrate processing system. The method further includes determining a duration for a process of the plurality of processes that is a longest duration among the durations. The method further includes calculating a pace for the substrate processing system based at least in part on the determined first duration. The method further includes causing multiple substrates to be introduced sequentially into the substrate processing system at the calculated pace for execution of the first sequence of processes with respect to each of the multiple substrates.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
B24B 51/00 - Arrangements for automatic control of a series of individual steps in grinding a workpiece
45.
LOW-FLOW RADICAL GAS GEOMETRICAL CONTROL THROUGH TWO- DIMENSIONAL COMPRESSION BETWEEN PLASMA SOURCE AND CHEMICAL REACTOR
The present disclosure generally relates to a processing system comprising a flow assembly for processing thin substrates using low flow rates. The flow assembly comprises at least one compression part configured to compress a volume occupied by gas radicals flowing at a rate of about 0.1 slm to 5 slm from a plasma source to a chamber in two dimensions. The at least one compression part compresses the volume occupied by the gas radicals about 50% to about 90% from an initial cross- sectional area of the port of the process chamber. In some embodiments, the at least one compression part is a two compression parts, where a first compression part coupled to the port of the process chamber is larger in volume than a second compression part coupled to the first compression part and the chamber. In such an embodiment, the first and second compression parts are removable.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
A brush cleaning system for cleaning a substrate includes a tank, and a first cylindrical roller, a second cylindrical roller, and a third cylindrical roller disposed in the tank. The brush cleaning system also includes a first cleaning position defined between the first cylindrical roller and the second cylindrical roller, and a second cleaning position defined between the second cylindrical roller and the third cylindrical roller. When the substrate is disposed in the first cleaning position, the first cylindrical roller is configured to clean a first side of the substrate and the second cylindrical roller is configured to clean a second side of the substrate. When the substrate is disposed in the second cleaning position, the second cylindrical roller is configured to clean the second side of the substrate and the third cylindrical roller is configured to clean a first side of the substrate.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
B08B 1/34 - Cleaning by methods involving the use of tools by movement of cleaning members over a surface using rotary cleaning members rotating about an axis parallel to the surface
47.
SUBSTRATE-TO-SUBSTRATE BONDING USING ELECTROSTATIC CHUCKS
Embodiments of the disclosure describe an apparatus including a first electrostatic chuck (ESC) disposed in a processing region includes one or more segments and a surface of each of the one or more segments of the first ESC defines a first chucking surface that is oriented in a first direction. A first chucking force causes a first substrate to be urged against the first chucking surface. A second ESC disposed in the processing region includes one or more segments and a surface of each of the one or more segments of the second ESC defines a second chucking surface that is oriented in a second direction that is opposite the first direction. A second chucking force causes a second substrate to be urged against the second chucking surface. An actuator is configured to position the first ESC relative to the second ESC.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/68 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for positioning, orientation or alignment
48.
MULTI-STATION SUBSTRATE PROCESSING CHAMBER WITH PRECISE TEMPERATURE AND FLOW CONTROL
Multiple station substrate processing chambers and methods are provided comprising four spatially separated substrate processing stations within a chamber wall are described. Independently controlled heating zones to the each of four spatially separated substrate processing stations and independently heated supply lines improve deposition uniformity of substrates simultaneously processed in each of the each of four spatially separated substrate processing stations.
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C23C 16/52 - Controlling or regulating the coating process
49.
LARGE FIELD-OF-VIEW FOLD-GRATING DIFFRACTIVE WAVEGUIDE
Embodiments of the present disclosure generally relate to augmented reality waveguides for augmented, virtual, and mixed reality. More specifically, embodiments described herein provide waveguides with a large field-of-view and a method of forming the same. In one embodiment, a waveguide is provided. The waveguide includes an incoupler (IC) grating. The incoupler (IC) grating includes a plurality of blazed structures disposed over a substrate. The plurality of blazed structures having a blazed surface with a slant angle relative to a plane parallel to the substrate. The waveguide further includes a metal material disposed over the plurality of blazed structures. An intermediate grating and an outcoupler (OC) grating each including a plurality of device structures. The plurality of device structures having a variable depth.
A method of forming a waveguide structure comprises forming a first plurality of photoresist segments over a plurality of hardmask segments and portions of a device layer exposed between the first plurality of hardmask segments, forming at least one step in portions of the device layer not covered by any of the plurality of photoresist segments or the plurality of hardmask segments, forming a second plurality of hardmask segments on the first staircase grating, removing the first plurality of hardmask segments to expose additional portions of the device layer, forming a second plurality of photoresist segments over the second plurality of hardmask segments and the additional exposed portions of the device layer, and forming at least one step in the additional exposed portions of the device layer not covered by any of the second plurality of photoresist segments or the second plurality of hardmask segments.
222), and a fluorine-containing hydrocarbon to etch an opening in the film stack. The fluorine-containing hydrocarbon may have a general formula (I) CxHyFz wherein x is an integer in a range of from 1 to 4, y is an integer in a range of from 0 to 8, and z is an integer in a range of from 1 to 8. The film stack may additionally be exposed to etch cycles of a plasma where the plasma can be turned off periodically.
Aspects of the present disclosure includes methods of forming a waveguide. The method of forming a waveguide includes depositing a mandrel disposed over a substrate. Portions of the mandrel are etched to form a trench. A spacer material is deposited over the mandrel and the substrate. The spacer material is etched to form a spacer in the trench. The mandrel is etched using ion beam etching (IBE). The mandrel and the substrate are etched to form a blazed grating. The spacer is removed.
Described are semiconductor devices, e.g., GAA, FinFET, CFET, having a bilayer dielectric wall. Methods of forming a semiconductor device form a bilayer dielectric wall during the formation of the shallow trench isolation (STI). The first or liner dielectric layer of the bilayer dielectric wall is designed to allow the second or core dielectric layer to withstand downstream etching and to be removed prior to formation of the source/drain epitaxial regions. In some embodiments, the core dielectric layer is removed to form an airgap, mitigating the performance penalty associated with the bilayer dielectric wall.
A system includes a process chamber, a substrate support assembly to support a substrate, and a shower head assembly. The shower head assembly includes a gas distribution plate including an inner region having a first radius and a first thickness and an outer region, that is concentric with the inner region, having a f second radius that is greater than the first radius. The outer region further having a second thickness that is less than the first thickness causing the inner region to have a first distance from the substrate and the outer region to have a second distance from the substrate. The first distance is less than the second distance. The gas distribution plate is configured to deposit a coating on an outer region of the substrate without depositing the coating on an inner region of the substrate.
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
C23C 16/505 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using radio frequency discharges
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
C23C 16/52 - Controlling or regulating the coating process
55.
PLATE FLOW PATHS FOR GAS ACTIVATION, AND RELATED CHAMBER KITS, METHODS, AND PROCESSING CHAMBERS
The present disclosure relates to plate flow paths for gas activation, and related chamber kits, methods, and processing chambers. In one or more embodiments, a processing chamber includes a plate apparatus that includes one or more gas inlet openings in the plate apparatus on the first side of the processing volume, one or more gas outlet openings in the plate apparatus on a second side of the processing volume, and one or more gas flow channels. The one or more gas flow channels are operable to flow a gas through the plate apparatus between the one or more gas inlet openings and the one or more gas outlet openings. The one or more gas outlet openings are operable to inject the gas into the processing volume on the second side to flow the gas horizontally across the processing volume and to the one or more gas exhaust outlets.
A method of processing a metal layer for a semiconductor structure includes performing a metal surface recovery process to remove an oxidized or nitridized layer from a surface of the metal layer and recover a metal surface of the metal layer, performing a metal passivation process to passivate the metal surface of the metal layer and form a passivation layer, and performing an encapsulation layer deposition process to deposit an encapsulation layer on the passivation layer.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
C23C 16/54 - Apparatus specially adapted for continuous coating
Aspects generally relate to methods and systems for modulating capacitance values of different components within a processing chamber. The processing chamber includes an electrode driven by a power source coupled to a substrate, where a first capacitance is produced between the electrode and the substrate, an edge ring disposed adjacent the substrate, the edge ring having a second capacitance, and at least one capacitor disposed within the processing chamber to match the second capacitance of the edge ring to the first capacitance between the electrode and the substrate. In one example, the at least one capacitor is a fixed capacitor. In another example, the at least one capacitor is a variable capacitor. Components of the processing chamber may be powered by either a radiofrequency source or a pulse generator.
Exemplary semiconductor processing methods may include providing a fluorine-containing precursor, a chlorine-containing precursor, and a hydrogen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region. A silicon-containing material and a silicon-andgermanium-containing material may be disposed on the substrate. The methods may include contacting the substrate with the fluorine-containing precursor, the chlorine-containing precursor, and the hydrogen-containing precursor. The methods may include selectively removing at least a portion of the silicon-containing material from the substrate.
Exemplary semiconductor processing methods may include providing a fluorine-containing precursor and a secondary precursor to a processing region of a semiconductor processing chamber. The secondary precursor may be or include a carbon-containing precursor, a hydrogen-containing precursor, a nitrogen-containing precursor, or an oxygen-containing precursor. A substrate may be housed within the processing region. A silicon-containing material and a silicon-and-germanium-containing material may be disposed on the substrate. The methods may include contacting the substrate with the fluorine-containing precursor and the secondary precursor. The methods may include selectively removing at least a portion of the silicon-and-germanium-containing material from the substrate. The processing region may be maintained at a temperature of greater than or about 200°C.
Approaches for forming 3D DRAM cells are disclosed. One method may include forming a dielectric liner and a fill material within a plurality of lateral openings extending from a slot, wherein the plurality of lateral openings and the slot are formed in a carbon-doped stack of alternating first layers and second layers, and partially removing the dielectric liner from the plurality of lateral openings. The method may further include forming a sacrificial layer along the plurality of lateral openings and the slot, removing the sacrificial layer, and forming a gate dielectric along the plurality of lateral openings and the slot following removal of the sacrificial layer.
Embodiments described herein relate to an apparatus that includes an RF power supply and an RF power splitter. In an embodiment, the RF power splitter includes a plurality of outputs, and a plurality of RF impedance matches are electrically coupled to different ones of the plurality of outputs of the RF power splitter. In an embodiment, a plurality of RF sensors are configured to measure a voltage and/or a current along a plurality of transmission lines that couple each of the plurality of outputs of the RF power splitter to a different one of the plurality of RF impedance matches. In an embodiment, the apparatus further includes a controller communicatively coupled to the plurality of RF sensors and the plurality of RF impedance matches. The controller is configured to balance power that passes through the plurality of RF impedance matches with a detuning operation.
Methods of depositing transition metal dichalcogenide (TMDC) films are described. The TMDC films can be used in electronic devices as, for example, a channel material in both back-end-of-line (BEOL) and front-end-of line (FEOL) applications depending on the TMDC growth temperature.
A shield for use with a rotatable platen is disclosed. The shield includes a frame, which is mounted to the base of the platen. The electrostatic chuck is then mounted to the frame. The frame includes a plurality of ribs that extend radially outward from a center portion. The ribs terminate in one or more arc shaped support members, which hold a protective cover. This protective cover surrounds the entirety of the circumference of the electrostatic chuck, protecting it from the incoming ion beam at high tilt angles.
H01J 37/09 - DiaphragmsShields associated with electron- or ion-optical arrangementsCompensation of disturbing fields
H01J 37/20 - Means for supporting or positioning the object or the materialMeans for adjusting diaphragms or lenses associated with the support
H01J 37/317 - Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. ion implantation
64.
EPITAXIAL SILICON AND DOPED SILICON GERMANIUM SUPERLATTICE AND METHODS FOR PREPARING THE SAME
Embodiments of the present disclosure generally relate to epitaxial film stacks and vapor deposition processes for preparing the epitaxial film stacks. In one or more embodiments, a multi-layered epitaxial stack is disposed on a substrate, and the multi-layered epitaxial stack contains a plurality of doped silicon-germanium and silicon mini-stacks. Each of the doped silicon germanium stack contains a doped-silicon-germanium layer disposed between a first silicon-germanium layer and a second silicon-germanium layer. Each of the doped-silicon-germanium layers independently contains a concentration of a dopant which may vary or be the same between each of the doped-silicon-germanium layers. The multi-layered epitaxial stack has a dopant gradient based on the concentration of the dopant within each of the doped-silicon-germanium layers such that the multi-layered epitaxial stack has a wafer bow value at a predetermined threshold. The multi-layered epitaxial stack may be used throughout the microelectronics industry.
Aspects generally relate to methods and systems for modulating capacitance values of different components within a processing chamber. The processing chamber includes an electrode driven by a power source coupled to a substrate, where a first capacitance is produced between the electrode and the substrate, an edge ring disposed adjacent the substrate, the edge ring having a second capacitance, and at least one capacitor disposed within the processing chamber to match the second capacitance of the edge ring to the first capacitance between the electrode and the substrate. In one example, the at least one capacitor is a fixed capacitor. In another example, the at least one capacitor is a variable capacitor. Components of the processing chamber may be powered by either a radiofrequency source or a pulse generator.
Embodiments described herein relate to a method of forming a sub-pixel. The method includes depositing an intermediate layer material over a substrate and an anode. The anode is disposed over the substrate. A separation structure material is disposed over the intermediate layer material. A portion of the separation structure material is removed to form separation structures. A first structure material and second structure material are deposited over the substrate. A portion of the first structure material and the second structure material are removed to form a first structure and a second structure. A portion of the intermediate layer material is removed to form an intermediate layer. An OLED material, a cathode, and an encapsulation layer are deposited over the intermediate layer. A resist is patterned in a first sub-pixel. A portion of the OLED material, the cathode, and the encapsulation layer exposed by the second resist are removed.
Embodiments includes an ophthalmic lens and a method of forming the ophthalmic lens, as shown and described herein. The ophthalmic lens includes a waveguide, world-side (WS) lens, a WS adhesive securing the WS lens to the waveguide, a WS air gap between the WS lens and the waveguide, an eye-side (ES) lens, an ES adhesive securing the ES lens to the waveguide, and an ES air gap between the ES lens and the waveguide. The WS adhesive has a WS thickness and the WS air gap has a WS air gap distance. The WS air gap distance is greater than the WS adhesive thickness. The ES adhesive having an ES thickness and the ES air gap has an ES air gap distance. The ES air gap distance is greater than the WS adhesive thickness.
Embodiments of the present disclosure generally relate to methods and processes to selectively deposit Si:P layers onto a semiconductor structure. More specifically, embodiments described herein provide for methods for enhancing epitaxial deposition of Si:P layers onto semiconductor structures at lower temperatures. In some embodiments, a method includes positioning a substrate within a processing volume of a processing chamber, introducing a process gas such as a silicon source and a dopant gas to the processing chamber, and forming an epitaxial layer on a surface of the substrate at a processing temperature of about 450° C. or less. The partial pressure of the silicon source is preferably about 10 Torr to about 300 Torr.
Disclosed embodiments include systems and techniques that deploy a gas showerhead having a first surface, a second surface, and a side surface. The gas showerhead includes one or more delivery channels, each delivery channel including one or more inlet ports through at least one of the first surface or the side surface, and a plurality of outlet ports through the second surface. The gas showerhead further includes an exhaust channel having a plurality of exhaust inlet ports through the second surface, and one or more exhaust outlet ports through at least one of the first surface, the second surface, or the side surface.
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
A polishing liquid delivery arm cleaning tool includes a body configured to be removably secured to a polishing liquid delivery arm of a chemical mechanical polishing system, and an insert removably secured to the body. The insert has an arm-facing surface shaped to direct a cleaning fluid from the polishing liquid delivery arm back to an inner surface of an enclosure of the polishing liquid delivery arm.
B24B 57/02 - Devices for feeding, applying, grading or recovering grinding, polishing or lapping agents for feeding of fluid, sprayed, pulverised, or liquefied grinding, polishing or lapping agents
The present disclosure relates to methods of correlating zones of processing chambers, and related systems and methods. In one implementation, a method of correlating zones of a processing chamber includes partitioning the processing volume into a plurality of zones along a first direction of the processing volume and a second direction of the processing volume. The second direction intersects the first direction. The plurality of zones have a first zone number (m), and a second zone number (n). The method includes determining a group number. The determining of the group number includes multiplying a first value by a second value. The first value correlates to a first zone number (m) of a plurality of zones and the second value correlates to a second zone number (n) of the plurality of zones. The method includes grouping the zones into groups having a number that is equal to the group number.
C23C 16/52 - Controlling or regulating the coating process
C23C 16/448 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for generating reactive gas streams, e.g. by evaporation or sublimation of precursor materials
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
72.
SYSTEMS AND METHODS FOR CONTROLLING A VOLTAGE WAVEFORM AT A SUBSTRATE DURING PLASMA PROCESSING
Systems and methods for controlling a voltage waveform at a substrate during plasma processing include applying a shaped pulse bias waveform to a substrate support, the substrate support including an electrostatic chuck, a chucking pole, a substrate support surface and an electrode separated from the substrate support surface by a layer of dielectric material. The systems and methods further include capturing a voltage representative of a voltage at a substrate positioned on the substrate support surface and iteratively adjusting the shaped pulse bias waveform based on the captured signal. In a plasma processing system a thickness and a composition of a layer of dielectric material separating the electrode and the substrate support surface can be selected such that a capacitance between the electrode and the substrate support surface is at least an order of magnitude greater than a capacitance between the substrate support surface and a plasma surface.
Exemplary semiconductor processing systems may include a gas source coupled with a number of processing chambers. The gas source may include a controller. Each chamber may include an exhaust assembly having a foreline and a pump. The systems may include at least one abatement system coupled with each pump. The systems may include a plurality of exhaust lines that extend between each pump and the abatement system. The systems may include a dilution gas source coupled with each exhaust line. The systems may include a mass flow controller coupled between the dilution gas source and each exhaust line. The systems may include a temperature sensor coupled with each exhaust line between the pump and the abatement system. The temperature sensor may be communicatively coupled with the controller of the gas source, which may control flow of a gas to a chamber based on a measurement from the temperature sensor.
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
Apparatus and methods to process one or more wafers are described. A spatial deposition tool comprises a plurality of substrate support surfaces on a substrate support assembly and a plurality of spatially separated and isolated processing stations. The spatially separated isolated processing stations have independently controlled temperature, processing gas types, and gas flows. In some embodiments, the processing gases on one or multiple processing stations are activated using plasma sources. The operation of the spatial tool comprises rotating the substrate assembly in a first direction, and rotating the substrate assembly in a second direction, and repeating the rotations in the first direction and the second direction until a predetermined thickness is deposited on the substrate surface(s).
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
75.
MODULAR FLOW CHAMBER KITS, PROCESSING CHAMBERS, AND RELATED APPARATUS AND METHODS APPLICABLE FOR SEMICONDUCTOR MANUFACTURING
Embodiments of the present disclosure relate to modular flow chamber kits, processing chambers, and related apparatus and methods applicable for semiconductor manufacturing. In one or more embodiments, a processing chamber includes a chamber body at least partially defining a processing volume. The chamber body includes a plurality of inject passages arranged in a plurality of flow levels, and one or more exhaust passages formed in the chamber body. The processing chamber includes one or more heat sources operable to heat the processing volume, a substrate support disposed in the processing volume, and a plate spaced from the substrate support. The substrate support and the plate are movable by at least one flow level of the plurality of flow levels to align the substrate support between one or more first inject passages of a first flow level and one or more second inject passages of a second flow level.
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
76.
PROCESS KITS AND RELATED METHODS FOR PROCESSING CHAMBERS TO FACILITATE DEPOSITION PROCESS ADJUSTABILITY
The present disclosure relates to flow guides, process kits, and related methods for processing chambers to facilitate deposition process adjustability. In one implementation, a flow guide includes a middle plate having a first side and a second side opposing the first side along a first direction. The first side and the second side are arcuate. The flow guide includes a first flange extending outwardly relative to a third side of the middle plate and outwardly relative to an outer face of the middle plate, and a second flange extending outwardly relative to a fourth side of the middle plate and outwardly relative to the outer face of the middle plate. The fourth side opposes the third side along a second direction that intersects the first direction. The flow guide includes a rectangular flow opening defined between the first flange and the second flange.
C23C 14/56 - Apparatus specially adapted for continuous coatingArrangements for maintaining the vacuum, e.g. vacuum locks
C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
C30B 25/10 - Heating of the reaction chamber or the substrate
C30B 25/14 - Feed and outlet means for the gasesModifying the flow of the reactive gases
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
77.
Integrated inspection for Enhanced Hybrid Bonding Yield in Advanced Semiconductor Packaging Manufacturing
Methods of hybrid bonding with inspection are provided herein. In some embodiments, a method of hybrid bonding with inspection includes: cleaning a substrate via a first cleaning chamber and a tape frame having a plurality of chiplets via a second cleaning chamber; inspecting, via a first metrology system, the substrate for pre-bond defects in a first metrology chamber and the tape frame for pre-bond defects in a second metrology chamber; bonding one or more of the plurality of chiplets to the substrate via a hybrid bonding process in a bonder chamber to form a bonded substrate; and performing, via a second metrology system different than the first metrology system, a post-bond inspection of the bonded substrate via a third metrology chamber for post-bond defects.
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 23/00 - Details of semiconductor or other solid state devices
78.
LOADING ETCH EFFECT MITIGATION FOR REACTIVE ION ETCHING
A method for etching a substrate includes pulsing an RF power at a given frequency to generate a plasma for etching the substrate where each pulse period has an ON-state and an OFF-state comprising a duty cycle, selecting an ON-state duration of the duty cycle based on, at least in part, a first duration for restriking the plasma, a second duration for a minimum on-time per a given RF power source providing the RF power, and a third duration for the plasma to reach a steady state, selecting an OFF- state duration of the duty cycle for each pulse period to alter a profile loading, a iso-dense depth loading, or a critical dimension (CD) loading etching effect associated with a feature to be formed on the substrate, and forming the feature by using the duty cycle for the RF power to etch the substrate.
The present disclosure generally provides substrate processing systems and methods thereof. The substrate processing systems include a substrate processing chamber including a transfer port. A substrate support assembly is disposed within the substrate processing chamber. The substrate support assembly having an electrostatic chuck and a substrate support surface. A transport robot is configured to transport a cathode ring in and out of the substrate processing chamber through the transfer port. A controller is configured to cause the substrate processing system to place the cathode ring on the substrate support surface of the substrate support assembly using the transport robot, and power the electrostatic chuck for a cleaning period while the cathode ring is disposed over the substrate support surface.
H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
80.
XENON PLASMA CURES TO ENABLE INCREASED CROSSLINKING IN LOW-K DIELECTRIC FILMS
The present technology includes methods and systems for forming advanced memory structures, and devices therefrom. Methods include forming a dummy material layer over a first sidewall, a second sidewall, and a bottom surface, of one or more features, where the first sidewall is spaced apart from the second sidewall and the bottom surface is disposed between the first sidewall and the second sidewall. Methods include filling a gap formed between the dummy material on the first sidewall and the low resistivity material on the second sidewall with a sacrificial isolation material. Methods include removing at least a portion of the bottom surface, exposing at least a portion of the dummy material and the sacrificial isolation material. Methods include removing the sacrificial isolation material and at least a portion of the dummy material and selectively depositing a conductive material on a remaining portion of the dummy material.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
82.
TRACKING SYSTEM ON MATRIX TWO-DIMENSIONAL CODE LABELS
A method for tracking of a semiconductor chamber part uses a matrix two-dimensional (2D) code label embedded with a tracking feature. In some embodiments, the method may include selecting a feature to embed into the matrix 2D code label to create a modified matrix 2D code label where the feature does not cause misreading of information from the matrix 2D code label when embedded into the matrix 2D code label and where the feature is configured to change based on treatment of the semiconductor chamber part, forming the modified matrix 2D code label into the semiconductor chamber part, optically inspecting the modified matrix 2D code label to determine changes to the feature, and analyzing the changes to the feature to determine a number of cleaning cycles undergone by the semiconductor chamber part based, at least in part, on the changes to the feature.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
G06K 7/14 - Methods or arrangements for sensing record carriers by electromagnetic radiation, e.g. optical sensingMethods or arrangements for sensing record carriers by corpuscular radiation using light without selection of wavelength, e.g. sensing reflected white light
G06K 19/06 - Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
83.
TRANSISTOR DIRECT BACKSIDE CONTACT WITH ETCH STOP LAYER
Semiconductor devices and methods of manufacturing the same are described. A silicon wafer is provided and an etch stop bilayer is formed on the silicon wafer. The insertion of an etch stop bilayer in the starting wafer will serve as an etch stop for deep trench formation on the wafer frontside and for wafer backside planarization. With this approach variations in the sacrificial material depth in a GAA device and substrate thickness may offer benefits in lithography overlay control.
Physical vapor deposition (PVD) chambers and deposition rings for physical vapor deposition (PVD) chambers are described. The deposition ring comprises a ring-shaped body having an upper portion and a lower portion, each of the upper portion and the lower portion independently comprising an inner diameter surface and an outer diameter surface defining an upper portion thickness and a lower portion thickness, and a top surface and a bottom surface defining an upper portion height and a lower portion height, the upper portion height greater than the lower portion height; and a plurality of circumferentially spaced notches formed along an edge of the inner diameter surface of the lower portion, wherein at least a portion of the upper portion defines a convex shape.
C23C 16/50 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
Methods of depositing transition metal dichalcogenide (TMDC) films are described. The TMDC films can be used in electronic devices as, for example, a channel material in both back-end-of-line (BEOL) and front-end-of line (FEOL) applications depending on the TMDC growth temperature.
C23C 16/02 - Pretreatment of the material to be coated
C23C 16/52 - Controlling or regulating the coating process
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
86.
NOBLE GAS PLASMA CURES TO ENABLE INCREASED CROSSLINKING IN LOW-K DIELECTRIC FILMS
Embodiments of the present disclosure generally relate to methods of plasma curing a dielectric material layer formed on a substrate. More specifically, the methods disclosed herein utilize a xenon (Xe) containing gas to generate a plasma that allows for greater dielectric compositional modulation. In some embodiments, a method of curing a substrate includes depositing a dielectric film onto a substrate to form a dielectric layer on a surface of a substrate, and performing a plasma cure operation on the formed dielectric layer. The plasma cure operation includes generating a plasma over a surface of the formed dielectric layer by delivering a RF power to a plasma process gas. The plasma process gas include Xe and H2.
C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
C23C 16/505 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using radio frequency discharges
87.
PROCESSING APPARATUS FOR PROCESSING A FLEXIBLE SUBSTRATE AND METHODS THEREFOR
A processing apparatus for processing a flexible substrate is described. The processing apparatus includes a vacuum processing chamber including at least one deposition source for depositing a layer of material on the flexible substrate. Further, the processing apparatus includes a postprocessing chamber comprising a post-processing roller and a gas supply. The post processing roller has a substrate facing surface comprising a plurality of gas outlets. The gas supply is connected to the post processing roller to provide a gas through the plurality of gas outlets into an interspace between the flexible substrate and the substrate facing surface
C23C 16/06 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
In one or more embodiments, a method includes conducting a first digital lithography process according to a mask pattern to form first vias having a first dimension over a first area and second vias having a second dimension over a second area of a first substrate, the first dimension and the second dimension are different. The method further includes receiving metrology data of first pillars and second pillars. The first pillars and the second pillars having different heights. A digital lithography device generates an updated mask pattern according to the metrology data. The method further includes conducting a second digital lithography process according to the updated mask pattern to form third vias having a third dimension over the first area and fourth vias having a fourth dimension over the second area of a second substrate, the third dimension and the fourth dimension are different.
G03F 1/44 - Testing or measuring features, e.g. grid patterns, focus monitors, sawtooth scales or notched scales
G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor
H01L 23/00 - Details of semiconductor or other solid state devices
89.
Molybdenum (0) Precursors For Deposition Of Molybdenum Films
Molybdenum(0) coordination complexes comprising ligands which each coordinate to the metal center by nitrogen or phosphorous are described. Methods for depositing molybdenum-containing films on a substrate are described. The substrate is exposed to a molybdenum precursor and a reactant to form the molybdenum-containing film (e.g., elemental molybdenum, molybdenum oxide, molybdenum carbide, molybdenum silicide, molybdenum nitride). The exposures can be sequential or simultaneous.
C07F 11/00 - Compounds containing elements of Groups 6 or 16 of the Periodic Table
C23C 16/02 - Pretreatment of the material to be coated
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
Multiple threshold voltage (Multi-Vt) integration schemes for semiconductor devices are described. The methods include the use of diffusion barrier layers configured to provide multi-Vt through controlled dopant diffusion.
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
91.
Integrated CMOS Source Drain Formation With Advanced Control
A finFET device includes a doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped or p-doped source or drain extension is disposed. The doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer. After formation of the cavity, advanced processing controls (APC) (i.e., integrated metrology) is used to determine the distance of recess, without exposing the substrate to an oxidizing environment. The isotropic etch process, the metrology, and selective epitaxial growth may be performed in the same platform.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
Methods and apparatus for bonding chiplets to substrates are provided herein. In some embodiments, a multi-chamber processing tool for processing substrates includes: an equipment front end module (EFEM) having one or more loadports for receiving one or more types of substrates; and a plurality of automation modules coupled to each other and having a first automation module coupled to the EFEM, wherein each of the plurality of automation modules include a transfer chamber and one or more process chambers coupled to the transfer chamber, wherein the transfer chamber includes a buffer, and wherein the transfer chamber includes a transfer robot configured to transfer the one or more types of substrates, wherein at least one of the plurality of automation modules include a bonder chamber and at least one of the plurality of automation modules include a wet clean chamber.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
H01L 23/00 - Details of semiconductor or other solid state devices
93.
DIRECTIONAL SELECTIVE FILL FOR SILICON GAP FILL PROCESSES
Exemplary processing methods may include providing a silicon-containing precursor and a carbon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed in the processing region. The substrate may define a feature within the substrate. The methods may include forming plasma effluents of the silicon-containing precursor and the carbon-containing precursor. The methods may include depositing a silicon-and-carbon-containing material on the substrate. The methods may include providing a hydrogen-containing precursor to the processing region of the semiconductor processing chamber, forming plasma effluents of the hydrogen-containing precursor, and etching the silicon-and-carbon-containing material from a sidewall of the feature within the substrate. The methods may include providing a nitrogen-containing precursor to the processing region of the semiconductor processing chamber, forming plasma effluents of the nitrogen-containing precursor, and doping the silicon-and-carbon-containing material with nitrogen.
Exemplary semiconductor processing methods may include providing a first fluorine-containing precursor and a nitrogen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region. One or more features may extend through alternating layers of a silicon-and-oxygen-containing material and a silicon-and-nitrogen-containing material are disposed on the substrate. The methods may include providing a second fluorine-containing precursor to the processing region of the semiconductor processing chamber. The methods may include contacting the substrate with the first fluorine-containing precursor, the nitrogen-containing precursor, and the second fluorine-containing precursor. The contacting may etch a portion of the silicon-and-oxygen-containing material, and wherein a top-to-bottom loading is characterized by less than 1.2.
A method for performing an inline detection and repair of a defect on a substrate or interposer that does not destroy the substrate or interposer. The method is performed in the manufacturing area in separate platforms or a single platform. In some embodiments, the method may include detecting a defect on a panel in line to a panel level packaging process using an electron beam to image at least a portion of a surface of the panel, identifying a type of the defect, and repairing the defect on the panel based on the type of the defect in line with the panel level packaging process using a material removal process to remove material to fix a defect or using the electron beam in conjunction with a precursor gas to deposit material to fix a defect. The material removal process may include a plasma beam or an ion beam.
A method for tracking of a semiconductor chamber part uses a matrix two-dimensional (2D) code label embedded with a tracking feature. In some embodiments, the method may include selecting a feature to embed into the matrix 2D code label to create a modified matrix 2D code label where the feature does not cause misreading of information from the matrix 2D code label when embedded into the matrix 2D code label and where the feature is configured to change based on treatment of the semiconductor chamber part, forming the modified matrix 2D code label into the semiconductor chamber part, optically inspecting the modified matrix 2D code label to determine changes to the feature, and analyzing the changes to the feature to determine a number of cleaning cycles undergone by the semiconductor chamber part based, at least in part, on the changes to the feature.
G06K 19/06 - Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor
97.
TRANSISTOR DIRECT BACKSIDE CONTACT WITH ETCH STOP LAYER
Semiconductor devices and methods of manufacturing the same are described. A silicon wafer is provided and an etch stop bilayer is formed on the silicon wafer. The insertion of an etch stop bilayer in the starting wafer will serve as an etch stop for deep trench formation on the wafer frontside and for wafer backside planarization. With this approach variations in the sacrificial material depth in a GAA device and substrate thickness may offer benefits in lithography overlay control.
Physical vapor deposition (PVD) chambers and deposition rings for physical vapor deposition (PVD) chambers are described. The deposition ring comprises a ring-shaped body having an upper portion and a lower portion, each of the upper portion and the lower portion independently comprising an inner diameter surface and an outer diameter surface defining an upper portion thickness and a lower portion thickness, and a top surface and a bottom surface defining an upper portion height and a lower portion height, the upper portion height greater than the lower portion height; and a plurality of circumferentially spaced notches formed along an edge of the inner diameter surface of the lower portion, wherein at least a portion of the upper portion defines a convex shape.
Disclosed herein is a chemical mechanical polishing apparatus, including a platen having an upper surface to support a polishing pad, the platen having an annular chamber below and separated from a portion of an upper surface of the platen by a plate that is sufficiently flexible to deflect under a change of a pressure in the annular chamber, the platen having a channel fluidically connecting the annular chamber to a port in the platen; a pressure source coupled to the port to control the pressure in the annular chamber; a carrier head to hold a surface of a substrate against the polishing pad; and a motor to generate relative motion between the platen and the carrier head so as to polish an overlying layer on the substrate.
B24B 37/10 - Lapping machines or devicesAccessories designed for working plane surfaces characterised by the movement of the work or lapping tool for single side lapping
B24B 37/04 - Lapping machines or devicesAccessories designed for working plane surfaces
H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
The present technology includes methods and systems for forming advanced memory structures, and devices therefrom. Methods include forming a dummy material layer over a first sidewall, a second sidewall, and a bottom surface, of one or more features, where the first sidewall is spaced apart from the second sidewall and the bottom surface is disposed between the first sidewall and the second sidewall. Methods include filling a gap formed between the dummy material on the first sidewall and the low resistivity material on the second sidewall with a sacrificial isolation material. Methods include removing at least a portion of the bottom surface, exposing at least a portion of the dummy material and the sacrificial isolation material. Methods include removing the sacrificial isolation material and at least a portion of the dummy material and selectively depositing a conductive material on a remaining portion of the dummy material.
