Methods of generating a plasma in a semiconductor processing chamber comprise: applying a radio frequency (RF) power to generate a plasma in a plasma region of the processing chamber, the processing chamber containing: a showerhead, an ion blocker plate, and a substrate, and the plasma region being defined by a front surface of the showerhead and a back surface of the ion blocker plate; and applying a bias the ion blocker plate so that there is no light-up in the processing chamber. Some methods further include dynamically tuning the bias by assessing conditions of light-up or no light-up and adjusting the bias. Some methods further include applying the bias zonally.
Methods for the formation of films comprising Si, C, O and N are provided. Certain methods involve sequential exposures of a hydroxide terminated substrate surface to a silicon precursor and an alcohol-amine to form a film with hydroxide terminations. Certain methods involved sequential exposures of hydroxide terminated substrate surface to a silicon precursor and a diamine to form a film with an amine terminated surface, followed by sequential exposures to a silicon precursor and a diol to form a film with a hydroxide terminated surface.
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
A chamber component for a plasma process chamber and methods of fabricating and using the same are provided. In one aspect, a chamber component used within a plasma processing chamber is provided. The chamber component includes a metallic base material that has a surface having an average peak-to-valley distance, RzAVG, of less than or equal to about 20 micro inches, or about 0.508 microns. The chamber component also includes a silica coating formed over the surface.
Embodiments of the present invention generally relate to devices and methods related to deoxyribonucleic acid (DNA) synthesis. A device for synthesizing DNA is provided. The device includes a LED panel, the LED panel includes a backplane, the backplane having a backplane surface, the backplane surface having at least one contact pad disposed over the backplane surface, a plurality of LED, the plurality of LEDs disposed over the backplane surface, where each LED of the plurality of LEDs couples to a contact pad, pixel isolation (PI) structures, the PI structures disposed over the backplane surface and between the plurality of LEDs, the PI structures defining a plurality of wells, and a coating disposed over the LED panel, the coating operable to seal each well to hold a liquid.
C07H 21/04 - Compounds containing two or more mononucleotide units having separate phosphate or polyphosphate groups linked by saccharide radicals of nucleoside groups, e.g. nucleic acids with deoxyribosyl as saccharide radical
B01J 19/00 - Chemical, physical or physico-chemical processes in generalTheir relevant apparatus
Embodiments of the disclosure include a processing chamber assembly that comprises: a chamber comprising a substrate-support assembly; a pulsed voltage generator comprising an output connection that is electrically coupled to a plurality of biasing electrodes embedded within the substrate-support assembly; and one or more chucking modules, wherein a chucking module of the one or more chucking modules comprises a direct-current voltage supply that is electrically coupled to one of the plurality of biasing electrodes through a corresponding bias compensation module that comprises a plurality of passive electrical components.
Embodiments described herein generally relate to displays. In one or more embodiments, a display device includes a backplane having a drain supply line (VDD) and a source supply line (Vss). Overhang structures are disposed over the backplane. Adjacent overhang structures define sub-pixels of the device. A plurality of sub-pixels are disposed on the backplane. Each sub-pixel includes a thin film transistor circuit including a driving thin film transistor (driving TFT). An anode is disposed on the backplane and electrically coupled to the drain supply line (VDD) via a common anode interconnect. An organic light-emitting (OLE) material is disposed over the anode. A cathode is disposed over the OLE material. The cathode is electrically coupled to the driving TFT such that the driving TFT individually drives the cathode of the sub-pixel.
H10K 59/122 - Pixel-defining structures or layers, e.g. banks
H10K 59/121 - Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
H10K 59/123 - Connection of the pixel electrodes to the thin film transistors [TFT]
H10K 59/131 - Interconnections, e.g. wiring lines or terminals
G09G 3/3233 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
Exemplary semiconductor processing methods may include providing an oxygen-containing precursor to a remote plasma region of a semiconductor processing chamber. The methods may include forming plasma effluents of the oxygen-containing precursor in the remote plasma region. The methods may include providing the plasma effluents of the oxygen-containing precursor to a processing region. A substrate may be housed within the processing region. The substrate may define an exposed region of a titanium-and-nitrogen containing material and an exposed region of one or more silicon-containing materials. The methods may include providing a fluorine-containing precursor to the processing region. The fluorine-containing precursor may be provided plasma-free. The methods may include contacting the substrate with the plasma effluents of the oxygen-containing precursor and the fluorine-containing precursor. The contacting may etch at least a portion of the exposed region of a titanium-and-nitrogen containing material.
The present technology includes methods and systems for forming advanced memory structures, and devices therefrom. Methods include forming a dielectric material layer over a first sidewall, a second sidewall, and a bottom surface, of one or more features, where the first sidewall is spaced apart from the second sidewall and the bottom surface is disposed between the first sidewall and the second sidewall. Methods include depositing a sacrificial backgate material in the one or more features, filling the one or more features with an isolation material, and forming one or more main gates adjacent to the one or more features. Methods include removing at least a portion of the bottom surface, exposing at least a portion of the sacrificial backgate material formed on the bottom surface and removing the sacrificial backgate material.
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
Exemplary substrate rinsing assemblies may include a rotor. The assemblies may include a plurality of substrate-grasping fingers disposed on the rotor. Each of the plurality of substrate-grasping fingers may be moveable between an open position and a closed position. An ultrasonic sensor may be disposed above the rotor at a position that is radially inward of the plurality of substrate-grasping fingers. The ultrasonic sensor may be configured to detect whether a position of a substrate received by the plurality of substrate-grasping fingers is within a predetermined operational range. The assemblies may include a plurality of reflective sensors. Each of the plurality of reflective sensors may be aligned with a respective one of the plurality of substrate grasping fingers. Each of the plurality of reflective sensors may be configured to detect whether the respective one of the plurality of substrate-grasping fingers is in the open position or the closed position.
H01L 21/68 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for positioning, orientation or alignment
G01V 8/22 - Detecting, e.g. by using light barriers using multiple transmitters or receivers using reflectors
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
Aspects of the present disclosure provide an apparatus for improving the performance of an output coupler of a waveguide display panel, such as reducing eye glow. An example waveguide includes an anti-reflective coating. The waveguide further includes a substrate disposed above the anti-reflective coating, wherein the substrate comprises a refractive index of 1.5 to 2.7. The waveguide further includes a grating layer disposed above the substrate, the grating layer comprising an output coupler grating comprising a refractive index of 2.1 to 2.5, and a coating that covers the output coupler grating, wherein the coating comprises a refractive index of 1.5 to 1.9.
G09G 3/3225 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
13.
SCANNING ELECTRON MICROSCOPE AND PHOTOMULTIPLIER THEREFOR AND METHOD OF EVALUATING A SAMPLE
A scanning electron microscope (SEM) configured to scan a sample by irradiating it with a plurality of source particles is provided. The SEM comprises a particle detector comprising a photomultiplier, the photomultiplier is configured to detect emitted particles from the sample and comprises a sensor surface having a plurality of cells each configured to detect one or more particles impinging thereon and to produce an output signal indicative of a quantity of impinging particles. The SEM further comprises a controller configured to define a plurality of zones each associated with one or more of the cells. The controller is further configured to calculate the magnitude of a triggering event based on the sum of output signals produced within a predetermined time interval by the cells within each of one or more of the zones. The geometry of the zones facilitates evaluating one or more properties of the sample.
Exemplary substrate rinsing assemblies may include a rotor. The assemblies may include a plurality of substrate-grasping fingers disposed on the rotor. Each of the plurality of substrate-grasping fingers may be moveable between an open position and a closed position. An ultrasonic sensor may be disposed above the rotor at a position that is radially inward of the plurality of substrate-grasping fingers. The ultrasonic sensor may be configured to detect whether a position of a substrate received by the plurality of substrate-grasping fingers is within a predetermined operational range. The assemblies may include a plurality of reflective sensors. Each of the plurality of reflective sensors may be aligned with a respective one of the plurality of substrate grasping fingers. Each of the plurality of reflective sensors may be configured to detect whether the respective one of the plurality of substrate-grasping fingers is in the open position or the closed position.
Techniques described herein relate to a design for a remote plasma source isolation valve with improved performance and extended life. Embodiments include a isolation valve comprising a valve body defining a flow passage between an upstream interface and a downstream interface, a closure member coupled to the valve body and movable between an open position permitting flow through the passage and a closed position obstructing the passage, and a sealing element disposed on a fixed wall of the valve body surrounding a port of the passage and recessed from a region of the passage traversed by flow when the closure member is in the open position, wherein the sealing element is arranged to engage the closure member in the closed position to fluidly isolate the upstream interface from the downstream interface.
An embodiment of a processing chamber includes an enclosure defining a processing volume, a substrate support positioned in the processing volume to support a substrate and to rotate the substrate about a central axis. In addition, the processing chamber includes a cleaning nozzle to direct a cleaning fluid onto a surface of the substrate within the processing volume. Further, the processing chamber includes an acoustic inspection assembly positioned in the processing volume, the acoustic inspection assembly including a fluid nozzle to direct a stream of fluid onto the surface of the substrate and an acoustic probe coupled to the fluid nozzle such that the acoustic probe is configured to direct an acoustic wave through the stream of fluid to detect a defect in the substrate.
G01N 29/22 - Investigating or analysing materials by the use of ultrasonic, sonic or infrasonic wavesVisualisation of the interior of objects by transmitting ultrasonic or sonic waves through the object Details
G01N 29/44 - Processing the detected response signal
17.
METHOD OF TRAINING AN ML-BASED PREDICTION MODEL FOR A THIN FILM MANUFACTURING PROCESS, METHOD FOR ASSISTING A THIN FILM MANUFACTURING PROCESS, METHOD FOR MANUFACTURING DEVICES, AND COMPUTER PROGRAM PRODUCT THEREFOR
A method of training an ML-based prediction model for a thin film manufacturing process, includes obtaining precision training data sets including selected directly controllable parameters used during manufacturing of thin films on substrates in design of experiments (DoE) one or more obtained result maps of a respective property of the manufactured thin films on the substrates in the DoE, and a metrology standard, and obtaining customer training data sets. The customer training data sets includes directly controllable parameters used during manufacturing of thin films on substrates in a customer facility, one or more obtained result maps of the respective property of the manufactured thin films, and metrology data referring to the respective property of the manufactured thin films. Based on the metrology data and the metrology standard, the ML-based prediction model is determined.
H01L 21/70 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereofManufacture of integrated circuit devices or of specific parts thereof
18.
Cover ring for use in a semiconductor processing chamber
Embodiments of the disclosure include a processing chamber assembly that comprises: a chamber comprising a substrate-support assembly; a pulsed voltage generator comprising an output connection that is electrically coupled to a plurality of biasing electrodes embedded within the substrate-support assembly; and one or more chucking modules, wherein a chucking module of the one or more chucking modules comprises a direct-current voltage supply that is electrically coupled to one of the plurality of biasing electrodes through a corresponding bias compensation module that comprises a plurality of passive electrical components.
C23C 16/06 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
C23C 16/503 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using DC or AC discharges
C23C 16/505 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using radio frequency discharges
C23C 16/515 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using pulsed discharges
Embodiments described herein relate to sub-pixel circuits, displays including sub-pixel circuits, and a method of forming sub-pixel circuits that may be utilized in a display such as an organic light-emitting diode (OLED) display. Some configurations of the displays described herein, include the sub-pixel circuits and at least one sensor opening adjacent to the overhang structure and an adjacent sub-pixel circuit. The at least one sensor opening includes a sensor disposed thereunder. Other configurations displays described herein, include sub-pixel circuits including OLED sub-pixels and a transparent sub-pixel such that a sensor is disposed thereunder. The configurations described herein utilize sensors that are integrated to increase the transmittance of the display while eliminating the need for bezels and reducing dead zones in the display.
Methods for forming a semiconductor structure and semiconductor structures are described. The method comprises non-selectively depositing an amorphous silicon layer on a top surface and a sidewall surface of at least one contact trench on a substrate and a crystalline silicon layer on a bottom surface of the at least one contact trench at a temperature less than or equal to 400 °C, the bottom surface including a source/drain material. The amorphous silicon layer is selectively removed from the top surface and the sidewall surface at a temperature less than or equal to 400 °C. The method may be performed in a processing chamber without breaking vacuum.
H10D 62/83 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
H10D 64/62 - Electrodes ohmically coupled to a semiconductor
Provided are methods to reduce the thickness of a high-ĸ layer needed in a DRAM capacitor and, thus, allow the cell electrodes to be larger, giving higher cell capacitance. A tantalum nitride (TaN) layer is introduced as a liner in the capacitor hole before a titanium nitride (TiN) electrode layer. The TaN layer converts to a thin layer of tantalum oxide (Ta2O5), which permits a reduction in the high-ĸ layer thickness for the same capacitance versus leakage. Because this Ta2O5 is formed directly on the cell electrode, it ensures a low leakage film exists in the narrowest gaps even before the high-ĸ layer is deposited.
Chemical precursor recovery systems and methods of recovering and reusing semiconductor manufacturing chemistry are disclosed. The recovery systems include a cold trap inlet line in fluid communication with a plurality of cold traps and a cold trap outlet line. The plurality of cold traps is configured to condense the chemical precursors and are arranged based on semiconductor manufacturing process conditions.
B01D 53/00 - Separation of gases or vapoursRecovering vapours of volatile solvents from gasesChemical or biological purification of waste gases, e.g. engine exhaust gases, smoke, fumes, flue gases or aerosols
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
25.
GAS DISTRIBUTION ASSEMBLIES FOR SEMICONDUCTOR DEVICES
Gas distribution assemblies for semiconductor devices are described. The gas distribution assemblies include a backplate, a faceplate, a counterbored hole, and at least one orifice. The at least one orifice includes, for example, at least one straight orifice, or at least two angled orifices. Some embodiments of the gas distribution assemblies provide for reduced plasma damage in a processing chamber. Some embodiments of the gas distribution assemblies provide for reduced jetting on a substrate in a processing chamber. Methods of reducing plasma damage in gas distribution assemblies are also described.
Board-level transmissions can inadvertently reveal secret information when intercepted by an EM probe within range of an electronic assembly. To mitigate the side-channel attacks, an electronic assembly may measure a real-time impedance at a receiving subsystem to detect changes in the impedance caused by the added impedance of the EM probe. A controller may then look up electric and magnetic field values corresponding to the measured impedance to identify a location of the EM probe. Component values may be selected for an adjustable impedance to steer the EM emissions away from the EM probe. The system may react continuously to any movements of the probe to adjust the direction of any EM emissions away from the probe.
H03H 7/40 - Automatic matching of load impedance to source impedance
G01R 27/32 - Measuring attenuation, gain, phase shift, or derived characteristics of electric four-pole networks, i.e. two-port networksMeasuring transient response in circuits having distributed constants
An embodiment of a processing chamber includes an enclosure defining a processing volume, a substrate support positioned in the processing volume to support a substrate and to rotate the substrate about a central axis. In addition, the processing chamber includes a cleaning nozzle to direct a cleaning fluid onto a surface of the substrate within the processing volume. Further, the processing chamber includes an acoustic inspection assembly positioned in the processing volume, the acoustic inspection assembly including a fluid nozzle to direct a stream of fluid onto the surface of the substrate and an acoustic probe coupled to the fluid nozzle such that the acoustic probe is configured to direct an acoustic wave through the stream of fluid to detect a defect in the substrate.
G01N 29/28 - Investigating or analysing materials by the use of ultrasonic, sonic or infrasonic wavesVisualisation of the interior of objects by transmitting ultrasonic or sonic waves through the object Details providing acoustic coupling
THE FLORIDA INTERNATIONAL UNIVERSITY BOARD OF TRUSTEES (USA)
Inventor
Khasgiwala, Mudit Sunilkumar
Ghosh, Kumal
Khosravi, Arvin
Kengeri, Subramani
Volakis, John Leonidas
Bojja Venkatakrishnan, Satheesh
Pulugurtha, Markondeyaraj
Al Duhni, Ghaleb Saleh Ghaleb
Jaiswal, Veeru
Abstract
A reconfigurable device may include a substrate including a glass structure. The glass structure cavity including one or more multiferroic bodies, the one or more multiferroic bodies able to move within the glass structure in response to a magnetic field. A device may be formed on a first side of the substrate and adjacent to the glass-lined cavity. The device may include performance characteristics based at least in part on a position of the one or more multiferroic bodies within the cavity. The device may include a control line formed on a second side of the substrate and adjacent to the glass-lined cavity, such that an electrical current in the metal line forms the magnetic field within the glass-lined cavity.
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H01F 1/44 - Magnets or magnetic bodies characterised by the magnetic materials thereforSelection of materials for their magnetic properties of magnetic liquids, e.g. ferrofluids
Board-level transmissions can inadvertently reveal secret information when intercepted by an EM probe within range of an electronic assembly. To mitigate the side-channel attacks, an electronic assembly may measure a real-time impedance at a receiving subsystem to detect changes in the impedance caused by the added impedance of the EM probe. A controller may then look up electric and magnetic field values corresponding to the measured impedance to identify a location of the EM probe. Component values may be selected for an adjustable impedance to steer the EM emissions away from the EM probe. The system may react continuously to any movements of the probe to adjust the direction of any EM emissions away from the probe.
A system configured to obtain, by a processor, a set of manufacturing data associated with a particle event that occurred during a manufacturing process performed by a substrate processing system. A respective subset of data from the set of manufacturing data is provided as input to each machine learning model of a plurality of machine learning models. A respective output is obtained from each of the machine learning models. Each output is indicative of diagnostic data associated with the particle event. A diagnostic report is generated based on the output data.
Embodiments described herein relate to optical waveguide devices, and related apparatus and methods. In one or more embodiments, a device includes a waveguide. The waveguide includes at least one grating disposed over an eye-side surface or a world-side surface opposing the eye-side surface of a waveguide substrate. The device includes a lens coupled to one of the eye-side surface or the world-side surface. There is at least one compensation lens disposed on the lens, the compensation lens having an additional optical property to compensate for the lens.
Embodiments described herein generally relate to a display. More specifically, embodiments described herein relate to sub-pixel circuits and methods of forming subpixel circuits that may be utilized in a display such as an organic light-emitting diode (OLED) display. In one or more embodiments, a sub-pixel circuit includes a substrate and a plurality of anodes disposed over the substrate. Overhang structures are disposed over the substrate in between adjacent anodes. Each overhang structure including a lower structure and an upper structure disposed over the lower structure. The upper structure has a bottom surface that laterally extends beyond a top surface of the lower structure to form an overhang. An organic light emitting (OLE) material is disposed over the anodes. A cathode is disposed over the OLE material. An encapsulation material disposed is over the cathode. A filler material disposed over the encapsulation material. A cover disposed over the filler material.
Embodiments described herein relate to a display device including a grid divided into zones, each zone with independently adjustable voltage levels that are dynamically adjusted based on the brightness or content requirements of the pixels within that zone, reference voltage (VSS) power lines extending across rows of the grid, and supply voltage (VDD) power lines extending across columns of the grid. Adjusting power delivery includes adjusting reference voltage (VSS) power lines connected to rows of the grid. Adjusting power delivery includes adjusting supply voltage (VDD) power lines connected to columns of the grid. Supply voltage (VDD) and reference voltage (VSS) are configured to be individually controlled in each column or row.
G09G 3/3266 - Details of drivers for scan electrodes
G09G 3/3233 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
G09G 3/3291 - Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
Provided is a DRAM device having a support layer to hold the bWL features before being filled with the electrode metal. The support layer keeps the structure supported from the top surface but does not prevent the gap fill. A temporary gap-fill material is first deposited in the bWL gaps and then recessed to expose the top edges. A support layer material is then deposited on the structure by plasma enhanced chemical vapor deposition (PECVD). The device is then patterned orthogonal and with pitch greater than the bWL pitch. The temporary gap-fill material is then removed, forming support beams comprising the support material. A metal can then be deposited to fill the bWL gaps under the support beams.
Embodiments herein include high throughput density chemical mechanical polishing (CMP) modules and customizable modular CMP systems formed thereof. In one embodiment, a polishing module features a carrier support module, a carrier loading station, and a polishing station. The carrier support module features a carrier platform and one or more carrier assemblies. The one or more carrier assemblies each comprise a corresponding carrier head suspended from the carrier platform. The carrier loading station is used to transfer substrates to and from the carrier heads. The polishing station comprises a polishing platen. The carrier support module, the substrate loading station, and the polishing station comprise a one-to-one-to-one relationship within each of the polishing modules. The carrier support module is positioned to move the one or more carrier assemblies between a substrate polishing position disposed above the polishing platen and a substrate transfer position disposed above the substrate loading station.
Methods of forming SiCON films comprising sequential exposure to a silicon precursor and a mixture of alkanolamine and amine reactants and an optional plasma are described. Methods of forming a silicon-containing film comprising sequential exposure to a silicon precursor and an epoxide with an optional plasma exposure are also described.
Methods of manufacturing electronic devices are described. Embodiments of the present disclosure advantageously provide methods of manufacturing electronic devices that meet reduced thickness, reduced leakage, lower thermal budget, and Vt requirements (including multi-Vt), and have improved device performance and reliability. The method comprises forming a P-dipole stack and an N-dipole stack on a semiconductor substrate by: depositing an interfacial layer (e.g., silicon oxide (SiOx)) on the top surface of the channel; depositing a hafnium-containing layer comprising hafnium oxide (HfOx) and having a thickness of less than or equal to 5 Å on the interfacial layer; and depositing a dipole layer comprising lanthanum nitride (LaN) on the hafnium-containing layer.
H10D 64/68 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
A method may include providing a nanosheet device stack that includes a lower patterned device stack and a upper patterned device stack, disposed above the lower patterned device stack, where the lower patterned device stack is disposed on a substrate base. The method may further include forming a lower dummy gate layer around the lower patterned device stack, and forming a upper dummy gate layer around the upper patterned device stack. The method may also include patterning the upper dummy gate layer to form a upper dummy gate around the upper patterned device stack, wherein an upper gate slot is formed. The method may also include patterning the lower dummy gate layer using the upper gate slot, wherein a gate slot is formed that extends through the lower patterned device stack and the upper patterned device stack.
A scanning electron microscope (SEM) configured to scan a sample by irradiating it with a plurality of source particles. The SEM comprises a particle detector comprising a photomultiplier, the photomultiplier is configured to detect emitted particles from the sample and comprises a sensor surface having a plurality of cells each configured to detect one or more particles impinging thereon and to produce an output signal indicative of a quantity of impinging particles. The SEM further comprises a controller configured to define a plurality of zones each associated with one or more of the cells. The controller is further configured to calculate the magnitude of a triggering event based on the sum of output signals produced within a predetermined time interval by the cells within each of one or more of the zones. The geometry of the zones facilitates evaluating one or more properties of the sample.
In one example, a swapper module includes a housing defining an internal volume, and a swapper at least partially disposed within the internal volume of the housing and actuatable within the housing. The swapper includes a shaft, a first arm coupled to the shaft, and a second arm coupled to the shaft. A first seal plate is disposed at a distal end of the first arm, and a second seal plate is disposed at a distal end of the second arm. An actuator is coupled to the swapper to vertically and rotatably actuate the swapper.
Methods for filling a substrate feature with a seamless fluorine free tungsten gap fill are described. Methods comprise exposing a substrate surface to a tungsten precursor and a reducing agent substantially simultaneously, wherein the dosage of the tungsten precursor is in a range of from greater than 0.2 sccm to less than 5 sccm.
A method may include providing a nanosheet device stack that includes a lower patterned device stack and a upper patterned device stack, disposed above the lower patterned device stack, where the lower patterned device stack is disposed on a substrate base. The method may further include forming a lower dummy gate layer around the lower patterned device stack, and forming a upper dummy gate layer around the upper patterned device stack. The method may also include patterning the upper dummy gate layer to form a upper dummy gate around the upper patterned device stack, wherein an upper gate slot is formed. The method may also include patterning the lower dummy gate layer using the upper gate slot, wherein a gate slot is formed that extends through the lower patterned device stack and the upper patterned device stack.
A method and a device are provided to measure temperatures of a semiconductor wafer in a semiconductor chamber. The device is formed by depositing a thin film matrix stack of aluminum thermoelements and zinc oxide thermoelements on a semiconductor wafer, wherein the aluminum thermoelements and the zinc oxide thermoelements form a junction at each intersection of the thin film matrix and each junction generates a thin film thermocouple. A multiplexor and a microprocessor are affixed to the thin film matrix stack to receive a thermoemf signal from each thin film thermocouple. The generated signals from the thin film thermocouples may be communicated wirelessly. The generated signals from the thin film thermocouples may be processed and compared to determine a number of signals that should be communicated from a local group based on available bandwidth.
Internal meshes may causes a material discontinuity at the edge of a silicon wafer at a transition to the material of the pedestal. This causes a corresponding discontinuity in the RF power delivered to the plasma and consequently in the plasma profile. To solve this problem, one or more external meshes may be added around the periphery of the pedestal around the substrate. These external meshes may be individually coupled to variable impedances or variable RF sources. A controller may adjust the variable impedances and/or RF sources in order to tune the plasma profile around the edge of the substrate. This allows plasma-enhanced processes to provide a uniform plasma profile over the substrate, resulting in consistent and uniform process.
The present disclosure relates to pre-heat ring structures for alignment, and related liners, chamber kits, processing chambers, and methods. In one or more embodiments, a chamber kit for disposition in a processing chamber includes a liner. The liner includes a wall, one or more ledges extending inwardly relative to the wall, and a plurality of posts extending relative to the one or more ledges. The plurality of posts are azimuthally spaced from each other by at least 100 degrees. A first post is spaced from a second post by a first angle, and the first post spaced from a third post by a second angle that is different than the first angle. The chamber kit includes a pre-heat ring that includes a plurality of openings formed in an outer region. The plurality of openings are sized and shaped to respectively receive at least one post of the plurality of posts.
Embodiments described herein generally relate to a display. More specifically, embodiments described herein relate to sub-pixel circuits and methods of forming sub-pixel circuits that may be utilized in a display such as an organic light-emitting diode (OLED) display. In one or more embodiments, a sub-pixel circuit includes at least two anodes disposed over a substrate. A pixel-isolation structure (PIS) is disposed between the anodes. An overhang structure is disposed over the PIS. A protective layer is disposed between the PIS and the overhang structure. The protective layer extends over a portion of an upper surface of the anodes.
A method of forming a microelectronic device includes depositing a metal cap layer on a metal surface of a feature formed in a substrate, depositing a self-assembled monolayer (SAM) selectively on the metal cap layer on the metal surface of the feature over a dielectric surface of the feature, depositing a barrier layer selectively on the dielectric surface, and removing the SAM.
A scanning electron microscope (SEM) is provided, configured to evaluate one or more properties of a sample comprising a plurality of repeating features. The SEM comprises a scanning arrangement to scan a site on the sample by irradiating it with source particles and detecting resulting signals, and a controller to operate the SEM and evaluate properties at the site based on the signals. The scanning arrangement scans equivalent sites of interest on the features for a scan-duration which is less than an acquisition- duration necessary for evaluation of a property of interest. The sum of the scan-durations is no less than the acquisition-duration. The controller aggregates measurements of the detected signals produced by each of the equivalent sites of interest, and evaluates one or more predetermined properties of the sites of interest on the plurality of repeating features based at least partially on the aggregated measurements.
36 - Financial, insurance and real estate services
Goods & Services
(1) Charitable services, namely, providing financial support to women college students in STEM areas to complete their college education for the purpose of facilitating their career pathway in technology, including the semiconductor industry.
50.
MULTI-ZONE RF FOR WAFER EDGE PLASMA PROFILE TUNING
Internal meshes may causes a material discontinuity at the edge of a silicon wafer at a transition to the material of the pedestal. This causes a corresponding discontinuity in the RF power delivered to the plasma and consequently in the plasma profile. To solve this problem, one or more external meshes may be added around the periphery of the pedestal around the substrate. These external meshes may be individually coupled to variable impedances or variable RF sources. A controller may adjust the variable impedances and/or RF sources in order to tune the plasma profile around the edge of the substrate. This allows plasma-enhanced processes to provide a uniform plasma profile over the substrate, resulting in consistent and uniform process.
C23C 16/505 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using radio frequency discharges
C23C 16/52 - Controlling or regulating the coating process
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
51.
METHOD OF LAMINATING AN INTERPOSER FOR DIE TRANSFER SUBSTRATES
Embodiments of the present disclosure generally relate to LED pixels and methods of fabricating LED pixels. The device includes a lamination module. The lamination module includes a polymer film roll configured to supply a polymer film to the lamination module, a bottom liner recovery roller, a top liner recovery roller, a cutting mechanism, a substrate source, a conveyor system, and a plurality of film rollers. The polymer film includes one or more polymer layers, a top liner, and a bottom liner. The cutting mechanism is configured to cut the one or more polymer layers and the top liner. The cutting mechanism comprises a first blade and a second blade. A space between the first blade and the second blade is less than about 10 cm. The substrate source is configured to supply a substrate.
B32B 38/00 - Ancillary operations in connection with laminating processes
B32B 37/00 - Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding
B32B 37/22 - Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by the properties of the layers with all layers existing as coherent layers before laminating involving the assembly of both discrete and continuous layers
B32B 37/26 - Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by the properties of the layers with at least one layer which influences the bonding during the laminating process, e.g. release layers or pressure equalising layers
B32B 39/00 - Layout of apparatus or plants, e.g. modular laminating systems
H10H 29/03 - Manufacture or treatment using mass transfer of LEDs, e.g. by using liquid suspensions
Embodiments herein are directed to localized stress modulation via ion implant to a nitride film. In some approaches, a nitride film may be formed over a substrate, a metrology scan of the nitride film may be performed to measure stress information of the nitride film at a plurality of locations, and ions may be directed to the nitride film during an ion implant. A dose of the ion implant may vary across the nitride film based on the stress information of the nitride film at each of the plurality of locations.
A scanning electron microscope (SEM) is provided, configured to evaluate one or more properties of a sample comprising a plurality of repeating features. The SEM comprises a scanning arrangement to scan a site on the sample by irradiating it with source particles and detecting resulting signals, and a controller to operate the SEM and evaluate properties at the site based on the signals. The scanning arrangement scans equivalent sites of interest on the features for a scan-duration which is less than an acquisition-duration necessary for evaluation of a property of interest. The sum of the scan-durations is no less than the acquisition-duration. The controller aggregates measurements of the detected signals produced by each of the equivalent sites of interest, and evaluates one or more predetermined properties of the sites of interest on the plurality of repeating features based at least partially on the aggregated measurements.
The Disclosure is directed to trench tip squaring in self-aligned multi-patterning process. One method may include forming a plurality of linear spacers over a base layer of a semiconductor device, wherein a set of adjacent linear spacers of the plurality of linear spacers define a trench. The method may further include providing a pillar in the trench, wherein the pillar comprises a plurality of recessed corner areas at an intersection between the pillar and the set of adjacent linear spacers. The method may further include performing a plasma treatment to form a film layer in the plurality of recessed corner areas, wherein the plasma treatment comprises directing ions to the plurality of linear spacers at a non-perpendicular angle relative to a plane defined by an upper surface of the base layer.
Certain aspects provided herein generally include apparatus, plasma processing systems and methods for chamber cleaning. One example apparatus generally includes: a plasma impeding element disposed adjacent to a substrate support element of a chamber, wherein the plasma impeding element includes a surface with one or more openings configured to allow fluid flow from an upper region of the chamber to a lower region of the chamber; and one or more straps coupled configured to be coupled between the plasma impeding element and a grounded body, wherein the one or more straps are disposed within the lower region of the chamber.
A chuck for a substrate includes a plurality of chucking units. Each chucking unit includes a chuck element having a substrate support surface and a chucking electrode. Each chuck element receives a portion of a substrate on the substrate support surface. Each chuck element is coupled to a base of the chuck by a driver having first and second actuators. Actuation of the drivers facilitates deforming the substrate, such as in preparation for a bonding operation.
A system configured to detect, by a processing device, an anomaly that occurred during a manufacturing process performed by a substrate processing system. A set of prompts is generated based on the anomaly. Each prompt is correlated to specific data obtained from one or more datastores. For each prompt, a respective output of the first trained machine learning model is obtained and a structured prompt is generated based on respective outputs. The structured prompt is provided as input to a second trained machine learning model an output of the second trained machine learning model is obtained. The output of the second trained machine learning model comprising a diagnostic report associated with the anomaly.
A processing system is provided including: a process chamber that includes: a chamber body disposed around an interior volume; a substrate support positioned in the interior volume; one or more gas injectors configured to direct gas into a first region of the interior volume; and an exhaust channel configured to exhaust gas from a second region of the interior volume. The first region and the second region are located on opposing sides of a central vertical axis extending through a center of the substrate support. The processing system further includes one or more gas conduits positioned over the substrate support in the interior volume, each gas conduit including a gas outlet configured to direct gas towards the substrate support.
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
Embodiments described herein relate to a method that includes obtaining a process parameter within a chamber with a sensor substrate, and inputting the process parameter into a model. In an embodiment, the model is configured to output a change to the chamber that improves a uniformity of a process. In an embodiment, the method further includes implementing the change to the chamber.
Embodiments described herein generally relate to metallization and activation of substrate surfaces for manufacturing and assembly of electronic devices. More particularly, embodiments provide apparatus and methods for improving surface property uniformity across large substrates. In some embodiment, a method is provided and includes measuring a surface property of a substrate at one or more locations on a surface of the substrate, subjecting the substrate to a pre-cleaning process, where at least one process variable of the pre-cleaning process is adjusted based on the surface property measurements, measuring a surface energy of the substrate at one or more locations on the surface of the substrate after the pre-cleaning process, and exposing one or more locations on the surface of the substrate to radiation to activate the substrate.
Embodiments described herein relate to a method including forming a pixel structure with sub-pixels, each pixel structure having a first structure and a second structure, where the second structure is disposed over the first structure, forming an overhang extension defining an outer surface and extending laterally past an upper surface of the first structure to define an overhang, and constructing a sub-pixel with a surface in a scan direction that is longer than a sub-pixel surface in a non-scan direction based on a location of the outer surface of the overhang extension. The sub- pixel of the sub-pixels has a rectangular shape with a long surface being perpendicular to the scan direction. An angle of the scan direction is between 80 and 100 degrees.
An embodiment of a substrate processing chamber includes a chamber body having a central axis and at least partially defining a processing region and a lid coupled to an upper end of the chamber body. The lid defines a cavity and includes a lower wall that is configured to separate the processing region from the cavity. In addition, the substrate processing chamber includes an inductively coupled plasma (ICP) assembly that includes one or more inductive coils at least partially positioned in the cavity. Further, the substrate processing chamber includes a substrate support assembly positioned in the chamber body that is configured to support a substrate. Still further, the substrate processing chamber includes a deposition block assembly positioned axially between the substrate support assembly and the one or more inductive coils, wherein the deposition block assembly is configured to restrict material deposition on the lower wall.
C23C 16/505 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using radio frequency discharges
C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
C23C 16/52 - Controlling or regulating the coating process
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C23C 16/46 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for heating the substrate
C23C 16/448 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for generating reactive gas streams, e.g. by evaporation or sublimation of precursor materials
C23C 16/54 - Apparatus specially adapted for continuous coating
63.
METAL HALIDE PRE-SOAK AND PLASMA TREATMENT PROCESS SEQUENCE
Embodiments of the disclosure include a method of forming an interconnect structure that is coupled to a metal gate of a field effect transistor (FET). The method includes exposing a device structure to a metal halide pre-soak, wherein the device structure comprises at least one feature formed in a first dielectric layer, wherein the at least one feature exposes a surface of a second dielectric layer surrounding a metal gate. The method further includes exposing the device structure to a plasma treatment, and at least partially filling the at least one feature with a metal fill material.
H10D 64/68 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
A method includes training a machine learning model using a training dataset including historical image data of a structure, the historical image data including a plurality of images of the structure. The training includes labeling regions of a source image of the plurality of images to create a source mask for the source image and providing as training input to the machine learning model the source image and a target image of the plurality of images. The training further includes receiving as output from the machine learning model a deformation field between the source image and the target image. The training further includes applying the deformation field to the source mask to create a warped source mask. The training further includes computing a loss associated with the warped source mask. The training further includes updating weights of the machine learning model based on the loss.
The techniques described herein relate to suppression of arcs during plasma-based semiconductor processes. The techniques can include delivering radio-frequency (RF) power a plasma in a semiconductor processing chamber. The techniques can include detecting a first indication of a first arc event in the semiconductor processing chamber. In response to detecting the first indication of the first arc event, causing the RF power to the plasma to pulse. Causing the RF power to the plasma to pulse can include repeatedly causing the RF power to pulse on and off to suppress the first arc event.
A system configured to obtain, by a processor, a set of manufacturing data associated with a particle event that occurred during a manufacturing process performed by a substrate processing system. A respective subset of data from the set of manufacturing data is provided as input to each machine learning model of a plurality of machine learning models. A respective output is obtained from each of the machine learning models. Each output is indicative of diagnostic data associated with the particle event. A diagnostic report is generated based on the output data.
In one example, a swapper module includes a housing defining an internal volume, and a swapper at least partially disposed within the internal volume of the housing and actuatable within the housing. The swapper includes a shaft, a first arm coupled to the shaft, and a second arm coupled to the shaft. A first seal plate is disposed at a distal end of the first arm, and a second seal plate is disposed at a distal end of the second arm. An actuator is coupled to the swapper to vertically and rotatably actuate the swapper.
H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
B25J 11/00 - Manipulators not otherwise provided for
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
68.
RECONFIGURABLE SYSTEMS BY SHIFTING MATERIALS INSIDE A CAVITY
The Florida International University Board of Trustees (USA)
Inventor
Khasgiwala, Mudit Sunilkumar
Ghosh, Kunal
Khosravi, Arvin
Kengeri, Subramani
Volakis, John Leonidas
Bojja Venkatakrishnan, Satheesh
Pulugurtha, Markondeyaraj
Al Duhni, Ghaleb Saleh Ghaleb
Jaiswal, Veeru
Abstract
A reconfigurable device may include a substrate including a glass structure. The glass structure cavity including one or more multiferroic bodies, the one or more multiferroic bodies able to move within the glass structure in response to a magnetic field. A device may be formed on a first side of the substrate and adjacent to the glass-lined cavity. The device may include performance characteristics based at least in part on a position of the one or more multiferroic bodies within the cavity. The device may include a control line formed on a second side of the substrate and adjacent to the glass-lined cavity, such that an electrical current in the metal line forms the magnetic field within the glass-lined cavity.
H10N 30/05 - Manufacture of multilayered piezoelectric or electrostrictive devices, or parts thereof, e.g. by stacking piezoelectric bodies and electrodes
H10N 30/20 - Piezoelectric or electrostrictive devices with electrical input and mechanical output, e.g. functioning as actuators or vibrators
H10N 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one piezoelectric, electrostrictive or magnetostrictive element covered by groups
Methods for filling a substrate feature with a seamless fluorine free tungsten gap fill are described. Methods comprise exposing a substrate surface to a tungsten precursor and a reducing agent substantially simultaneously, wherein the dosage of the tungsten precursor is in a range of from greater than 0.2 sccm to less than 5 sccm.
C23C 16/04 - Coating on selected surface areas, e.g. using masks
C23C 16/08 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metal halides
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
A method and a device are provided to measure temperatures of a semiconductor wafer in a semiconductor chamber. The device is formed by depositing a thin film matrix stack of aluminum thermoelements and zinc oxide thermoelements on a semiconductor wafer, wherein the aluminum thermoelements and the zinc oxide thermoelements form a junction at each intersection of the thin film matrix and each junction generates a thin film thermocouple. A multiplexor and a microprocessor are affixed to the thin film matrix stack to receive a thermoemf signal from each thin film thermocouple. The generated signals from the thin film thermocouples may be communicated wirelessly. The generated signals from the thin film thermocouples may be processed and compared to determine a number of signals that should be communicated from a local group based on available bandwidth.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
G01K 7/02 - Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat using thermoelectric elements, e.g. thermocouples
71.
RESIDUAL LIQUID METAL TREATMENT DURING LED FABRICATION
The present disclosure generally includes a method for forming a light emitting diode (LED) device, that includes using laser irradiation to remove a carrier substrate from the LED device, oxidizing a residual liquid metal layer formed by the laser irradiation by soaking the LED device in heated de-ionized water, rinsing the de-ionized water off the LED device, and drying the LED device using a drying process.
C23C 8/42 - Solid state diffusion of only non-metal elements into metallic material surfacesChemical surface treatment of metallic material by reaction of the surface with a reactive gas, leaving reaction products of surface material in the coating, e.g. conversion coatings, passivation of metals using liquids, e.g. salt baths, liquid suspensions only one element being applied
H10H 29/24 - Assemblies of multiple devices comprising at least one light-emitting semiconductor device covered by group comprising multiple light-emitting semiconductor devices
Embodiments described herein relate to a photonic device having a microlens and micromirror embedded therein and methods of fabricating such a device. An example photonic device comprises a substrate; a buried oxide (BOX) layer disposed over the substrate; a waveguide layer disposed over the BOX layer, the waveguide layer comprising a waveguide; a micromirror arranged in at least a portion of the waveguide layer; a cladding disposed over the waveguide layer; and a lens layer disposed over the cladding, the lens layer having a microlens aligned with the micromirror.
G02B 6/122 - Basic optical elements, e.g. light-guiding paths
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
73.
PHARMACEUTICAL COMPOSITIONS WITH IMPROVED DISSOLUTION
This disclosure pertains to a coated particle that has a drug-containing core and an inorganic coating layer and methods of preparing thereof. The coated particle has an improved solubility comparing to the uncoated drug-containing core. The drug-containing core comprises an active pharmaceutical ingredient (API) with a low solubility.
A device including a first signal pad and a second signal pad. Each signal pad includes an electrically conductive layer coupled to a complementary metal-oxide-semiconductor (CMOS) layer. Each CMOS layer includes a light source driver coupled to a light source and a transimpedance amplifier coupled with a photodetector. The first and second signal pads are connected via an optical medium that is configured to couple a first optical signal between the light source of the first signal pad and the photodetector of the second signal pad and a second optical signal between the light source of the second signal pad and the photodetector of the first signal pad.
G02B 6/42 - Coupling light guides with opto-electronic elements
H10D 80/30 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising integrated circuit processor chips
H10D 86/80 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple passive components, e.g. resistors, capacitors or inductors
75.
IN SITU CLEANING OF DEPOSITION CHAMBER WITH MICROWAVE PLASMA
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
The techniques described herein relate to suppression of arcs during plasma-based semiconductor processes. The techniques can include delivering radio-frequency (RF) power a plasma in a semiconductor processing chamber. The techniques can include detecting a first indication of a first arc event in the semiconductor processing chamber. In response to detecting the first indication of the first arc event, causing the RF power to the plasma to pulse. Causing the RF power to the plasma to pulse can include repeatedly causing the RF power to pulse on and off to suppress the first arc event.
Techniques for measuring uniformity of layer thicknesses on semiconductor wafers are described herein. The techniques can include capturing an image of a portion of a wafer with a transmission electron microscope. The wafer includes a plurality of alternating layers of a first material and a second material. The techniques can include determining pixel intensities across the plurality of alternating layers in the image. The techniques can include fitting the pixel intensities to a model that is descriptive of a trend in the pixel intensities. The techniques can include determining a thickness for a first layer of the wafer based on the model.
A processing system is provided that includes a process chamber and a gas supply system. The process chamber includes: a chamber body disposed around an interior volume; a substrate support positioned in the interior volume; a plurality of gas injectors configured to direct gas into a first region of the interior volume; and an exhaust channel configured to exhaust gas from a second region of the interior volume. The gas supply system includes a main gas line coupled with a plurality of gas sources that include a first gas source; a plurality of gas lines, each gas line of the plurality of gas lines coupled between the main gas line and one of the gas injectors; and one or more auxiliary gas lines including a first auxiliary gas line coupled between the first gas source and a first gas line of the plurality of gas lines.
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
79.
DIE STRESS MODULATION FOR IMPROVED DEVICE LAYER STACKING
Embodiments herein are directed to localized die distortion correction. In some embodiments, a method includes performing a metrology scan of a substrate, wherein the metrology scan determines a die warp or a die bow for each die of a plurality of dies across the substrate. The method further includes directing first ions to the substrate, wherein the first ions are directed to a first die at a first dose and a first energy, and wherein the first dose and the first energy are determined based on the die warp or the die bow of the first die. The method further includes directing second ions to the substrate, wherein the second ions are directed to a second die at a second dose and a second energy, and wherein the second dose and the second energy are determined based on the die warp or the die bow of the second die.
H01J 37/317 - Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. ion implantation
H01J 37/302 - Controlling tubes by external information, e.g. programme control
Provided are memory devices and methods of manufacture that include an etch stop layer on the bottom of the memory stack. A memory device comprises a memory stack on an etch stop layer on a substrate, the memory stack comprising a plurality of channel layers and a corresponding plurality of sacrificial layers alternatingly arranged in a plurality of stack pairs, the etch stop layer having an etch stop layer thickness and each of the plurality of sacrificial layers having a sacrificial layer thickness, the etch stop layer thickness greater than the sacrificial layer thickness. The etch stop layer on the bottom of the memory stack is advantageous for backside wafer thinning in hybrid bonded memory devices.
Embodiments described herein relate to a device having a substrate, a first anode of a first organic light emitting diode (OLED) material disposed over the substrate, a second anode of a second OLED material disposed over the substrate, a third anode of a third OLED material disposed over the substrate, separation structures separating the first anode, the second anode, and the third another from each other and pixel structures formed over the separation structures, each pixel structure having a first structure and a second structure, the second structure disposed over the first structure, wherein the second structure includes an overhang extension extending laterally past an upper surface of the first structure to define an overhang.
An embodiment of a method includes depositing a metal silicide layer in a recessed feature defined on a substrate in a processing chamber by use of an inductively coupled plasma (ICP) assembly of the processing chamber. The recessed feature defines one or more sidewalls therein. In addition, the method includes etching the metal silicide layer off of the one or more sidewalls in the processing chamber. Further, the method includes depositing a second metal layer in the recessed feature on the metal silicide layer in the processing chamber.
A method of forming a microelectronic device includes pre-treating a metal surface formed on a substrate, depositing a self-assembled monolayer (SAM) selectively on the metal surface against a dielectric surface formed on the substrate, depositing a barrier layer selectively on the dielectric surface against the SAM, and removing the SAM.
A device including a first signal pad and a second signal pad. Each signal pad includes an electrically conductive layer coupled to a complementary metal-oxide-semiconductor (CMOS) layer. Each CMOS layer includes a light source driver coupled to a light source and a transimpedance amplifier coupled with a photodetector. The first and second signal pads are connected via an optical medium that is configured to couple a first optical signal between the light source of the first signal pad and the photodetector of the second signal pad and a second optical signal between the light source of the second signal pad and the photodetector of the first signal pad.
Embodiments herein relate to an optical defect inspection system and corresponding method. The optical defect inspection system includes a first camera disposed above a top side of optical devices formed on a substrate that is disposed on a stage and a second camera disposed below a bottom side of the optical devices, the bottom side opposing the top side. The defect inspection system further includes a first in-line light engine disposed below the first camera and above the top side, a second in-line light engine disposed above the second camera and below the bottom side, a first ring light engine disposed below the first in-line light engine and above the top side, and a second ring light engine disposed above the second in-line light engine and below the bottom side.
Embodiments of the present disclosure are directed to liners for glass vias and method for forming multi-layer liners for stress buffering in glass vias. In an embodiment, the method includes depositing a first sublayer over a surface of a substrate comprising a glass core and a via extending therethrough, in which the first sublayer comprises a compressive stress between about -500 MPa and about -1500 MPa. The method also includes depositing a second sublayer over the first sublayer inside the via, and a third sublayer over the second sublayer. The second sublayer comprises a Young’s modulus between about 1 GPa and about 15 GPa, and the third sublayer comprises a stress between about -100 MPa and about -800 MPa compressive stress.
Embodiments of the disclosure relate to articles, coated chamber components and methods of coating chamber components with a protective coating that includes at least one metal fluoride having a formula selected from the group consisting of M1xFw, M1xM2yFw and M1xM2yM3zFw, where at least one of M1, M2, or M3 is magnesium or lanthanum. The protective coating can be deposited by atomic layer deposition, chemical vapor deposition, electron beam ion assisted deposition, or physical vapor deposition.
C23C 16/30 - Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
89.
APPARATUS AND TECHNIQUES FOR SUBSTRATE PROCESSING USING INDEPENDENT ION SOURCE AND RADICAL SOURCE
A system may include a substrate stage to support a substrate, and a plurality of beam sources. The plurality of beam sources may include an ion beam source, the ion beam source arranged to direct an ion beam to the substrate, and a radical beam source, the radical beam source arranged to direct a radical beam to the substrate. The system may include a controller configured to control the ion beam source and the radical beam source to operate independently of one another, in at least one aspect, wherein the at least one aspect includes beam composition, beam angle of incidence, and relative scanning of a beam source with respect to the substrate.
Apparatus provide plasma to a processing volume of a chamber. The Apparatus may comprise a plurality of plasma sources, each with at least a dielectric tube inlet which is at least partially surrounded by a conductive tube which is configured to be connected to RF power to generate plasma and a gas inlet positioned opposite the dielectric tube inlet for a process gas and a dielectric tube directly connected to each of the plurality of plasma sources where the dielectric tube is configured to at least partially contain plasma generated by the plurality of plasma sources and to release radicals generated in the plasma via holes in the dielectric tube.
Methods of surface pretreatment during selective deposition are disclosed. One or more embodiment of the disclosure provides surface pretreatments which facilitate the removal of blocking layers. Some embodiments of the disclosure include a surface pretreatment comprising exposure of a substrate with a first surface and a second surface to modify the first surface, a blocking layer is deposited on the modified first surface, a film is selectively deposited on the second surface over the blocking layer, and the blocking layer is removed.
C23C 16/02 - Pretreatment of the material to be coated
C23C 16/04 - Coating on selected surface areas, e.g. using masks
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
A system includes a chamber having a substrate support and an upper member having an upper member surface positioned within the chamber that is vertically movable relative to the substrate support. One or more sensors each measure an edge location of a substrate on the substrate support. A linear stage assembly is coupled to the upper member and first and second motors operatively are coupled to a first side of a first linear stage and a second side of a second linear stage of a set of linear stages to move the linear stage assembly in a first direction and in a second direction. Control logic receives the edge location, determines an offset value of the substrate relative to the edge location, and controls at least one of the first or second motor using the offset value to center the upper member surface over the substrate.
H01L 21/68 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for positioning, orientation or alignment
C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
C23C 16/52 - Controlling or regulating the coating process
G01B 11/14 - Measuring arrangements characterised by the use of optical techniques for measuring distance or clearance between spaced objects or spaced apertures
93.
APPARATUS AND METHODS FOR SUBSTRATE-TO-SUBSTRATE BONDING
A chuck for a substrate includes a plurality of chucking units. Each chucking unit includes a chuck element having a substrate support surface and a chucking electrode. Each chuck element receives a portion of a substrate on the substrate support surface. Each chuck element is coupled to a base of the chuck by a driver having first and second actuators. Actuation of the drivers facilitates deforming the substrate, such as in preparation for a bonding operation.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 23/00 - Details of semiconductor or other solid state devices
94.
Trench Tip Squaring in Self-Aligned Multi-Patterning Process
The Disclosure is directed to trench tip squaring in self-aligned multi-patterning process. One method may include forming a plurality of linear spacers over a base layer of a semiconductor device, wherein a set of adjacent linear spacers of the plurality of linear spacers define a trench. The method may further include providing a pillar in the trench, wherein the pillar comprises a plurality of recessed corner areas at an intersection between the pillar and the set of adjacent linear spacers. The method may further include performing a plasma treatment to form a film layer in the plurality of recessed corner areas, wherein the plasma treatment comprises directing ions to the plurality of linear spacers at a non-perpendicular angle relative to a plane defined by an upper surface of the base layer.
Devices, systems, and methods for handling a wafer can include the use of an end effector comprising a pick body and one or more vacuum pick pad assembly attached to the pick body. Each vacuum pick pad assembly can include a pad base fixedly coupled to the pick body and a gimballed pad arranged against the pad base, where the gimballed pad is slidably movable relative to the pad base to any of a range of angular positions relative to the pad base. In addition, a suction path is arranged within the pick body in communication between a suction source and the gimballed pad.
B65G 47/90 - Devices for picking-up and depositing articles or materials
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
96.
RADIO FREQUENCY (RF) CHOKE FOR PARTICLE REDUCTION AND INCREASED CONDUCTANCE IN PRECLEAN CHAMBER
Certain aspects provided herein generally include apparatus, plasma processing systems and methods for chamber cleaning. One example apparatus generally includes: a plasma impeding element disposed adjacent to a substrate support element of a chamber, wherein the plasma impeding element includes a surface with one or more openings configured to allow fluid flow from an upper region of the chamber to a lower region of the chamber; and one or more straps coupled configured to be coupled between the plasma impeding element and a grounded body, wherein the one or more straps are disposed within the lower region of the chamber.
There is provided a system and method of examining a semiconductor specimen using a machine learning (ML) system comprising a first ML model and a second ML model. The method includes obtaining a runtime image capturing an image pattern of interest (POI) in the specimen, and a design image containing a design POI corresponding to the image POI; using the trained first ML model to process the runtime image and the design image, to obtain a spatial transformation map indicative of spatial transformation from the design POI to the image POI; and applying the spatial transformation map on the design image to obtain a transformed design image comprising a transformed design POI matching the geometry of the image POI in the runtime image. The first ML model has been previously trained in conjunction with the second ML model.
There is provided a system and method of hotspot searching. The method includes obtaining design data usable for manufacturing a semiconductor specimen; processing the design data using a machine learning (ML) model, to obtain a simulated image predicting appearance of an actual image of the semiconductor specimen, the ML model being previously trained for design-based image simulation to simulate one or more physical effects resulting from a manufacturing process of the specimen; extracting one or more contours from the simulated image; obtaining a metrology measurement pertaining to a metrology application based on the extracted contours; and comparing the metrology measurement with respect to a metrology rule related to the metrology application to identify one or more hotspots on the design data.
A metrology module for use with a substrate processing system includes a camera for scanning a substrate and a light source configured to direct light toward the substrate at a non-zero incidence angle. The module also includes a reflector having a non-flat mirror configured to reflect light to the camera. The non-flat mirror is configured to receive light reflected from the substrate at a consistent reflected angle.
B24B 49/12 - Measuring or gauging equipment for controlling the feed movement of the grinding tool or workArrangements of indicating or measuring equipment, e.g. for indicating the start of the grinding operation involving optical means
H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
Methods for reducing the resistance of a contact leverage fine grain sizes to increase thermal expansion during hybrid bonding for increased bonding strength and fine grain growth after bonding to decrease resistance of the contact. In some embodiments, the method may comprise bonding a first contact on a first substrate to a second contact on a second substrate where a first end region of the first contact has a bonding surface and has a first average grain size that is smaller than a second average grain size of a second end region that is opposite of the first end region and where the first end region has grain boundary pinning additives in the first end region and driving the additives from the first end region to the second end region after bonding using a thermal treatment to promote grain growth within the first end region.
