Devices, systems, and methods for handling a wafer can include the use of an end effector comprising a pick body and one or more vacuum pick pad assembly attached to the pick body. Each vacuum pick pad assembly can include a pad base fixedly coupled to the pick body and a gimballed pad arranged against the pad base, where the gimballed pad is slidably movable relative to the pad base to any of a range of angular positions relative to the pad base. In addition, a suction path is arranged within the pick body in communication between a suction source and the gimballed pad.
B65G 47/90 - Dispositifs pour saisir et déposer les articles ou les matériaux
H01L 21/683 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension
H01L 21/687 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension en utilisant des moyens mécaniques, p. ex. mandrins, pièces de serrage, pinces
2.
RADIO FREQUENCY (RF) CHOKE FOR PARTICLE REDUCTION AND INCREASED CONDUCTANCE IN PRECLEAN CHAMBER
Certain aspects provided herein generally include apparatus, plasma processing systems and methods for chamber cleaning. One example apparatus generally includes: a plasma impeding element disposed adjacent to a substrate support element of a chamber, wherein the plasma impeding element includes a surface with one or more openings configured to allow fluid flow from an upper region of the chamber to a lower region of the chamber; and one or more straps coupled configured to be coupled between the plasma impeding element and a grounded body, wherein the one or more straps are disposed within the lower region of the chamber.
Embodiments of the present disclosure are directed to liners for glass vias and method for forming multi-layer liners for stress buffering in glass vias. In an embodiment, the method includes depositing a first sublayer over a surface of a substrate comprising a glass core and a via extending therethrough, in which the first sublayer comprises a compressive stress between about -500 MPa and about -1500 MPa. The method also includes depositing a second sublayer over the first sublayer inside the via, and a third sublayer over the second sublayer. The second sublayer comprises a Young’s modulus between about 1 GPa and about 15 GPa, and the third sublayer comprises a stress between about -100 MPa and about -800 MPa compressive stress.
Methods of surface pretreatment during selective deposition are disclosed. One or more embodiment of the disclosure provides surface pretreatments which facilitate the removal of blocking layers. Some embodiments of the disclosure include a surface pretreatment comprising exposure of a substrate with a first surface and a second surface to modify the first surface, a blocking layer is deposited on the modified first surface, a film is selectively deposited on the second surface over the blocking layer, and the blocking layer is removed.
C23C 16/04 - Revêtement de parties déterminées de la surface, p. ex. au moyen de masques
C23C 16/455 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c.-à-d. procédés de dépôt chimique en phase vapeur [CVD] caractérisé par le procédé de revêtement caractérisé par le procédé utilisé pour introduire des gaz dans la chambre de réaction ou pour modifier les écoulements de gaz dans la chambre de réaction
H01J 37/32 - Tubes à décharge en atmosphère gazeuse
There is provided a system and method of hotspot searching. The method includes obtaining design data usable for manufacturing a semiconductor specimen; processing the design data using a machine learning (ML) model, to obtain a simulated image predicting appearance of an actual image of the semiconductor specimen, the ML model being previously trained for design-based image simulation to simulate one or more physical effects resulting from a manufacturing process of the specimen; extracting one or more contours from the simulated image; obtaining a metrology measurement pertaining to a metrology application based on the extracted contours; and comparing the metrology measurement with respect to a metrology rule related to the metrology application to identify one or more hotspots on the design data.
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
There is provided a system and method of examining a semiconductor specimen using a machine learning (ML) system comprising a first ML model and a second ML model. The method includes obtaining a runtime image capturing an image pattern of interest (POI) in the specimen, and a design image containing a design POI corresponding to the image POI; using the trained first ML model to process the runtime image and the design image, to obtain a spatial transformation map indicative of spatial transformation from the design POI to the image POI; and applying the spatial transformation map on the design image to obtain a transformed design image comprising a transformed design POI matching the geometry of the image POI in the runtime image. The first ML model has been previously trained in conjunction with the second ML model.
The Disclosure is directed to trench tip squaring in self-aligned multi-patterning process. One method may include forming a plurality of linear spacers over a base layer of a semiconductor device, wherein a set of adjacent linear spacers of the plurality of linear spacers define a trench. The method may further include providing a pillar in the trench, wherein the pillar comprises a plurality of recessed corner areas at an intersection between the pillar and the set of adjacent linear spacers. The method may further include performing a plasma treatment to form a film layer in the plurality of recessed corner areas, wherein the plasma treatment comprises directing ions to the plurality of linear spacers at a non-perpendicular angle relative to a plane defined by an upper surface of the base layer.
Apparatus provide plasma to a processing volume of a chamber. The Apparatus may comprise a plurality of plasma sources, each with at least a dielectric tube inlet which is at least partially surrounded by a conductive tube which is configured to be connected to RF power to generate plasma and a gas inlet positioned opposite the dielectric tube inlet for a process gas and a dielectric tube directly connected to each of the plurality of plasma sources where the dielectric tube is configured to at least partially contain plasma generated by the plurality of plasma sources and to release radicals generated in the plasma via holes in the dielectric tube.
A system includes a chamber having a substrate support and an upper member having an upper member surface positioned within the chamber that is vertically movable relative to the substrate support. One or more sensors each measure an edge location of a substrate on the substrate support. A linear stage assembly is coupled to the upper member and first and second motors operatively are coupled to a first side of a first linear stage and a second side of a second linear stage of a set of linear stages to move the linear stage assembly in a first direction and in a second direction. Control logic receives the edge location, determines an offset value of the substrate relative to the edge location, and controls at least one of the first or second motor using the offset value to center the upper member surface over the substrate.
H01L 21/68 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le positionnement, l'orientation ou l'alignement
C23C 16/458 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c.-à-d. procédés de dépôt chimique en phase vapeur [CVD] caractérisé par le procédé de revêtement caractérisé par le procédé utilisé pour supporter les substrats dans la chambre de réaction
C23C 16/52 - Commande ou régulation du processus de dépôt
G01B 11/14 - Dispositions pour la mesure caractérisées par l'utilisation de techniques optiques pour mesurer la distance ou la marge entre des objets ou des ouvertures espacés
10.
APPARATUS AND TECHNIQUES FOR SUBSTRATE PROCESSING USING INDEPENDENT ION SOURCE AND RADICAL SOURCE
A system may include a substrate stage to support a substrate, and a plurality of beam sources. The plurality of beam sources may include an ion beam source, the ion beam source arranged to direct an ion beam to the substrate, and a radical beam source, the radical beam source arranged to direct a radical beam to the substrate. The system may include a controller configured to control the ion beam source and the radical beam source to operate independently of one another, in at least one aspect, wherein the at least one aspect includes beam composition, beam angle of incidence, and relative scanning of a beam source with respect to the substrate.
A chuck for a substrate includes a plurality of chucking units. Each chucking unit includes a chuck element having a substrate support surface and a chucking electrode. Each chuck element receives a portion of a substrate on the substrate support surface. Each chuck element is coupled to a base of the chuck by a driver having first and second actuators. Actuation of the drivers facilitates deforming the substrate, such as in preparation for a bonding operation.
H01L 21/683 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
Embodiments of the disclosure relate to articles, coated chamber components and methods of coating chamber components with a protective coating that includes at least one metal fluoride having a formula selected from the group consisting of M1xFw, M1xM2yFw and M1xM2yM3zFw, where at least one of M1, M2, or M3 is magnesium or lanthanum. The protective coating can be deposited by atomic layer deposition, chemical vapor deposition, electron beam ion assisted deposition, or physical vapor deposition.
H01J 37/32 - Tubes à décharge en atmosphère gazeuse
C23C 16/30 - Dépôt de composés, de mélanges ou de solutions solides, p. ex. borures, carbures, nitrures
C23C 16/44 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c.-à-d. procédés de dépôt chimique en phase vapeur [CVD] caractérisé par le procédé de revêtement
C23C 16/455 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c.-à-d. procédés de dépôt chimique en phase vapeur [CVD] caractérisé par le procédé de revêtement caractérisé par le procédé utilisé pour introduire des gaz dans la chambre de réaction ou pour modifier les écoulements de gaz dans la chambre de réaction
13.
METROLOGY MODULE WITH NON-FLAT MIRROR FOR CHEMICAL MECHANICAL POLISHING SYSTEMS
A metrology module for use with a substrate processing system includes a camera for scanning a substrate and a light source configured to direct light toward the substrate at a non-zero incidence angle. The module also includes a reflector having a non-flat mirror configured to reflect light to the camera. The non-flat mirror is configured to receive light reflected from the substrate at a consistent reflected angle.
B24B 49/12 - Appareillage de mesure ou de calibrage pour la commande du mouvement d'avance de l'outil de meulage ou de la pièce à meulerAgencements de l'appareillage d'indication ou de mesure, p. ex. pour indiquer le début de l'opération de meulage impliquant des dispositifs optiques
H01L 21/304 - Traitement mécanique, p. ex. meulage, polissage, coupe
14.
POWER DELIVERY FOR AI COMPUTING WITH ORTHOGONAL EMBEDDING AND EDGE ACCESS
THE FLORIDA INTERNATIONAL UNIVERSITY BOARD OF TRUSTEES (USA)
Inventeur(s)
Khasgiwala, Mudit Sunilkumar
Kengeri, Subramani
Pulugurtha, Markondeyaraj
Pial, Mohammad Mohtasim Hamid
Al Duhni, Ghaleb Saleh Ghaleb
Abrégé
A semiconductor device with a vertically mounted IPD may include a substrate may include a cavity. The device may include a vertically mounted IPD disposed within the cavity. The vertically mounted IPD may include a capacitor including electrical contacts on a vertical edge of the capacitor. The vertically mounted IPD may include an inductor with electrical contacts on a vertical edge of the inductor. The device may include a metal layer in electrical contact on a first edge of the vertically mounted IPD, the first edge in electrical contact with at least one of the electrical contacts on the vertical edge of the capacitor or the electrical contacts on the vertical edge of the inductor. The device may include a device layer in electrical contact with the metal layer. The device may include a backside power delivery network in electrical contact with a second edge of the vertically mounted IPD.
A base ring for a substrate processing chamber includes a coating on one or more radially inward surfaces and on one or more upward-facing surfaces. A cover is disposed on the base ring. The cover experiences thermal expansion during a processing operation, and thermal contraction during a subsequent cooling period. The coating prevents contact and abrasion between the cover and the material of the base ring during the thermal expansion and contraction of the cover.
Methods for reducing the resistance of a contact leverage fine grain sizes to increase thermal expansion during hybrid bonding for increased bonding strength and fine grain growth after bonding to decrease resistance of the contact. In some embodiments, the method may comprise bonding a first contact on a first substrate to a second contact on a second substrate where a first end region of the first contact has a bonding surface and has a first average grain size that is smaller than a second average grain size of a second end region that is opposite of the first end region and where the first end region has grain boundary pinning additives in the first end region and driving the additives from the first end region to the second end region after bonding using a thermal treatment to promote grain growth within the first end region.
The present disclosure generally provides waveguide combiners for augmented reality applications and methods thereof. The waveguide combiners include a substrate. A coating layer having a refractive index of about 1.03 to 1.3 is disposed over the substrate. One or more seal structures having refractive indices of about 1.15 to 2.0 are disposed adjacent to the coating layer. An edge black material is disposed over the edges of the substrate, the coating layer, and the seal structures. The edge black material functions to absorb stray light and improve image contrast. The coating layer prevents light leakage, while the seal structures protect the coating layer from moisture and debris.
G02B 6/00 - Guides de lumièreDétails de structure de dispositions comprenant des guides de lumière et d'autres éléments optiques, p. ex. des moyens de couplage
Implementations of the present disclosure generally relate to the selective deposition of barrier layers on dielectric materials. More particularly, implementations described herein provide a method to selectively deposit a barrier layer on an Al-containing dielectric material over a metal material. In at least one implementation, a process for selectively depositing a barrier layer is provided and includes selectively depositing a first inhibitor on a substrate comprising an Al-containing dielectric material, a Si-containing dielectric material, and a metal material, where the first inhibitor is selectively deposited on the Al-containing dielectric material of the substrate, depositing a second inhibitor on the metal material of the substrate, removing the first inhibitor to expose the Al-containing dielectric material, and depositing the barrier layer on the exposed Al-containing dielectric material and the Si-containing dielectric material.
C23C 16/04 - Revêtement de parties déterminées de la surface, p. ex. au moyen de masques
C23C 16/455 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c.-à-d. procédés de dépôt chimique en phase vapeur [CVD] caractérisé par le procédé de revêtement caractérisé par le procédé utilisé pour introduire des gaz dans la chambre de réaction ou pour modifier les écoulements de gaz dans la chambre de réaction
A substrate processing chamber includes a first actuator coupled to a first shaft to raise and lower a substrate support, and a second actuator coupled to a second shaft to raise and lower a seal plate disposed below the substrate support. The processing chamber further includes a third actuator coupled to a third shaft to raise and lower a hoop plate to operate a plurality of lift pins.
There is provided a high voltage (HV) resistive conductor cable for operation under vacuum conditions, the cable including a resistive conductor core coated with an insulating material configured to prevent leakage of contaminants when operating under vacuum conditions, wherein said resistive conductor core includes glassy fibers and conductive carbon, wherein the conductive carbon is about 2-25% (w/w) of the resistive conductor core, such that the resistive conductor core is characterized by having an electric resistance of about 1-500 kΩ/m and by being configured to withstand a temperature of at least about 250 °C.
B29C 48/18 - Articles comprenant au moins deux composants, p. ex. couches coextrudées les composants étant des couches
H01B 5/10 - Pluralité de fils ou analogues toronnés en forme de corde toronnés autour d'un espace, d'un matériau isolant ou d'un matériau conducteur dissemblable
B29B 11/04 - Fabrication de préformes par assemblage de matière préformée
H01B 1/24 - Matériau conducteur dispersé dans un matériau organique non conducteur le matériau conducteur comportant des compositions à base de carbone-silicium, du carbone ou du silicium
21.
EQUAL MATCHING OF OXIDATION RATE BETWEEN SIGE AND SI THROUGH CLUSTERED PRE-CLEAN AND PRE-SURFACE NITRIDATION
Embodiments disclosed herein generally relate to methods and systems that facilitate the formation of silicon dioxide (SiO2) layers in complementary metal-oxide semiconductor (CMOS) film stack structures. In some embodiments, a method of forming a metal phosphide hardmask includes providing the substrate to a processing chamber, the substrate comprising a silicon (Si) layer and a silicon germanium (SiGe) layer, removing native oxides from the Si layer and the SiGe layer, performing thermal nitridation on the Si layer and the SiGe layer, and oxidizing the Si layer and the SiGe layer with atomic oxygen or hydroxyl (OH) radicals.
Embodiments of the present disclosure generally relate to methods and apparatus for forming thin films. More particularly, embodiments of the present disclosure generally relate to methods and apparatus of selectively depositing a gettering metal atop an exposed metal surface. Embodiments of the present disclosure include a method of forming a capping layer. The method of forming a capping layer includes selectively depositing a cobalt capping layer on an exposed metal surface formed on a substrate using a vapor deposition process and selectively depositing a gettering metal layer atop an exposed surface of the cobalt capping layer.
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
C23C 16/16 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c.-à-d. procédés de dépôt chimique en phase vapeur [CVD] caractérisé par le dépôt d'un matériau métallique à partir de métaux carbonyles
C23C 16/18 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c.-à-d. procédés de dépôt chimique en phase vapeur [CVD] caractérisé par le dépôt d'un matériau métallique à partir de composés organométalliques
C23C 16/52 - Commande ou régulation du processus de dépôt
23.
METHODS AND MECHANISMS FOR USING MACHINE LEARNING TO GENERATE DIAGNOSTIC REPORTS BASED ON ANOMALOUS DATA
A system configured to detect, by a processing device, an anomaly that occurred during a manufacturing process performed by a substrate processing system. A set of prompts is generated based on the anomaly. Each prompt is correlated to specific data obtained from one or more datastores. For each prompt, a respective output of the first trained machine learning model is obtained and a structured prompt is generated based on respective outputs. The structured prompt is provided as input to a second trained machine learning model an output of the second trained machine learning model is obtained. The output of the second trained machine learning model comprising a diagnostic report associated with the anomaly.
Techniques for measuring uniformity of layer thicknesses on semiconductor wafers are described herein. The techniques can include capturing an image of a portion of a wafer with a transmission electron microscope. The wafer includes a plurality of alternating layers of a first material and a second material. The techniques can include determining pixel intensities across the plurality of alternating layers in the image. The techniques can include fitting the pixel intensities to a model that is descriptive of a trend in the pixel intensities. The techniques can include determining a thickness for a first layer of the wafer based on the model.
G01B 15/02 - Dispositions pour la mesure caractérisées par l'utilisation d'ondes électromagnétiques ou de radiations de particules, p. ex. par l'utilisation de micro-ondes, de rayons X, de rayons gamma ou d'électrons pour mesurer l'épaisseur
H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
H01L 21/67 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants
25.
IN SITU CLEANING OF DEPOSITION CHAMBER WITH MICROWAVE PLASMA
Methods of cleaning a vapor deposition substrate processing chamber comprise injecting through a first gas injector having a front face and gas openings of the vapor deposition processing chamber a first cleaning gas mixture comprising first a fluorine-containing gas and a first inert gas at a first temperature and generating a first microwave plasma from the first cleaning gas mixture. The method includes exposing a pedestal including a substrate support surface of the vapor deposition chamber to a second cleaning gas mixture comprising a second fluorine-containing gas and a second inert gas and generating a second microwave plasma from the second cleaning gas mixture at a second temperature. The method includes heating the pedestal and the substrate support surface to a third temperature that is greater than the second temperature. The method removes AlFx cleaning residue.
C23C 16/44 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c.-à-d. procédés de dépôt chimique en phase vapeur [CVD] caractérisé par le procédé de revêtement
C23C 16/458 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c.-à-d. procédés de dépôt chimique en phase vapeur [CVD] caractérisé par le procédé de revêtement caractérisé par le procédé utilisé pour supporter les substrats dans la chambre de réaction
H01J 37/32 - Tubes à décharge en atmosphère gazeuse
26.
PRE-TREATMENT FOR SAM REMOVAL IMPROVEMENT WITH LESS CARBON RESIDUE
A method of forming a microelectronic device includes pre-treating a metal surface formed on a substrate, depositing a self-assembled monolayer (SAM) selectively on the metal surface against a dielectric surface formed on the substrate, depositing a barrier layer selectively on the dielectric surface against the SAM, and removing the SAM.
C23C 30/00 - Revêtement avec des matériaux métalliques, caractérisé uniquement par la composition du matériau métallique, c.-à-d. non caractérisé par le procédé de revêtement
27.
METHOD FOR TESTING A PACKAGING SUBSTRATE, AND APPARATUS FOR TESTING A PACKAGING SUBSTRATE
A method for testing a packaging substrate with at least one electron beam column is provided. The method includes a first test operation, wherein the first test operation includes: positioning the packaging substrate in a vacuum chamber; connecting a voltage source to one or more first contact pads of a first large network of the packaging substrate, the first large network comprising a first plurality of contact pads having a large number of contact pads, the first large network further comprising first electrical interconnect paths for interconnecting the first plurality of contact pads; applying a first electric potential to the one or more first contact pads using the voltage source; charging one or more further networks of the packaging substrate to a second electric potential different from the first electric potential, wherein the one or more further networks comprise a further plurality of contact pads; obtaining information about one or more electric potentials of a second plurality of contact pads comprising the further plurality of contact pads, wherein obtaining the information about one or more electric potentials comprises directing an electron beam of the at least one electron beam column via vector addressing onto each of the second plurality of contact pads and obtaining information about an electric potential of each of the second plurality of contact pads; and determining at least one defect of the packaging substrate based on the information about one or more electric potentials of the second plurality of contact pads.
G01R 31/52 - Test pour déceler la présence de courts-circuits, de fuites de courant ou de défauts à la terre
G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
G01R 31/305 - Test sans contact utilisant des faisceaux électroniques
G01R 31/309 - Test sans contact utilisant des rayonnements électromagnétiques non ionisants, p. ex. des rayonnements optiques de circuits imprimés ou hybrides
28.
DIE STRESS MODULATION FOR IMPROVED DEVICE LAYER STACKING
Embodiments herein are directed to localized die distortion correction. In some embodiments, a method includes performing a metrology scan of a substrate, wherein the metrology scan determines a die warp or a die bow for each die of a plurality of dies across the substrate. The method further includes directing first ions to the substrate, wherein the first ions are directed to a first die at a first dose and a first energy, and wherein the first dose and the first energy are determined based on the die warp or the die bow of the first die. The method further includes directing second ions to the substrate, wherein the second ions are directed to a second die at a second dose and a second energy, and wherein the second dose and the second energy are determined based on the die warp or the die bow of the second die.
H01L 21/265 - Bombardement par des radiations ondulatoires ou corpusculaires par des radiations d'énergie élevée produisant une implantation d'ions
H01J 37/305 - Tubes à faisceau électronique ou ionique destinés aux traitements localisés d'objets pour couler, fondre, évaporer ou décaper
H01J 37/317 - Tubes à faisceau électronique ou ionique destinés aux traitements localisés d'objets pour modifier les propriétés des objets ou pour leur appliquer des revêtements en couche mince, p. ex. implantation d'ions
H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
Provided are memory devices and methods of manufacture that include an etch stop layer on the bottom of the memory stack. The etch stop layer on the bottom of the memory stack is advantageous for backside wafer thinning in hybrid bonded memory devices.
H10D 62/832 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe IV, p. ex. Si dopé B ou Ge non dopé étant des matériaux du groupe IV comprenant deux éléments ou plus, p. ex. SiGe
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
30.
METAL HALIDE PRE-SOAK AND PLASMA TREATMENT PROCESS SEQUENCE
Embodiments of the disclosure include a method of forming an interconnect structure that is coupled to a metal gate of a field effect transistor (FET). The method includes exposing a device structure to a metal halide pre-soak, wherein the device structure comprises at least one feature formed in a first dielectric layer, wherein the at least one feature exposes a surface of a second dielectric layer surrounding a metal gate. The method further includes exposing the device structure to a plasma treatment, and at least partially filling the at least one feature with a metal fill material.
A processing system is provided that includes a process chamber and a gas supply system. The process chamber includes: a chamber body disposed around an interior volume; a substrate support positioned in the interior volume; a plurality of gas injectors configured to direct gas into a first region of the interior volume; and an exhaust channel configured to exhaust gas from a second region of the interior volume. The gas supply system includes a main gas line coupled with a plurality of gas sources that include a first gas source; a plurality of gas lines, each gas line of the plurality of gas lines coupled between the main gas line and one of the gas injectors; and one or more auxiliary gas lines including a first auxiliary gas line coupled between the first gas source and a first gas line of the plurality of gas lines.
H01J 37/32 - Tubes à décharge en atmosphère gazeuse
H01L 21/67 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants
32.
AIR-GAP ENCAPSULATION OF NANOSTRUCTURED OPTICAL DEVICES
Embodiments described herein relate to encapsulated optical devices and methods of forming optical devices with controllable air-gapped encapsulation. In one embodiment, a plurality of openings are formed in a support layer surrounding the plurality of optical device structures to create a high refractive index contrast between the optical device structures, the support layer, and the openings. In another embodiment, sacrificial material is disposed in-between the optical device structures and then an encapsulation layer is disposed on the optical device structures. The sacrificial material is removed, forming a space bounded by the encapsulation layer, the substrate, and each of the optical device structures. In yet another embodiment, the encapsulation layer is disposed over the optical device structures forming a space bounded by the encapsulation layer, the substrate, and each of the optical device structures.
Embodiments of the present disclosure generally relate to methods for seam- free filling of features. In one or more embodiments, a method of filling gaps includes exposing a plurality of features on a substrate to a deposition-etch process to fill openings within the plurality of features with a material, such as titanium nitride. Each cycle of the deposition-etch process includes depositing the material onto surfaces of the plurality of features during a vapor deposition process, wherein the material is conformally lined on the surfaces of the plurality of features during the vapor deposition process and ceasing the vapor deposition process, exposing the material to an etchant containing a metal chloride during an etch process, wherein the material is non- conformally removed from the surfaces of the plurality of features during the etch process and ceasing the etch process, and sequentially repeating the cycle of the deposition-etch process.
A gripping member for use on a rotating substrate support in a substrate processing system is provided. The gripping member includes an annular body including an outer radial surface and an inner radial surface and a groove disposed in the outer radial surface. The groove including a first sidewall, a second sidewall, and a base surface. A downward force on a portion of the groove causes the annular body to deform such that the first sidewall and the second sidewall are moved inward towards a center of the groove.
H01L 21/67 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants
H01L 21/687 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension en utilisant des moyens mécaniques, p. ex. mandrins, pièces de serrage, pinces
35.
CLEANING UNIT IN CHEMICAL MECHANICAL POLISHING SYSTEM
A brush cleaning system for cleaning a substrate includes a tank and a cylindrical roller disposed in the tank for cleaning the substrate. The cleaning system also includes a substrate holder for retaining the substrate in a vertical orientation and rotating the substrate. A movable substrate support is used to support the substrate in the tank.
H01L 21/67 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants
H01L 21/683 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
Embodiments of the present disclosure generally relate to methods of detecting errors during a substrate processing operation, and related apparatuses and components. In one or more embodiments, a non-transitory computer readable medium stores instructions that when executed by one or more processors of a system, cause the system to determine a presence of one or more errors of one or more components disposed within an internal volume of a processing chamber based on a video signal. The one or more errors include a displaced substrate, a dripping nozzle mechanism, a fluid present on a rotor cover, or a fluid present on a substrate.
Embodiments of the present disclosure generally relate to planarization of surfaces on substrates. More specifically, embodiments of the present disclosure relate to methods and systems for polishing a substrate. In one or more embodiments, the method includes polishing a device side of the substrate in the presence of a first polishing fluid, the first polishing fluid comprising a first ratio of recycled slurry to new slurry; and polishing the device side of the substrate in the presence of a second polishing fluid, the second polishing fluid comprising a second ratio of recycled slurry to new slurry that is smaller than the first ratio of recycled slurry to new slurry.
B24B 37/005 - Moyens de commande pour machines ou dispositifs de rodage
B24B 55/12 - Dispositifs d'évacuation du nuage d'huile ou de l'agent de refroidissementDispositifs pour collecter ou récupérer des matériaux issus du meulage ou du polissage, p. ex. métaux précieux, pierres précieuses, diamants ou similaires
B24B 57/02 - Dispositifs pour l'alimentation, l'application, le triage ou la récupération de produits de meulage, polissage ou rodage pour l'alimentation en produits de meulage, polissage ou rodage à l'état fluide, vaporisés, pulvérisés ou liquéfiés
An ion implanter is disclosed. The ion implanter generates a vertically oriented ion beam that is used to impact a workpiece. The vertically oriented ion beam may be a spot beam that is directed toward the workpiece. The workpiece is mounted on a hollow workpiece holder. The hollow workpiece holder is attached to a workpiece motion system, which is capable of moving the hollow workpiece holder in at least two directions such that the entirety of the workpiece may be impacted by the stationary spot ion beam. In some embodiments, the workpiece motion system may support a plurality of workpieces.
H01J 37/317 - Tubes à faisceau électronique ou ionique destinés aux traitements localisés d'objets pour modifier les propriétés des objets ou pour leur appliquer des revêtements en couche mince, p. ex. implantation d'ions
The present disclosure relates to liners for defect reduction and source/drain formation, and related methods, apparatus, and processing chambers. In one or more embodiments, a method of substrate processing includes forming an amorphous liner on a structure on a substrate. The amorphous liner includes silicon, and the forming includes a formation temperature. The method includes annealing the amorphous liner to crystallize the amorphous liner into a crystalline liner. The annealing includes ramping the formation temperature to an anneal temperature at a ramp rate, the ramp rate less than 5.0 degrees Celsius-per-second. The method includes removing liner material from a plurality of cap layers of the structure, and forming source and drain material on the crystalline liner.
H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
A system includes a chamber having a substrate support and an upper member having an upper member surface positioned within the chamber that is vertically movable relative to the substrate support. One or more sensors each measure an edge location of a substrate on the substrate support. A linear stage assembly is coupled to the upper member and first and second motors operatively are coupled to a first side of a first linear stage and a second side of a second linear stage of a set of linear stages to move the linear stage assembly in a first direction and in a second direction. Control logic receives the edge location, determines an offset value of the substrate relative to the edge location, and controls at least one of the first or second motor using the offset value to center the upper member surface over the substrate.
Methods and systems for predicting substrate process emissions chemistry are provided. A process recipe for a process to be performed using one or more manufacturing equipment is provided as an input to an artificial intelligence (AI) model. The AI model is trained to predict emissions characterization data for a respective process based on a given process recipe. Output(s) of the AI model is obtained, where the output(s) indicate emissions characterization data associated with the process. A determination is made of whether the emissions characterization data associated with the process satisfies one or more emission criteria. Upon a determination that the emissions characterization data associated with the process satisfies the one or more emission criteria, one or more operations of the process are performed using the one or more manufacturing equipment in accordance with the process recipe.
22) layers in complementary metal-oxide semiconductor (CMOS) film stack structures. In some embodiments, a method of forming a metal phosphide hardmask includes providing the substrate to a processing chamber, the substrate comprising a silicon (Si) layer and a silicon germanium (SiGe) layer, removing native oxides from the Si layer and the SiGe layer, performing thermal nitridation on the Si layer and the SiGe layer, and oxidizing the Si layer and the SiGe layer with atomic oxygen or hydroxyl (OH) radicals.
THE FLORIDA INTERNATIONAL UNIVERSITY BOARD OF TRUSTEES (USA)
Inventeur(s)
Khasgiwala, Mudit Sunilkumar
Khosravi, Arvin
Kengeri, Subramani
Pulugurtha, Markondeyaraj
Pial, Mohammad Mohtasim Hamid
Abrégé
A toroidal inductor may include a substrate. The toroidal inductor may also include a magnetic film deposited on the substrate during a manufacturing process, wherein the substrate is exposed to one or more magnetic fields creating local and/or spatially-variant anisotropy. The toroidal inductor may also include one or more metal windings deposited on the substrate corresponding to the spatially-variant anisotropy.
H01F 17/06 - Inductances fixes du type pour signaux avec noyau magnétique avec noyau refermé sur lui-même, p. ex. tore
H01F 41/04 - Appareils ou procédés spécialement adaptés à la fabrication ou à l'assemblage des aimants, des inductances ou des transformateursAppareils ou procédés spécialement adaptés à la fabrication des matériaux caractérisés par leurs propriétés magnétiques pour la fabrication de noyaux, bobines ou aimants pour la fabrication de bobines
H01F 1/057 - Alliages caractérisés par leur composition contenant des métaux des terres rares et des métaux de transition magnétiques, p. ex. SmCo5 et des éléments IIIa, p. ex. Nd2Fe14B
H01F 1/147 - Alliages caractérisés par leur composition
44.
Method of Processing Substrates and Semiconductor Assemblies Having Wide Bandgap Materials
Methods for processing a semiconductor substrate are disclosed herein which include bonding to a silicon layer to a wide bandgap semiconductor layer through a dielectric layer, wherein the dielectric layer is bonded to at least one of the silicon layer or the wide bandgap semiconductor layer by a wafer-to-wafer or a die-to-wafer bonding process. Semiconductor assemblies are also disclosed herein.
The Florida International University Board of Trustees (USA)
Inventeur(s)
Khasgiwala, Mudit Sunilkumar
Kengeri, Subramani
Pulugurtha, Markondeyaraj
Pial, Mohammad Mohtasim Hamid
Al Duhni, Ghaleb Saleh Ghaleb
Abrégé
A semiconductor device with a vertically mounted IPD may include a substrate may include a cavity. The device may include a vertically mounted IPD disposed within the cavity. The vertically mounted IPD may include a capacitor including electrical contacts on a vertical edge of the capacitor. The vertically mounted IPD may include an inductor with electrical contacts on a vertical edge of the inductor. The device may include a metal layer in electrical contact on a first edge of the vertically mounted IPD, the first edge in electrical contact with at least one of the electrical contacts on the vertical edge of the capacitor or the electrical contacts on the vertical edge of the inductor. The device may include a device layer in electrical contact with the metal layer. The device may include a backside power delivery network in electrical contact with a second edge of the vertically mounted IPD.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
Methods for reducing the resistance of a contact leverage fine grain sizes to increase thermal expansion during hybrid bonding for increased bonding strength and fine grain growth after bonding to decrease resistance of the contact. In some embodiments, the method may comprise bonding a first contact on a first substrate to a second contact on a second substrate where a first end region of the first contact has a bonding surface and has a first average grain size that is smaller than a second average grain size of a second end region that is opposite of the first end region and where the first end region has grain boundary pinning additives in the first end region and driving the additives from the first end region to the second end region after bonding using a thermal treatment to promote grain growth within the first end region.
An ion implanter is disclosed. The ion implanter generates a vertically oriented ion beam that is used to impact a workpiece. The vertically oriented ion beam may be a spot beam that is directed toward the workpiece. The workpiece is mounted on a hollow workpiece holder. The hollow workpiece holder is attached to a workpiece motion system, which is capable of moving the hollow workpiece holder in at least two directions such that the entirety of the workpiece may be impacted by the stationary spot ion beam. In some embodiments, the workpiece motion system may support a plurality of workpieces.
H01J 37/317 - Tubes à faisceau électronique ou ionique destinés aux traitements localisés d'objets pour modifier les propriétés des objets ou pour leur appliquer des revêtements en couche mince, p. ex. implantation d'ions
48.
DIVERSION GAS SUPPLY ASSEMBLIES, AND RELATED PROCESSING SYSTEMS, PROCESSING CHAMBERS, AND METHODS
Embodiments of the present disclosure generally relate to semiconductor processing equipment. In one or more embodiments, a processing system includes a plasma source assembly, an exhaust line operable to exhaust materials, a flow adapter, and a gas supply assembly fluidly connected to the flow adapter. The gas supply assembly includes a first gas source operable to flow a first composition, a first supply valve fluidly between the flow adapter and the first gas source, and a first diverter valve between the exhaust line and an upstream side of the first supply valve. The gas supply assembly includes a second gas source operable to flow a second composition, a second supply valve fluidly between the flow adapter and the second gas source, and a second diverter valve between the exhaust line and an upstream side of the second supply valve.
Semiconductor fabrication component preparation methods are described. In embodiments, the methods include forming a first layer on a surface of the semiconductor fabrication component. The first layer is characterized by a porosity of greater than or about 0.01 vol.%. The methods further include depositing a second layer on the first layer, where the second layer is characterized by a porosity of less than or about 20 vol.%. Treated semiconductor fabrication components are also described. In embodiments, the treated components include a first layer formed on the surface of the semiconductor fabrication component, where the first layer is characterized by a porosity of greater than or about 0.01 vol.%., and a second layer positioned on the first layer, where the second layer is characterized by a porosity of less than or about 20 vol.%.
H01J 37/32 - Tubes à décharge en atmosphère gazeuse
C23C 16/455 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c.-à-d. procédés de dépôt chimique en phase vapeur [CVD] caractérisé par le procédé de revêtement caractérisé par le procédé utilisé pour introduire des gaz dans la chambre de réaction ou pour modifier les écoulements de gaz dans la chambre de réaction
C23C 28/04 - Revêtements uniquement de matériaux inorganiques non métalliques
C25D 11/18 - Post-traitement, p. ex. bouchage des pores
50.
Substrate Processing Chamber with Plasma Confinement
A plasma confinement screen system for a process chamber includes an inner plasma screen having an inner annular body with a central opening, the annular body including a plurality of first openings; and an outer plasma screen having an outer annular body with a central opening surrounding the inner plasma screen, the outer annular body including a plurality of second openings, wherein the outer plasma screen is configured for vertical movement relative to the inner plasma screen.
There is provided a high voltage (HV) resistive conductor cable for operation under vacuum conditions, the cable including a resistive conductor core coated with an insulating material configured to prevent leakage of contaminants when operating under vacuum conditions, wherein said resistive conductor core includes glassy fibers and conductive carbon, wherein the conductive carbon is about 2-25 % (w/w) of the resistive conductor core, such that the resistive conductor core is characterized by having an electric resistance of about 1-500 kΩ/m and by being configured to withstand a temperature of at least about 250° C.
H01B 1/18 - Matériau conducteur dispersé dans un matériau inorganique non conducteur le matériau conducteur comportant des compositions à base de carbone-silicium, du carbone ou du silicium
H01B 3/44 - Isolateurs ou corps isolants caractérisés par le matériau isolantEmploi de matériaux spécifiés pour leurs propriétés isolantes ou diélectriques composés principalement de substances organiques matières plastiquesIsolateurs ou corps isolants caractérisés par le matériau isolantEmploi de matériaux spécifiés pour leurs propriétés isolantes ou diélectriques composés principalement de substances organiques résinesIsolateurs ou corps isolants caractérisés par le matériau isolantEmploi de matériaux spécifiés pour leurs propriétés isolantes ou diélectriques composés principalement de substances organiques cires résines vinyliquesIsolateurs ou corps isolants caractérisés par le matériau isolantEmploi de matériaux spécifiés pour leurs propriétés isolantes ou diélectriques composés principalement de substances organiques matières plastiquesIsolateurs ou corps isolants caractérisés par le matériau isolantEmploi de matériaux spécifiés pour leurs propriétés isolantes ou diélectriques composés principalement de substances organiques résinesIsolateurs ou corps isolants caractérisés par le matériau isolantEmploi de matériaux spécifiés pour leurs propriétés isolantes ou diélectriques composés principalement de substances organiques cires résines acryliques
H01B 7/04 - Câbles, conducteurs ou cordons flexibles, p. ex. câbles traînants
H01J 37/28 - Microscopes électroniques ou ioniquesTubes à diffraction d'électrons ou d'ions avec faisceaux de balayage
52.
HIGH DENSITY DIE TO DIE INTERCONNECT SHIFT CORRECTION FOR OVERLAY ALIGNMENT
A method of forming a DTD interconnect includes measuring a shift in a multi-die interconnect bridge of a partial DTD interconnect. A plurality of via channels and bridge via channels are formed in the build-up layers. A plurality of vias and a plurality of bridge vias are formed in the via channels and the bridge via channels. Interconnect layers are disposed over the plurality of vias and an elongated bridge interconnect is disposed over the plurality of bridge via channels. A plurality of package micro-bump pads and a plurality of bridge micro-bump pads are disposed over the plurality of vias and the bridge vias, respectively. The plurality of vias are aligned with the package micro-bump pads and the plurality of bridge vias are aligned with the plurality of bridge micro-bump pads. One or more dies are bonded to the DTD interconnect.
An end effector that includes replaceable pads is disclosed. The pads may be constructed from a different dielectric material than the end effector. This difference in dielectric material may help reduce particle generation and workpiece damage. Additionally, the pad is attached to the end effector using a latch and a spring, which allows the assembly to remain operational over a wide range of temperatures, even if the end effector and pad have coefficients of thermal expansion that differ by an order of magnitude or more. This assembly may operate to temperatures from -150°C up to 500°C.
The present disclosure relates to plate and absorptive mass arrangements for localized thermal adjustability, and related methods and processing chambers. In one or more embodiments, a processing chamber includes a chamber body at least partially defining an internal volume, a substrate support disposed in the internal volume, a plate apparatus disposed in the internal volume and at least partially defining a processing volume between the plate apparatus and the substrate support. The plate apparatus includes one or more flow openings formed in one or more plate walls. The processing chamber includes one or more absorptive masses disposed in the one or more flow openings.
Embodiments of the present disclosure generally relate to apparatus and methods utilized in the manufacture of semiconductor devices. More particularly, embodiments of the present disclosure relate to a substrate processing chamber, and components thereof, for forming semiconductor devices.
Methods of depositing ruthenium-containing films are described. Methods of manufacturing interconnect structures as part of a microelectronic device fabrication process are also described. The methods include forming a dielectric layer including at least one feature defining a gap having sidewalls and a bottom on a substrate. The method may further include forming a blocking layer on the bottom by exposing the substrate to a blocking compound; selectively depositing a ruthenium-containing film on the sidewalls; removing the blocking layer; and performing a gap fill process to fill the gap with a gap fill material.
C23C 16/18 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c.-à-d. procédés de dépôt chimique en phase vapeur [CVD] caractérisé par le dépôt d'un matériau métallique à partir de composés organométalliques
C07F 15/00 - Composés contenant des éléments des groupes 8, 9, 10 ou 18 du tableau périodique
C23C 16/04 - Revêtement de parties déterminées de la surface, p. ex. au moyen de masques
C23C 16/455 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c.-à-d. procédés de dépôt chimique en phase vapeur [CVD] caractérisé par le procédé de revêtement caractérisé par le procédé utilisé pour introduire des gaz dans la chambre de réaction ou pour modifier les écoulements de gaz dans la chambre de réaction
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
57.
MAGNETIC THIN FILM PROCESS CHAMBER DESIGN FOR HIGH-DENSITY POWER CONVERTERS
The Florida International University Board of Trustees (USA)
Inventeur(s)
Khasgiwala, Mudit Sunilkumar
Khosravi, Arvin
Kengeri, Subramani
Pulugurtha, Markondeyaraj
Pial, Mohammad Mohtasim Hamid
Abrégé
A toroidal inductor may include a substrate. The toroidal inductor may also include a magnetic film deposited on the substrate during a manufacturing process, wherein the substrate is exposed to one or more magnetic fields creating local and/or spatially-variant anisotropy. The toroidal inductor may also include one or more metal windings deposited on the substrate corresponding to the spatially-variant anisotropy.
H01F 41/02 - Appareils ou procédés spécialement adaptés à la fabrication ou à l'assemblage des aimants, des inductances ou des transformateursAppareils ou procédés spécialement adaptés à la fabrication des matériaux caractérisés par leurs propriétés magnétiques pour la fabrication de noyaux, bobines ou aimants
H01F 41/14 - Appareils ou procédés spécialement adaptés à la fabrication ou à l'assemblage des aimants, des inductances ou des transformateursAppareils ou procédés spécialement adaptés à la fabrication des matériaux caractérisés par leurs propriétés magnétiques pour appliquer des pellicules magnétiques sur des substrats
58.
METHODS AND SYSTEMS FOR PREDICTING SUBSTRATE PROCESS EMISSIONS CHEMISTRY
Methods and systems for predicting substrate process emissions chemistry are provided. A process recipe for a process to be performed using one or more manufacturing equipment is provided as an input to an artificial intelligence (AI) model. The AI model is trained to predict emissions characterization data for a respective process based on a given process recipe. Output(s) of the AI model is obtained, where the output(s) indicate emissions characterization data associated with the process. A determination is made of whether the emissions characterization data associated with the process satisfies one or more emission criteria. Upon a determination that the emissions characterization data associated with the process satisfies the one or more emission criteria, one or more operations of the process are performed using the one or more manufacturing equipment in accordance with the process recipe.
H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
H01L 21/67 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants
59.
ERROR DETECTION METHOD FOR SUBSTRATE PROCESSING AND RELATED APPARATUSES
Embodiments of the present disclosure generally relate to methods of detecting errors during a substrate processing operation, and related apparatuses and components. In one or more embodiments, a non-transitory computer readable medium stores instructions that when executed by one or more processors of a system, cause the system to determine a presence of one or more errors of one or more components disposed within an internal volume of a processing chamber based on a video signal. The one or more errors include a displaced substrate, a dripping nozzle mechanism, a fluid present on a rotor cover, or a fluid present on a substrate.
H01L 21/67 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants
G05B 19/418 - Commande totale d'usine, c.-à-d. commande centralisée de plusieurs machines, p. ex. commande numérique directe ou distribuée [DNC], systèmes d'ateliers flexibles [FMS], systèmes de fabrication intégrés [IMS], productique [CIM]
Embodiments of the present disclosure generally relate to planarization of surfaces on substrates. More specifically, embodiments of the present disclosure relate to methods and systems for polishing a substrate. In one or more embodiments, the method includes polishing a device side of the substrate in the presence of a first polishing fluid, the first polishing fluid comprising a first ratio of recycled slurry to new slurry; and polishing the device side of the substrate in the presence of a second polishing fluid, the second polishing fluid comprising a second ratio of recycled slurry to new slurry that is smaller than the first ratio of recycled slurry to new slurry.
B24B 57/02 - Dispositifs pour l'alimentation, l'application, le triage ou la récupération de produits de meulage, polissage ou rodage pour l'alimentation en produits de meulage, polissage ou rodage à l'état fluide, vaporisés, pulvérisés ou liquéfiés
B24B 37/04 - Machines ou dispositifs de rodageAccessoires conçus pour travailler les surfaces planes
H01L 21/306 - Traitement chimique ou électrique, p. ex. gravure électrolytique
61.
PRECISE CONTROL OF ETCH TOPOGRAPHY AND PATTERN TRANSFER
Exemplary semiconductor processing methods may include providing one or more etchant precursors to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region. Alternating pairs of a silicon-and-oxygen-containing material and a silicon-and-nitrogen-containing material may be disposed on the substrate. A feature may extend at least partially through the alternating layers. The methods may include forming plasma effluents. The methods may include contacting the substrate with the plasma effluents. The contacting may etch the silicon-and-oxygen-containing material and/or the silicon-and-nitrogen-containing material. The methods may include applying a bias power while contacting the substrate with the plasma effluents. The bias power may be applied at a first duty cycle to selectively etch the silicon-and-oxygen-containing material. The bias power may be applied at a second duty cycle less than the first duty cycle to selectively etch the silicon-and-nitrogen-containing material.
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
C09K 13/08 - Compositions pour l'attaque chimique, la gravure, le brillantage de surface ou le décapage contenant un acide inorganique contenant un composé du fluor
H01J 37/32 - Tubes à décharge en atmosphère gazeuse
H01L 21/67 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants
62.
HALIDE-FREE CO-REACTANTS FOR RUTHENIUM FILM DEPOSITION
Methods of depositing ruthenium-containing films are described. Methods of manufacturing interconnect structures as part of a microelectronic device fabrication process are also described. The methods include forming a dielectric layer including at least one feature defining a gap having sidewalls and a bottom on a substrate. The method may further include forming a blocking layer on the bottom by exposing the substrate to a blocking compound; selectively depositing a ruthenium-containing film on the sidewalls; removing the blocking layer; and performing a gap fill process to fill the gap with a gap fill material.
C23C 16/18 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c.-à-d. procédés de dépôt chimique en phase vapeur [CVD] caractérisé par le dépôt d'un matériau métallique à partir de composés organométalliques
C23C 16/455 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c.-à-d. procédés de dépôt chimique en phase vapeur [CVD] caractérisé par le procédé de revêtement caractérisé par le procédé utilisé pour introduire des gaz dans la chambre de réaction ou pour modifier les écoulements de gaz dans la chambre de réaction
C23C 16/04 - Revêtement de parties déterminées de la surface, p. ex. au moyen de masques
63.
METHOD OF PROCESSING SUBSTRATES AND SEMICONDUCTOR ASSEMBLIES HAVING WIDE BANDGAP MATERIALS
Methods for processing a semiconductor substrate are disclosed herein which include bonding to a silicon layer to a wide bandgap semiconductor layer through a dielectric layer, wherein the dielectric layer is bonded to at least one of the silicon layer or the wide bandgap semiconductor layer by a wafer-to-wafer or a die-to-wafer bonding process. Semiconductor assemblies are also disclosed herein.
H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
H10D 64/62 - Électrodes couplées de manière ohmique à un semi-conducteur
H10D 30/60 - Transistors à effet de champ à grille isolée [IGFET]
A method of forming a contact to a source/drain (S/D) region of a semiconductor structure includes forming a sidewall nitride layer on inner surfaces of an S/D recess that is aligned with the S/D region, depositing a bottom layer on a bottom surface of the S/D recess, forming a protection layer on shoulder portions of the S/D recess, removing the bottom layer, and forming the contact to the S/D region within the S/D recess.
H10D 84/03 - Fabrication ou traitement caractérisés par l'utilisation de technologies basées sur les matériaux utilisant une technologie du groupe IV, p. ex. technologie au silicium ou au carbure de silicium [SiC]
H10D 64/23 - Électrodes transportant le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. sources, drains, anodes ou cathodes
H10D 64/00 - Électrodes de dispositifs ayant des barrières de potentiel
Embodiments of the present disclosure generally relate to semiconductor processing equipment. In one or more embodiments, a processing system includes a plasma source assembly, an exhaust line operable to exhaust materials, a flow adapter, and a gas supply assembly fluidly connected to the flow adapter. The gas supply assembly includes a first gas source operable to flow a first composition, a first supply valve fluidly between the flow adapter and the first gas source, and a first diverter valve between the exhaust line and an upstream side of the first supply valve. The gas supply assembly includes a second gas source operable to flow a second composition, a second supply valve fluidly between the flow adapter and the second gas source, and a second diverter valve between the exhaust line and an upstream side of the second supply valve.
C23C 16/455 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c.-à-d. procédés de dépôt chimique en phase vapeur [CVD] caractérisé par le procédé de revêtement caractérisé par le procédé utilisé pour introduire des gaz dans la chambre de réaction ou pour modifier les écoulements de gaz dans la chambre de réaction
C23C 16/44 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c.-à-d. procédés de dépôt chimique en phase vapeur [CVD] caractérisé par le procédé de revêtement
C23C 16/52 - Commande ou régulation du processus de dépôt
66.
LOW HYDROGEN AND UNIFORM SILICON NITRIDE FILM FOR WAVEGUIDES
4222) precursor at a third flow rate. A radio frequency (RF) power is applied to the first gas mixture at a first frequency and first power to deposit a silicon-nitride film on a surface of the substrate. The silicon-nitride film has a hydrogen content between about 3% and about 10% and a refractive index (Rl) uniformity between about 0.1% and about 0.7% across the surface of the substrate.
C23C 16/505 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c.-à-d. procédés de dépôt chimique en phase vapeur [CVD] caractérisé par le procédé de revêtement au moyen de décharges électriques utilisant des décharges à radiofréquence
C23C 16/455 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c.-à-d. procédés de dépôt chimique en phase vapeur [CVD] caractérisé par le procédé de revêtement caractérisé par le procédé utilisé pour introduire des gaz dans la chambre de réaction ou pour modifier les écoulements de gaz dans la chambre de réaction
C23C 16/52 - Commande ou régulation du processus de dépôt
A method includes receiving a first group of parameters corresponding to a substrate manufacturing process, generating, using a statistical model, a first health index of a flow controller, receiving a second group of parameters corresponding to a flow controller used during the substrate manufacturing process, generating, using a physical model, a second health index of the flow controller, and based on at least one of the first and second health indices, perform a corrective action with respect to the flow controller.
C23C 16/52 - Commande ou régulation du processus de dépôt
C23C 16/455 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c.-à-d. procédés de dépôt chimique en phase vapeur [CVD] caractérisé par le procédé de revêtement caractérisé par le procédé utilisé pour introduire des gaz dans la chambre de réaction ou pour modifier les écoulements de gaz dans la chambre de réaction
Examples described herein generally related to a process kit for a semiconductor processing chamber. In one example, the process kit includes an edge ring having an inner diameter, a bottom surface and a top surface. The edge ring is configured to circumscribe a substrate in a semiconductor processing chamber. The process kit includes a insert ring positioned beneath the edge ring. The insert ring has an upper surface configured to contact the bottom surface of the edge ring. The insert ring has a body having a lower surface, an electrode disposed in the body, and a pin extending into the body through the lower surface coupled to the electrode. A conductive pin of the pin protrudes from the lower surface and is configured to couple to a power supply for the electrode.
H01L 21/683 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension
H01J 37/32 - Tubes à décharge en atmosphère gazeuse
69.
ORGANIC DEFECT SOURCE IDENTIFICATION USING ARTIFICIAL INTELLIGENCE
Methods and systems for organic defect source identification using artificial intelligence (AI) are provided. One or more images depicting a surface of a substrate processed using one or more manufacturing equipment is provided as input to an artificial intelligence (AI) model. Output(s) of the AI model is obtained, where the output(s) indicate defect characterization data associated with a defect detected on the surface of the substrate depicted by the one or more images. A determination is made of whether a level of confidence of at least one defect type and associated defect source from the defect characterization data satisfies one or more confidence criteria. Upon a determination that at least one defect type and associated defect source satisfy the one or more confidence criteria, the at least one defect type and associated defect source are provided to a client device for presentation to one or more users.
A method of forming a DTD interconnect includes measuring a shift in a multi-die interconnect bridge of a partial DTD interconnect. A plurality of via channels and bridge via channels are formed in the build-up layers. A plurality of vias and a plurality of bridge vias are formed in the via channels and the bridge via channels. Interconnect layers are disposed over the plurality of vias and an elongated bridge interconnect is disposed over the plurality of bridge via channels. A plurality of package micro-bump pads and a plurality of bridge micro-bump pads are disposed over the plurality of vias and the bridge vias, respectively. The plurality of vias are aligned with the package micro-bump pads and the plurality of bridge vias are aligned with the plurality of bridge micro-bump pads. One or more dies are bonded to the DTD interconnect.
H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
71.
PLATE AND ABSORPTIVE MASS ARRANGEMENTS FOR LOCALIZED THERMAL ADJUSTABILITY, AND RELATED METHODS AND PROCESSING CHAMBERS
The present disclosure relates to plate and absorptive mass arrangements for localized thermal adjustability, and related methods and processing chambers. In one or more embodiments, a processing chamber includes a chamber body at least partially defining an internal volume, a substrate support disposed in the internal volume, a plate apparatus disposed in the internal volume and at least partially defining a processing volume between the plate apparatus and the substrate support. The plate apparatus includes one or more flow openings formed in one or more plate walls. The processing chamber includes one or more absorptive masses disposed in the one or more flow openings.
A method includes receiving a first group of parameters corresponding to a substrate manufacturing process, generating, using a statistical model, a first health index of a flow controller, receiving a second group of parameters corresponding to a flow controller used during the substrate manufacturing process, generating, using a physical model, a second health index of the flow controller, and based on at least one of the first and second health indices, perform a corrective action with respect to the flow controller.
An aligner station includes an aligner stage configured to support a carrier for a process kit ring. The aligner station further includes a lift mechanism configured to lift the process kit ring from the carrier. The aligner station, using the aligner stage and the lift mechanism, is configured to independently align the process kit ring and the carrier to a target orientation.
This disclosed subject matter includes a computer-implemented method and computer system for enhancing and/or optimizing metrology recipes for Edge Placement Error (EPE) measurements, including roughness, Critical Dimensions (CD), and Critical Dimension Uniformity (CDU). The approach uses skewed CAD versions and a CAD-to-SEM ML model to generate synthetic SEM images for recipe validation. An iterative process refines recipes by adjusting recipe parameters based on discrepancies between measured values and true values.
G06F 30/12 - CAO géométrique caractérisée par des moyens d’entrée spécialement adaptés à la CAO, p. ex. interfaces utilisateur graphiques [UIG] spécialement adaptées à la CAO
75.
METHOD OF TRANSPORTING A SUBSTRATE, CARRIER ASSEMBLY FOR CARRYING A SUBSTRATE, SHIELD CARRIER, AND DEPOSITION SYSTEM
A carrier assembly comprises a shield carrier detachably connectable to a substrate support component to provide a combined carrier. The substrate support component comprises a chucking device for holding the substrate at a substrate holding surface. The shield carrier comprises: an edge exclusion shield configured to cover an edge region of the substrate support component and of the substrate held at the substrate holding surface, when the substrate support component and the shield carrier are connected; and a shield carrier transport unit configured to interact with a first carrier transport system for transporting the shield carrier along a first carrier transport path in the deposition system. At least one of the substrate support component and the shield carrier comprises at least one connector configured to attach the shield carrier and the substrate support component to each other to provide the combined carrier.
INTEGRATED SEMICONDUCTOR DEVICE MODULE, METHOD OF OPERATING AN APPARATUS FOR TESTING OF AN INTEGRATED SEMICONDUCTOR DEVICE MODULE, AND APPARATUS FOR TESTING INTEGRATED SEMICONDUCTOR DEVICE MODULE
A 3D integrated semiconductor device module, particularly a high-bandwidth memory module, is described. The 3D integrated semiconductor device module includes a semiconductor body having a first surface opposite a second surface; a plurality of device connections; one or more data buses coupled to the plurality of device connections; a plurality of logic elements coupled to the one or more data buses; a plurality of ground connections; a ground network coupled directly or indirectly to the plurality of ground connections; a plurality of test connections, the plurality of test connections disconnected from the one or more data buses, and disconnected from the ground network, the plurality of test connections configured for voltage signal testing of the 3D integrated semiconductor device module; and a plurality of test interconnect paths, each coupled to one or more of the plurality of test connections.
H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
G01R 31/307 - Test sans contact utilisant des faisceaux électroniques de circuits intégrés
G01R 31/303 - Test sans contact de circuits intégrés
H01J 37/28 - Microscopes électroniques ou ioniquesTubes à diffraction d'électrons ou d'ions avec faisceaux de balayage
77.
METHODS TO IMPROVE ALUMINUM METALLIZATION OF SUBSTRATES
Embodiments of methods of performing an Al metallization process on a substrate are provided herein. In some embodiments, a method of performing an Al metallization on a substrate includes: depositing a diffusion stopping layer on the substrate; depositing an interfacial layer comprising a nitrogen-enriched titanium layer, or a titanium alloy, or a nitrogen-enriched titanium alloy on the diffusion stopping layer; and depositing a bulk aluminum layer on the interfacial layer to metallize the substrate.
Examples described herein generally related to a process kit for a semiconductor processing chamber. In one example, the process kit includes an edge ring having an inner diameter, a bottom surface and a top surface. The edge ring is configured to circumscribe a substrate in a semiconductor processing chamber. The process kit includes a insert ring positioned beneath the edge ring. The insert ring has an upper surface configured to contact the bottom surface of the edge ring. The insert ring has a body having a lower surface, an electrode disposed in the body, and a pin extending into the body through the lower surface coupled to the electrode. A conductive pin of the pin protrudes from the lower surface and is configured to couple to a power supply for the electrode.
A method for stress management in a substrate. The method may include providing a stress compensation layer on a main surface of the substrate and performing a high-temperature implant procedure in an ion implanter to implant a dose of ions into the stress compensation layer. The high temperature implant procedure may include heating the substrate to an implant temperature, the implant temperature being between 300 ºC and 750 ºC, and exposing the substrate to an ion beam while the substrate is held at the implant temperature, wherein the implant procedure alters an out-of-plane distortion of the substrate.
H01J 37/317 - Tubes à faisceau électronique ou ionique destinés aux traitements localisés d'objets pour modifier les propriétés des objets ou pour leur appliquer des revêtements en couche mince, p. ex. implantation d'ions
80.
CAVITY CONTACT FORMATION USING PLASMA DOPING PROCESS
Approaches herein relate to devices and methods for forming cavity contacts using a plasma doping process. One method may include forming a plurality of alternating first layers and second layers, and forming a source/drain epitaxial material within a trench of the plurality of alternating first layers and second layers. The method may further include forming a cavity in source/drain epitaxial material, and performing a plasma doping process to form a doped area in the source/drain epitaxial material.
The present disclosure relates to systems, apparatus, and methods for multi-wavelength monitoring for semiconductor manufacturing. In one or more embodiments, a system for processing substrates includes a chamber body at least partially defining an internal volume, one or more heat sources configured to heat the internal volume, a substrate support disposed in the internal volume, and a sensor assembly operable to measure energy of a plurality of wavelengths in the internal volume. The sensor assembly includes one or more optical sensors, a movable tray coupled to a motor, and a plurality of filters supported by the movable tray, the motor operable to move the movable tray to move the plurality of filters relative to the one or more optical sensors to respectively align the plurality of filters with at least one of the one or more optical sensors.
The present technology is directed to methods and systems for cleaning deposition and/or fill byproducts from a backside or edge of a substrate. Methods include providing one or more deposition and/or fill precursors to a processing region of a semiconductor processing chamber and depositing one or more layers of the deposition and/or fill material on the substrate. Methods include forming a gap between the substrate and a substrate support surface of the substrate support. Methods include generating a DC plasma between the substrate support and a sidewall of the semiconductor processing chamber. Methods include treating the deposition and/or fill material with a DC plasma to remove at least a portion of the deposition and/or fill material from a back side and/or a bevel of the substrate.
C23C 16/50 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c.-à-d. procédés de dépôt chimique en phase vapeur [CVD] caractérisé par le procédé de revêtement au moyen de décharges électriques
C23C 16/458 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c.-à-d. procédés de dépôt chimique en phase vapeur [CVD] caractérisé par le procédé de revêtement caractérisé par le procédé utilisé pour supporter les substrats dans la chambre de réaction
H01J 37/32 - Tubes à décharge en atmosphère gazeuse
A workpiece processing system for extracting ion beams at low extraction voltages is disclosed. The workpiece processing system includes an ion source with an extraction plate having an extraction aperture. A ground electrode is rigidly affixed to the extraction plate so as to tightly control the positioning accuracy between the extraction aperture and the aperture in the ground electrode. A suppression electrode is located between the extraction plate and the ground electrode. This suppression electrode is also rigidly mounted so as to create a fixed first gap between the extraction plate and the suppression electrode and a fixed second gap between the suppression electrode and the ground electrode. This system may be operated at extraction voltages as low as 100V and as high as several kV.
H01J 37/317 - Tubes à faisceau électronique ou ionique destinés aux traitements localisés d'objets pour modifier les propriétés des objets ou pour leur appliquer des revêtements en couche mince, p. ex. implantation d'ions
84.
ETCHING METHOD TO RECESS SIGE AND SIGEC IN EPI STACK WITH SELECTIVITY TO SILICON
Embodiments of the present disclosure generally relate to 3D semiconductor device fabrication techniques. More specifically, embodiments, described herein provide processes by which to selectively etch layers of SiGe and/or SiGeC from Si layers. In some embodiments, a method for processing a semiconductor device includes positioning a semiconductor device in a processing volume of a processing chamber. The semiconductor device includes alternating silicon (Si) layers and silicon germanium (SiGe) layers. The method further includes introducing a process gas to the processing chamber. The process gas includes an etchant gas and a passivation gas. The method further includes performing a selective etch operation using the process gas to remove the SiGe layers from the semiconductor device.
A workpiece processing system for extracting ion beams at low extraction voltages is disclosed. The workpiece processing system includes an ion source with an extraction plate having an extraction aperture. A ground electrode is rigidly affixed to the extraction plate so as to tightly control the positioning accuracy between the extraction aperture and the aperture in the ground electrode. A suppression electrode is located between the extraction plate and the ground electrode. This suppression electrode is also rigidly mounted so as to create a fixed first gap between the extraction plate and the suppression electrode and a fixed second gap between the suppression electrode and the ground electrode. This system may be operated at extraction voltages as low as 100V and as high as several kV.
An end effector that includes replaceable pads is disclosed. The pads may be constructed from a different dielectric material than the end effector. This difference in dielectric material may help reduce particle generation and workpiece damage. Additionally, the pad is attached to the end effector using a latch and a spring, which allows the assembly to remain operational over a wide range of temperatures, even if the end effector and pad have coefficients of thermal expansion that differ by an order of magnitude or more. This assembly may operate to temperatures from −150° C. up to 500° C.
B25J 15/04 - Têtes de préhension avec possibilité pour l'enlèvement ou l'échange à distance de la tête ou de parties de celle-ci
H01L 21/687 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension en utilisant des moyens mécaniques, p. ex. mandrins, pièces de serrage, pinces
87.
METHOD FOR COATING AN OPTICALLY REFLECTIVE LAYER ON A WAVEGUIDE AND SCREEN PRINTING DEVICE
A method for coating an optically reflective layer on a waveguide having an in-coupler grating, the method comprising:
depositing an ink by screen printing on the in-coupler grating of the waveguide.
C03C 17/10 - Traitement de surface du verre, p. ex. du verre dévitrifié, autre que sous forme de fibres ou de filaments, par revêtement par des métaux par dépôt à partir d'une phase liquide
G02B 6/34 - Moyens de couplage optique utilisant des prismes ou des réseaux
88.
MODULATION TRANSFER FUNCTION MEASUREMENT APPARATUS AND METHOD FOR OPTICAL DEVICES
Embodiments herein provide for a measurement system for determining an optical device modulation transfer function (MTF). The measurement system includes a stage operable to retain an optical device or an optical device substrate having at least one optical device disposed thereon. A light engine is disposed above the stage. The light engine includes a light source operable to project a light to the optical device at a range of wavelengths. A reticle is operable to form a pattern from the light projected from the light source. A first lens operable to collimate the light from the light source toward the optical device or optical device substrate. A near field detector is operable to detect the light from the optical device or optical device substrate. A far field detector is operable to detect the light from the optical device of optical device substrate.
Embodiments of plasma processing systems are provided. The plasma processing systems include a junction box enclosure electrically coupling a direct current voltage source and a pulsed voltage source to a direct current conductor that is coupled to a substrate support and further electrically coupling the pulsed voltage source to a radio frequency conductor coupled to the radio frequency baseplate. The junction box enclosure includes a pulsed voltage filter circuit coupled between the radio frequency source and the radio frequency conductor. The junction box enclosure includes a radio frequency filter circuit coupled between the pulsed voltage source and the direct current conductor. The junction box enclosure includes a bias compensation module coupled between the radio frequency filter circuit and the direct current voltage source. The junction box enclosure includes a compensator circuit configured to compensate for a parasitic capacitance generated by the bias compensation module.
Exemplary substrate processing systems may include a plurality of processing regions. The systems may include a transfer region housing defining a transfer region fluidly coupled with the plurality of processing regions. The systems may include a plurality of substrate supports, and each substrate support of the plurality of substrate supports may be vertically translatable between the transfer region and an associated processing region of the plurality of processing regions. The systems may include a transfer apparatus including a rotatable shaft extending through the transfer region housing. The transfer apparatus may include an end effector coupled with the rotatable shaft. The end effector may include a central hub defining a central aperture fluidly coupled with a purge source. The end effector may also include a plurality of arms having a number of arms equal to a number of substrate supports of the plurality of substrate supports.
C23C 16/455 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c.-à-d. procédés de dépôt chimique en phase vapeur [CVD] caractérisé par le procédé de revêtement caractérisé par le procédé utilisé pour introduire des gaz dans la chambre de réaction ou pour modifier les écoulements de gaz dans la chambre de réaction
C23C 16/54 - Appareillage spécialement adapté pour le revêtement en continu
Embodiments of the disclosure provided herein include systems and methods for cleaning semiconductor substrates The method includes rotating a substrate disposed on a substrate support, spraying a front side of the substrate using a cleaning agent including one or more chelating agents through a front side nozzle assembly disposed above the substrate support, and spraying a back side of the substrate using the cleaning agent through a back side dispenser assembly disposed below the substrate support.
B08B 3/08 - Nettoyage impliquant le contact avec un liquide le liquide ayant un effet chimique ou dissolvant
B08B 3/04 - Nettoyage impliquant le contact avec un liquide
B08B 3/12 - Nettoyage impliquant le contact avec un liquide avec traitement supplémentaire du liquide ou de l'objet en cours de nettoyage, p. ex. par la chaleur, par l'électricité ou par des vibrations par des vibrations soniques ou ultrasoniques
Disclosed herein is a removable isolation panel for an equipment front end module (EFEM). The removable isolation panel may include a rectangular body having dimensions that approximately correspond to dimensions of one or more filters of the EFEM, a gas inlet, one or more handles to facilitate carrying of the removable isolation panel and positioning of the removable isolation panel into the EFEM, and a gasket at a peripheral edge of the rectangular body to seal the removable isolation panel against a surface of an upper plenum of the EFEM or an EFEM chamber of the EFEM. In some embodiments, the removable isolation panel is configured to flow a gas through the gas inlet towards one or more filters of the EFEM while the EFEM is open to an ambient environment to prevent the one or more filters from absorbing moisture of the ambient environment.
Multi-die packages may include a cover or lid that is placed over vertical stacks of silicon dies. This lid connects to a cooling system or heatsink to dissipate heat away from the dies. However, as thermal expansion/contraction occurs, the dies may lose contact with the cover and heat may build up within the cover around the dies. To solve this problem, a cover may include a flexible membrane on the bottom surface of the cover. The flexible membrane may create an internal cavity filled with a pressurized thermally conductive liquid. The liquid may cause the flexible membrane to expand and conform to a profile of the dies as they move due to temperature changes. The flexible membrane ensures that a thermally conductive pathway is maintained between the cover and the dies to effectively dissipate heat away from the dies.
Methods and systems for organic defect source identification using artificial intelligence (AI) are provided. One or more images depicting a surface of a substrate processed using one or more manufacturing equipment is provided as input to an artificial intelligence (AI) model. Output(s) of the AI model is obtained, where the output(s) indicate defect characterization data associated with a defect detected on the surface of the substrate depicted by the one or more images. A determination is made of whether a level of confidence of at least one defect type and associated defect source from the defect characterization data satisfies one or more confidence criteria. Upon a determination that at least one defect type and associated defect source satisfy the one or more confidence criteria, the at least one defect type and associated defect source are provided to a client device for presentation to one or more users.
G06T 3/4053 - Changement d'échelle d’images complètes ou de parties d’image, p. ex. agrandissement ou rétrécissement basé sur la super-résolution, c.-à-d. où la résolution de l’image obtenue est plus élevée que la résolution du capteur
The present disclosure generally relates to methods for forming a semiconductor device, a semiconductor device, and a processing system. The method includes forming a first epitaxial semiconductor layer on a cavity within the source/drain region of a semiconductor device structure formed on a substrate, forming a second highly doped recessed semiconductor layer that wraps around the first epitaxial semiconductor layer, and forming a metal contact plug. The first epitaxial semiconductor layer and the second epitaxial semiconductor layer are formed without breaking vacuum in the processing system. Embodiments of the present disclosure enable the formation of the semiconductor device that includes one or more layers with reduced contact resistance by using integrated processes that allows various operations of epitaxial semiconductor layer formation be performed within the same processing system.
H10D 84/03 - Fabrication ou traitement caractérisés par l'utilisation de technologies basées sur les matériaux utilisant une technologie du groupe IV, p. ex. technologie au silicium ou au carbure de silicium [SiC]
C23C 16/44 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c.-à-d. procédés de dépôt chimique en phase vapeur [CVD] caractérisé par le procédé de revêtement
Embodiments described herein relate to a method of modifying a resist layer that is provided over an underlayer. In an embodiment, the method includes exposing a portion of the resist layer and the underlayer to extreme ultraviolet (EUV) radiation to form an exposed region and an unexposed region, where the EUV radiation releases an acid from the exposed region of the underlayer. In an embodiment, the method further includes neutralizing photo decomposable quenchers (PDQs) in the exposed region of the resist layer with the acid.
G03F 7/11 - Matériaux photosensibles caractérisés par des détails de structure, p. ex. supports, couches auxiliaires avec des couches de recouvrement ou des couches intermédiaires, p. ex. couches d'ancrage
G03F 7/16 - Procédés de couchageAppareillages à cet effet
G03F 7/00 - Production par voie photomécanique, p. ex. photolithographique, de surfaces texturées, p. ex. surfaces impriméesMatériaux à cet effet, p. ex. comportant des photoréservesAppareillages spécialement adaptés à cet effet
97.
ELECTROMAGNETIC RADIATION SOURCES FOR USE IN SEMICONDUCTOR PROCESSING
In one or more embodiments, a processing chamber includes a first plate, a second plate, and a plurality of sidewalls partially defining a processing volume. A cover is disposed above the first plate. The cover and the first plate at least partially define an upper heating area. A first energy module is disposed within the upper heating area. The first energy module includes a plurality of heating elements. A plurality of ribs are disposed around the first plate, the second plate, and the sidewalls. A substrate support is disposed in the processing volume. One or more spot heaters are configured to emit a radiation beam toward the substrate support. The one or more spot heaters include a collimator supported by a holder and a stage. The holder is disposed on the stage. The one or more spot heaters further include a support, wherein the stage is disposed on the support.
Embodiments described herein relate to a method for changing a tone of a metal oxide resist (MOR) layer that is patterned to have a first pattern. In an embodiment, the method includes transferring the first pattern into an underlayer below the MOR layer, forming a hardmask around the underlayer with an area selective deposition process, and removing the underlayer to form a second pattern in the hardmask. In an embodiment, the second pattern is an inverse of the first pattern.
G03F 7/11 - Matériaux photosensibles caractérisés par des détails de structure, p. ex. supports, couches auxiliaires avec des couches de recouvrement ou des couches intermédiaires, p. ex. couches d'ancrage
99.
PULSED VOLTAGE SOURCE WITH MULTIPLE STAGES FOR PLASMA PROCESSING APPLICATIONS
iiiiiiiii) generating a third pulse at a third voltage at the common node at the first time based on a third transformer ratio of a third transformer included in a third voltage stage.
