Abstract

A semiconductor fabrication method includes: providing a separating wall and a plurality of liners including a first liner and a second liner between a first fin and a second fin having an epitaxial stack and a sacrificial gate stack over channel regions of the second fin; recessing a sacrificial epitaxial layer of the epitaxial stack to form a cavity; recessing the first line thereby expanding the cavity; recessing the second liner thereby expanding the cavity; forming inner spacer material in the first and second cavities; forming source/drain features; and replacing the sacrificial epitaxial layer and the sacrificial gate stack with a metal gate layer; wherein the metal gate layer has a first critical dimension (CD) measured between the inner spacer material, and wherein the first liner after recessing has a second CD measured between the inner spacer material that is approximately equal to the first CD.

IPC Classes  ?

• H01L 29/66 - Types of semiconductor device
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
• H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/786 - Thin-film transistors

Abstract

A semiconductor device includes first nanostructures vertically separated from one another, a first gate structure wrapping around each of the first nanostructures, and second nanostructures vertically separated from one another. The semiconductor device also includes a second gate structure wrapping around the second nanostructures, a first drain/source structure coupled to a first end of the first nanostructures, a second drain/source structure coupled to both of a second end of the first nanostructures and a first end of the second nanostructures, and a third drain/source structure coupled to a second end of the second nanostructures. The first drain/source structure has a first doping type, the second and third drain/source structures have a second doping type, and the first doping type is opposite to the second doping type.

IPC Classes  ?

• H10D 64/20 - Electrodes characterised by their shapes, relative sizes or dispositions
• G11C 11/402 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration individual to each memory cell, i.e. internal refresh
• G11C 17/12 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
• G11C 17/16 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
• H01L 23/00 - Details of semiconductor or other solid state devices
• H10B 20/00 - Read-only memory [ROM] devices
• H10B 20/25 - One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links

Abstract

Source/drain fabrication methods for stacked device structures are disclosed herein. An exemplary method for forming a source/drain stack may include a frontside process and a backside process. The frontside process may include forming a frontside source/drain trench, forming a dummy source/drain in the frontside source/drain trench, and forming an upper source/drain in the frontside source/drain trench over the dummy source/drain. The backside process may include exposing a backside of the dummy source/drain, removing (partially or completely) the dummy source/drain to form a backside source/drain trench, and forming a lower source/drain in the backside source/drain trench. The dummy source/drain may be formed of semiconductor material or dielectric material, and a portion of the dummy source/drain may remain between the upper source/drain and the lower source/drain. In some embodiments, the backside process includes replacing substrate/mesa with a backside insulation structure and selectively removing the dummy source/drain relative to the backside insulation structure.

IPC Classes  ?

• H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
• H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 29/786 - Thin-film transistors

Abstract

An IC device includes a first electrode including a first bus and first plurality of fingers extending in a first direction in a first metal layer of a substrate and a second bus and a second plurality of fingers extending in a second, perpendicular direction in a second metal layer adjacent to the first metal layer, and a second electrode including a third bus and third plurality of fingers extending in the first direction in the first metal layer and fourth and fifth buses and a fourth plurality of fingers between the fourth and fifth buses extending in the second direction in the second metal layer. The fingers of the first plurality of fingers alternate with those of the third plurality of fingers along the second direction, and the fingers of the second plurality of fingers alternate with those of the fourth plurality of fingers along the first direction.

IPC Classes  ?

• H01L 23/528 - Layout of the interconnection structure
• G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
• G06F 30/3953 - Routing detailed
• G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H10D 1/68 - Capacitors having no potential barriers

Abstract

Embodiments of the present disclosure provide a semiconductor device structure having vertically stacked complementary field effect transistors (CFETs). The CFETs are formed by bonding two substrates having semiconductor stacks formed thereon. A bonding structure is formed between the semiconductor stacks using wafer bonding technology. Embodiments of the resent disclosure enable the flexibility of choosing different N/P channel properties, provide a simple way to form the N/P channel isolation structure, and reduce potential leakage path and defects in stacked CFETs.

IPC Classes  ?

• H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
• H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
• H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET

Abstract

A method for manufacturing a semiconductor structure includes: forming a first patterned structure on a memory region of a base structure and forming a second patterned structure and a third patterned structure on a logic region of the base structure, the first patterned structure including a first channel portion, the second patterned structure including a second channel portion, the third patterned structure including a third channel portion, each of the first, second and third channel portions having two exposed end surfaces which are opposite to each other; forming a patterned hard mask covering the first and third patterned structures; and performing an etching process through the patterned hard mask so as to reduce a minimum distance between the two exposed end surfaces of the second channel portion.

IPC Classes  ?

• H10B 10/00 - Static random access memory [SRAM] devices
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 29/786 - Thin-film transistors

Abstract

A method of using an exhaust structure includes receiving a gas at an intake section, the intake section has a first inner diameter at a first position. The method includes passing the gas from the intake section to a piping section, wherein the piping section has the first inner diameter in a central region of the piping section, and the first position is farthest from the central region. The method includes outputting the gas from an output section connected to the piping section, wherein the output section comprises a curved portion configured to change a direction of the gas, and the output section has the first inner diameter at a position of the output section farthest from the central region. The method includes resisting turbulence and condensation during propagation of the gas through the piping section using a plurality of smoothing layers on an inner diameter of the piping section.

IPC Classes  ?

• H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
• F23J 13/02 - LiningsJacketsCasings
• F27D 17/30 - Arrangements for extraction or collection of waste gasesHoods therefor

Abstract

A semiconductor structure includes a first conductive line, a first conductive segment, a second conductive segment, and a third conductive segment. The first conductive segment is electrically coupled to the first conductive line. The second conductive segment is electrically coupled the first conductive segment. The second conductive segment is disposed between the first conductive segment and the third conductive segment. A top surface of the first conductive segment is aligned with a top surface of the second conductive segment in a same layer.

IPC Classes  ?

• H01L 23/528 - Layout of the interconnection structure
• H01L 21/762 - Dielectric regions
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H10D 1/00 - Resistors, capacitors or inductors
• H10D 30/01 - Manufacture or treatment
• H10D 30/62 - Fin field-effect transistors [FinFET]
• H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
• H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
• H10D 84/85 - Complementary IGFETs, e.g. CMOS
• H10D 89/10 - Integrated device layouts

Abstract

Optical devices and methods of manufacture are presented in which a first connecting structure with a lens is utilized to transmit and receive optical signals to and from an optical device. In embodiments the first connecting structure comprises a first mirror and a lens aligned with the first mirror. The first mirror and the lens redirect optical signals into and out of the optical devices through an edge coupler within the optical device.

IPC Classes  ?

• G02B 6/42 - Coupling light guides with opto-electronic elements

Abstract

An integrated circuit includes a set of active regions, a first set of contacts, a first gate, a first set of power rails, and a first set of vias. The first set of contacts overlaps the set of active regions, and a first and second cell boundary. The first gate overlaps the set of active regions, not overlapping the first and second cell boundary, and is between the first set of contacts. The first set of power rails is configured to supply a first or second supply voltage, and overlaps the first gate. The first set of vias is between the first gate and the first set of power rails, and electrically couples the first gate and the first set of power rails together. At least one active region of the set of active regions extends continuously through the first and second cell boundary.

IPC Classes  ?

• H10D 89/10 - Integrated device layouts
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

Abstract

A wafer chuck assembly is provided. In one embodiment, the chuck assembly comprises a hub, a plurality of arms mounted to the hub and a plurality of holders. Each arm extends outwardly from the hub, and each arm has a proximal end adjacent the hub and a distal end remote from the hub. Each holder is mounted at the distal end of each respective arm, and each holder has a plurality of support pins configured to support a wafer.

IPC Classes  ?

• H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
• H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
• H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

Abstract

Optical devices and methods of manufacture are presented in which metallization layers are formed over a first active layer of first optical components, a first opening is formed through the metallization layers, a first semiconductor die is bonded over the metallization layers, and a laser die is bonded over the metallization layers, wherein after the bonding the laser die a first mirror located within the laser die is aligned with a second mirror through the first opening.

IPC Classes  ?

• G02B 6/122 - Basic optical elements, e.g. light-guiding paths
• G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
• G02B 6/13 - Integrated optical circuits characterised by the manufacturing method

Abstract

A memory circuit includes a first and second bit line coupled to a set of memory cells, a local input output (LIO) circuit coupled to the set of memory cells by the first and second bit line. The LIO circuit includes a first and second data line, and a first control circuit. The LIO circuit further includes a switching circuit configured to transfer a first and second input signal to the corresponding first and second data line during a write operation of the set of memory cells, and to electrically isolate the first and second data line from the first and second input signal during a read operation of the set of memory cells. The LIO circuit further includes a first latch circuit configured as a sense amplifier during the read operation, and configured as a write-in latch during the write operation.

IPC Classes  ?

• G11C 7/08 - Control thereof
• G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

A memory device includes a metal structure, a bottom electrode, a storage element, a top electrode, a first spacer, and a second spacer. The metal structure is embedded in a dielectric layer. The bottom electrode is disposed over the metal structure. The top electrode is disposed over the storage element. The first spacer interfaces a first sidewall of the top electrode. The first spacer has a topmost point lower than a topmost point of the top electrode in a cross-sectional view. The second spacer interfaces a second sidewall of the top electrode. The second spacer has a topmost point higher than the topmost point of the top electrode in the cross-sectional view.

IPC Classes  ?

• H10N 70/20 - Multistable switching devices, e.g. memristors
• H10N 50/01 - Manufacture or treatment
• H10N 70/00 - Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching

Abstract

A structure has stacks of semiconductor layers over a substrate and adjacent a dielectric feature. A gate dielectric is formed wrapping around each layer and the dielectric feature. A first layer of first gate electrode material is deposited over the gate dielectric and the dielectric feature. The first layer on the dielectric feature is recessed to a first height below a top surface of the dielectric feature. A second layer of the first gate electrode material is deposited over the first layer. The first gate electrode material in a first region of the substrate is removed to expose a portion of the gate dielectric in the first region, while the first gate electrode material in a second region of the substrate is preserved. A second gate electrode material is deposited over the exposed portion of the gate dielectric and over a remaining portion of the first gate electrode material.

IPC Classes  ?

• H10D 30/67 - Thin-film transistors [TFT]
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H10D 84/85 - Complementary IGFETs, e.g. CMOS

Abstract

A hardmask (HM), for protecting a magnetic tunnel junction (MTJ), may be formed with two portions of HM material: a taper HM portion and a vertical HM portion, separated by one or more dielectric layers. For example, a first etch process may shape the taper HM portion and the vertical HM portion such that a taller HM remains as compared with only using one HM portion. As a result, the MTJ is protected during a second etch process, which results in increased removal efficiency and lower sidewall redeposition. As a result, the taller HM reduces leakage current and increases yields. For example, the MTJ is sufficiently protected during etching such that the MTJ is less likely to experience conductive bridging and thus less likely to suffer from electrical shorts.

IPC Classes  ?

• H10N 50/01 - Manufacture or treatment
• H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• H10N 50/20 - Spin-polarised current-controlled devices

Abstract

A package structure is provided. The package structure includes a die, an encapsulant and an RDL structure. The RDL structure is disposed on the die and the encapsulant. The RDL structure includes a first dielectric structure and a first redistribution layer. The first dielectric structure includes a first dielectric material layer and a second dielectric material layer on the first dielectric material layer. The first redistribution layer is embedded in the first dielectric structure and electrically connected to the die. The redistribution layer includes a first seed layer and a first conductive layer surrounded by the first seed layer. A topmost surface of the first seed layer and a topmost surface of the first conductive layer are substantially level with a top surface of the second dielectric material layer.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

A manufacturing method of a semiconductor structure is provided. The method includes: forming contact pads on an interconnect structure over a semiconductor substrate; forming a dielectric material stack on the interconnect structure; forming holes and a recess in the dielectric material stack to form a dielectric structure, wherein the holes accessibly expose portions of the contact pads, and the recess is formed between adjacent two of the holes; and forming conductive materials in the holes and the recess to respectively form bonding connectors and a dummy feature. The bonding connectors land on the contact pads, and the dummy feature is isolated and substantially equidistant from adjacent two of the bonding connectors.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

A method of fabricating a contact structure includes the following steps. An opening is formed in a dielectric layer. A conductive material layer is formed within the opening and on the dielectric layer, wherein the conductive material layer includes a bottom section having a first thickness and a top section having a second thickness, the second thickness is greater than the first thickness. A first treatment is performed on the conductive material layer to form a first oxide layer on the bottom section and on the top section of the conductive material layer. A second treatment is performed to remove at least portions of the first oxide layer and at least portions of the conductive material layer, wherein after performing the second treatment, the bottom section and the top section of the conductive material layer have substantially equal thickness.

IPC Classes  ?

• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
• H10B 10/00 - Static random access memory [SRAM] devices
• H10D 62/83 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
• H10D 64/01 - Manufacture or treatment
• H10D 64/62 - Electrodes ohmically coupled to a semiconductor

Abstract

Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes an active region including a channel region and a source/drain region and extending along a first direction, and a source/drain contact structure over the source/drain region. The source/drain contact structure includes a base portion extending lengthwise along a second direction perpendicular to the first direction, and a via portion over the base portion. The via portion tapers away from the base portion.

IPC Classes  ?

• H01L 23/528 - Layout of the interconnection structure
• H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

Abstract

A method for forming a semiconductor device structure includes forming nanostructures over a substrate. The method also includes forming a gate structure wrapped around the nanostructures. The method also includes forming source/drain epitaxial structures over opposite sides of the nanostructures. The method also includes forming an interlayer dielectric structure over the source/drain epitaxial structures. The method also includes etching the interlayer dielectric structure to form an opening exposing the source/drain epitaxial structures. The method also includes depositing a first spacer layer over sidewalls of the interlayer dielectric structure in the opening. The method also includes forming a silicide structure over the source/drain epitaxial structures. The method also includes forming a bottom contact structure over the silicide structure. The method also includes depositing a second spacer layer over the first spacer layer. The method also includes forming an upper contact structure over the first contact structure.

IPC Classes  ?

• H01L 29/40 - Electrodes
• H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/45 - Ohmic electrodes
• H01L 29/66 - Types of semiconductor device
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET

Abstract

Disclosed herein are related to performing layout verification of a layout design of an integrated circuit having a slanted layout component. In one aspect, a slanted layout component having a side slanted from a base axis by an offset angle is detected. In one aspect, a first location of a vertex of the slanted layout component according to the offset angle is transformed to obtain a second location of a rotated vertex of a rotated layout component. In one aspect, layout verification is performed on the rotated layout component with respect to the base axis.

IPC Classes  ?

• G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
• G06F 30/31 - Design entry, e.g. editors specifically adapted for circuit design
• G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement

Abstract

A magnetic tunneling junction (MTJ) structure is described. The MJT structure includes a stress modulating layer on a first electrode layer, where a material of the stress modulating layer is different from a material of the first electrode layer. The MJT structure further includes a MTJ material stack on the stress modulating layer. And the MJT structure further includes a second electrode layer on the MTJ material stack. The stress modulating layer reduces crystal growth defects and interfacial defects during annealing and improve the interface lattice epitaxy. This will improve device performance.

IPC Classes  ?

• H10N 50/80 - Constructional details
• G11B 5/39 - Structure or manufacture of flux-sensitive heads using magneto-resistive devices
• G11B 5/48 - Disposition or mounting of heads relative to record carriers
• G11B 5/60 - Fluid-dynamic spacing of heads from record carriers
• G11B 19/20 - DrivingStartingStoppingControl thereof
• H10N 50/01 - Manufacture or treatment

Abstract

A method for manufacturing a semiconductor device includes: forming a dummy gate structure on a semiconductor substrate, the dummy gate structure including a lower portion disposed on the semiconductor substrate and an upper portion disposed on the lower portion and opposite to the semiconductor substrate; and trimming the lower portion of the dummy gate structure by an etching process such that the lower portion of the dummy gate structure has a width less than that of the upper portion of the dummy gate structure.

IPC Classes  ?

• H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

A semiconductor device has a conductive via laterally separated from the semiconductor, an encapsulant between the semiconductor device and the conductive via, and a mark. The mark is formed from characters that are either cross-free characters or else have a overlap count of less than two. In another embodiment the mark is formed using a wobble scan methodology. By forming marks as described, defects from the marking process may be reduced or eliminated.

IPC Classes  ?

• H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement

Abstract

A semiconductor device includes a plurality of first decoder lines disposed in a first metallization layer and extending in a first direction. Each of the first decoder lines includes at least a first segment and a second segment operatively coupled to a plurality of first memory cells and a plurality of second memory cells, respectively. The first segment and second segment of each of the first decoder lines are arranged side-by-side along the first direction.

IPC Classes  ?

• G11C 8/10 - Decoders

Abstract

Semiconductor device structures with a gate structure having different profiles at different portions of the gate structure may include a fin structure on a substrate, a source/drain structure on the fin structure, and a gate structure over the fin structure and along a sidewall of the fin. The source/drain structure is proximate the gate structure. The gate structure has a top portion having a first sidewall profile and a bottom portion having a second sidewall profile different from the first sidewall profile.

IPC Classes  ?

• H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
• H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
• H10D 30/01 - Manufacture or treatment
• H10D 30/62 - Fin field-effect transistors [FinFET]

Abstract

A sensing method of a sense amplifier circuit is provided. The sense amplifier circuit comprises a differential amplifier. The differential amplifier comprises a first input node, a second input node, a first output node and a second output node. The sensing method comprising: providing a first switch and a second switch, wherein the first switch is coupled to the first input node and the first output node; pre-charging the first input node using a first output voltage of the first output node in response to a select signal by the first switch; and pre-charging the second input node using a second output voltage of the second output node in response to a select signal by the second switch.

IPC Classes  ?

• G11C 11/419 - Read-write [R-W] circuits
• G11C 11/418 - Address circuits

Abstract

Semiconductor device isolation is provided. In one aspect, a semiconductor device include a spiral inductor. The semiconductor device includes a patterned ground shield (PGS) electrically coupled with the spiral inductor. The semiconductor device includes a filter configured to exchange energy with the PGS. The semiconductor device includes a circuit vertically spaced from the inductor, the PGS disposed between the circuit and the spiral inductor.

IPC Classes  ?

• H01F 27/28 - CoilsWindingsConductive connections
• H01F 17/00 - Fixed inductances of the signal type
• H01F 27/29 - TerminalsTapping arrangements
• H01L 23/498 - Leads on insulating substrates
• H01L 23/552 - Protection against radiation, e.g. light
• H01L 23/66 - High-frequency adaptations

Abstract

A photomask and a method of manufacturing a photomask are provided. According to an embodiment, the method includes: providing a substrate; depositing a reflective layer including molybdenum layers and silicon layers over the substrate, the reflective layer including a first area and a second area laterally surrounding the first area from a top-view perspective; depositing a capping layer over the reflective layer; depositing an absorption layer over the capping layer; and causing an energy to pass through the absorption layer, the capping layer and the reflective layer within the second area for forming molybdenum silicide in a border region of the reflective layer and keeping the absorption layer and the capping layer substantially intact.

IPC Classes  ?

• G03F 1/24 - Reflection masksPreparation thereof

Abstract

A spin torque oscillator (STO) device includes a main pole, a trailing shield, an STO stack disposed between the main pole and the trailing shield, a passivation layer disposed on a sidewall of the STO stack, and a dielectric layer disposed on the passivation layer. The passivation layer is non-magnetic and includes one or more layers that is selected from the group consisting of a B-containing layer, a C-containing layer, and a Ge-containing layer.

IPC Classes  ?

• H10N 50/10 - Magnetoresistive devices
• G01R 33/09 - Magneto-resistive devices
• G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
• H01F 10/32 - Spin-exchange-coupled multilayers, e.g. nanostructured superlattices
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H03B 15/00 - Generation of oscillations using galvano-magnetic devices, e.g. Hall-effect devices, devices using spin transfer effects, devices using giant magnetoresistance, or using super-conductivity effects
• H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• H10N 50/01 - Manufacture or treatment
• H10N 50/80 - Constructional details
• H10N 50/85 - Materials of the active region

Abstract

Semiconductor structures and methods for manufacturing the same are provided. The method includes nanostructures formed over a substrate, and a gate structure formed on the nanostructures. The semiconductor structure includes a source/drain (S/D) structure formed adjacent to the gate structure. The semiconductor structure includes a contact structure formed on the S/D structure, and a portion of the contact structure is embedded in the S/D structure, and the contact structure has a T-shaped structure.

IPC Classes  ?

• H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
• H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
• H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET

Abstract

A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions. A top portion of the semiconductor fin is formed of a first semiconductor material. A semiconductor cap layer is formed on a top surface and sidewalls of the semiconductor fin. The semiconductor cap layer is formed of a second semiconductor material different from the first semiconductor material. The method further includes forming a gate stack on the semiconductor cap layer, forming a gate spacer on a sidewall of the gate stack, etching a portion of the semiconductor fin on a side of the gate stack to form a first recess extending into the semiconductor fin, recessing the semiconductor cap layer to form a second recess directly underlying a portion of the gate spacer, and performing an epitaxy to grow an epitaxy region extending into both the first recess and the second recess.

IPC Classes  ?

• H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/3065 - Plasma etchingReactive-ion etching
• H10D 30/01 - Manufacture or treatment
• H10D 30/62 - Fin field-effect transistors [FinFET]
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
• H10D 64/01 - Manufacture or treatment
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology

Abstract

A semiconductor device is disclosed. The device includes a source/drain feature formed over a substrate. A dielectric layer formed over the source/drain feature. A contact trench formed through the dielectric layer to expose the source/drain feature. A titanium nitride (TiN) layer deposited in the contact trench and a cobalt layer deposited over the TiN layer in the contact trench.

IPC Classes  ?

• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H10D 30/01 - Manufacture or treatment
• H10D 30/62 - Fin field-effect transistors [FinFET]
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology

Abstract

A conductive line structure (in an integrated circuit (IC)) includes: in a first layer of metallization (M_first layer), M_first segments extending in a first direction and being aligned to M_first routing tracks, the M_first segments including first and second ones thereof; and in a second layer of metallization (M_second layer) over the M_first layer, M_second segments extending in a second direction perpendicular to the first direction and being aligned to M_second routing tracks, the M_second segments including first and second ones thereof correspondingly overlapping the first and second M_first segments; and the first and second M_first segments being aligned to different first and second ones of the M_first routing tracks; and relative to the first direction, the first and second M_first segments being separated by a first gap having a size substantially equal to or greater than a minimum permissible offset between co-track aligned M_first segments.

IPC Classes  ?

• H01L 23/528 - Layout of the interconnection structure
• G06F 30/394 - Routing
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

Abstract

Some embodiments relate to an integrated device, including a substrate having at least one active component; an interconnect structure disposed on the substrate; a bonding layer disposed over the interconnect structure; a carrier substrate disposed over the bonding structure; a heat dissipating module disposed over the carrier substrate; and a first thermal control layer disposed between the carrier substrate and the heat dissipating module, the bonding layer and the interconnect structure, or the carrier substrate and the bonding layer, wherein the first thermal control layer comprises a phase change material (PCM).

IPC Classes  ?

• H01L 23/427 - Cooling by change of state, e.g. use of heat pipes
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/367 - Cooling facilitated by shape of device
• H01L 23/528 - Layout of the interconnection structure

Abstract

A method for forming a semiconductor device includes forming a fin structure protruding from a substrate of the semiconductor device; forming a first conductive rail on the substrate, wherein a side of the first conductive rail facing the fin structure has a recess; forming a first conductive line in a same layer as the first conductive rail by filling a first conductive material into the recess, wherein the first conductive line extends across the fin structure and wraps a first portion of the fin structure; forming a second conductive line in the same layer as the first conductive rail, wherein the second conductive line extends across the fin structure and contacts a second portion of the fin structure different from the first portion; and forming an isolation region on the substrate to separate the first conductive rail from the second conductive line.

IPC Classes  ?

• H10D 89/10 - Integrated device layouts
• H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 23/528 - Layout of the interconnection structure
• H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
• H10D 30/01 - Manufacture or treatment
• H10D 30/62 - Fin field-effect transistors [FinFET]
• H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H10D 84/85 - Complementary IGFETs, e.g. CMOS

Abstract

A method for forming a semiconductor device structure is provided. The method includes providing a substrate. The method includes performing a first degas process on the substrate. The method includes forming a first magnetic layer over the substrate. The method includes forming a second magnetic layer on the first magnetic layer. The method includes performing a second degas process on the substrate, the first magnetic layer, and the second magnetic layer. The method includes forming a third magnetic layer on the second magnetic layer after the second degas process is performed. The method includes partially removing the first magnetic layer, the second magnetic layer, and the third magnetic layer.

IPC Classes  ?

• H10D 1/20 - Inductors

Abstract

A MEMS support structure and a cap structure are provided. At least one vertically-extending trench is formed into the MEMS support structure or a portion of the cap structure. A vertically-extending outgassing material portion having a surface that is physically exposed to a respective vertically-extending cavity is formed in each of the at least one vertically-extending trench. A matrix material layer is attached to the MEMS support structure. A movable element laterally confined within a matrix layer is formed by patterning the matrix material layer. The matrix layer is bonded to the cap structure. A sealed chamber containing the movable element is formed. Each vertically-extending outgassing material portion has a surface that is physically exposed to the sealed chamber, and outgases a gas to increase the pressure in the sealed chamber.

IPC Classes  ?

• B81B 7/00 - Microstructural systems
• B81C 1/00 - Manufacture or treatment of devices or systems in or on a substrate

Abstract

A semiconductor structure includes a first transistor, a second transistor, a first dummy source/drain, a third transistor, a fourth transistor, and a second dummy source/drain. The first transistor and a second transistor adjacent to the first transistor are at a first elevation. The first dummy source/drain is disposed at the first elevation. The third transistor and a fourth transistor adjacent to the third transistor, are at a second elevation different from the first elevation. The second dummy source/drain is disposed at the second elevation. The second transistor is vertically aligned with the third transistor. The first dummy source/drain is vertically aligned with a source/drain of the fourth transistor. The second dummy source/drain is vertically aligned with a source/drain of the first transistor. The gate structure between the second dummy source/drain and a source/drain of the third transistor is absent. A method for manufacturing a semiconductor structure is also provided.

IPC Classes  ?

• H10D 86/00 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 23/528 - Layout of the interconnection structure
• H10D 86/01 - Manufacture or treatment

Abstract

A semiconductor die includes a first semiconductor substrate; a first interconnect structure disposed on a front side of the first semiconductor substrate; a first through-substrate via (TSV) structure extending through the first semiconductor substrate; and a first fuse structure disposed between and electrically connecting the TSV structure and the first interconnect structure.

IPC Classes  ?

• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
• H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

A package includes a first die over and bonded to a first side of a package component, where a first bond between the first die and the package component includes a dielectric-to-dielectric bond between a first bonding layer of the first die and a second bonding layer on the package component, and second bonds between the first die and the package component include metal-to-metal bonds between first bonding pads of the first die and second bonding pads on the package component, a first portion of a redistribution structure adjacent to the first die and over the second bonding layer, and a second die over and coupled to the first portion of the redistribution structure using first conductive connectors, where the first conductive connectors are electrically connected to first conductive pads in the second bonding layer.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/498 - Leads on insulating substrates
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or

Abstract

A semiconductor device includes a substrate, an isolation feature disposed on the substrate, first and second fins protruding from the substrate and upwardly through the isolation feature, and a gate stack engaging each of the fins. The semiconductor device also includes a first epitaxial layer having a first portion over top and sidewall surfaces of S/D regions of the first fin and a second portion over top and sidewall surfaces of S/D regions of the second fin, a second epitaxial layer having a first portion over top and sidewall surfaces of the first portion of the first epitaxial layer and a second portion over top and sidewall surfaces of the second portion of the first epitaxial layer. The first and second portions of the second epitaxial layer are spaced apart. Each of the first and second portions of the second epitaxial layer is in physical contact with the isolation feature.

IPC Classes  ?

• H10D 84/01 - Manufacture or treatment
• H10D 30/01 - Manufacture or treatment
• H10D 30/62 - Fin field-effect transistors [FinFET]
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H10D 84/85 - Complementary IGFETs, e.g. CMOS

Abstract

A semiconductor device includes a first semiconductor die that operates at a first power, a second semiconductor die that is formed in a stack on the first semiconductor die and operates at a second power different than the first power, and a power management semiconductor die that is formed in the stack and provides the first power to the first semiconductor die through a first via and provides the second power to the second semiconductor die through a second via.

IPC Classes  ?

• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• G06F 1/3203 - Power management, i.e. event-based initiation of a power-saving mode
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates

Abstract

The current disclosure describes a new vertical tunnel field-effect transistor (TFET). The TFET includes a source layer over a substrate. A first channel layer is formed over the source layer. A drain layer is stacked over the first channel layer with a second channel layer stacked therebetween. The drain layer and the second channel layer overlap a first surface portion of the first channel layer. A gate structure is positioned over the channel layer by a second surface portion of the channel layer and contacts a sidewall of the second channel layer.

IPC Classes  ?

• H10D 30/69 - IGFETs having charge trapping gate insulators, e.g. MNOS transistors
• H10D 10/00 - Bipolar junction transistors [BJT]
• H10D 30/01 - Manufacture or treatment
• H10D 30/60 - Insulated-gate field-effect transistors [IGFET]
• H10D 30/63 - Vertical IGFETs
• H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
• H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates

Abstract

A bias voltage generating device includes a reference bias circuit and a first transistor. The reference bias circuit includes a first diode-connected transistor pair and a second diode-connected transistor pair serially connected between a first voltage and a second voltage. The first diode-connected transistor pair includes a diode-connected p-type transistor and a diode-connected n-type transistor. The first transistor is coupled to the reference bias circuit, and configured to provide a third voltage based on the first voltage and the second voltage. Gates of the diode-connected p-type transistor and the diode-connected n-type transistor of the first diode-connected transistor pair are connected to a gate of the first transistor.

IPC Classes  ?

• G05F 3/26 - Current mirrors
• G05F 3/24 - Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode-transistor combinations wherein the transistors are of the field-effect type only

Abstract

A method includes bonding a first device die and a second device die to a substrate, and filling a gap between the first device die and the second device die with a gap-filling material. A top portion of the gap-filling material covers the first device die and the second device die. Vias are formed to penetrate through the top portion of the gap-filling material. The vias are electrically coupled to the first device die and the second device die. The method further includes forming redistribution lines over the gap-filling material using damascene processes, and forming electrical connectors over and electrically coupling to the redistribution lines.

IPC Classes  ?

• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/367 - Cooling facilitated by shape of device
• H01L 23/467 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing gases, e.g. air
• H01L 23/473 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing liquids
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 23/498 - Leads on insulating substrates
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices

Abstract

In an embodiment, a device includes: a first dielectric layer having a first sidewall; a second dielectric layer having a second sidewall; a word line between the first dielectric layer and the second dielectric layer, the word line having an outer sidewall and an inner sidewall, the inner sidewall recessed from the outer sidewall, the first sidewall, and the second sidewall; a memory layer extending along the outer sidewall of the word line, the inner sidewall of the word line, the first sidewall of the first dielectric layer, and the second sidewall of the second dielectric layer; and a semiconductor layer extending along the memory layer.

IPC Classes  ?

• H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
• G11C 7/18 - Bit line organisationBit line lay-out
• G11C 8/14 - Word line organisationWord line lay-out
• H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout

Abstract

A method includes a number of operations. A plurality of isolation regions is formed between a plurality of fin structures over a substrate. A dummy gate structure is formed over the fin structures and the isolation regions. After forming the dummy gate structure, a first refilled isolation material is formed over the isolation regions. The first refilled isolation material is etched to form a plurality of first isolation layers having a top surface below top surfaces of the fin structures. A plurality of source/drain epitaxial structures is formed in the fin structures. The dummy gate structure is replaced with a gate structure.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/762 - Dielectric regions
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device

Abstract

The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin active region formed on a semiconductor substrate and spanning between a first sidewall of a first shallow trench isolation (STI) feature and a second sidewall of a second STI feature; an anti-punch through (APT) feature of a first type conductivity; and a channel material layer of the first type conductivity, disposed on the APT feature and having a second doping concentration less than the first doping concentration. The APT feature is formed on the fin active region, spans between the first sidewall and the second sidewall, and has a first doping concentration.

IPC Classes  ?

• H10D 62/17 - Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
• H10D 30/69 - IGFETs having charge trapping gate insulators, e.g. MNOS transistors
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 64/01 - Manufacture or treatment
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
• H10D 86/00 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
• H10D 86/01 - Manufacture or treatment

Abstract

A fluid filtration system for a semiconductor processing station is provided. The fluid filtration system includes a first filter configured to filter metal ions from a first fluid to produce a first filtered fluid. The fluid filtration system includes a second filter configured to filter particles from the first filtered fluid to produce a second filtered fluid. The fluid filtration system includes a conduit configured to conduct the second filtered fluid to the semiconductor processing station.

IPC Classes  ?

• B01D 15/18 - Selective adsorption, e.g. chromatography characterised by constructional or operational features relating to flow patterns
• B01D 15/36 - Selective adsorption, e.g. chromatography characterised by the separation mechanism involving ionic interaction, e.g. ion-exchange, ion-pair, ion-suppression or ion-exclusion
• B01D 15/38 - Selective adsorption, e.g. chromatography characterised by the separation mechanism involving specific interaction not covered by one or more of groups , e.g. affinity, ligand exchange or chiral chromatography
• B01D 61/58 - Multistep processes
• G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor
• G03F 7/30 - Imagewise removal using liquid means
• H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

Abstract

A load-lock chamber with reduced particle contamination is disclosed. At least one movable particle shield is placed between the gate valve and a wafer location. Particles which can be generated due to contact between the gate valve door and its seat are blocked or inhibited by the particle shield from landing in the wafer location, reducing particle contamination. Methods for operating the load-lock chamber are also disclosed.

IPC Classes  ?

• G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor
• H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations

Abstract

Three-dimensional integrated circuit (3DIC) structures and methods of forming the same are provided. A 3DIC structure includes a semiconductor package, a first package substrate, a molded underfill layer and a thermal interface material. The semiconductor package is disposed over and electrically connected to the first package substrate through a plurality of first bumps. The semiconductor package includes at least one semiconductor die and an encapsulation layer aside the semiconductor die. The molded underfill layer surrounds the plurality of first bumps and a sidewall of the semiconductor package, and has a substantially planar top surface. The CTE of the molded underfill layer is different from the CTE of the encapsulation layer of the semiconductor package. The thermal interface material is disposed over the semiconductor package.

IPC Classes  ?

• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/498 - Leads on insulating substrates
• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits

Abstract

A photoresist composition includes a conjugated resist additive, a photoactive compound, and a polymer resin. The conjugated resist additive is one or more selected from the group consisting of a polyacetylene, a polythiophene, a polyphenylenevinylene, a polyfluorene, a polypryrrole, a polyphenylene, and a polyaniline. The polyacetylene, polythiophene, polyphenylenevinylene, polyfluorene, polypryrrole, the polyphenylene, and polyaniline includes a substituent selected from the group consisting of an alkyl group, an ether group, an ester group, an alkene group, an aromatic group, an anthracene group, an alcohol group, an amine group, a carboxylic acid group, and an amide group. Another photoresist composition includes a polymer resin having a conjugated moiety and a photoactive compound. The conjugated moiety is one or more selected from the group consisting of a polyacetylene, a polythiophene, a polyphenylenevinylene, a polyfluorene, a polypryrrole, a polyphenylene, and a polyaniline.

IPC Classes  ?

• G03F 7/038 - Macromolecular compounds which are rendered insoluble or differentially wettable
• G03F 7/012 - Macromolecular azidesMacromolecular additives, e.g. binders
• G03F 7/16 - Coating processesApparatus therefor

Abstract

A semiconductor structure includes a waveguide and an optical attenuator. The waveguide is disposed over an insulating layer and configured to guide light. The optical attenuator is connected to the waveguide. The optical attenuator has a first surface and a second surface opposite the first surface, and a cross-sectional width of the optical attenuator decreases from the first surface to the second surface.

IPC Classes  ?

• G02B 6/122 - Basic optical elements, e.g. light-guiding paths
• G02B 6/13 - Integrated optical circuits characterised by the manufacturing method

Abstract

A system and method for dynamically controlling a temperature of a thermostatic reticle. A thermostatic reticle assembly that includes a reticle, temperature sensors located in proximity to the reticle, and one or more heating elements. A thermostat component that is in communication with the temperature sensors and the heating element monitors the current temperature of the reticle relative to a steady-state temperature. In response to the current temperature of the reticle being lower than the steady-state temperature, the heating elements are activated to preheat the reticle to the steady-state temperature.

IPC Classes  ?

• G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor

Abstract

Various embodiments of the present application are directed towards an integrated chip. The integrated chip includes a first fin structure and a second fin structure disposed on a base region of a substrate. A first source/drain region is disposed on the first fin structure. A second source/drain region is disposed on the second fin structure. A gate structure overlies the base region of the substrate and is spaced laterally between the first and second fin structures. A bottom surface of the gate structure is disposed below bottoms of the first and second source/drain regions.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

Embodiments of the present disclosure provide an integrated circuit die with vertical interconnect features to enable direct connection between vertically stacked integrated circuit dies. The vertical interconnect features may be formed in a sealing ring, which allows higher routing density than interposers or redistribution layer. The direct connection between vertically stacked integrated circuit dies reduces interposer layers, redistribution process, and bumping processes in multi-die integration, thus, reducing cost of manufacturing.

IPC Classes  ?

• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 23/498 - Leads on insulating substrates
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
• H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers

Abstract

A semiconductor device includes an integrated circuit and one or more guard rings around the integrated circuit in a top view of the semiconductor device. At least one guard ring of the one or more guard rings includes an active region in the substrate, a first plurality of elongated conductive structures extending in a first direction in the top view of the semiconductor device and arranged in a second direction in the top view of the semiconductor device, and a second plurality of elongated conductive structures extending in the second direction and arranged in the first direction. The combination of the first and second pluralities of elongated conductive structures forms a conductive grid above the active region, and provides increased coverage of the surface area of the active region relative to including only the first plurality of elongated conductive structures or only the second plurality of elongated conductive structures.

IPC Classes  ?

• H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/528 - Layout of the interconnection structure

Abstract

Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The structure includes a first plurality of source/drain regions disposed along a first direction, a second plurality of source/drain regions disposed along the first direction and spaced apart from the first plurality of source/drain regions, a conductive feature disposed between the first and second pluralities of source/drain regions, and a plurality of conductive contacts disposed over and in contact with the conductive feature. Each conductive contact of the plurality of conductive contacts is in contact with a source/drain region of the first plurality of source/drain regions and a source/drain region of the second plurality of source/drain regions.

IPC Classes  ?

• H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
• H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
• H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 29/786 - Thin-film transistors

Abstract

A PIN diode detector includes a substrate, wherein the substrate includes a pixel region and a peripheral region, and the peripheral region surrounds the pixel region. The PIN diode detector further includes a plurality of PIN diode wells in the pixel region, wherein each of the plurality of PIN diode wells has a first dopant type. The PIN diode detector further includes a plurality of ring wells in the peripheral region, wherein a first ring well of the plurality of ring wells has the first dopant type, and a second ring well of the plurality of ring wells has a second dopant type opposite the first dopant type. The PIN diode detector further includes a blanket doped region, wherein the blanket doped region extends continuously through an entirety of the pixel region and an entirety of the peripheral region, and the blanket doped region has the second dopant type.

IPC Classes  ?

• H10F 30/223 - Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices having only one potential barrier, e.g. photodiodes the potential barrier being a PIN barrier
• G01T 1/24 - Measuring radiation intensity with semiconductor detectors
• H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
• H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors
• H10F 77/124 - Active materials comprising only Group III-V materials, e.g. GaAs

Abstract

The present disclosure provides a semiconductor structure. The semiconductor structure includes: a first layer including a plurality of first power lines; a second layer including a plurality of VFETs; a third layer including a plurality of second power line; wherein the second layer is disposed between the first layer and the third layer, a first part of the VETs is connected to the first power lines and a second part of the VETs is connected to the second power lines.

IPC Classes  ?

• H01L 23/528 - Layout of the interconnection structure
• H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

A method includes forming a p-well and an n-well in a substrate. The method further includes forming a stack of interleaving first semiconductor layers and second semiconductor layers over the p-well and the n-well, the first semiconductor layers having a first thickness and the second semiconductor layers having a second thickness different than the first thickness. The method further includes annealing the stack of interleaving semiconductor layers. The method further includes patterning the stack to form fin-shaped structures including a first fin-shaped structure over the n-well and a second fin-shaped structure over the p-well. The method further includes etching to remove the second semiconductor layers from the first and second fin-shaped structures, where the first semiconductor layers have a different thickness within each of the first and second fin-shaped structures after the etching. The method further includes forming a metal gate over the first and second fin-shaped structures.

IPC Classes  ?

• H10D 30/67 - Thin-film transistors [TFT]
• H10D 30/62 - Fin field-effect transistors [FinFET]
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 64/01 - Manufacture or treatment

Abstract

An integrated circuit includes a memory cell array, a row decoder configured to generate a first decoder signal, a column decoder configured to generate a second decoder signal and an array of write assist circuits electrically coupled to the row and column decoder and the memory cell array. Each write assist circuit is configured to set an operating voltage of a corresponding memory cell. The operating voltage corresponds to an output signal. Each write assist circuit includes a set of P-type transistors coupled together in parallel and further coupled to a supply voltage, and configured to set the output signal in response to an input control signal, and a first N-type transistor coupled to the set of P-type transistors. A first terminal of the first N-type transistor is configured to receive the input control signal. A second terminal of the first N-type transistor is coupled to the supply voltage.

IPC Classes  ?

• G11C 8/10 - Decoders
• G11C 7/02 - Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
• G11C 8/14 - Word line organisationWord line lay-out
• G11C 11/418 - Address circuits
• G11C 11/419 - Read-write [R-W] circuits

Abstract

A sensing amplifier of a memory array, a memory device and a data read method with two state reference voltages are provided. The sensing amplifier comprises a sampling circuit, a latch circuit, and a reset circuit. The sampling circuit compares data voltages, a first state reference voltage, and a second state reference voltage according to a bit line pre-charge signal and a word line to generate a first sampling signal on the output node and a second sampling signal on the inverted output node. The latch circuit implements that the first sampling signal and the second sampling signal are inverted signals and latches the first sampling signal on an output node and the second sampling signal on the inverted output node.

IPC Classes  ?

• G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
• G11C 7/06 - Sense amplifiersAssociated circuits

Abstract

Semiconductor devices and methods of manufacture are presented herein. In accordance with some embodiments, a device includes a first semiconductor device, the first semiconductor device including a first interconnect structure, an integrated cooling structure bonded to the first interconnect structure, wherein the integrated cooling structure is configured for a working fluid to enter and exit the integrated cooling structure, a second semiconductor device including a second interconnect structure, the second semiconductor device bonded to the integrated cooling structure opposite the first interconnect structure, and a plurality of through substrate vias extending through the integrated cooling structure, wherein the plurality of through substrate vias electrically couple the first semiconductor device to the second semiconductor device.

IPC Classes  ?

• H01L 23/473 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing liquids
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements

Abstract

A semiconductor package is provided. The semiconductor package includes a semiconductor substrate, a lower interconnect structure, an upper interconnect structure, a conductive pad, and a pillar bump. The lower interconnect structure is formed over the semiconductor substrate. The lower interconnect structure includes a plurality of lower dielectric layers. The lower interconnect structure also includes a plurality of lower metal lines and a plurality of lower metal vias formed in the lower dielectric layers. The upper interconnect structure is formed over the lower interconnect structure. The conductive pad is formed over the upper interconnect structure. The pillar bump structure is in direct contact with the conductive pad. The pillar bump structure includes at least two protrusions protruding toward the conductive pad and laterally separated from each other.

IPC Classes  ?

• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/528 - Layout of the interconnection structure

Abstract

A system and method for providing and programming a programmable inductor is provided. The structure of the programmable inductor includes multiple turns, with programmable interconnects incorporated at various points around the turns to provide a desired isolation of the turns during programming. In an embodiment the programming may be controlled using the size of the vias, the number of vias, or the shapes of the interconnects.

IPC Classes  ?

• H01F 41/04 - Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformersApparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils or magnets for manufacturing coils
• H01F 17/00 - Fixed inductances of the signal type
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections

Abstract

A chip package structure is provided. The chip package structure includes a first redistribution structure having a first surface and a second surface opposite to the first surface. The chip package structure includes a first chip over the first surface. The chip package structure includes a second chip over the second surface. The chip package structure includes a conductive pillar over the second surface and adjacent to the second chip. The chip package structure includes a molding layer over the second surface and surrounding the second chip. The chip package structure includes a second redistribution structure over the second chip. The chip package structure includes a buffer layer between the second redistribution structure and the second chip. The chip package structure includes a third chip over the second redistribution structure.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
• H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
• H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers

Abstract

A plating apparatus includes a workpiece holder. a plating bath, and a clamp ring. The plating bath is underneath the workpiece holder. The clamp ring is connected to the workpiece holder. The clamp ring includes channels communicating an inner surface of the clamp ring and an outer surface of the clamp ring.

IPC Classes  ?

• C25D 21/04 - Removal of gases or vapours
• C25D 7/12 - Semiconductors
• C25D 17/00 - Constructional parts, or assemblies thereof, of cells for electrolytic coating
• C25D 17/08 - Racks
• C25D 21/10 - Agitating of electrolytesMoving of racks
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

Abstract

A package structure includes a circuit substrate, a semiconductor device and a ring structure. The circuit substrate has a first region and a second region connected thereto. The circuit substrate includes at least one routing layer including a dielectric portion and a conductive portion disposed thereon. A first ratio of a total volume of the conductive portion of the routing layer within the first region to a total volume of the dielectric and conductive portions of the routing layer within the first region is less than a second ratio of a total volume of the conductive portion of the routing layer within the second region to a total volume of the dielectric and conductive portions of the routing layer within the second region. The semiconductor device is disposed over the circuit substrate within the first region, and is electrically coupled to the circuit substrate. The ring structure is disposed over the circuit substrate within the second region.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
• H01L 23/16 - Fillings or auxiliary members in containers, e.g. centering rings
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/367 - Cooling facilitated by shape of device
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for

Abstract

A method includes forming a plurality of fin structures extending along a first direction. The method includes forming a dummy fin structure disposed between two adjacent fin structures. The dummy fin structure also extends along the first direction and includes a deformable layer. The method includes recessing portions of each fin structure. The method includes forming source/drain structures over the recessed fin structures. The method includes deforming the deformable layer of the dummy fin structure to apply either a tensile stress or a compressive stress on the source/drain structures coupled to each of the two adjacent fin structures.

IPC Classes  ?

• H10D 30/01 - Manufacture or treatment
• H10D 30/62 - Fin field-effect transistors [FinFET]
• H10D 30/69 - IGFETs having charge trapping gate insulators, e.g. MNOS transistors
• H10D 62/822 - Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
• H10D 64/01 - Manufacture or treatment
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]

Abstract

A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate. The semiconductor fin has at least one recess thereon. The epitaxy structure is present in the recess of the semiconductor fin. The epitaxy structure includes a topmost portion, a first portion and a second portion arranged along a direction from the semiconductor fin to the substrate. The first portion has a germanium atomic percentage higher than a germanium atomic percentage of the topmost portion and a germanium atomic percentage of the second portion.

IPC Classes  ?

• H10D 62/60 - Impurity distributions or concentrations
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
• H10D 30/01 - Manufacture or treatment
• H10D 30/62 - Fin field-effect transistors [FinFET]
• H10D 30/69 - IGFETs having charge trapping gate insulators, e.g. MNOS transistors
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 62/834 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge further characterised by the dopants

Abstract

A semiconductor device includes: active regions extending in a first direction; in a first metal layer on a first side of the active regions, first segments including as follows, first and second rails extending in the first direction, and first fingers between the first and second rails, each of the first fingers extending in a second direction substantially perpendicular to the first direction, and the first fingers extending across one or more of the active regions; and the first and second rails and the first fingers representing a ladder arrangement in which the first fingers representing rungs of the ladder arrangement and the first and second rails representing siderails of the ladder arrangement.

IPC Classes  ?

• H01L 23/528 - Layout of the interconnection structure
• G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
• G06F 30/3953 - Routing detailed
• G06F 119/06 - Power analysis or power optimisation

Abstract

A memory device includes a memory cell in a first power domain of a first power supply voltage, a bit line coupled to the memory cell, and a write assist circuit. The write assist circuit includes an input, an output electrically couplable to the bit line in a write operation of the memory cell, an input circuit electrically coupled to the input, and an output circuit electrically coupled between the input circuit and the output. The input circuit is in a second power domain of a second power supply voltage different from the first power supply voltage, and the output circuit is in the first power domain.

IPC Classes  ?

• G11C 11/419 - Read-write [R-W] circuits

Abstract

An image sensor includes a storage device, where the storage device includes a memory element, a first dielectric layer and a light shielding element. The memory element includes a storage node and a storage transistor gate, where the storage transistor gate is located over the storage node. The first dielectric layer is located over a portion of the storage transistor gate. The light shielding element is located on the first dielectric layer and includes a semiconductor layer. The semiconductor layer is electrically isolated from the memory element, where the light shielding element is overlapped with at least a part of a perimeter of the storage transistor gate in a vertical projection on a plane along a stacking direction of the memory element and the light shielding element, and the stacking direction is normal to the plane.

IPC Classes  ?

• H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
• H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors

Abstract

Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The structure includes a first source/drain region, a second source/drain region disposed adjacent the first source/drain region along a first direction, a third source drain region, a fourth source/drain region disposed adjacent the third source/drain region along the first direction, a first dielectric layer having a first end and a second end opposite the first end, a conductive contact disposed between the first and third source/drain regions and between the second and fourth source/drain regions, and the conductive contact is disposed in the first dielectric layer. The structure further includes a conductive feature disposed in the first dielectric layer, and the conductive feature is electrically connected to the conductive contact.

IPC Classes  ?

• H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/40 - Electrodes
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/45 - Ohmic electrodes
• H01L 29/66 - Types of semiconductor device
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 29/786 - Thin-film transistors

Abstract

A method of testing a circuit structure includes applying a voltage to a first testing site, wherein the testing site is electrically connected to a conductive line which traces a perimeter of a chip, and the chip is between an interposer and the conductive line. The method further includes measuring a current at a second testing site to determine an integrity of the conductive line, wherein the interposer is between the first testing site and the second testing site.

IPC Classes  ?

• G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
• H01L 21/66 - Testing or measuring during manufacture or treatment
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/12 - Mountings, e.g. non-detachable insulating substrates
• H01L 23/498 - Leads on insulating substrates

Abstract

Conductive vias, semiconductor devices with conductive vias, and methods for fabricating semiconductor devices are provided. A conductive via includes a first end and a second end; a first portion adjacent to the first end; a second portion adjacent to the second; and a middle portion located between the first portion and the second portion, wherein the conductive via is comprised of metal grains, the metal grains in the first portion have a first grain size; the metal grains in the second portion have a second grain size; the metal grains in the middle portion have a third grain size; the first grain size is greater than the third grain size; and the second grain size is greater than the third grain size.

IPC Classes  ?

• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials

Abstract

A method includes: generating first specification data of a semiconductor device; performing, to the first specification data, a first evaluation operation corresponding to a first physical feature to the first specification data, to generate first parameters; performing, to the first specification data, a second evaluation operation corresponding to a second physical feature different from the first physical feature, to generate second parameters; comparing the first parameters and the second parameters with preset parameters; and when the first parameters and the second parameters meet the preset parameters, manufacturing the semiconductor device according to the first specification data.

IPC Classes  ?

• G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
• G06F 30/20 - Design optimisation, verification or simulation
• G06F 119/06 - Power analysis or power optimisation

Abstract

A method and system for optimizing scan speed of a lithography scanner. A process design layout corresponding to a plurality of rows of fields to be formed on an associated wafer is received and a default machine constant of the lithography scanner is determined. Each of the plurality of rows is then identified corresponding to the received process design layout. A scan speed for each determined type of row and the determined default machine constant is then determined. The associated wafer is then processed utilizing the determined scan speed for each of the plurality of rows in accordance with the process design layout.

IPC Classes  ?

• G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor

Abstract

An optical package structure is provided. The optical package structure includes a photonic integrated circuit die, an electronic integrated circuit die, an oxide layer, and a silicon carrier. The photonic integrated circuit die includes a coupler. The electronic integrated circuit die is bonded to the photonic integrated circuit die. The oxide layer is adjacent to the electronic integrated circuit die. The silicon carrier includes a first part over the electronic integrated circuit die and a second part over the oxide layer. A trench is formed in the second part of the silicon carrier.

IPC Classes  ?

• G02B 6/42 - Coupling light guides with opto-electronic elements
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
• H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or

Abstract

A FinFET structure with a gate structure having two notch features therein and a method of forming the same is disclosed. The FinFET notch features ensure that sufficient spacing is provided between the gate structure and source/drain regions of the FinFET to avoid inadvertent shorting of the gate structure to the source/drain regions. Gate structures of different sizes (e.g., different gate widths) and of different pattern densities can be provided on a same substrate and avoid inadvertent of shorting the gate to the source/drain regions through application of the notched features.

IPC Classes  ?

• H10D 30/62 - Fin field-effect transistors [FinFET]
• G01N 21/88 - Investigating the presence of flaws, defects or contamination
• H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
• H01L 21/66 - Testing or measuring during manufacture or treatment
• H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
• H10D 30/01 - Manufacture or treatment
• H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
• H10D 64/66 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
• H10D 64/68 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology

Abstract

A method includes: forming a redistribution layer (RDL) comprising metal material over a substrate; forming an oxidation layer of the metal material on sidewalls of the RDL; and depositing a passivation layer over the RDL and the oxidation layer, wherein the oxidation layer is formed between the RDL and the passivation layer; wherein the oxidation layer strengthens bonding between the RDL and the passivation layer to resist hydrogen induced voids from forming. The method may allow for performing a hydrogen plasma annealing treatment without hydrogen-induced voiding in top or bottom corners of the RDL. A device includes: an RDL comprising metal material formed over a substrate; a passivation layer formed over the RDL; and an oxidation layer of the metal material formed on sidewalls of the RDL between the RDL and the passivation layer. The device may be formed without voids in top or bottom corners of the RDL.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or

Abstract

A first wafer having a first portion closer to a first surface and a thicker second portion connected with the first portion and closer to the second surface opposite to the first surface is provided. A second wafer is provided to bond with the first wafer. An edge trimming process is performed to form a trench penetrating through the second wafer and extending beyond the first portion and extending into the second portion. After bonding dies to the second wafer, a filling material is formed over the dies and the first and second wafers, wrapping around and between the dies, covering the first and second wafers, and partially filling the trench. A wafer thinning process is performed to remove the second portion and partially remove the filling material in the trench to level the surface of the thinned first wafer with the surface of the thinned filling material.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement

Abstract

In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a plurality of transistor devices disposed on or within a substrate. A plurality of memory devices are disposed on or within the substrate. A first isolation structure is disposed within the substrate between the plurality of transistor devices and the plurality of memory devices. The first isolation structure has a first upper surface and a second upper surface coupled to the first upper surface by a sidewall disposed therebetween. The first upper surface is vertically above the second upper surface. A dummy gate structure is arranged on the first upper surface.

IPC Classes  ?

• H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
• H01L 21/76 - Making of isolation regions between components
• H01L 21/762 - Dielectric regions
• H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
• H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies

Abstract

A first wafer having a two-dimensional array of first semiconductor dies including arrays of first top metal bonding pads attached to a top surface of a first carrier wafer. A second wafer having a two-dimensional array of second semiconductor dies including arrays of second top metal bonding pads and arrays of second bottom metal bonding pads bonded to the first wafer by performing a first metal-to-metal bonding process in which the arrays of first top metal bonding pads are bonded to the arrays of second bottom metal bonding pads through first intermetallic diffusion. A third wafer having a two-dimensional array of third semiconductor dies including arrays of third bottom metal bonding pads bonded to the second wafer by performing a second metal-to-metal bonding process in which the arrays of second top metal bonding pads are bonded to the arrays of third bottom metal bonding pads through second intermetallic diffusion.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/498 - Leads on insulating substrates
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

The present disclosure provides a method that includes providing a semiconductor structure having a bottom channel region and a top channel region over the bottom channel region; forming a gate dielectric layer over and wrapping around top channels in the top channel region; performing a radical treatment on the dielectric layer in a supercritical fluid; and forming a metal gate electrode on the dielectric layer.

IPC Classes  ?

• H01L 29/66 - Types of semiconductor device
• H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
• H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
• H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched

Abstract

An example embodiment of the present disclosure involves a method for semiconductor device fabrication. The method comprises providing a structure that includes a conductive component and an interlayer dielectric (ILD) that includes silicon and surrounds the conductive component, and forming, over the conductive component and the ILD, an etch stop layer (ESL) that includes metal oxide. The ESL includes a first portion in contact with the conductive component and a second portion in contact with the ILD. The method further comprises baking the ESL to transform the metal oxide located in the second portion of the ESL into metal silicon oxide, and selectively etching the ESL so as to remove the first portion of the ESL but not the second portion of the ESL.

IPC Classes  ?

• H01L 21/311 - Etching the insulating layers
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
• H01L 21/321 - After-treatment
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 23/528 - Layout of the interconnection structure
• H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology

Abstract

An embodiment photonic device may include a first photonic interconnect formed over a first horizontal plane, a second photonic interconnect formed over a second horizontal plane that is vertically displaced relative to the first horizontal plane, and a photonic coupler connected to the first photonic interconnect and the second photonic interconnect. The photonic coupler may be configured such that first photonic signals that are incident on the photonic coupler from the first photonic interconnect are directed by the photonic coupler into the second photonic interconnect, and second photonic signals that are incident on the photonic coupler from the second photonic interconnect are directed by the photonic coupler into the first photonic interconnect. The photonic coupler may further include a photonic via that connects the first photonic interconnect to the second photonic interconnect and that allows photonic signals to propagate between the first photonic interconnect and the second photonic interconnect.

IPC Classes  ?

• G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
• G02B 6/122 - Basic optical elements, e.g. light-guiding paths

Abstract

A method for fabricating a magnetic tunneling junction (MTJ) structure is described. A first dielectric layer is deposited on a bottom electrode and partially etched through to form a first via opening having straight sidewalls, then etched all the way through to the bottom electrode to form a second via opening having tapered sidewalls. A metal layer is deposited in the second via opening and planarized to the level of the first dielectric layer. The remaining first dielectric layer is removed leaving an electrode plug on the bottom electrode. MTJ stacks are deposited on the electrode plug and on the bottom electrode wherein the MTJ stacks are discontinuous. A second dielectric layer is deposited over the MTJ stacks and polished to expose a top surface of the MTJ stack on the electrode plug. A top electrode layer is deposited to complete the MTJ structure.

IPC Classes  ?

• H10N 50/80 - Constructional details
• B82Y 25/00 - Nanomagnetism, e.g. magnetoimpedance, anisotropic magnetoresistance, giant magnetoresistance or tunneling magnetoresistance
• H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• H10N 50/01 - Manufacture or treatment
• H10N 50/85 - Materials of the active region

Abstract

Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.

IPC Classes  ?

• H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
• H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
• H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
• H10D 30/01 - Manufacture or treatment
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 64/66 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes

Abstract

A semiconductor device structure and methods of forming the same are described. The method includes forming a fin structure from a substrate, depositing a first semiconductor material on a first semiconductor layer of the fin structure, depositing a second semiconductor material on the first semiconductor material, depositing an interlayer dielectric layer over the second semiconductor material, forming an opening in the interlayer dielectric layer to expose the second semiconductor material, performing a first implantation process to form an amorphous region in the second semiconductor material and to implant a first species in the amorphous region, and performing a second implantation process to implant a second species in the amorphous region. The second species includes fluorine, nitrogen, or carbon. The method further includes performing an annealing process to recrystallize the amorphous region.

IPC Classes  ?

• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET

Abstract

A memory circuit includes first and second memory cells aligned along a first active structure including a first shared source portion of the first and second memory cells, third and fourth memory cells aligned along a second active structure including a second shared source portion of the third and fourth memory cells, a first bit line overlying the first and second memory cells, a second bit line overlying the third and fourth memory cells, a reference voltage line positioned in a same metal layer as the first and second bit lines, and a first conductive structure electrically connected to each of the first and second shared source portions and the reference voltage line. The first conductive structure is positioned in a metal layer different from the same metal layer.

IPC Classes  ?

• H10D 89/10 - Integrated device layouts
• G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 23/528 - Layout of the interconnection structure
• H10B 20/00 - Read-only memory [ROM] devices

Abstract

In one exemplary aspect, the present disclosure is directed to a method for lithography patterning. The method includes providing a substrate and forming a target layer over the substrate. A patterning layer is formed by depositing a first layer having an organic composition; depositing a second layer including over 50 atomic percent of silicon; and depositing a photosensitive layer on the second layer. In some implementations, the second layer is deposited by ALD, CVD, or PVD processes.

IPC Classes  ?

• H01L 21/308 - Chemical or electrical treatment, e.g. electrolytic etching using masks
• H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
• H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
• H01L 21/311 - Etching the insulating layers

Abstract

A package includes a package substrate including an insulating layer having a trench and a package component bonded to the package substrate. The package component includes a redistribution structure, an optical die bonded to the redistribution structure, the optical die including an edge coupler near a first sidewall of the optical die, a dam structure on the redistribution structure near the first sidewall of the optical die, a first underfill between the optical die and the redistribution structure, an encapsulant encapsulating the optical die, and an optical glue in physical contact with the first sidewall of the optical die. The first underfill does not extend along the first sidewall of the optical die. The optical glue separates the dam structure from the encapsulant. The package further includes a second underfill between the insulating layer and the package component. The second underfill is partially disposed in the trench.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• G02B 6/42 - Coupling light guides with opto-electronic elements
• H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
• H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers

Abstract

The present disclosure relates to an apparatus and a method for wafer cleaning. The apparatus can include a wafer holder configured to hold a wafer; a cleaning nozzle configured to dispense a cleaning fluid onto a first surface (e.g., front surface) of the wafer; and a cleaning brush configured to clean a second surface (e.g., back surface) of the wafer. Using the cleaning fluid, the cleaning brush can clean the second surface of the wafer with a scrubbing motion and ultrasonic vibration.

IPC Classes  ?

• B08B 7/04 - Cleaning by methods not provided for in a single other subclass or a single group in this subclass by a combination of operations
• A46B 13/02 - Brushes with driven brush bodies power-driven
• B08B 1/12 - Brushes
• B08B 1/20 - Cleaning of moving articles, e.g. of moving webs or of objects on a conveyor
• B08B 1/32 - Cleaning by methods involving the use of tools by movement of cleaning members over a surface using rotary cleaning members
• B08B 3/04 - Cleaning involving contact with liquid
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

Abstract

A semiconductor structure includes a substrate, a device layer over the substrate, an interconnect structure over the device layer, and a first plurality of through vias and a second plurality of through vias extending through the substrate, the device layer, and the interconnect structure. The device layer includes first and second device regions. From a top view, the first device region has a first side facing and spaced apart from a second side of the second device region. From the top view, the first plurality of through vias are disposed along a third side of the first device region opposite to the first side of the first device region, the second plurality of through vias are disposed along a fourth side of the second device region opposite to the second side of the second device region. Each through via has a racetrack shape from the top view.

IPC Classes  ?

• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or

Abstract

Embodiments of the present disclosure relate to a method of forming a low-k dielectric material, for example, a low-k gate spacer layer in a FinFET device. The low-k dielectric material may be formed using a precursor having a general chemical structure comprising at least one carbon atom bonded between two silicon atoms. A target k-value of the dielectric material may be achieved by controlling carbon concentration in the dielectric material.

IPC Classes  ?

• H10D 30/62 - Fin field-effect transistors [FinFET]
• H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
• H10D 30/01 - Manufacture or treatment
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]

Abstract

A semiconductor package includes a redistribution structure, first and second integrated circuit dies that are connected to a first side of the redistribution structure, and third and fourth integrated circuit dies that are connected on a second side, opposite to the first side, of the redistribution structure. An optical bridge die is connected between the third and fourth integrated circuit dies, to the second side of the redistribution structure, which is configured such that the first and second integrated circuit dies optically communicate through the optical bridge die.

IPC Classes  ?

• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement