Abstract

In order to prevent long down-time that occurs with unexpected material depletion, an inline tin stream monitor (ITSM) system precisely measures the tin amount introduced by an in-line refill system and precisely estimates remaining runtime by measuring pressure level changes before and after in-line refill.

IPC Classes  ?

• G03F 7/20 - ExposureApparatus therefor

Abstract

A behavior recognition device for recognizing behaviors of a semiconductor manufacturing apparatus includes a storage device and a control unit. The storage device is configured to store log data of the semiconductor manufacturing apparatus. The control unit is cooperatively connected to the storage device, and configured to build a transition state model based on the log data to analyze behaviors related to wafer transfer sequences and manufacturing operations of the semiconductor manufacturing apparatus.

IPC Classes  ?

• G05B 19/4099 - Surface or curve machining, making 3D objects, e.g. desktop manufacturing
• H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

Abstract

A semiconductor device is disclosed. The semiconductor device includes a first substrate. The first substrate includes a first dielectric layer, and a vertical conductive area, where the vertical conductive area includes at least two vertical conductive structures extending through the first dielectric layer, where each line segment of a non-square quadrilateral contacts at least one of the at least two vertical conductive structures. The vertical conductive area also includes a continuous conductive guard ring structure in the first dielectric layer, where the continuous conductive guard ring structure surrounds the at least two vertical conductive structures. The semiconductor device also includes a second substrate, including a first conductor, and a second conductor, where the first conductor of the second substrate is electrically connected to at least one of the at least two vertical conductive structures of the first substrate.

IPC Classes  ?

• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

Field effect transistors and method of making. The field effect transistor includes a pair of active regions over a channel layer, a channel region formed in the channel layer and located between the pair of active regions, a pair of contact via structures electrically connected to the pair of active regions, and a lower passivation protection layer. The lower passivation protection layer extends over a top surface of an end portion of the channel layer, a side surface of the end portion of the channel layer, and a side surface of a gate dielectric layer disposed under the channel layer.

IPC Classes  ?

• H10D 30/67 - Thin-film transistors [TFT]
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H10D 64/01 - Manufacture or treatment
• H10D 99/00 - Subject matter not provided for in other groups of this subclass

Abstract

A method of manufacturing a semiconductor device includes applying a polymer mixture over a substrate, exposing and developing at least a portion of the polymer mixture to form a developed dielectric, and curing the developed dielectric to form a dielectric layer. The polymer mixture includes a polymer precursor, a photosensitizer, and a solvent. The polymer precursor may be a polyamic acid ester.

IPC Classes  ?

• G03F 7/031 - Organic compounds not covered by group
• C08G 73/10 - PolyimidesPolyester-imidesPolyamide-imidesPolyamide acids or similar polyimide precursors
• G03F 7/038 - Macromolecular compounds which are rendered insoluble or differentially wettable
• G03F 7/039 - Macromolecular compounds which are photodegradable, e.g. positive electron resists
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or

Abstract

The present disclosure relates to a memory device that includes a bottom electrode, a data storage structure overlying the bottom electrode, a top electrode overlying the data storage structure, a mask overlying the top electrode, and a sidewall spacer extending alongside the data storage structure and alongside the mask. The sidewall spacer extends to a height above an upper surface of the mask. A top electrode via (TEVA) extends through the mask to the top electrode and extends into the sidewall spacer, where a first curved portion of the sidewall spacer extends along a top surface of the mask and is spaced apart from the TEVA.

IPC Classes  ?

• H10N 70/00 - Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
• H10N 70/20 - Multistable switching devices, e.g. memristors

Abstract

A semiconductor device includes a semiconductor die. The semiconductor die includes a substrate including at least one active component, an interconnect disposed over and electrically coupled to the at least one active component, and at least one first thermal control element disposed inside the interconnect and thermally coupled to the at least one active component. The at least one active component is surrounded by the at least one first thermal control element in a vertical projection along a stacking direction of the substrate and the interconnect.

IPC Classes  ?

• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices

Abstract

A method for manufacturing a semiconductor device is provided. A gate oxide layer is formed over a high-voltage N-type well region, an N-type well region and a P-type well region. The gate oxide layer includes a first layer portion and a second layer portion. The first and second layer portions have different thicknesses. A main gate is formed on the first layer portion and the second layer portion. At least one split gate is formed on the second layer portion, and the main gate and the split gate extend along an interface between the high-voltage N-type well region and the P-type well region. An inter-level dielectric (ILD) layer is formed over the main gate and the split gate. A plurality of connecting features penetrating the ILD layer to contact the main gate and the split gate are formed. An electrode is formed to contact the connecting features.

IPC Classes  ?

• H01L 29/66 - Types of semiconductor device
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

A memory device is provided. The memory device includes a plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns. A first column of the plurality of columns of the matrix includes a first plurality of memory cells of the plurality of memory cells, a first pair of bit lines connected to each of the first plurality of bit cells, and a second pair of bit lines connectable to the first pair of bit lines through a plurality of switches.

IPC Classes  ?

• G11C 11/419 - Read-write [R-W] circuits
• G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

A method of an interconnect structure includes the following steps. A first etching stop layer, a first dielectric layer, a second etching stop layer, an insert layer and a second dielectric layer are deposited over the second etching stop layer are deposited over a substrate. The second dielectric layer, the insert layer, the second etching stop layer, the first dielectric layer and the first etching stop layer are patterned thereby forming a trench opening and a via hole. A conductive feature is filled in the trench opening and the via hole thereby forming a conductive line in the second dielectric layer and the insert layer and a via in the first etching stop layer and the first dielectric layer. A material of the insert layer is different from the second dielectric layer and the second etching stop layer.

IPC Classes  ?

• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/528 - Layout of the interconnection structure

Abstract

Disclosed herein are related to operating a memory system including memory banks and buffers. Each buffer may perform a write process to write data to a corresponding memory bank. In one aspect, the memory system includes a buffer controller including a queue register, a first pointer register, a second pointer register, and a queue controller. In one aspect, the queue register includes entries, where each entry may store an address of a corresponding memory bank. The first pointer register may indicate a first entry storing an address of a memory bank, on which the write process is predicted to be completed next. The second pointer register may indicate a second entry to be updated. The queue controller may configure the queue register according to the first pointer register and the second pointer register, and configure one or more buffers to perform the write process, according to the entries.

IPC Classes  ?

• G11C 7/22 - Read-write [R-W] timing or clocking circuitsRead-write [R-W] control signal generators or management
• G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

A method includes: forming a bottom electrode over a substrate; depositing a first seed layer over the bottom electrode; performing a first surface treatment on the first seed layer to convert a crystal phase of the first seed layer; depositing a dielectric layer over the bottom electrode adjacent to the first seed layer; depositing an upper layer over the dielectric layer; and performing a thermal operation on the dielectric layer subsequent to the first surface treatment to thereby convert the dielectric layer into a ferroelectric layer.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H10B 51/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region

Abstract

In some aspects of the present disclosure, a memory array structure is disclosed. In some embodiments, the memory array structure includes a word array. In some embodiments, the word array stores an N-bit word. In some embodiments, the word array includes a plurality of first memory structures and a plurality of second memory structures. In some embodiments, each first memory structure includes a first transistor and a first memory element. In some embodiments, each second memory structure includes a second transistor and a plurality of second memory elements, each second memory element includes a first end and a second end, the first end of each second memory element is coupled to a corresponding bit line, and the second end of each second memory element is coupled to a first end of the second transistor.

IPC Classes  ?

• G11C 7/16 - Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters
• G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
• H03M 1/12 - Analogue/digital converters

Abstract

A semiconductor package and a method of forming the same are provided. The semiconductor package includes a package substrate and a semiconductor device mounted on the surface of the package substrate. A first ring is disposed over the surface of the package substrate and surrounds the semiconductor device. A second ring is disposed over the top surface of the first ring. Also, a protruding part and a matching recessed part are formed on the top surface of the first ring and the bottom surface of the second ring, respectively. The protruding part extends into and engages with the recessed part to connect the first ring and the second ring. An adhesive layer is disposed between the surface of the package substrate and the bottom surface of the first ring for attaching the first ring and the overlying second ring to the package substrate.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/16 - Fillings or auxiliary members in containers, e.g. centering rings
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for

Abstract

A semiconductor device including a semiconductor substrate and an interconnect structure is provided. The semiconductor substrate includes a transistor, wherein the transistor has a source region and a drain region. The interconnect structure is disposed over the semiconductor substrate, wherein the interconnect structure includes a plurality of interlayer dielectric layers, a first via and a memory cell. The plurality of interlayer dielectric layers are over the semiconductor substrate. The first via is embedded in at least two interlayer dielectric layers among the plurality of interlayer dielectric layers and electrically connected with the drain region of the transistor. The memory cell is disposed over the at least two interlayer dielectric layers among the plurality of interlayer dielectric layers and electrically connected with the first via.

IPC Classes  ?

• H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 23/528 - Layout of the interconnection structure
• H10N 50/01 - Manufacture or treatment
• H10N 50/80 - Constructional details

Abstract

An integrated circuit includes a Schmitt trigger circuit. The Schmitt trigger circuit includes a first, second, third and fourth transistor, a first and second feedback transistor, and a first and second circuit. The first transistor is connected between a first node and a first voltage supply having a first supply voltage. The fourth transistor is connected between the third transistor and a second voltage supply having a second supply voltage. The first circuit is connected to a second node, the first and second voltage supply, and configured to supply the second supply voltage to the second node in response to being enabled. The second feedback transistor is connected to a third node, and a fourth node. The second circuit is connected to the fourth node, the first and second voltage supply, and configured to supply the first supply voltage to the fourth node in response to being enabled.

IPC Classes  ?

• H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
• H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]

Abstract

Semiconductor devices and methods which utilize a treatment process of a bottom anti-reflective layer are provided. The treatment process may be a physical treatment process in which material is added in order to fill holes and pores within the material of the bottom anti-reflective layer or else the treatment process may be a chemical treatment process in which a chemical reaction is used to form a protective layer. By treating the bottom anti-reflective layer the diffusion of subsequently applied chemicals is reduced or eliminated, thereby helping to prevent defects that arise from such diffusion.

IPC Classes  ?

• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
• H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
• H10D 84/01 - Manufacture or treatment

Abstract

Improved inner spacers for semiconductor devices and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a substrate; a plurality of semiconductor channel structures over the substrate; a gate structure over the semiconductor channel structures, the gate structure extending between adjacent ones of the semiconductor channel structures; a source/drain region adjacent of the gate structure, the source/drain region contacting the semiconductor channel structures; and an inner spacer interposed between the source/drain region and the gate structure, the inner spacer including a first inner spacer layer contacting the gate structure and the source/drain region, the first inner spacer layer including silicon and nitrogen; and a second inner spacer layer contacting the first inner spacer layer and the source/drain region, the second inner spacer layer including silicon, oxygen, and nitrogen, the second inner spacer layer having a lower dielectric constant than the first inner spacer layer.

IPC Classes  ?

• H10D 64/01 - Manufacture or treatment
• H10D 30/67 - Thin-film transistors [TFT]
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]

Abstract

A method for fabricating magnetoresistive random-access memory cells (MRAM) on a substrate is provided. The substrate is formed with a magnetic tunneling junction (MTJ) layer thereon. When the MTJ layer is etched to form the MRAM cells, there may be metal components deposited on a surface of the MRAM cells and between the MRAM cells. The metal components are then removed by chemical reaction. However, the removal of the metal components may form extra substances on the substrate. A further etching process is then performed to remove the extra substances by physical etching.

IPC Classes  ?

• H10N 50/01 - Manufacture or treatment
• H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• H10N 50/80 - Constructional details

Abstract

A circuit includes a signal source configured to provide a test signal to at least one of a plurality of conductive structures based on a decoded signal, a plurality of switches configured to connect the signal source to the plurality of conductive structures, respectively, based on the decoded signal, a multiplexer configured to select a test voltage present on the at least one conductive structure, based on the decoded signal, and an analog-to-digital converter (ADC) configured to provide a digital output based on comparing the test voltage with a reference voltage.

IPC Classes  ?

• G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

Abstract

A manufacturing method of a semiconductor package includes the following steps. A semiconductor device is attached to a carrier by an adhesive layer on the carrier. The semiconductor device is encapsulated by an encapsulating material. A redistribution structure is provided over the semiconductor device and the encapsulating material. The carrier is removed. The adhesive layer is partially removed by anisotropic etching process to form an adhesive residue, wherein the adhesive residue at least reveals a back surface of the semiconductor device and at least partially covers the encapsulating material.

IPC Classes  ?

• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/367 - Cooling facilitated by shape of device
• H01L 23/498 - Leads on insulating substrates

Abstract

A data retention circuit includes a flip-flop circuit including a master latch coupled to a slave latch, wherein the slave latch includes a first input terminal and a first output terminal, and a series combination of a retention latch and a level shifter coupled between the first input terminal and the first output terminal. The slave latch is configured to be selectively coupled to the series combination through a first transmission gate responsive to a restore signal.

IPC Classes  ?

• H03K 3/037 - Bistable circuits
• G06F 1/3237 - Power saving characterised by the action undertaken by disabling clock generation or distribution
• H03K 3/356 - Bistable circuits
• H03K 19/00 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits

Abstract

Some embodiments relate to an integrated circuit device including a semiconductor layer, a pixel including a photodetector in the semiconductor layer, a conductive structure electrically coupled to the pixel on a first side of the semiconductor layer, a plurality of light diffusors overlying the photodetector on a second side of the semiconductor layer opposite the first side, and a light-focusing structure overlying the plurality of light diffusors. The light-focusing structure includes a plurality of light-focusing portions. Each of the plurality of light-focusing portions overlies, and is configured to focus light on, a corresponding one or more of the plurality of light diffusors.

IPC Classes  ?

• H01L 27/146 - Imager structures

Abstract

A memory circuit includes a non-volatile memory cell, a comparator and a detection circuit that includes a flip-flop. A first input terminal of the comparator is coupled to the non-volatile memory cell. A first output terminal of the comparator is configured to output a first output signal. The detection circuit is configured to latch the first output signal and disrupt a current path between the non-volatile memory cell and the detection circuit. A first input terminal of the flip-flop is coupled to the first output terminal of the comparator. A second input terminal of the flip-flop is configured to receive a first data signal. A third input terminal of the flip-flop is configured to receive a first reset signal. A first output terminal of the flip-flop is configured to generate a second output signal. A second output terminal of the flip-flop is configured to generate an inverted second output signal.

IPC Classes  ?

• G11C 17/18 - Auxiliary circuits, e.g. for writing into memory
• G11C 17/16 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links

Abstract

A semiconductor device structure is provided. The semiconductor device structure includes first nanostructures and second nanostructures formed over a substrate, and a first gate structure formed over the first nanostructures. The semiconductor device structure includes a second gate structure formed over the second nanostructures. The semiconductor device structure includes a first isolation layer between the first gate structure and the second gate structure. The first isolation layer has a first sidewall surface, a first portion and a second portion, the first sidewall surface of the first isolation layer is sloped, and a width of the first portion is greater than a width of the second portion.

IPC Classes  ?

• H10D 30/62 - Fin field-effect transistors [FinFET]
• H10D 30/01 - Manufacture or treatment
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies

Abstract

A method of forming a semiconductor device includes mounting a bottom wafer on a bottom chuck and mounting a top wafer on a top chuck, wherein one of the bottom chuck and the top chuck has a gasket. The top chuck is moved towards the bottom chuck. The gasket forms a sealed region between the bottom chuck and the top chuck around the top wafer and the bottom wafer. An ambient pressure in the sealed region is adjusted. The top wafer is bonded to the bottom wafer.

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

Abstract

A coolant system including one or more cooling fin assemblies that are movably coupled to a coolant tank. Each one of the one or more cooling fin assemblies has a first position (i.e., closed position) in which the one or more cooling fin assemblies are slightly tilted with respect to inner sides of the coolant tank. Each one of the one or more cooling fin assemblies has a second position (i.e., opened position) in which the one or more cooling fin assemblies are tiled by a greater amount than the first position exposing an access opening of the coolant tank such that a transfer device may access a coolant cavity within the coolant tank. Each one of the one or more cooling fin assemblies includes a cooling fin structure and a porous drip tray coupled to the cooling fin structure.

IPC Classes  ?

• H05K 7/20 - Modifications to facilitate cooling, ventilating, or heating

Abstract

A method includes forming Complementary Field-Effect Transistors including a lower transistor comprising a lower source/drain region, and an upper transistor including an upper source/drain region. An upper dielectric layer over the upper source/drain region and a lower dielectric layer under the upper source/drain region are etched to form an opening. A sidewall of the upper source/drain region and a top surface of the lower source/drain region are exposed to the opening. An epitaxy process is performed to form a first semiconductor layer on the sidewall of the upper source/drain region, and a second semiconductor layer on the top surface of the lower source/drain region. The first semiconductor layer is then removed, a contact plug is formed in the opening to electrically connects the upper source/drain region to the second semiconductor layer and the lower source/drain region.

IPC Classes  ?

• H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
• H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/40 - Electrodes
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/45 - Ohmic electrodes
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 29/786 - Thin-film transistors

Abstract

A pellicle for an EUV photo mask includes a first layer; a second layer; and a main layer disposed between the first layer and second layer and including a plurality of nanotubes. At least one of the first layer or the second layer includes a two-dimensional material in which one or more two-dimensional layers are stacked. In one or more of the foregoing and following embodiments, the first layer includes a first two-dimensional material and the second layer includes a second two-dimensional material.

IPC Classes  ?

• G03F 1/62 - Pellicles or pellicle assemblies, e.g. having membrane on support framePreparation thereof
• G03F 1/24 - Reflection masksPreparation thereof
• G03F 1/64 - Pellicles or pellicle assemblies, e.g. having membrane on support framePreparation thereof characterised by the frames, e.g. structure or material thereof

Abstract

In some embodiments, the present application provides an integrated chip (IC). The IC includes a metal-insulator-metal (MIM) device disposed over a substrate. The MIM device includes a plurality of conductive plates that are spaced from one another. The MIM device further includes a first conductive plug structure that is electrically coupled to a first conductive plate and to a third conductive plate of the plurality of conductive plates. A first plurality of insulative segments electrically isolate a second conductive plate and a fourth conductive plate from the first conductive plug structure. The MIM device further includes a second conductive plug structure that is electrically coupled to the second conductive plate and to the fourth conductive plate of the plurality of conductive plates. A second plurality of insulative segments electrically isolate the first conductive plate and the third conductive plate from the second conductive plug structure.

IPC Classes  ?

• H10D 1/68 - Capacitors having no potential barriers
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 23/528 - Layout of the interconnection structure

Abstract

Depositing gallium nitride and carbon (GaN:C) (e.g., in the form of composite layers) when forming a gallium nitride drain of a transistor provides a buffer between the gallium nitride of the drain and silicon of a substrate in which the drain is formed. As a result, gaps and other defects caused by lattice mismatch are reduced, which improves electrical performance of the drain. Additionally, current leakage into the substrate is reduced, which further improves electrical performance of the drain. Additionally, or alternatively, implanting silicon in an aluminum nitride (AlN) liner for a gallium nitride drain reduces contact resistance at an interface between the gallium nitride and the silicon. As a result, electrical performance of the transistor is improved.

IPC Classes  ?

• H10D 62/13 - Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/223 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regionsRedistribution of impurity materials, e.g. without introduction or removal of further dopant using diffusion into, or out of, a solid from or into a gaseous phase
• H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
• H10D 62/854 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs further characterised by the dopants
• H10F 30/28 - Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices being characterised by field-effect operation, e.g. junction field-effect phototransistors

Abstract

A semiconductor device includes a substrate, an interconnect, and a vertical connection structure. The substrate has a front-side and a back-side. The interconnect is disposed over the front-side of the substrate. The vertical connection structure is embedded in the interconnect and penetrates through the substrate, and the vertical connection structure includes a first portion and a second portion. The first portion is embedded inside the interconnect and further extends into the substrate. The second portion is disposed in the substrate and extends from the back-side to the first portion, and the second portion is in contact with the first portion. An aspect ratio of the second portion is less than an aspect ratio of the first portion.

IPC Classes  ?

• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/498 - Leads on insulating substrates
• H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for

Abstract

Circuits, systems, and methods are described herein for generating a boost voltage for a write operation of a memory cell. In one embodiment, a boost circuit includes a first inverter and a second inverter, each configured to invert a write signal. The boost circuit also includes a transistor and a capacitor. The transistor is coupled to an output of the first inverter. The transistor is configured to charge a capacitor based on the write signal and provide a supply voltage to a write driver. The capacitor is coupled to an output of the second inverter. The capacitor is configured to generate and provide a delta voltage to the write driver.

IPC Classes  ?

• G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• G11C 5/02 - Disposition of storage elements, e.g. in the form of a matrix array
• G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
• G11C 11/4094 - Bit-line management or control circuits
• G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches

Abstract

A package assembly includes an interposer module on a package substrate, a liquid alloy thermal interface material (TIM) on the interposer module, a seal ring surrounding the liquid alloy TIM, and a package lid on the liquid alloy TIM and seal ring, wherein the seal ring, interposer module and package lid seal the liquid alloy TIM.

IPC Classes  ?

• H01L 23/42 - Fillings or auxiliary members in containers selected or arranged to facilitate heating or cooling
• H01L 21/52 - Mounting semiconductor bodies in containers
• H01L 23/053 - ContainersSeals characterised by the shape the container being a hollow construction and having an insulating base as a mounting for the semiconductor body
• H01L 23/10 - ContainersSeals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

An LDMOS device includes a gate structure, a multi-layered dielectric structure and at least a conductive field plate. The gate structure is disposed over a substrate and between a source region and a drain region. The multi-layered dielectric structure is disposed over the gate structure. The multi-layered dielectric structure includes a first dielectric layer in contact with the gate structure, and a second dielectric layer over the first dielectric layer. A thickness of the second dielectric layer is equal to or greater than a thickness of the first dielectric layer. The conductive field plate is disposed over the multi-layered dielectric structure.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/40 - Electrodes
• H01L 29/66 - Types of semiconductor device

Abstract

In some aspects of the present disclosure, a memory array includes: a plurality of memory cells; and a plurality of logic gates, each of the plurality of logic gates having a first input, a second input, and an output gating a corresponding one of the plurality of memory cells, wherein the first input of each of the plurality of logic gates of a first subset is coupled to a first bit select line.

IPC Classes  ?

• G11C 17/16 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
• G11C 17/18 - Auxiliary circuits, e.g. for writing into memory

Abstract

A dummy gate structure may be formed for a semiconductor device. The dummy gate structure may be formed from an amorphous polysilicon layer. The amorphous polysilicon layer may be deposited in a blanket deposition operation. An annealing operation is performed for the semiconductor device to remove voids, seams, and/or other defects from the amorphous polysilicon layer. The annealing operation may cause the amorphous polysilicon layer to crystallize, thereby resulting in the amorphous polysilicon layer transitioning into a crystallized polysilicon layer. A dual radio frequency (RF) source etch technique may be performed to increase the directionality of ions and radicals in a plasma that is used to etch the crystallized polysilicon layer to form the dummy gate structure. The increased directionality of the ions increases the effectiveness of the ions in etching through the different crystal grain boundaries which increases the etch rate uniformity across the crystallized polysilicon layer.

IPC Classes  ?

• H10D 64/01 - Manufacture or treatment
• H10D 30/01 - Manufacture or treatment

Abstract

Semiconductor devices, integrated circuits and methods of forming the same are provided. In one embodiment, a semiconductor device includes a metal-insulator-metal structure which includes a bottom conductor plate layer including a first opening and a second opening, a first dielectric layer over the bottom conductor plate layer, a middle conductor plate layer over the first dielectric layer and including a third opening, a first dummy plate disposed within the third opening, and a fourth opening, a second dielectric layer over the middle conductor plate layer, and a top conductor plate layer over the second dielectric layer and including a fifth opening, a second dummy plate disposed within the fifth opening, a sixth opening, and a third dummy plate disposed within the sixth opening. The first opening, the first dummy plate, and the second dummy plate are vertically aligned.

IPC Classes  ?

• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
• H01L 21/3105 - After-treatment
• H01L 21/311 - Etching the insulating layers
• H01L 21/321 - After-treatment
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/528 - Layout of the interconnection structure
• H10D 1/00 - Resistors, capacitors or inductors
• H10D 1/66 - Conductor-insulator-semiconductor capacitors, e.g. MOS capacitors
• H10D 1/68 - Capacitors having no potential barriers

Abstract

The present disclosure relates to a semiconductor structure. The semiconductor structure includes a conductive gate arranged over a substrate. A first lower source/drain and a second lower source/drain are disposed on opposing sides of the conductive gate. A dielectric is arranged over the first lower source/drain and the second lower source/drain and on the opposing sides of the conductive gate. A first upper source/drain and a second upper source/drain are disposed on the opposing sides of the conductive gate and vertically above the dielectric. A first channel structure is arranged laterally between the conductive gate and both the first lower source/drain and the first upper source/drain. A second channel structure is arranged laterally between the conductive gate and both the second lower source/drain and the second upper source/drain.

IPC Classes  ?

• H10D 30/67 - Thin-film transistors [TFT]
• H10D 86/01 - Manufacture or treatment
• H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
• H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
• H10D 99/00 - Subject matter not provided for in other groups of this subclass

Abstract

An integrated circuit includes a first memory cell array configured to store a first set of data, a second memory cell array configured to store a first inverted set of check bits, a first set of inverters and an error correction code (ECC) decoder. The first set of inverters is configured to generate a second set of check bits in response to a third set of check bits inverted from the second set of check bits. The third set of check bits corresponds to the first inverted set of check bits stored in the second memory cell array. The ECC decoder is configured to detect or correct an error in a second set of data or the second set of check bits thereby generating a set of output data and a been-attacked signal. The been-attacked signal indicating a reset attack by a user.

IPC Classes  ?

• G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
• G06F 21/55 - Detecting local intrusion or implementing counter-measures
• G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
• G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or

Abstract

A method (of manufacturing a semiconductor device) includes migrating a circuit design from a first netlist corresponding with a first semiconductor process technology (SPT) to a second netlist corresponding with a second SPT, the migrating including: expanding a first version of the first netlist and a first precursor of the second netlist correspondingly to form a second version of the first netlist and a second precursor of the second netlist; before conducting (A) placement and routing (P&R) of a layout diagram corresponding to the second netlist or (B) a static timing analysis of the layout diagram; performing a logic equivalence check (LEC) between the second version of the first netlist and the second precursor of the second netlist, thereby identifying migration errors, and revising the second precursor of the second netlist to reduce the migration errors, thereby resulting in a third precursor of the second netlist.

IPC Classes  ?

• G06F 30/323 - Translation or migration, e.g. logic to logic, hardware description language [HDL] translation or netlist translation
• G03F 1/70 - Adapting basic layout or design of masks to lithographic process requirements, e.g. second iteration correction of mask patterns for imaging
• G06F 30/3323 - Design verification, e.g. functional simulation or model checking using formal methods, e.g. equivalence checking or property checking
• G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
• G06F 30/394 - Routing
• G06F 119/12 - Timing analysis or timing optimisation

Abstract

A semiconductor device according to the present disclosure includes a dielectric fin having a helmet layer, a gate structure disposed over a first portion of the helmet layer and extending along a direction, and a dielectric layer adjacent the gate structure and disposed over a second portion of the helmet layer. A width of the first portion along the direction is greater than a width of the second portion along the direction.

IPC Classes  ?

• H10D 30/62 - Fin field-effect transistors [FinFET]
• H10D 30/01 - Manufacture or treatment
• H10D 30/67 - Thin-film transistors [TFT]
• H10D 64/01 - Manufacture or treatment

Abstract

An optical waveguide includes a first portion, a second portion, and a third portion. The first portion includes an input port configured to allow an input optical signal of a first propagation direction entering therefrom. The second portion includes a taper waveguide portion configured to expanding the input optical signal and a rectangular waveguide portion configure to split the input optical signal, where the rectangular waveguide portion is connected to the taper waveguide portion. The third portion includes at least one output port configured to allow an output optical signal of an output propagation direction exiting therefrom, where the output propagation direction is different from the first propagation direction. The second portion is sandwiched between the first portion and the third portion.

IPC Classes  ?

• G02B 6/122 - Basic optical elements, e.g. light-guiding paths

Abstract

A method includes forming a first gate stack over a first semiconductor region, depositing a spacer layer on the first gate stack, and depositing a dummy spacer layer on the spacer layer. The dummy spacer layer includes a metal-containing material. An anisotropic etching process is performed on the dummy spacer layer and the spacer layer to form a gate spacer and a dummy sidewall spacer, respectively. The first semiconductor region is etched to form a recess extending into the first semiconductor region. The first semiconductor region is etched using the first gate stack, the gate spacer, and the dummy sidewall spacer as an etching mask. The method further includes epitaxially growing a source/drain region in the recess, and removing the dummy sidewall spacer after the source/drain region is grown.

IPC Classes  ?

• H10D 84/01 - Manufacture or treatment
• H01L 21/311 - Etching the insulating layers
• H10D 30/67 - Thin-film transistors [TFT]
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology

Abstract

An apparatus includes a wafer stage and a particle removing assembly. The wafer stage includes a cup adjacent to a wafer chuck. The particle removing assembly is configured to remove contaminant particles from the cup. In some embodiments, the particle removing assembly comprises a flexible ejecting member that includes one or more elongated tubes, a front tip, and a cleaning tip adapter configured to attach the front tip to each of the one or more elongated tubes. The front tip includes front openings and lateral openings from which pressurized cleaning material are introduced onto an unreachable area of the cup to remove the contaminant particles from the cup.

IPC Classes  ?

• B08B 9/08 - Cleaning of containers, e.g. tanks
• H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

Abstract

In some embodiments, the present disclosure relates to an integrated circuit device. A transistor structure is disposed over a substrate and includes a pair of source/drain regions and a gate electrode between the pair of source/drain regions. A lower inter-layer dielectric (ILD) layer is disposed over the pair of source/drain regions and surrounds the gate electrode. The gate electrode is recessed from top of the lower ILD layer. A gate capping layer is disposed on the gate electrode. The gate capping layer has a top surface aligned or coplanar with that of the lower ILD layer.

IPC Classes  ?

• H10D 64/23 - Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
• H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]

Abstract

A semiconductor device includes a first cell. The first cell includes: a substrate; a plurality of gate electrodes extending in a first direction and defining at least one odd-numbered track and at least one even-numbered track within the first cell, the at least one odd-numbered track alternatingly arranged with the at least one even-numbered track; a first power rail extending in a second direction perpendicular to the first direction; a first conductive via connected to the first power rail, the first conductive via being within a first odd-numbered track of the at least one odd-numbered track; a second power rail extending in the second direction; and a second conductive via connected to the second power rail, the second conductive via being within a first even-numbered track of the at least one even-numbered track.

IPC Classes  ?

• H10D 89/10 - Integrated device layouts
• G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
• G06F 30/394 - Routing
• G06F 119/06 - Power analysis or power optimisation
• H10D 84/85 - Complementary IGFETs, e.g. CMOS

Abstract

A semiconductor structure includes a first and second integrated circuit (IC) components stacked upon and electrically coupled to each other. The first IC component includes a first bonding structure including a first bonding dielectric layer and a first bonding feature disposed in the first bonding dielectric layer, and a first alignment pattern disposed in the first bonding dielectric layer. The second IC component includes a second bonding structure including a second bonding dielectric layer bonded to the first bonding dielectric layer and a second bonding feature disposed in the second bonding dielectric layer and bonded to the first bonding feature, and a second alignment pattern disposed in the second bonding dielectric layer and aligned with the first alignment pattern in a staggered manner. The second alignment pattern is disposed within a boundary of the first IC component in a top-down view.

IPC Classes  ?

• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices

Abstract

An embodiment package comprises an integrated circuit die encapsulated in an encapsulant, a patch antenna over the integrated circuit die, and a dielectric feature disposed between the integrated circuit die and the patch antenna. The patch antenna overlaps the integrated circuit die in a top-down view. The thickness of the dielectric feature is in accordance with an operating bandwidth of the patch antenna.

IPC Classes  ?

• H01L 23/66 - High-frequency adaptations
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
• H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 23/552 - Protection against radiation, e.g. light
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
• H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers
• H01P 3/00 - WaveguidesTransmission lines of the waveguide type
• H01Q 1/22 - SupportsMounting means by structural association with other equipment or articles
• H01Q 1/38 - Structural form of radiating elements, e.g. cone, spiral, umbrella formed by a conductive layer on an insulating support
• H01Q 9/04 - Resonant antennas
• H01Q 21/06 - Arrays of individually energised antenna units similarly polarised and spaced apart

Abstract

A semiconductor structure includes a first interconnect structure disposed over a first semiconductor substrate and a thermal sensing device. The thermal sensing device includes a first transistor, a second transistor, a first capacitor coupled to the first transistor, a second capacitor coupled to the second transistor, and a metallization pattern embedded in the first interconnect structure and serving as a resistive heater. At least one selected from the group of the first and second transistors is embedded in the first interconnect structure.

IPC Classes  ?

• G01K 7/34 - Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat using capacitative elements
• G01K 7/01 - Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat using semiconducting elements having PN junctions
• G01K 13/00 - Thermometers specially adapted for specific purposes

Abstract

Low-flow tungsten chemical vapor deposition (CVD) techniques described herein provide substantially uniform deposition of tungsten on a semiconductor substrate. In some implementations, a flow of a processing vapor is provided to a CVD processing chamber such that a flow rate of tungsten hexafluoride in the processing vapor results in the tungsten layer being grown at a slower rate than a higher flow rate of the tungsten hexafluoride to promote substantially uniform growth of the tungsten layer. In this way, the low-flow tungsten CVD techniques may be used to achieve similar surface uniformity performance to an atomic layer deposition (ALD) while being a faster deposition process relative to ALD (e.g., due to the lower deposition rate and large quantity of alternating processing cycles of ALD). This reduces the likelihood of defect formation in the tungsten layer while increasing the throughput of semiconductor device processing for the semiconductor substrate (and other semiconductor substrates).

IPC Classes  ?

• C23C 16/14 - Deposition of only one other metal element
• C23C 16/52 - Controlling or regulating the coating process
• H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
• H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
• H10D 64/01 - Manufacture or treatment

Abstract

A semiconductor device structure is provided. The semiconductor device structure includes a first substrate including a first face and a second face opposite the first face. A second substrate is bonded to the first face of the first substrate such that the second face of the first substrate faces away from the second substrate. One or more recesses are arranged in the second face of the first substrate and are configured to compensate for thermal expansion or thermal contraction.

IPC Classes  ?

• B81C 1/00 - Manufacture or treatment of devices or systems in or on a substrate
• B81C 3/00 - Assembling of devices or systems from individually processed components

Abstract

A memory cell includes patterning a first trench extending through a first conductive line, depositing a memory film along sidewalls and a bottom surface of the first trench, depositing a channel layer over the memory film, the channel layer extending along the sidewalls and the bottom surface of the first trench, depositing a first dielectric layer over and contacting the channel layer to fill the first trench, patterning a first opening, wherein patterning the first opening comprises etching the first dielectric layer, depositing a gate dielectric layer in the first opening, and depositing a gate electrode over the gate dielectric layer and in the first opening, the gate electrode being surrounded by the gate dielectric layer.

IPC Classes  ?

• H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H10B 51/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
• H10D 62/80 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials

Abstract

An SoIC structure including a first semiconductor die, second semiconductor dies, dummy dies, and a gap filling layer is provided. The second semiconductor dies are disposed over and electrically connected to the first semiconductor die. The dummy dies are disposed over the first semiconductor die to laterally surround the second semiconductor dies. The gap filling layer is disposed on the first semiconductor die to laterally encapsulate the dummy dies and the second semiconductor dies.

IPC Classes  ?

• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/24 - Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel, at the normal operating temperature of the device
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices

Abstract

A filler cell region (in a semiconductor device) includes: filler-gate segments; for which a majority of first ends substantially align with a first reference line and a majority of second ends substantially align with a second reference line, the first and second reference lines being parallel and proximal to a top and bottom boundaries of the filler cell region; first and second filler-gate segments extending continuously across the filler cell region; and third & fourth and fifth & sixth filler-gate segments being correspondingly coaxial and separated by corresponding gate-gaps located centrally in the filler cell region; the first and second filler-gate segments being between the third & fourth filler-gate segments and the fifth & sixth filler-gate segments; and a first end of the first or second filler-gate segment extending to the top boundary; and a second end of the first or second filler-gate segment extending to the bottom boundary.

IPC Classes  ?

• H10D 89/10 - Integrated device layouts
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H10D 84/90 - Masterslice integrated circuits

Abstract

In some aspects of the present disclosure, a memory device is disclosed. In some aspects, the memory device includes a first voltage regulator to receive a word line voltage provided to a memory array; a resistor network coupled to the first voltage regulator to provide an inhibit voltage to the memory array, wherein the resistor network comprises a plurality of resistors and wherein each of the resistors are coupled in series to an adjacent one of the plurality of resistors; and a switch network comprising a plurality of switches, wherein each of the switches are coupled to a corresponding one of the plurality of resistors and to the memory array via a second voltage regulator.

IPC Classes  ?

• G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or

Abstract

Semiconductor devices and methods of manufactured are presented in which a first redistribution structure is formed, semiconductor devices are bonded to the first redistribution structure, and the semiconductor devices are encapsulated in an encapsulant. First openings are formed within the encapsulant, such as along corners of the encapsulant, in order to help relieve stress and reduce cracks.

IPC Classes  ?

• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement

Abstract

A semiconductor structure is provided. The semiconductor structure includes a substrate, a plurality of well regions, a gate structure, a drain region, a source region, a circuit, and a voltage source. The gate structure includes a gate oxide over a first surface of the substrate and a gate electrode over the gate oxide. The gate oxide includes a first portion and a second portion connected with the first portion, wherein a thickness of the second portion is greater than that of the second portion. The voltage source is coupled to the drain region, configured to provide a first voltage to the drain region. The circuit is coupled to the gate structure, configured to provide a second voltage to the gate structure. A ratio of the first voltage to the second voltage is in a range from 2 to 4. Methods for manufacturing the semiconductor structure are also provided.

IPC Classes  ?

• H01L 29/66 - Types of semiconductor device
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

A method for manufacturing a semiconductor device is provided. A gate oxide layer is formed over an N-type well region and a P-type well region. The gate oxide layer comprises an input/output (I/O) oxide layer portion and a reduced surface field oxide (ROX) layer portion. A poly gate is formed on the I/O oxide layer portion. The poly gate extends along an interface between the N-type well region and the P-type well region. At least one poly strap is formed on the ROX layer portion. A resist protect oxide (RPO) layer is formed to completely cover the poly strap and partially cover the poly gate. An inter-level dielectric (ILD) layer is formed over the RPO layer. A connecting feature is formed to penetrate the ILD layer and the RPO layer to contact the poly strap.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/40 - Electrodes
• H01L 29/66 - Types of semiconductor device

Abstract

A method includes conducting an electromigration (EM) check process on a schematic design, conducting a mitigating process to mitigate one or more electromigration violations identified during conducting the EM check process, and generating a layout design of the schematic design after at least one iteration of a design process including the EM check process and the mitigating process. The EM check process includes selecting at least some circuits in the schematic design as selected circuits for electromigration check, and checking electromigration compliance in the selected circuits. The mitigating process includes modifying the schematic design.

IPC Classes  ?

• G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
• G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
• G06F 119/10 - Noise analysis or noise optimisation

Abstract

In some aspects of the present disclosure, a memory device is disclosed. In some aspects, the memory device includes a plurality of memory cells arranged in an array, an input/output (I/O) interface connected to the plurality of memory cells to output data signal from each memory cell, and a control circuit. In some embodiments, the control circuit includes a first clock generator to generate a first clock signal and a second clock signal according to an input clock signal and a chip enable (CE) signal and provide the first clock signal to the plurality of memory cells. In some embodiments, the control circuit includes a second clock generator to generate a third clock signal according to the input clock signal and a DFT (design for testability) enable signal. In some embodiments, the control circuit generates an output clock signal according to the second clock signal or the third clock signal.

IPC Classes  ?

• G11C 29/12 - Built-in arrangements for testing, e.g. built-in self testing [BIST]
• G11C 29/36 - Data generation devices, e.g. data inverters
• G11C 29/46 - Test trigger logic

Abstract

Provided are FinFET devices and methods of forming the same. A FinFET device includes a substrate, a metal gate strip, gate spacers and a dielectric helmet. The substrate has fins. The metal gate strip is disposed across the fins and has a reversed T-shaped portion between two adjacent fins. The gate spacers are disposed on opposing sidewalls of the metal gate strip. A dielectric helmet is disposed over the metal gate strip.

IPC Classes  ?

• H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
• H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
• H10D 30/01 - Manufacture or treatment
• H10D 30/62 - Fin field-effect transistors [FinFET]
• H10D 64/01 - Manufacture or treatment
• H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
• H10D 64/66 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology

Abstract

A structure including a first semiconductor die and a second semiconductor die is provided. The first semiconductor die includes a first bonding structure. The first bonding structure includes a first dielectric layer and first conductors embedded in the first dielectric layer. The second semiconductor die includes a second bonding structure. The second bonding structure includes a second dielectric layer and second conductors embedded in the second dielectric layer. The first dielectric layer is in contact with the second dielectric layer, and the first conductors are in contact with the second conductors. Thermal conductivity of the first dielectric layer and the second dielectric layer is greater than thermal conductivity of silicon dioxide.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements

Abstract

A multiple die container load port may include a housing with an opening, and an elevator to accommodate a plurality of different sized die containers. The multiple die container load port may include a stage supported by the housing and moveable within the opening of the housing by the elevator. The stage may include one or more positioning mechanisms to facilitate positioning of the plurality of different sized die containers on the stage, and may include different portions movable by the elevator to accommodate the plurality of different sized die containers. The multiple die container load port may include a position sensor to identify one of the plurality of different sized die containers positioned on the stage.

IPC Classes  ?

• H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
• B23Q 15/00 - Automatic control or regulation of feed movement, cutting velocity or position of tool or work
• B23Q 16/00 - Equipment for precise positioning of tool or work into particular locations not otherwise provided for
• G05D 5/04 - Control of dimensions of material of the size of items, e.g. of particles
• H01L 23/04 - ContainersSeals characterised by the shape

Abstract

In one embodiment, a method of forming metal interconnects uses a direct metal etch approach to form and fill the metal gap. The method may include directly etching a metal layer to form metal patterns. The metal patterns may be spaced apart from one another by recesses. A dielectric spacer may be formed extending along the sidewalls of each of the recesses. The recesses may be filled with a conductive material to form a second set of metal patterns. By directly etching the metal film, the technique allows for reduced line width roughness. The disclosed structure may have the advantages of increased reliability, better RC performance and reduced parasitic capacitance.

IPC Classes  ?

• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer

Abstract

Disclosed embodiments herein relate to an integrated circuit including power switches with active regions connected to form a contiguous region. In one aspect, the integrated circuit includes a first layer including a first metal rail extending in a first direction. In one aspect, the integrated circuit includes a second layer above the first layer along a second direction perpendicular to the first direction. The second layer may include active regions for power switches. In one aspect, the active regions of the power switches are connected to form a contiguous region extending in the first direction. The first metal rail may be electrically coupled to the active regions through via contacts. In one aspect, the integrated circuit includes a third layer above the second layer along the second direction. The third layer may include a second metal rail electrically coupled to some of the power switches through additional via contacts.

IPC Classes  ?

• H10D 89/10 - Integrated device layouts
• G06F 30/31 - Design entry, e.g. editors specifically adapted for circuit design
• G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
• G06F 117/12 - Sizing, e.g. of transistors or gates
• H01L 23/528 - Layout of the interconnection structure
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology

Abstract

A transport case is configured to hold a plurality of wafers for transport of the wafers. The transport case includes a plurality of slots each configured to receive and hold a respective wafer. The transport case includes a sensor system configured to measure the positions or orientations of wafers within the slots or during loading into the slots. The transport case includes a communication system configured to transmit sensor data from the sensor system to an external control system.

IPC Classes  ?

• H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
• G01B 11/26 - Measuring arrangements characterised by the use of optical techniques for measuring angles or tapersMeasuring arrangements characterised by the use of optical techniques for testing the alignment of axes
• H01L 21/673 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components using specially adapted carriers

Abstract

In some embodiments, an integrated circuit device includes a substrate having a frontside and a backside; one or more active semiconductor devices formed on the frontside of the substrate; conductive paths formed on the frontside of the substrate; and conductive paths formed on the backside of the substrate. At least some of the conductive paths formed on the backside of the substrate, and as least some of the conductive paths formed on the front side of the substrate, are signal paths among the active semiconductor devices. In some embodiments, other conductive paths formed on the backside of the substrate are power grid lines for powering at least some of the active semiconductor devices.

IPC Classes  ?

• H01L 23/528 - Layout of the interconnection structure
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]

Abstract

Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method of forming a semiconductor device comprises forming a fin over a substrate, wherein the fin comprises a first semiconductor layer and a second semiconductor layer comprising different semiconductor materials, and the fin includes a channel region and a source/drain region; forming a dummy gate structure over the substrate and the fin; etching a portion of the fin in the source/drain region; selectively removing an edge portion of the second semiconductor layer in the channel region of the fin such that the second semiconductor layer is recessed, and an edge portion of the first semiconductor layer is suspended; performing a reflow process to the first semiconductor layer to form an inner spacer, wherein the inner spacer forms sidewall surfaces of the source/drain region of the fin; and epitaxially growing a sour/drain feature in the source/drain region.

IPC Classes  ?

• H10D 64/01 - Manufacture or treatment
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
• H10D 30/01 - Manufacture or treatment
• H10D 30/62 - Fin field-effect transistors [FinFET]
• H10D 30/67 - Thin-film transistors [TFT]
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]

Abstract

A fusible structure includes: a conductive segment in a first layer extending along a first direction; and a first dummy structure being proximal to the conductive segment relative to a second direction, the second direction being perpendicular to the first direction, the first dummy structure being in a second layer different than the first layer; and wherein: relative to the first direction, the conductive segment includes first, second and third portions, the second portion being between the first portion and the third portion; and relative to a third direction that is perpendicular to the first direction and the second direction, the first portion is thicker than the second portion.

IPC Classes  ?

• H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
• H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
• H10B 20/25 - One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links

Abstract

Various embodiments of the present disclosure are directed towards an integrated chip including a first electrode over a substrate. A dielectric layer is on the first electrode. A second electrode is on the dielectric layer. The second electrode includes a first conductive layer, a diffusion barrier layer on the first conductive layer, and a second conductive layer on the diffusion barrier layer. The first conductive layer comprises a first plurality of grain boundaries continuously extending from a top surface of the dielectric layer in a first direction away from the dielectric layer. The diffusion barrier layer comprises a second plurality of grain boundaries stacked vertically over one another and continuously extending in a second direction approximately perpendicular to the first direction. The second conductive layer comprises a third plurality of grain boundaries extending in the first direction and over the second plurality of grain boundaries.

IPC Classes  ?

• H10D 1/68 - Capacitors having no potential barriers
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H10D 1/00 - Resistors, capacitors or inductors

Abstract

A phase shifter includes a first transistor, and a second transistor coupled to the first transistor. The first transistor includes an active region extending in a first direction, and a first set of gates extending in a second direction. The first set of gates overlaps the active region and is configured to receive a first voltage. The first transistor is configured to adjust a resistance or a first capacitance of the phase shifter responsive to the first voltage. The second transistor includes the active region, and a second set of gates extending in the second direction. The second set of gates overlaps the active region, is positioned along opposite edges of the active region, and is configured to receive a second voltage. The second transistor is configured to adjust a second capacitance of the phase shifter responsive to the second voltage.

IPC Classes  ?

• G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
• G03F 1/36 - Masks having proximity correction featuresPreparation thereof, e.g. optical proximity correction [OPC] design processes
• G03F 1/70 - Adapting basic layout or design of masks to lithographic process requirements, e.g. second iteration correction of mask patterns for imaging
• H03H 11/20 - Two-port phase shifters providing an adjustable phase shift

Abstract

Some embodiments relate to an integrated circuit device including upper and lower layers. The upper layer includes pixel cells that each include a photodetector and a transfer transistor to transfer electrical charge collected at the photodetector. The upper layer also includes first conductive pads at a lower surface of the upper layer, each of the first pads carrying an indication of the electrical charge transferred by the transfer transistor of one or more of the pixel cells. The lower layer includes second conductive pads at an upper surface of the lower layer, the upper surface of the lower layer lying adjacent the lower surface of the upper layer. Each of the second pads directly contact a corresponding one of the first pads. The lower layer also includes a processing circuit conductively coupled to the second pads and configured to process signals carried via the first and second pads.

IPC Classes  ?

• H01L 27/146 - Imager structures
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements

Abstract

The present disclosure relates to an integrated chip. The integrated chip comprises a dielectric layer over a substrate. A first metal feature is over the dielectric layer. A second metal feature is over the dielectric layer and is laterally adjacent to the first metal feature. A first dielectric liner segment extends laterally between the first metal feature and the second metal feature along an upper surface of the dielectric layer. The first dielectric liner segment extends continuously from along the upper surface of the dielectric layer, to along a sidewall of the first metal feature that faces the second metal feature, and to along a sidewall of the second metal feature that faces the first metal feature. A first cavity is laterally between sidewalls of the first dielectric liner segment and is above an upper surface of the first dielectric liner segment.

IPC Classes  ?

• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 23/528 - Layout of the interconnection structure
• H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology

Abstract

A ferroelectric memory cell (FeRAM) is disclosed that includes an active device (e.g., a transistor) and a passive device (e.g., a ferroelectric capacitor) integrated in a substrate. The transistor and its gate contacts are formed on a front side of the substrate. A carrier wafer can be bonded to the active device to allow the active device to be inverted so that the passive device and associated contacts can be electrically coupled from a back side of the substrate.

IPC Classes  ?

• H10B 53/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 23/528 - Layout of the interconnection structure
• H10B 51/10 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the top-view layout
• H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
• H10B 53/00 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
• H10B 53/10 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the top-view layout
• H10D 30/67 - Thin-film transistors [TFT]

Abstract

A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through substrate via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through substrate via. The second insulating encapsulation contacts with the second semiconductor die, the first insulting encapsulation, and the dielectric layer structure.

IPC Classes  ?

• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
• H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers

Abstract

A graphene liner deposited between at least one liner material (e.g., barrier layer, ruthenium liner, and/or cobalt liner) and a copper conductive structure reduces surface scattering at an interface between the at least one liner material and the copper conductive structure. Additionally, or alternatively, the carbon-based liner reduces contact resistance at an interface between the at least one liner material and the copper conductive structure. A carbon-based cap may additionally or alternatively be deposited on a metal cap, over the copper conductive structure, to reduce surface scattering at an interface between the metal cap and an additional copper conductive structure deposited over the metal cap.

IPC Classes  ?

• H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

Abstract

A semiconductor package structure includes a conductive pad over a substrate. The semiconductor package structure also includes a passivation layer over the conductive pad. The semiconductor package structure further includes a first via structure over the passivation layer and the conductive pad and electrically connected to the conductive pad. In addition, the semiconductor package structure includes a first encapsulating material over the passivation layer and surrounding the first via structure. The first via structure has a first portion on a top surface of the passivation layer and a second portion on the first portion and on a top surface of the first encapsulating material.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers

Abstract

A method of bonding semiconductor chips is described. The method includes the following steps. A semiconductor wafer is provided on a chuck table of a bonding apparatus. A bond head of the bonding apparatus is driven for picking up a first semiconductor chip from a support, wherein the first semiconductor chip has a first warpage amount. The bond head is driven for moving the first semiconductor chip to a position located over a first bonding region of the semiconductor wafer. A deforming process is performed using a deforming mechanism to deform the chuck table and the first bonding region of the semiconductor wafer by a first deform amount, wherein the first deform amount corresponds to the first warpage amount. The first semiconductor chip is bonded to the first bonding region of the semiconductor wafer while maintaining the first deform amount. The deforming mechanism is released from deforming the chuck table.

IPC Classes  ?

• H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
• H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
• H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches

Abstract

A semiconductor device and methods of forming the semiconductor device are described herein and are directed towards forming a source/drain contact plug for adjacent finFETs. The source/drain regions of the adjacent finFETs are embedded in an interlayer dielectric and are separated by an isolation region of a cut-metal gate (CMG) structure isolating gate electrodes of the adjacent finFETs The methods include recessing the isolation region, forming a contact plug opening through the interlayer dielectric to expose portions of a contact etch stop layer disposed over the source/drain regions through the contact plug opening, the contact etch stop layer being a different material from the material of the isolation region. Once exposed, the portions of the CESL are removed and a conductive material is formed in the contact plug opening and in contact with the source/drain regions of the adjacent finFETs and in contact with the isolation region.

IPC Classes  ?

• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
• H01L 21/266 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation using masks
• H01L 21/3105 - After-treatment
• H01L 21/311 - Etching the insulating layers
• H01L 21/762 - Dielectric regions
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/528 - Layout of the interconnection structure
• H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
• H10D 62/13 - Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
• H10D 64/01 - Manufacture or treatment
• H10D 84/01 - Manufacture or treatment
• H10D 84/85 - Complementary IGFETs, e.g. CMOS

Abstract

Various embodiments of the present disclosure are directed towards an integrated chip comprising a first photodetector arranged in a first substrate. The first photodetector absorbs light in a first wavelength range. A second substrate underlies the first substrate. A second photodetector is arranged on the second substrate. The second photodetector absorbs light in a second wavelength range different from the first wavelength range. A dielectric structure is arranged between a first surface of the first substrate and a first surface of the second substrate.

IPC Classes  ?

• H10F 39/15 - Charge-coupled device [CCD] image sensors
• H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays

Abstract

A semiconductor device includes an error correction code circuit and a register circuit. The error correction code circuit is configured to generate first data according to second data. The register circuit is configured to generate reset information according to a difference between the first data and the second data, for adjusting a memory cell associated with the second data. A method is also disclosed herein.

IPC Classes  ?

• G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
• G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

Abstract

A semiconductor device includes a plurality of first stack structures formed in a first area of a substrate, wherein the plurality of first stack structures are configured to form a plurality of first transistors that operate under a first voltage level. The semiconductor device includes a plurality of second stack structures formed in a second area of the substrate, wherein the plurality of second stack structures are configured to form a plurality of second transistors that operate under a second voltage level greater than the first voltage level. The semiconductor device includes a first isolation structure disposed between neighboring ones of the plurality of first stack structures and has a first height. The semiconductor device includes a second isolation structure disposed between neighboring ones of the plurality of second stack structures and has a second height. The first height is greater than the second height.

IPC Classes  ?

• H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology

Abstract

A ferroelectric memory device includes a first conductive region, a second conductive region and a ferroelectric structure. The second conductive region is disposed over the first conductive region. The ferroelectric structure includes a plurality of different ferroelectric materials stacked between the first conductive region and the second conductive region.

IPC Classes  ?

• H10B 53/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
• H01L 21/3115 - Doping the insulating layers
• H10B 51/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
• H10D 1/68 - Capacitors having no potential barriers
• H10D 30/01 - Manufacture or treatment
• H10D 30/69 - IGFETs having charge trapping gate insulators, e.g. MNOS transistors
• H10D 64/01 - Manufacture or treatment

Abstract

An integrated chip (IC) device according to the present disclosure includes a device region, an interconnect structure disposed over the device region, and a seal ring surrounding the device region and the interconnect structure. The device region includes a transistor having a gate structure. The seal ring includes a metal structure. The gate structure is thermally coupled to the metal structure by way of a diode.

IPC Classes  ?

• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
• H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 29/786 - Thin-film transistors
• H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
• H01L 29/861 - Diodes

Abstract

A test key configured to measure resistance of a through semiconductor via in a semiconductor substrate is provided. The test key includes a first resistor, a first conductor, a first probe pad, a second conductor, a second probe pad, a third conductor, a third probe pad, a fourth conductor, and a fourth probe pad. The first probe pad is electrically connected to a first end of the through semiconductor via by the first resistor and the first conductor. The second probe pad is electrically connected to the first end of the through semiconductor via by the second conductor. The third probe pad is electrically connected to a second end of the through semiconductor via by the third conductor. The fourth probe pad is electrically connected to the second end of the through semiconductor via by the fourth conductor.

IPC Classes  ?

• H01L 21/66 - Testing or measuring during manufacture or treatment
• G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 23/498 - Leads on insulating substrates
• H10D 1/47 - Resistors having no potential barriers

Abstract

A semiconductor package includes a package substrate, an integrated interconnect structure, an optical engine module, and an integrated circuit package. The integrated interconnect structure is bonded over the package substrate and includes an insulation body, a plurality of through vias extending through the insulation body. The optical engine module includes an electronic die, a photonic die, and a waveguide. A portion of the optical engine module is embedded in the integrated interconnect structure. The integrated circuit package is bonded over the integrated interconnect structure and electrically coupled to the optical engine module.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

A method of transporting a first carrier is provided. The method includes responsive to a processing station being scheduled to receive a semiconductor wafer that is carried by the first carrier, moving a first transport vehicle from a first track to a second track via a first junction while the first carrier is supported by a first carrier support component of the first transport vehicle. The method includes transferring the first carrier from the first carrier support component to the buffer support component while the first transport vehicle is engaged with the second track. The method includes responsive to the processing station being available to receive the semiconductor wafer, transferring the first carrier from the buffer support component to a second carrier support component of the second transport vehicle. The method includes transferring the first carrier from the second carrier support component to the processing station.

IPC Classes  ?

• H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
• H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

Abstract

A method includes providing a workpiece comprising a stack of semiconductor layers including interleaving first semiconductor layers and second semiconductor layers, forming a dummy gate structure to wrap over a channel region of the stack of semiconductor layers, performing a first etching process to selectively recess the second semiconductor layers, forming a gate spacer layer over the dummy gate structure and the stack of semiconductor layers, recessing a source/drain region of the stack of semiconductor layers to form a source/drain opening, performing a second etching process to selectively recess the second semiconductor layers from the source/drain opening to form inner spacer recesses, forming inner spacers in the inner spacer recesses, forming a source/drain feature in the source/drain opening, and replacing the dummy gate structure and the second semiconductor layers with a gate structure.

IPC Classes  ?

• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 21/8234 - MIS technology
• H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/66 - Types of semiconductor device
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 29/786 - Thin-film transistors

Abstract

A semiconductor photonics device may include a photonic integrated circuit and may be coupled with an output optical fiber at a top surface of the semiconductor photonics device. To facilitate coupling of modulated optical signals to the output optical fiber at the top surface of the semiconductor photonics device, the semiconductor photonics device may include a mirror structure that is supported by a semiconductor support structure included in the semiconductor photonics device. The mirror structure may be positioned at an angle relative to a surface of a semiconductor substrate of the semiconductor photonics device, which enables the mirror structure to transfer a modulated optical signal propagating in a first direction to a second direction toward the output optical fiber.

IPC Classes  ?

• G02B 6/42 - Coupling light guides with opto-electronic elements

Abstract

Embodiments of the present disclosure provide a method for forming semiconductor devices. Particularly, embodiments of the present disclosure provide a method for incorporating a filler element to a high-K dielectric layer in a gate structure. The filler element reduces vacancies in the high-K dielectric layer, thereby, improving threshold voltage control and device performance.

IPC Classes  ?

• H01L 29/66 - Types of semiconductor device
• H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
• H01L 21/3115 - Doping the insulating layers
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/40 - Electrodes
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 29/786 - Thin-film transistors

Abstract

An integrated circuit (IC) device includes a first transistor positioned on a front side of a semiconductor substrate, the first transistor including a first gate electrode, first and second epitaxial regions, a first channel extending between the first and second epitaxial regions and through the first gate electrode, and first and second metal-like defined (MD) segments directly overlying the respective first and second epitaxial regions. A first power rail is positioned on a back side of the semiconductor substrate, a first via structure extends from the first epitaxial region to the first power rail, and a second via structure extends from the first MD segment to the first power rail.

IPC Classes  ?

• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 23/528 - Layout of the interconnection structure
• H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 29/786 - Thin-film transistors

Abstract

A method includes forming a stack of alternating oxide semiconductor channel layers and sacrificial layers over a substrate; removing first portions of the sacrificial layers to expose channel regions of the oxide semiconductor channel layers; forming a gate structure wrapping around each of the channel regions of the oxide semiconductor channel layers; removing second portions of the sacrificial layers to expose source/drain regions of the oxide semiconductor channel layers; and forming source/drain electrodes wrapping around and in contact with each of the source/drain regions of the oxide semiconductor channel layers, wherein the source/drain electrodes are made of a metal-containing material.

IPC Classes  ?

• H01L 29/66 - Types of semiconductor device
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/383 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regions using diffusion into, or out of, a solid from or into a gaseous phase
• H01L 21/477 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 29/786 - Thin-film transistors

Abstract

A lithography method includes the following steps. A target layer is formed over a substrate. A photoresist composition is applied over the target layer to form a photoresist layer. The photoresist layer is exposed. A hydrophobic material is formed over the photoresist layer. A reflow process is performed to the photoresist layer and the hydrophobic material. The hydrophobic material is removed. The target layer is patterned using the photoresist layer as an etch mask.

IPC Classes  ?

• H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
• G03F 7/11 - Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers having cover layers or intermediate layers, e.g. subbing layers
• G03F 7/16 - Coating processesApparatus therefor
• G03F 7/32 - Liquid compositions therefor, e.g. developers
• H01L 21/308 - Chemical or electrical treatment, e.g. electrolytic etching using masks
• H01L 21/311 - Etching the insulating layers
• H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer

Abstract

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a plurality of fin structures, a gate oxide layer and a gate electrode layer. The fin structures are disposed on the substrate. The gate oxide layer is formed on the fin structures. The gate electrode layer covers the gate oxide layer and is substantially perpendicular to the fin structures, wherein the fin structures include a first type of fin and a second type of fin, and the gate oxide layer includes a first gate oxide portion and a second gate oxide portion, the first gate oxide portion covers the first type of fin, and the second gate oxide portion covers the second type of fin.

IPC Classes  ?

• H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
• H01L 21/8234 - MIS technology

Abstract

A semiconductor structure may include a wire-bond pad including a first electrically conducting surface, a flip-chip bump including a second electrically conducting surface, a polymer layer formed over a surface of the semiconductor structure, wherein the first electrically conducting surface of the wire-bond pad is located under a first opening in the polymer layer, and wherein the flip-chip bump extends through a second opening in the polymer layer.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

Methods and structures for inserting disposable interposers include forming a first gate over a first fin and a first spacer layer on sidewalls of the first gate, and a second gate over a second fin and a second spacer layer on sidewalls of the second gate. The method further includes replacing, within the first fin, epitaxial layers of a second composition with disposable interposers disposed beneath the first gate and first inner spacers on opposing ends of the disposable interposers. The method further includes etching back, within the second fin, opposing lateral ends of the epitaxial layers of the second composition to form recesses disposed beneath the second spacer layer and between adjacent epitaxial layers of the first composition. The method further includes forming second inner spacers, within the second fin, within each of the recesses on the opposing lateral ends of the epitaxial layers of the second composition.

IPC Classes  ?

• H01L 29/66 - Types of semiconductor device
• H01L 21/311 - Etching the insulating layers
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/786 - Thin-film transistors

Abstract

A method includes: positioning a mask in a processing chamber of a mask repair apparatus; determining whether a first abnormality is present by a first gas analysis device during forming a first vacuum in a column over the processing chamber; determining whether a second abnormality is present by a second gas analysis device during forming a second vacuum in the processing chamber; determining whether a third abnormality is present by a third gas analysis device during flowing a process gas into the processing chamber; determining whether a fourth abnormality is present by a fourth gas analysis device during directing an electron beam or ion beam at the mask with the process gas in the processing chamber; and in response to determining that one of the first, second, third or fourth abnormalities is present: halting the directing an electron beam or ion beam at the mask; and performing a repair associated with the first, second, third or fourth abnormality that is present.

IPC Classes  ?

• G03F 1/22 - Masks or mask blanks for imaging by radiation of 100 nm or shorter wavelength, e.g. X-ray masks, extreme ultraviolet [EUV] masksPreparation thereof
• G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor
• H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or

Abstract

A semiconductor device structure and methods of forming the same are described. The structure includes a first gate dielectric layer disposed over a substrate, the first gate dielectric layer includes an inner surface and an outer surface opposite the inner surface, and the first gate dielectric layer includes a fluorine concentration that decreases from the inner surface towards the outer surface. The structure further includes a second gate dielectric layer disposed on the first gate dielectric layer, the first and second gate dielectric layers have a combined thickness, and a thickness of the first gate dielectric layer ranges from about 30 percent to about 80 percent of the combined thickness. The structure further includes a gate electrode layer disposed over the second gate dielectric layer and a spacer disposed adjacent the first gate dielectric layer.

IPC Classes  ?

• H01L 29/51 - Insulating materials associated therewith
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/40 - Electrodes
• H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 29/786 - Thin-film transistors

Abstract

A sense amplifier is provided. A first terminal of a first invertor is connected to a power node and a second terminal of the first invertor is connected to a cell current source. A first terminal of a second invertor is connected to the power node and a second terminal of the second invertor is connected to a reference current source. The first invertor is cross coupled with the second invertor at a first node and a second node. A pre-charge circuit is connected to the first node and the second node. A first pull up transistor and a second pull up transistor are connected between a supply voltage node and the power node. A signal level detector circuit is connected to the second pull up transistor. The signal level detector circuit switches on the second pull up transistor when a remaining voltage on one of the first node and the second node is below a reference voltage.

IPC Classes  ?

• G11C 7/06 - Sense amplifiersAssociated circuits