Abstract

A substrate structure includes a substrate, a redistribution structure, and a pad-connection layer. The substrate has a first die region, a second die region, and a spacing region between the first die region and the second die region. The redistribution structure is disposed on the substrate, wherein the redistribution structure includes multiple signal wirings and multiple shielding wirings. The signal wirings and the shielding wirings are alternately disposed in a vertical direction and a lateral direction, and a width of the shielding wiring is within a range of 3.5 times to 4.6 times a width of the signal wiring. The pad-connection layer is disposed on the substrate, and the redistribution structure is located between the pad-connection layer and the substrate, wherein the pad-connection layer includes multiple pad-connection patterns located in the first die region and the second die region.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
• H01L 23/528 - Layout of the interconnection structure
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 23/552 - Protection against radiation, e.g. light
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or

Abstract

A method includes forming an interconnect structure over a front-side of a substrate; forming a power rail over a back-side of the substrate, wherein a footprint of the interconnect structure overlaps a footprint of the power rail on the substrate; forming a first seal ring structure over the back-side of the substrate, wherein from a top view, the first seal ring structure surrounds the power rail.

IPC Classes  ?

• H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for
• H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 23/528 - Layout of the interconnection structure

Abstract

A method of forming a semiconductor device includes forming a first layer on a semiconductor fin; forming a mask on the first layer, the mask being thicker on a top of the semiconductor fin than along a sidewall of the semiconductor fin. The first layer is thinned along the sidewall of the semiconductor fin using the mask. A second layer is formed on the semiconductor fin, the second layer covering the mask and the first layer. A dummy gate layer is formed on the semiconductor fin and patterned to expose a top surface of the semiconductor fin.

IPC Classes  ?

• H10D 30/01 - Manufacture or treatment
• H10D 30/62 - Fin field-effect transistors [FinFET]
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology

Abstract

A method includes forming a multilayer stack over a semiconductor region, wherein the multilayer stack comprises a plurality of sacrificial layers and a plurality of semiconductor nanostructures located alternatingly. The method further includes removing the plurality of sacrificial layers, forming a plurality of disposable interposers between the plurality of semiconductor nanostructures, performing an oxidation process on the plurality of disposable interposers, laterally recessing the plurality of disposable interposers to form lateral recesses between the plurality of semiconductor nanostructures, forming inner spacers in the lateral recesses, removing the plurality of disposable interposers, and forming a replacement gate in spaces between the plurality of semiconductor nanostructures.

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 29/66 - Types of semiconductor device

Abstract

Embodiments of the present disclosure provide a semiconductor device structure and methods of forming the same. The method includes forming a fin structure from a substrate, and the fin structure includes a plurality of semiconductor layers. The method further includes depositing a gate dielectric layer around a portion of each semiconductor layer of the plurality of semiconductor layers, depositing an adhesion layer on the gate dielectric layer, and the adhesion layer surrounds the portion of each semiconductor layer of the plurality of semiconductor layers. The method further includes depositing a fluorine-containing layer on the adhesion layer, and the fluorine-containing layer surrounds the portion of each semiconductor layer of the plurality of semiconductor layers. The method further includes performing an annealing process on the fluorine-containing layer, removing the fluorine-containing layer and the adhesion layer, and forming a gate electrode layer on the gate dielectric layer.

IPC Classes  ?

• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
• H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
• H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/66 - Types of semiconductor device
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 29/786 - Thin-film transistors

Abstract

A photonic integrated circuit has an asymmetric dual ring resonator. The asymmetric dual ring resonator includes a first ring having a first effective length and a second ring having a second effective length, which is distinct from the first effective length. The first effective length and the second effective length are near integer multiples of a third effective length. The third effective length is within about an order or magnitude of the first effective length and the second effective length. The asymmetric dual ring resonator has a free spectral range corresponding to a single ring resonator having the third effective length but has a lower sensitivity to manufacturing process variations than would a single ring resonator having the third effective length.

IPC Classes  ?

• G02B 6/293 - Optical coupling means having data bus means, i.e. plural waveguides interconnected and providing an inherently bidirectional system by mixing and splitting signals with wavelength selective means
• G02B 6/136 - Integrated optical circuits characterised by the manufacturing method by etching

Abstract

A semiconductor package includes an interposer having a first principle surface and a second principle surface opposite the first principle surface. One or more semiconductor dies are disposed on the first principle surface of the interposer, and are electrically connected with the second principle surface of the interposer by electrical vias passing through the interposer. A heat spreading lid disposed over the one or more semiconductor dies. A thermally conductive material is disposed between the one or more semiconductor dies and the heat spreading lid. The thermally conductive material thermally couples the one or more semiconductor dies and the heat spreading lid. In some examples, the heat spreading lid may be a thermoelectric cooler. In some examples, the thermally conductive material may be a mixture of a gel and a liquid metal.

IPC Classes  ?

• H01L 23/42 - Fillings or auxiliary members in containers selected or arranged to facilitate heating or cooling
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/367 - Cooling facilitated by shape of device
• H01L 23/38 - Cooling arrangements using the Peltier effect
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

A semiconductor structure, a package structure and a manufacturing method of a semiconductor structure are provided. The semiconductor structure includes a first semiconductor die, a second semiconductor die and an insulating encapsulant. The second semiconductor die is overlapped with and electrically connected to the first semiconductor die. The insulating encapsulant is disposed on the second semiconductor die and at least laterally encapsulates the first semiconductor die. The first semiconductor die includes a first portion and a second portion located between the first portion and the second semiconductor die. In a sectional view, the second portion is wider than the first portion.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

Abstract

A package structure is provided. The package structure includes a first package component and a second package component bonded to the first package component. The package structure includes an electronic component disposed on the second package component. The package structure includes a thermal interface material over the first package component. The package structure includes a first adhesive wall located between the first package component and the electronic component. The package structure also includes a lid structure bonded to the second package component.

IPC Classes  ?

• H01L 23/053 - ContainersSeals characterised by the shape the container being a hollow construction and having an insulating base as a mounting for the semiconductor body
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

A method of fabricating a device includes forming a first layer. The first layer may be a ferroelectric layer if the device is a ferroelectric field effect transistor (FeFET), or a gate dielectric layer if the device is a transistor. Alternatively, the first layer may be a channel of the device. A metal oxide layer is formed on the first layer by depositing a metal layer on the first layer by physical vapor deposition followed by exposing the metal layer to ozone or ozone plasma. A second layer is formed on the metal oxide layer. The forming of the metal oxide layer may further include, prior to the depositing of the metal layer, exposing the first layer to ozone or ozone plasma. The metal layer may be a titanium layer.

IPC Classes  ?

• H01L 29/66 - Types of semiconductor device
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 29/51 - Insulating materials associated therewith
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

Embodiments of the present disclosure provide a package structure. The package structure includes a semiconductor die. An underfill material is below the semiconductor die and extends up to a sidewall of the semiconductor die. A molding compound surrounds the semiconductor die and the underfill material. An interface material is between the molding compound and the underfill material.

IPC Classes  ?

• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/367 - Cooling facilitated by shape of device
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 23/498 - Leads on insulating substrates

Abstract

The present disclosure provides a method. In some embodiments, the method includes providing a substrate; bonding a package structure to the substrate; attaching a ring structure on the substrate and surrounding the package structure; forming a thermal interface material (TIM) layer over the package structure; attaching a heat sink structure to the TIM layer and the ring structure.

IPC Classes  ?

• H01L 23/367 - Cooling facilitated by shape of device
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits

Abstract

An embodiment semiconductor package may include a semiconductor device, a molding material laterally surrounding the semiconductor device, and an alignment mark including a first through-molding-via (TMV) and a second TMV, each formed in the molding material. The first TMV may have a first specific dimension that is between 10 microns and 150 microns and the second TMV may have a second specific dimension that is between 100 microns and 500 microns. One or more first TMVs may be located in a first region and one or more second TMVs may be located in a second region that surrounds the first region. The first region may have a diameter that is between 100 microns and 1000 microns and the second region may be an annular region having an inner diameter that is between 120 microns and 1600 microns and an outer diameter that is between 270 microns and 2000 microns.

IPC Classes  ?

• H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or

Abstract

Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes first nanostructures formed over a substrate along a first direction, and second nanostructures parallel to the first nanostructures. The semiconductor structure includes a merged S/D structure formed on the first nanostructures and the second nanostructures, and a first gate structure formed over the first nanostructures and the second nanostructures along a second direction. The semiconductor structure includes a second gate structure formed parallel to the first gate structure. The semiconductor structure includes a first dielectric wall structure formed along the first direction. The first gate structure and the merged S/D structure are divided by the first dielectric wall structure, and an end of the first dielectric wall structure extends beyond an outer sidewall surface of the merged S/D structure.

IPC Classes  ?

• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 21/8234 - MIS technology
• H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/66 - Types of semiconductor device
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 29/786 - Thin-film transistors

Abstract

A method of forming a package assembly includes the following operations. An interposer structure, a first die and a second die are provided. The interposer structure includes a first tilted metal layer and a second tilted metal layer facing each other. The first die includes a first substrate and a third tilted metal layer embedded in a first insulating layer on the first substrate. The second die includes a second substrate and a fourth tilted metal layer embedded in a second insulating layer on the second substrate. The first die and the second die are bonded to the interposer structure with the first substrate and the second substrate facing up, so that a light beam from an optical fiber over the first die is reflected by the third tilted metal layer, the first tilted metal layer, the second tilted metal layer, and the fourth tilted metal layer sequentially.

IPC Classes  ?

• H01L 25/04 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers
• G02B 6/42 - Coupling light guides with opto-electronic elements
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

An optical phase-shifting device includes a ribbed waveguide portion on an insulating layer, the waveguide portion having a p-n or p-i-n junction extending in a longitudinal direction and having a height. A pair of slab portions are disposed adjacent the waveguide portion, one on each side of the ribbed waveguide portion and on the insulation layer. The slab portion have higher doping concentrations than the respective doping concentrations in the ribbed waveguide portion. At least a portion of each slab portion has a height increasing with distance from the waveguide portion, with the slab height being smaller than that of the waveguide portion at the junction between the waveguide portion and slab portion. A pair of contact portions are formed adjacent the respective slab portion and further away from the waveguide portion. A portion of each contact portion can also have a height varying with distance from the waveguide portion.

IPC Classes  ?

• G02F 1/025 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour based on semiconductor elements having potential barriers, e.g. having a PN or PIN junction in an optical waveguide structure
• G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
• G02B 6/136 - Integrated optical circuits characterised by the manufacturing method by etching
• G02F 1/225 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour by interference in an optical waveguide structure

Abstract

Some embodiments relate to a semiconductor device. The semiconductor device includes a first dielectric layer, a metal line embedded in the first dielectric layer, a second dielectric layer over the first dielectric layer, a bottom electrode via surrounded by the second dielectric layer, a bottom electrode over the bottom electrode via, a memory stack above the bottom electrode, and a top electrode over the memory stack. The bottom electrode via interfaces with a top surface of the metal line. A top surface of the bottom electrode via bends towards the first dielectric layer. A bottom surface of the bottom electrode bends towards the first dielectric layer. A top surface of the bottom electrode is flat. A bottom surface of the memory stack fully covers the top surface of the bottom electrode.

IPC Classes  ?

• H10N 50/80 - Constructional details
• H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• H10N 50/01 - Manufacture or treatment

Abstract

A method for manufacturing a semiconductor structure includes forming a fin over a substrate. The fin includes first semiconductor layers and second semiconductor layers alternating stacked in a first direction. The method also includes forming a dummy gate structure over the fin, forming first gate spacers on opposite sides of the dummy gate structure in a second direction, forming source/drain features on opposite sides of the dummy gate structure in the second direction, replacing the dummy gate structure and the first semiconductor layers with a gate structure, replacing the first gate spacers with second gate spacers, and forming inner spacers between the second semiconductor layers in the first direction. The gate structure wraps around the first semiconductor layers. Each of the second gate spacers has a first air gap. Each of the inner gate spacers has a second air gap.

IPC Classes  ?

• H01L 29/49 - Metal-insulator semiconductor electrodes
• G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
• H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H03K 19/21 - EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one inputCOINCIDENCE circuits, i.e. giving output only if all input signals are identical

Abstract

A package structure and a formation method are provided. The method includes disposing a chip-containing structure over a substrate and forming a thermal conductive layer over the chip-containing structure. The method also includes disposing a heat-spreading lid over the chip-containing structure and the thermal conductive layer. A metallic structure is embedded in the heat-spreading lid, and the metallic structure faces the thermal conductive layer. The method further includes pressing the heat-spreading lid against the chip-containing structure at an elevated temperature such that a portion of or an entirety of the metallic structure and a portion of or an entirety of the thermal conductive layer are transformed into an intermetallic compound material.

IPC Classes  ?

• H01L 23/367 - Cooling facilitated by shape of device
• H01L 21/603 - Attaching leads or other conductive members, to be used for carrying current to or from the device in operation involving the application of pressure, e.g. thermo-compression bonding
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/498 - Leads on insulating substrates
• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits

Abstract

An elongated conductive structure is included through a device layer of a semiconductor die included in a semiconductor die package. The elongated conductive structure connects to metallization layers in interconnect layers on opposing sides of the device layer. A blocking material is used to inhibit growth of barrier layers on the elongated conductive structure during formation of the barrier layers for the metallization layers. This enables the metallization layers to land directly on the elongated conductive structure as opposed to the barrier layers being between the elongated conductive structure and the metallization layers. In this way, metal-to-metal connections may be achieved between the conductive structure and the metallization layers, which enables a low contact resistance to be achieved between the conductive structure and the metallization layers while enabling barrier layers to be formed to provide diffusion protection for the metallization layers.

IPC Classes  ?

• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/528 - Layout of the interconnection structure
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

A semiconductor module includes a first semiconductor die, a second semiconductor die on the first semiconductor die, and a first corner die adjacent the second semiconductor die on the first semiconductor die and including a first corner die first side, a first corner die second side and a first corner die corner side connecting the first corner die first side and the first corner die second side, wherein the first corner die is located over a side of the first semiconductor die.

IPC Classes  ?

• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

A method includes forming a multilayer stack over a semiconductor region, wherein the multilayer stack comprises a plurality of sacrificial layers and a plurality of semiconductor nanostructures located alternatingly. The method further includes removing the plurality of sacrificial layers, forming a plurality of disposable interposers between the plurality of semiconductor nanostructures, performing an oxidation process on the plurality of disposable interposers, laterally recessing the plurality of disposable interposers to form lateral recesses between the plurality of semiconductor nanostructures, forming inner spacers in the lateral recesses, removing the plurality of disposable interposers, and forming a replacement gate in spaces between the plurality of semiconductor nanostructures.

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H10D 30/01 - Manufacture or treatment
• H10D 64/01 - Manufacture or treatment

Abstract

One or more sensors are integrated into a processor module that includes a semiconductor package and a heat sink. A plurality of processor modules is present in a server, and data from each processor module is sent to a digitally integrated monitoring system which can be part of a data center hardware monitoring system. The server may be one of many servers located in a data center. The data may be further sent to a remote data center maintenance center that concurrently monitors several data centers. When compared to different benchmarks, the data can be used to determine in real time whether maintenance is needed for a given processor module.

IPC Classes  ?

• G05B 23/02 - Electric testing or monitoring

Abstract

Some embodiments relate to an integrated circuit cooling system including: an impingement coolant block overlying a semiconductor die; an inlet opening in the impingement coolant block and coupled to an inlet; a plurality of tubes extending in a first direction directly beneath the inlet opening and having first ends and second ends, where the plurality of tubes are respectively centered on first axes; a plurality of valves coupling the first ends of the plurality of tubes to the inlet opening; a plurality of impingement openings within the impingement coolant block and respectively surrounding the second ends of the second plurality of tubes, where the plurality of impingement openings are respectively centered on the first axes; and an outlet opening within the impingement coolant block and between the inlet opening and the plurality of impingement openings, the outlet opening physically coupling the plurality of impingement openings to an outlet.

IPC Classes  ?

• H05K 7/20 - Modifications to facilitate cooling, ventilating, or heating
• H05K 1/02 - Printed circuits Details

Abstract

A semiconductor device is formed such that isolation regions between a medium voltage transistor region and a low voltage transistor region are manufactured to have different properties than isolation regions between low voltage transistors in the low voltage transistor region. A dual STI technique described herein is used to form the isolation regions between the low voltage transistors in the low voltage transistor region using low voltage transistor isolation design rules may, and additional STI formation operations may be performed to form the isolation regions between the low voltage transistor region and the medium voltage transistor region. In particular, the dual STI technique described herein may be used to form the isolation regions between the low voltage transistor region and the medium voltage transistor region such that these isolation regions are deeper than other isolation regions in the semiconductor device.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 21/762 - Dielectric regions
• H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
• H01L 29/66 - Types of semiconductor device

Abstract

A semiconductor device includes a substrate, a transistor over the substrate, and a first isolation structure adjacent to the transistor. The transistor includes a channel layer extending along a first direction, a gate structure over the channel layer and extending along a second direction substantially perpendicular to the first direction, and source/drain structures on opposite ends of the channel layer. In a top view, the first isolation structure includes a first extension portion and a second extension portion extending along the first direction, and a connection portion extending along the second direction and connecting with the first extension portion and the second extension portion.

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device

Abstract

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least a circuit substrate, a semiconductor die and a filling material. The circuit substrate has a first surface, a second surface opposite to the first surface and a cavity concave from the first surface. The circuit substrate includes a dielectric material and a metal floor plate embedded in the dielectric material and located below the cavity. A location of the metal floor plate corresponds to a location of the cavity. The metal floor plate is electrically floating and isolated by the dielectric material. The semiconductor die is disposed in the cavity and electrically connected with the circuit substrate. The filling material is disposed between the semiconductor die and the circuit substrate. The filling material fills the cavity and encapsulates the semiconductor die to attach the semiconductor die and the circuit substrate.

IPC Classes  ?

• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

Optical devices and methods of manufacture are presented in which optical interposers are embedded within interposers. In some embodiments a method includes embedding an optical interposer into an interposer with one or more waveguides, with or without other semiconductor devices, and then bonding one or more semiconductor devices onto the interposer.

IPC Classes  ?

• G02B 6/43 - Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
• G02B 6/42 - Coupling light guides with opto-electronic elements
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

A memory device includes a plurality of one-time-programming (OTP) memory cells grouped at least into a first portion and a second portion, wherein the first and second portions are disposed next to each other along a first lateral direction; a first driver circuit disposed next to the first portion along a first lateral direction, wherein the first portion is interposed between the second portion and the first driver circuit along the first lateral direction; and a second driver circuit disposed next to both of the first and second portions along a second lateral direction perpendicular to the first lateral direction. The OTP memory cells of the first portion are associated with a first electrical/physical characteristic and the OTP memory cells of the second portion are associated with a second electrical/physical characteristic, in which the first electrical/physical characteristic is different from the second electrical/physical characteristic.

IPC Classes  ?

• H10B 20/25 - One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links

Abstract

A method includes forming a dielectric layer over an epitaxial source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the epitaxial source/drain region. A barrier layer is formed on a sidewall and a bottom of the opening. An oxidation process is performing on the sidewall and the bottom of the opening. The oxidation process transforms a portion of the barrier layer into an oxidized barrier layer and transforms a portion of the dielectric layer adjacent to the oxidized barrier layer into a liner layer. The oxidized barrier layer is removed. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with the liner layer.

IPC Classes  ?

• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions

Abstract

Embodiments utilize a bridge die that directly bonds to and bridges two or more device dies. Each of the device dies can have additional device dies stacked thereupon. In some embodiments, the bridge die can bridge device dies disposed both under and over the bridge die. In some embodiments, several bridge dies may be used to bridge a device die to other adjacent device dies.

IPC Classes  ?

• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

A semiconductor structure is provided. The semiconductor structure includes an interconnection structure, a first conductive pad, a second conductive pad, a conductive material and a conductive coil. The first and second conductive pads are disposed over and electrically connected to the interconnection structure individually. The conductive material is electrically isolated from the interconnection structure. Bottom surfaces of the conductive material, the first conductive pad and the second conductive pad are substantially aligned. The conductive coil is disposed in the interconnection structure and overlapped by the conductive material. A manufacturing method of a semiconductor structure is also provided.

IPC Classes  ?

• H01L 21/66 - Testing or measuring during manufacture or treatment
• H01L 23/00 - Details of semiconductor or other solid state devices
• H10D 1/20 - Inductors

Abstract

A method of manufacturing a semiconductor structure includes forming a first dielectric layer surrounding an optical component. The method includes forming a thermal control mechanism adjacent to the optical component and at least partially surrounded by the first dielectric layer. Forming the thermal control mechanism includes forming a first thermoelectric member having a first conductivity type, forming a second thermoelectric member having a second conductivity type opposite to the first conductivity type, wherein the second thermoelectric member is opposite to the first thermoelectric member; and electrically connecting the first thermoelectric member to the second thermoelectric member.

IPC Classes  ?

• H10N 10/17 - Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects operating with only the Peltier or Seebeck effects characterised by the structure or configuration of the cell or thermocouple forming the device
• H01L 23/38 - Cooling arrangements using the Peltier effect
• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
• H10N 10/01 - Manufacture or treatment
• H10N 10/80 - Constructional details

Abstract

A silicon photonics integrated circuit includes a polarization splitting grating coupler (PSGC) configured to receive an optical signal and split the optical signal into two polarization components. The circuit includes a phase controller coupled to the PSGC, and the phase controller is configured to tune the split optical signal such that the two polarization components are in phase. The circuit includes a first and a second photodiode coupled to the phase controller, where the first photodiode receives a first component of the two polarization components and the second photodiode receives a second component of the two polarization components, and the first and second photodiodes converts the first and second components into first and second electrical signals, respectively. The circuit includes an amplitude controller coupled to the first and the second photodiodes, the amplitude controller configured to add the first and the second electrical signals to output a combined electrical signal.

IPC Classes  ?

• G02F 1/01 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour
• G02B 6/293 - Optical coupling means having data bus means, i.e. plural waveguides interconnected and providing an inherently bidirectional system by mixing and splitting signals with wavelength selective means
• G02F 1/21 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour by interference
• G02F 1/225 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour by interference in an optical waveguide structure

Abstract

A semiconductor structure according to the present disclosure includes a first memory cell that includes a first pull-down transistor and a first pull-up transistor sharing a first gate structure extending along a first direction, a second pull-down transistor and a second pull-up transistor sharing a second gate structure extending along the first direction, a first pass-gate transistor having a third gate structure spaced apart but aligned with the second gate structure along the first direction, and a second pass-gate transistor having a fourth gate structure spaced apart but aligned with the first gate structure along the first direction, a frontside interconnect structure disposed over the first memory device, a backside interconnect structure disposed below the first memory device. A source of the second pull-down transistor is electrically coupled to the backside interconnect structure by way of a first backside contact via.

IPC Classes  ?

• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H10B 10/00 - Static random access memory [SRAM] devices
• H10D 30/43 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 1D charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
• H10D 30/67 - Thin-film transistors [TFT]
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies

Abstract

A device structure includes a first series connection of a first phase change memory (PCM) switch and a second PCM switch. The first PCM switch includes a first heater line, a first PCM line, and a first contact electrode and a second contact electrode located on the first heater line. The second PCM switch includes a second heater line, a second PCM line, and a third contact electrode and a fourth contact electrode located on the second heater line. The second contact electrode is electrically connected to the third contact electrode. The fourth contact electrode is electrically grounded. One of the first contact electrode and the second contact electrode includes an radio-frequency (RF) signal input port. Another of the first contact electrode and the second contact electrode comprises an RF signal output port. The device structure may function as a combination PCM switch that decreases noise level during signal transmission.

IPC Classes  ?

• H10B 63/10 - Phase change RAM [PCRAM, PRAM] devices
• G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
• H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices

Abstract

A method includes depositing a gate dielectric layer on a first channel region; depositing a p-type work function tuning layer on the gate dielectric layer; exposing the p-type work function tuning layer to a silicon-based precursor for a duration of time; and depositing a n-type work function tuning layer on the p-type work function tuning layer. Exposing the p-type work function tuning layer to the silicon-based precursor can form a silicon-containing layer on the p-type work function tuning layer.

IPC Classes  ?

• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
• H10D 30/01 - Manufacture or treatment
• H10D 30/43 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 1D charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
• H10D 30/67 - Thin-film transistors [TFT]
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 64/01 - Manufacture or treatment
• H10D 84/01 - Manufacture or treatment
• H10D 84/85 - Complementary IGFETs, e.g. CMOS

Abstract

In an embodiment, a device includes: a gallium nitride device on a substrate, the gallium nitride device including an electrode; a dielectric layer on and around the gallium nitride device; an isolation layer on the dielectric layer; a semiconductor layer on the isolation layer, the semiconductor layer including a silicon device; a through via extending through the semiconductor layer, the isolation layer, and the dielectric layer, the through via electrically and physically coupled to the electrode of the gallium nitride device; and an interconnect structure on the semiconductor layer, the interconnect structure including metallization patterns electrically coupled to the through via and the silicon device.

IPC Classes  ?

• H10D 84/08 - Manufacture or treatment characterised by using material-based technologies using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies
• H01L 21/762 - Dielectric regions
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
• H10D 86/00 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
• H10D 86/01 - Manufacture or treatment
• H10D 87/00 - Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate

Abstract

A method includes forming a gate electrode and a source/drain region over a bulk portion of a semiconductor substrate, forming a cut-metal-gate region to separate the gate electrode into a first portion and a second portion, forming a source/drain contact plug overlapping and electrically connected to the source/drain region, forming a first contact rail overlapping a portion of the cut-metal-gate region, removing the bulk portion of the semiconductor substrate, and etching the cut-metal-gate region to form a trench. A surface of the first contact rail is revealed to the trench. A via rail is formed in the trench, and the via rail is electrically connected to the source/drain region through the first contact rail.

IPC Classes  ?

• H10D 30/67 - Thin-film transistors [TFT]
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 23/528 - Layout of the interconnection structure
• H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
• H10D 30/01 - Manufacture or treatment
• H10D 30/43 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 1D charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 64/01 - Manufacture or treatment
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]

Abstract

A thin film transistor includes a gate electrode embedded in an insulating layer that overlies a substrate, a gate dielectric overlying the gate electrode, an active layer comprising a compound semiconductor material and overlying the gate dielectric, and a source electrode and drain electrode contacting end portions of the active layer. The gate dielectric may have thicker portions over interfaces with the insulating layer to suppress hydrogen diffusion therethrough. Additionally or alternatively, a passivation capping dielectric including a dielectric metal oxide material may be interposed between the active layer and a dielectric layer overlying the active layer to suppress hydrogen diffusion therethrough.

IPC Classes  ?

• H10D 30/67 - Thin-film transistors [TFT]
• H10D 30/01 - Manufacture or treatment
• H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates

Abstract

A dielectric structure is formed over a layer than contains a conductive component. An opening is formed in the dielectric structure. The opening exposes an upper surface of the conductive component. A first deposition process is performed that deposits a first conductive layer over the dielectric structure and partially in the opening. A treatment process is performed on a first portion of the first conductive layer formed over the dielectric structure. The treatment process introduces a non-metal material to the first portion of the first conductive layer. After the treatment process has been performed, a second deposition process is performed that at least partially fills the opening with a second conductive layer without trapping a gap therein.

IPC Classes  ?

• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 23/528 - Layout of the interconnection structure
• H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
• H10B 99/00 - Subject matter not provided for in other groups of this subclass
• H10D 88/00 - Three-dimensional [3D] integrated devices

Abstract

An integrated circuit package and the method of forming the same are provided. The integrated circuit package may include a first die having a first substrate and a first through via extending through the first substrate, a first gap-fill layer along a sidewall of the first substrate, an isolation layer on a surface of the first substrate and a surface of the first gap-fill layer, a first bonding layer over the isolation layer, and a first bonding pad in the first bonding layer. The isolation layer may overlap an interface between the sidewall of the first substrate and a sidewall of the first gap-fill layer, and may extend on sidewalls of the first through via.

IPC Classes  ?

• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or

Abstract

Semiconductor device packages and methods of forming the same are discussed. In an embodiment, a device includes: a redistribution structure comprising an upper dielectric layer and an under-bump metallization; a buffer feature on the under-bump metallization and the upper dielectric layer, the buffer feature covering an edge of the under-bump metallization, the buffer feature bonded to the upper dielectric layer; a reflowable connector extending through the buffer feature, the reflowable connector coupled to the under-bump metallization; an interposer coupled to the reflowable connector; and an encapsulant around the interposer and the reflowable connector, the encapsulant different from the buffer feature.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

A semiconductor package includes a redistribution structure, first and second integrated circuit dies that are connected to a first side of the redistribution structure, and third and fourth integrated circuit dies that are connected on a second side, opposite to the first side, of the redistribution structure. An optical bridge die is connected between the third and fourth integrated circuit dies, to the second side of the redistribution structure, which is configured such that the first and second integrated circuit dies optically communicate through the optical bridge die.

IPC Classes  ?

• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement

Abstract

A memory circuit includes a bit line driver circuit, a first bit line, a selection circuit, a first word line, a first source line, and a memory cell. The selection circuit includes a first transistor on a first level of a substrate; and a second transistor on a second level of the substrate below the first level. The first transistor and the second transistor are part of a complementary field-effect transistor (CFET). The first transistor is configured to perform a write operation of the memory cell in response to the memory cell being configured to store a first logical value. The second transistor is configured to perform a read operation of the memory cell, and the write operation of the memory cell in response to the memory cell being configured to store a second logical value different from the first logical value.

IPC Classes  ?

• G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or

Abstract

Semiconductor devices and methods of forming the same are provided. A method of the present disclosure includes depositing an aluminum nitride layer over a substrate, treating the aluminum nitride layer to convert a top portion of the aluminum nitride layer to an aluminum oxynitride layer, depositing a III-V semiconductor layer on the aluminum oxynitride layer, and forming a gate structure over the III-V semiconductor layer.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]

Abstract

One aspect of the present disclosure pertains to an integrated circuit (IC) structure. The IC structure includes a die and an integrated heat sink structure disposed over the die. In some embodiments, the integrated heat sink structure includes a first closed-loop microchannel structure adjacent to the die and a second closed-loop microchannel structure disposed over the first closed-loop microchannel structure. In an example, the second closed-loop microchannel structure is disposed further away from the die than the first closed-loop microchannel structure. In some implementations, a plurality of microchannels and a micromixer chamber collectively provide the first and second closed-loop microchannel structures.

IPC Classes  ?

• H05K 7/20 - Modifications to facilitate cooling, ventilating, or heating

Abstract

A semiconductor device includes a first chip including an array of photo-sensitive devices. The semiconductor device further includes a second chip bonded to the first chip. The second chip includes an array of pixel units. In some embodiments, at least one pixel unit of the array of pixel units includes a photo diode including. The photo diode includes an anode coupled to an electrical ground. The photo diode further includes a cathode coupled to a source of a transfer gate transistor. The second chip further includes a plurality of input/output transistors disposed along at least one edge of the array of pixel units.

IPC Classes  ?

• H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

A first side of a sensor wafer is bonded to a first side of a first logic wafer. The sensor wafer contains pixels configured to detect radiation that enters the sensor wafer through a second side of the sensor wafer opposite the first side. The first logic wafer contains circuitry configured to operate the pixels. The sensor wafer or the first logic wafer contains a protection diode. The first logic wafer is thinned from a second side of the first logic wafer opposite the first side. A through-substrate-via (TSV) is formed in the first logic wafer. The protection diode protects the sensor wafer or the first logic wafer from being damaged during the forming of the TSV. The second side of the first logic wafer is bonded to a second logic wafer. The sensor wafer is thinned from the second side of the sensor wafer.

IPC Classes  ?

• H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
• H01L 23/00 - Details of semiconductor or other solid state devices
• H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays

Abstract

A semiconductor device includes a plurality of top semiconductor dies. Each of the plurality of top semiconductor dies can be bonded to a bottom semiconductor die. The semiconductor device includes a redistribution structure disposed opposite the plurality of top semiconductor dies from the plurality of bottom semiconductor dies and comprising a plurality of interconnect structures. A top semiconductor die can connect to another top semiconductor die via a first subset of the plurality of interconnect structures.

IPC Classes  ?

• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices

Abstract

A semiconductor devices include first and second active regions and first and second gate structures. The first gate structure engages the first and second active regions in forming first and second transistors, respectively. The second gate structure engages the first and second active region in forming third and fourth transistors, respectively. The first and third transistors share a first common source/drain region, and the second and fourth transistors share a second common source/drain region. A frontside contact is disposed above and electrically coupled to the first common source/drain region. A frontside contact via is disposed above and electrically coupled to the frontside contact. A frontside metal line is disposed above and electrically coupled to the frontside contact via. A backside via is disposed under and electrically coupled to the second common source/drain region. A backside metal line is disposed under and electrically coupled to the backside via.

IPC Classes  ?

• H10B 10/00 - Static random access memory [SRAM] devices

Abstract

The present disclosure provides a semiconductor structure and a method of forming the same. A semiconductor structure according to the present disclosure includes a plurality of nanostructures disposed over a substrate and a gate structure wrapping around each of the plurality of nanostructure. Each of the plurality of nanostructures includes a channel layer sandwiched between two cap layers along a direction perpendicular to the substrate.

IPC Classes  ?

• H10D 30/67 - Thin-film transistors [TFT]
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H10D 30/01 - Manufacture or treatment
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 64/01 - Manufacture or treatment

Abstract

A dipole layer is formed over a semiconductor channel region. A doped gate dielectric layer is formed over the dipole layer. The doped gate dielectric layer contains an amorphous material. Via an annealing process, the amorphous material of the doped gate dielectric layer is converted into a material with at least partially crystal phases. After the doped gate dielectric layer is converted into the layer with partially crystal phases, a metal-containing gate electrode is formed over the doped gate dielectric layer.

IPC Classes  ?

• H10D 84/85 - Complementary IGFETs, e.g. CMOS
• H10D 64/01 - Manufacture or treatment
• H10D 64/68 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology

Abstract

Embodiments provide a device structure and method of forming a device structure including an infill structure to capture solder materials within confines of openings of the infill structure. Metal pillars of one device can penetrate through a non-conductive film and contact solder regions of another device. A separate underfill is not needed.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

A semiconductor device includes a first and second semiconductor chip having a respective first surface and a second surface opposite to each other. The semiconductor device can include a second semiconductor chip having a third surface and a fourth surface opposite to each other. The third surface of the second semiconductor chip can face the second surface of the first semiconductor chip. A first portion of a dielectric filling material can be in contact with a first sidewall of the first semiconductor chip. A second portion of a dielectric filling material can be in contact with a second sidewall of the second semiconductor chip. The first and second portions of the dielectric filling material can have a width that decreases in a corresponding increasing depth toward the first surface of the first semiconductor chip.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
• H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

In an embodiment, a device includes: a first integrated circuit die including a first device layer and a first front-side interconnect structure, the first front-side interconnect structure including first interconnects interconnecting first devices of the first device layer; a second integrated circuit die including a second device layer and a second front-side interconnect structure, the second front-side interconnect structure including second interconnects interconnecting second devices of the second device layer; and an interposer bonded to a back-side of the first integrated circuit die and to a back-side of the second integrated circuit die, the interposer including a die-to-die interconnect structure, the die-to-die interconnect structure including a pillar, the first integrated circuit die overlapping the pillar.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/42 - Fillings or auxiliary members in containers selected or arranged to facilitate heating or cooling
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

A method includes forming Complementary Field-Effect Transistors including a lower transistor comprising a lower source/drain region, and an upper transistor including an upper source/drain region. An upper dielectric layer over the upper source/drain region and a lower dielectric layer under the upper source/drain region are etched to form an opening. A sidewall of the upper source/drain region and a top surface of the lower source/drain region are exposed to the opening. An epitaxy process is performed to form a first semiconductor layer on the sidewall of the upper source/drain region, and a second semiconductor layer on the top surface of the lower source/drain region. The first semiconductor layer is then removed, a contact plug is formed in the opening to electrically connects the upper source/drain region to the second semiconductor layer and the lower source/drain region.

IPC Classes  ?

• H10D 84/01 - Manufacture or treatment
• H10D 30/43 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 1D charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
• H10D 30/67 - Thin-film transistors [TFT]
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 62/83 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
• H10D 64/01 - Manufacture or treatment
• H10D 64/62 - Electrodes ohmically coupled to a semiconductor
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H10D 84/85 - Complementary IGFETs, e.g. CMOS

Abstract

A circuit includes local computing cells. Each of the local computing cells can provide, in response to identifying that the input data elements and weight data elements are in a first data type, a first sum including (i) a first product of a first input data element and a first weight data element; and (ii) a second product of a second input data element and a second weight data element. Each of the local computing cells can provide, in response to identifying that the input data elements and weight data elements are in a second data type, (i) a second sum of a first portion of a third input data element and a first portion of a third weight data element; and (ii) a third product of a second portion of the third input data element and a second portion of the third weight data element.

IPC Classes  ?

• G06F 7/499 - Denomination or exception handling, e.g. rounding or overflow
• G06F 7/50 - AddingSubtracting

Abstract

Optical devices and methods of manufacture are presented in which optical interposers are formed with facets. In some embodiments a method includes receiving a first optical interposer bonded to a first semiconductor device, attaching a support substrate to the first semiconductor device, forming a facet recess to recess a sidewall of the first optical interposer and expose the support substrate, and forming a first spacer along a sidewall of the first optical interposer after the forming the facet recess.

IPC Classes  ?

• G02B 6/42 - Coupling light guides with opto-electronic elements

Abstract

A ferroelectric memory device and a memory array are provided. The ferroelectric memory device includes a word line; a pair of source/drain electrodes, a channel layer, a work function layer and a ferroelectric layer. The source/drain electrodes are disposed at opposite sides of the word line, and elevated from the word line. The channel layer has a bottom planar portion and wall portions. The bottom planar portion extends along a top surface of the word line, and opposite ends of the bottom planar portion are connected to sidewalls of the source/drain electrodes through opposite ones of the wall portions. The work function layer is electrically connected to the word line, and extends along the bottom planar portion and the wall portions of the channel layer. The ferroelectric layer separates the channel layer from the work function layer.

IPC Classes  ?

• H10B 51/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
• H10B 12/00 - Dynamic random access memory [DRAM] devices
• H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
• H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates

Abstract

A substrate has a first side and a second side opposite the first side. A first transistor has a first gate, a second transistor has a second gate, and a third transistor has a third gate. The first gate, the second gate, and the third gate are each disposed over the first side of the substrate. The second gate is disposed between the first gate and the third gate. The first gate and the third gate have different material compositions. A structure is disposed over the second side of the substrate. The structure includes a first opening aligned with the first transistor, a second opening aligned with the second transistor, and a third opening aligned with the third transistor. A sensing film is disposed over the second side of the substrate. The sensing film is configured to attach to one or more predefined miniature targets.

IPC Classes  ?

• G01N 27/414 - Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS
• G01N 27/327 - Biochemical electrodes

Abstract

In an embodiment, a device includes: a source/drain region adjoining a channel region of a substrate; a contact etch stop layer on the source/drain region; a first source/drain contact extending through the contact etch stop layer, the first source/drain contact connected to the source/drain region; a gate structure on the channel region; a gate contact connected to the gate structure; and a contact spacer around the gate contact, where the contact spacer, the gate structure, the contact etch stop layer, and the substrate collectively define a void between the gate structure and the first source/drain contact.

IPC Classes  ?

• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H10D 30/01 - Manufacture or treatment
• H10D 30/62 - Fin field-effect transistors [FinFET]
• H10D 64/01 - Manufacture or treatment
• H10D 64/23 - Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology

Abstract

Methods and devices that include forming a first epitaxial region and a second epitaxial region above the first epitaxial region. An opening may be formed extending from the first region to the second region. And a liner layer is deposited on a sidewall and a bottom of the opening. A plasma treatment is performed on the liner layer, which can form a conditioned or passivated region of the first epitaxial region that may be maintained during the growth of additional epitaxial material on the second epitaxial region.

IPC Classes  ?

• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H10D 87/00 - Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
• H10D 88/00 - Three-dimensional [3D] integrated devices

Abstract

In an embodiment, a method includes: heating a byproduct transport ring of an extreme ultraviolet source, the byproduct transport ring disposed beneath vanes of the extreme ultraviolet source; after heating the byproduct transport ring for a first duration, heating the vanes; after heating the vanes, cooling the vanes; and after cooling the vanes for a second duration, cooling the byproduct transport ring.

IPC Classes  ?

• G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor
• H05G 2/00 - Apparatus or processes specially adapted for producing X-rays, not involving X-ray tubes, e.g. involving generation of a plasma

Abstract

Methods and devices include a chip package structure, including a first semiconductor die, a second semiconductor die, a redistribution structure, and a first underfill material portion located between the redistribution structure and the first semiconductor die and the second semiconductor die. The redistribution structure includes a first redistribution structure portion physically and electrically connected to the first semiconductor die, a second redistribution structure portion physically and electrically connected to the second semiconductor die, and a dummy bump region positioned between and electrically isolated from the first redistribution structure portion and the second redistribution structure portion.

IPC Classes  ?

• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or

Abstract

Embodiments of the present disclosure provide a semiconductor device structure. The structure includes a substrate comprising a front side, a backside, and a first trench extending from the front side into the substrate. The structure also includes a trench capacitor comprising a plurality of capacitor electrode layers and a plurality of capacitor dielectric layers disposed in alternating manner within the trench and over the front side of the substrate, wherein the plurality of the capacitor electrode layers and the plurality of the capacitor dielectric layers enclose an air gap within the trench, wherein the trench has a first critical dimension measuring at the front side of the substrate, which is gradually decreased to a second critical dimension measuring near a middle part of the trench, and then gradually increased to a third critical dimension measuring at a bottom of the trench.

IPC Classes  ?

• H10D 1/00 - Resistors, capacitors or inductors
• H01L 21/764 - Air gaps
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for
• H10D 1/68 - Capacitors having no potential barriers

Abstract

The present disclosure relates to a memory device that includes a substrate and source and drain regions formed in the substrate. The memory device includes a gate dielectric formed on the substrate and between the source and drain regions. The memory device also includes a gate structure formed on the gate dielectric and the gate structure has a planar top surface. The memory device further includes a multi-spacer structure that includes first, second, and third spacers. The first spacer is formed on a sidewall of the gate structure and a top surface of one of the source and drain regions. The second spacer is formed on a sidewall of the first spacer and the second spacer has a dielectric constant greater than a dielectric constant of the first spacer. The third spacer is formed on a sidewall of the second spacer and a horizontal surface of the first spacer.

IPC Classes  ?

• H10B 43/30 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
• H10D 30/69 - IGFETs having charge trapping gate insulators, e.g. MNOS transistors
• H10D 64/01 - Manufacture or treatment

Abstract

A semiconductor device structure and a formation method are provided. The method includes forming a sacrificial base layer over a substrate and forming a semiconductor stack over the sacrificial base layer. The semiconductor stack has multiple sacrificial layers and multiple semiconductor layers laid out alternately. The method also includes forming a gate stack to partially cover the sacrificial base layer, the semiconductor layers, and the sacrificial layers. The method further includes removing the sacrificial base layer to form a recess between the substrate and the semiconductor stack. In addition, the method includes forming a metal-containing dielectric structure to partially or completely fill the recess. The metal-containing dielectric structure has multiple sub-layers.

IPC Classes  ?

• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/762 - Dielectric regions
• H10D 30/01 - Manufacture or treatment
• H10D 30/67 - Thin-film transistors [TFT]
• H10D 64/01 - Manufacture or treatment

Abstract

A method includes forming a composite package substrate. The formation of the composite package substrate includes encapsulating an interconnect die in an encapsulant, with the interconnect die including a plurality of through-vias therein, and forming a first plurality of redistribution lines (RDLs) and a second plurality of RDLs on opposite sides of the interconnect die. The method further includes bonding an organic package substrate to the composite package substrate, and bonding a first package component and a second package component to the first plurality of RDLs. The first package component and the second package component are electrically interconnected through the interconnect die and the first plurality of RDLs.

IPC Classes  ?

• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
• H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

Abstract

Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a first semiconductor stack and a second semiconductor stack over a substrate, wherein each of the first and second semiconductor stacks includes semiconductor layers stacked up and separated from each other; a dummy spacer between the first and second semiconductor stacks, wherein the dummy spacer contacts a first sidewall of each semiconductor layer of the first and second semiconductor stacks; and a gate structure wrapping a second sidewall, a top surface, and a bottom surface of each semiconductor layer of the first and second semiconductor stacks.

IPC Classes  ?

• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H10D 30/01 - Manufacture or treatment
• H10D 30/62 - Fin field-effect transistors [FinFET]
• H10D 84/01 - Manufacture or treatment
• H10D 84/85 - Complementary IGFETs, e.g. CMOS

Abstract

In an embodiment, a package includes an interposer; a first integrated circuit device attached to the interposer, wherein the first integrated circuit device includes a die and a heat dissipation structure, the die having an active surface facing the interposer and an inactive surface opposite to the active surface, the heat dissipation structure attached to the inactive surface of the die and including a plurality of channels recessed from a first surface of the heat dissipation structure, the first surface of the heat dissipation structure facing away from the die; and an encapsulant disposed on the interposer and laterally around the die and the heat dissipation structure, wherein a top surface of the encapsulant is coplanar with the top surface of the heat dissipation structure.

IPC Classes  ?

• H01L 23/473 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing liquids
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or

Abstract

A method of forming a semiconductor device includes: forming a fin structure that protrudes above a substrate, where the fin structure includes a fin and a layer stack overlying the fin, where the layer stack includes alternating layers of a first semiconductor material and a second semiconductor material; forming a gate structure over the fin structure; forming source/drain openings in the fin structure on opposing sides of the gate structure; replacing first end portions of the first semiconductor material exposed by the source/drain openings with inner spacers; after the replacing, performing an ion implantation process, where the ion implantation process implants a first dopant into second end portions of the second semiconductor material exposed by the source/drain openings; and after performing the ion implantation process, forming source/drain regions in the source/drain openings.

IPC Classes  ?

• H10D 30/01 - Manufacture or treatment
• H01L 21/225 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regionsRedistribution of impurity materials, e.g. without introduction or removal of further dopant using diffusion into, or out of, a solid from or into a solid phase, e.g. a doped oxide layer
• H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
• H10D 30/43 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 1D charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
• H10D 30/67 - Thin-film transistors [TFT]
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 62/13 - Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
• H10D 64/01 - Manufacture or treatment

Abstract

An exemplary testing environment can operate in a testing mode of operation to test whether a memory device or other electronic devices communicatively coupled to the memory device operate as expected or unexpectedly as a result of one or more manufacturing faults. The testing mode of operation includes a shift mode of operation, a capture mode of operation, and/or a scan mode of operation. In the shift mode of operation and the scan mode of operation, the exemplary testing environment delivers a serial input sequence of data to the memory device. In the capture mode of operation, the exemplary testing environment delivers a parallel input sequence of data to the memory device. The memory device thereafter passes through the serial input sequence of data or the parallel input sequence of data to provide an output sequence of data in the shift mode of operation or the capture mode of operation or passes through the serial input sequence of data to provide a serial output sequence of scan data in the scan mode of operation.

IPC Classes  ?

• G06F 11/263 - Generation of test inputs, e.g. test vectors, patterns or sequences
• G06F 1/10 - Distribution of clock signals
• G06F 11/22 - Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
• G06F 11/267 - Reconfiguring circuits for testing, e.g. LSSD, partitioning
• G11C 29/12 - Built-in arrangements for testing, e.g. built-in self testing [BIST]
• G11C 29/32 - Serial accessScan testing
• G11C 29/48 - Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths

Abstract

A method includes removing a dummy gate stack to form a trench between gate spacers, depositing a gate dielectric extending into the trench, and performing a first treatment process on the gate dielectric. The first treatment process is performed using a fluorine-containing gas. A first drive-in process is then performed to drive fluorine in the fluorine-containing gas into the gate dielectric. The method further includes performing a second treatment process on the gate dielectric, wherein the second treatment process is performed using the fluorine-containing gas, and performing a second drive-in process to drive fluorine in the fluorine-containing gas into the gate dielectric. After the second drive-in process, conductive layers are formed to fill the trench.

IPC Classes  ?

• H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H10D 30/01 - Manufacture or treatment
• H10D 30/67 - Thin-film transistors [TFT]
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 64/01 - Manufacture or treatment

Abstract

A method includes forming a gate stack, growing a source/drain region on a side of the gate stack through epitaxy, depositing a contact etch stop layer (CESL) over the source/drain region, depositing an inter-layer dielectric over the CESL, etching the inter-layer dielectric and the CESL to form a contact opening, and etching the source/drain region so that the contact opening extends into the source/drain region. The method further includes depositing a metal layer extending into the contact opening. Horizontal portions, vertical portions, and corner portions of the metal layer have a substantially uniform thickness. An annealing process is performed to react the metal layer with the source/drain region to form a source/drain silicide region. The contact opening is filled to form a source/drain contact plug.

IPC Classes  ?

• H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/3065 - Plasma etchingReactive-ion etching
• H01L 21/311 - Etching the insulating layers
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H10D 30/01 - Manufacture or treatment
• H10D 30/67 - Thin-film transistors [TFT]
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 62/13 - Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
• H10D 64/01 - Manufacture or treatment
• H10D 64/23 - Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
• H10D 64/62 - Electrodes ohmically coupled to a semiconductor
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology

Abstract

A device structure according to the present disclosure may include a first die having a first substrate and a first interconnect structure, a second die having a second substrate and a second interconnect structure, and a third die having a third interconnect structure and a third substrate. The first interconnect structure is bonded to the second substrate via a first plurality of bonding layers. The second interconnect structure is bonded to the third interconnect structure via a second plurality of bonding layers. The third substrate includes a plurality of photodiodes and a first transistor. The second die includes a second transistor having a source connected to a drain of the first transistor, a third transistor having a gate connected to drain of the first transistor and the source of the second transistor, and a fourth transistor having a drain connected to the source of the third transistor.

IPC Classes  ?

• H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
• H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors

Abstract

A bonded assembly including a first structure and a second structure is provided. The first structure includes first metallic connection structures surrounded of which a passivation dielectric layer includes openings therein, and first metallic bump structures having a respective first horizontal bonding surface segment that is vertically recessed from a first horizontal plane including a distal horizontal surface of the passivation dielectric layer. The second structure includes second metallic bump structures having a respective second horizontal bonding surface segment that protrudes toward the first structure. The first metallic bump structures is bonded to the second metallic bump structures through solder material portions.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

The present disclosure relates to an integrated chip including a bottom electrode arranged within a dielectric layer. A memory element is directly over the bottom electrode and is arranged within the dielectric layer. A top electrode is directly over the memory element and is arranged within the dielectric layer. A conductive via is directly over the top electrode. A pair of lines that extend along opposing sidewalls of the top electrode are directly over, and intersect, an uppermost surface of the memory element. The pair of lines are directly under, and intersect, a lowermost surface of the via.

IPC Classes  ?

• H10N 50/80 - Constructional details
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• H10N 50/01 - Manufacture or treatment
• H10N 50/10 - Magnetoresistive devices

Abstract

A semiconductor device and method of manufacture are provided which utilize a remote plasma process which reduces or eliminates segregation of material. By reducing segregation of the material, overlying conductive material can be deposited on a smoother interface. By depositing on smoother interfaces, overall losses of the deposited material may be avoided, which improves the overall yield.

IPC Classes  ?

• H10D 64/01 - Manufacture or treatment
• H01L 21/311 - Etching the insulating layers
• H01L 21/3215 - Doping the layers
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
• H10D 30/62 - Fin field-effect transistors [FinFET]
• H10D 62/83 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
• H10D 64/62 - Electrodes ohmically coupled to a semiconductor

Abstract

A method includes forming a source/drain region, forming a dielectric layer over the source/drain region, and etching the dielectric layer to form a contact opening. The source/drain region is exposed to the contact opening. The method further includes depositing a dielectric spacer layer extending into the contact opening, etching the dielectric spacer layer to form a contact spacer in the contact opening, implanting a dopant into the source/drain region through the contact opening after the dielectric spacer layer is deposited, and forming a contact plug to fill the contact opening.

IPC Classes  ?

• H10D 30/62 - Fin field-effect transistors [FinFET]
• H10D 30/01 - Manufacture or treatment
• H10D 64/01 - Manufacture or treatment
• H10D 64/23 - Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H10D 84/85 - Complementary IGFETs, e.g. CMOS

Abstract

A method includes forming a first capacitor electrode; forming a first oxygen-blocking layer on the first capacitor electrode; forming an capacitor insulator layer on the first oxygen-blocking layer; forming a second oxygen-blocking layer on the capacitor insulator layer; forming a second capacitor electrode on the second oxygen-blocking layer; and forming a first contact plug that is electrically coupled to the first capacitor electrode and a second contact plug that is electrically coupled to the second capacitor electrode.

IPC Classes  ?

• H10D 1/00 - Resistors, capacitors or inductors
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H10D 1/68 - Capacitors having no potential barriers

Abstract

An embodiment interfacial bonding test structure may include a first substrate having a first planar surface, a second substrate having a second planar surface that is parallel to the first planar surface, a first semiconductor die, and a second semiconductor die, each semiconductor die bonded between the first substrate and the second substrate thereby forming a sandwich structure. The first semiconductor die and the second semiconductor die may be bonded to the first surface with a first adhesive and may be bonded to the second surface with a second adhesive. The first semiconductor die and the second semiconductor die may be displaced from one another by a first separation along a direction parallel to the first planar surface and the second planar surface. The second substrate may include a notch having an area that overlaps with an area of the first separation in a plan view.

IPC Classes  ?

• G01N 3/20 - Investigating strength properties of solid materials by application of mechanical stress by applying steady bending forces
• G01N 19/04 - Measuring adhesive force between materials, e.g. of sealing tape, of coating

Abstract

An integrated circuit includes a first nanostructure transistor and a second nanostructure transistor on a substrate. The source/drain regions of the first nanostructure are electrically isolated from the semiconductor substrate by bottom dielectric regions. The source/drain regions of the second nanostructure transistor in direct contact with the semiconductor substrate.

IPC Classes  ?

• H10D 30/67 - Thin-film transistors [TFT]
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]

Abstract

A device package includes a first die comprising a semiconductor substrate; an isolation layer on the semiconductor substrate, wherein the isolation layer is a first dielectric material; a first dummy via penetrating through the isolation layer and into the semiconductor substrate; a bonding layer on the isolation layer, wherein the bonding layer is a second dielectric material that has a smaller thermal conductivity than the first dielectric material; a first dummy pad within the bonding layer and on the first dummy via; a dummy die directly bonded to the bonding layer; a second die directly bonded to the bonding layer and to the first dummy pad; and a metal gap-fill material between the dummy die and the second die.

IPC Classes  ?

• H01L 23/367 - Cooling facilitated by shape of device
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/373 - Cooling facilitated by selection of materials for the device
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

In an embodiment, a method includes forming a device region along a first substrate; forming an interconnect structure over the device region and the first substrate; forming a metal pillar over the interconnect structure, forming the metal pillar comprising: forming a base layer over the interconnect structure; forming an intermediate layer over the base layer; and forming a capping layer over the intermediate layer; forming a solder region over the capping layer; and performing an etch process to recess sidewalls of the base layer and the capping layer from sidewalls of the intermediate layer and the solder region.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

Abstract

A method of manufacturing an integrated circuit (IC) includes generating first and second active region shapes extending in a first direction, the second active region shape separated from the first active region shape in a second direction. The method includes generating first and second sets of gate structure shapes extending in the second direction and overlapping the first and second active region shapes. The method includes generating a first conductive shape and a second conductive shape extending in the first direction, the first conductive shape overlapping the first active region shape, and the second conductive shape overlapping the second active region shape. The method includes generating a third conductive shape, the third conductive shape extending in the second direction and overlapping the first conductive shape and the second conductive shape. The method includes generating a fourth conductive shape extending in the first direction and overlapping the third conductive shape.

IPC Classes  ?

• G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

Abstract

A source/drain component is disposed over an active region and surrounded by a dielectric material. A source/drain contact is disposed over the source/drain component. The source/drain contact includes a conductive capping layer and a conductive material having a different material composition than the conductive capping layer. The conductive material has a recessed bottom surface that is in direct contact with the conductive capping layer. A source/drain via is disposed over the source/drain contact. The source/drain via and the conductive material have different material compositions. The conductive capping layer contains tungsten, the conductive material contains molybdenum, and the source/drain via contains tungsten.

IPC Classes  ?

• H10D 30/62 - Fin field-effect transistors [FinFET]
• H10D 30/01 - Manufacture or treatment
• H10D 30/43 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 1D charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
• H10D 30/67 - Thin-film transistors [TFT]
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]

Abstract

A method includes forming a first fin and a second fin protruding from a substrate; forming an isolation layer surrounding the first fin and the second fin; epitaxially growing a first epitaxial region on the first fin and a second epitaxial region on the second fin, wherein the first epitaxial region and the second epitaxial region are merged together; performing an etching process on the first epitaxial region and the second epitaxial region, wherein the etching process separates the first epitaxial region from the second epitaxial region; depositing a dielectric material between the first epitaxial region and the second epitaxial region; and forming a first gate stack extending over the first fin.

IPC Classes  ?

• H10D 30/01 - Manufacture or treatment
• H10D 30/62 - Fin field-effect transistors [FinFET]
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]

Abstract

The present disclosure, in some embodiments, relates to a method of forming a capacitor structure. The method includes forming a capacitor dielectric layer over a lower electrode layer, and forming an upper electrode layer over the capacitor dielectric layer. The upper electrode layer is etched to define an upper electrode and to expose a part of the capacitor dielectric layer. A spacer structure is formed over horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and also along sidewalls of the upper electrode. The spacer structure is etched to remove the spacer structure from over the horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and to define a spacer. The capacitor dielectric layer and the lower electrode layer are etched according to the spacer to define a capacitor dielectric and a lower electrode.

IPC Classes  ?

• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H10D 1/00 - Resistors, capacitors or inductors
• H10D 1/68 - Capacitors having no potential barriers

Abstract

Semiconductor structures and methods are provided. An exemplary method includes receiving a structure comprising a metal feature, a first passivation structure over the metal feature, and a first opening extending through the first passivation structure and exposing the metal feature. The exemplary method also includes forming a conductive layer in the first opening; forming a second passivation structure over the conductive layer, performing a first etching process to form a second opening extending through the second passivation structure and exposing the conductive layer, performing a second etching process to selectively remove an upper portion of the second passivation structure to enlarge an upper portion of the second opening, and after the performing of the second etching process, forming a conductive feature in the second opening.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

A metallization structure is formed over an integrated circuit (IC) substrate from a first side. A patterning process is performed to the metallization structure from the first side. The metallization structure is patterned into a plurality of metallization islands by the patterning process. A plurality of metal-containing structures is formed over the plurality of the metallization islands, respectively, from the first side. A second side of the IC substrate is coupled to an organic substrate. The second side is opposite the first side.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
• H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

Abstract

Methods of forming vias for coupling source/drain regions to backside interconnect structures in semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a semiconductor device includes a conductive feature adjacent a gate structure; a dielectric layer on the conductive feature and the gate structure; a metal via embedded in the dielectric layer; and a liner layer between and in contact with the metal via and the dielectric layer, the liner layer being boron nitride.

IPC Classes  ?

• H01L 23/528 - Layout of the interconnection structure
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
• H10D 30/67 - Thin-film transistors [TFT]
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies

Abstract

An optical device and methods of manufacturing such optical devices are presented. In embodiments the optical device is a tunable beam splitter which is made by forming a first dopant region over a substrate, the first dopant region comprising a first waveguide and a second waveguide, depositing a cladding material over the first waveguide and the second waveguide, and forming a second dopant region overlying the first waveguide and the second waveguide, wherein the forming the second dopant region comprises forming a first region extending over both the first waveguide and the second waveguide, the first region having a constant concentration of a first dopant.

IPC Classes  ?

• G02F 1/025 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour based on semiconductor elements having potential barriers, e.g. having a PN or PIN junction in an optical waveguide structure
• G02F 1/015 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour based on semiconductor elements having potential barriers, e.g. having a PN or PIN junction

Abstract

A sacrificial layer is formed over a first channel structure of an N-type transistor (NFET) and over a second channel structure of a P-type transistor (PFET). A PFET patterning process is performed at least in part by etching away the sacrificial layer in the PFET while protecting the NFET from being etched. After the PFET patterning process has been performed, a P-type work function (WF) metal layer is deposited in both the NFET and the PFET. An NFET patterning process is performed at least in part by etching away the P-type WF metal layer and the sacrificial layer in the NFET while protecting the PFET from being etched. After the NFET patterning process has been performed, an N-type WF metal layer is deposited in both the NFET and the PFET.

IPC Classes  ?

• H10D 84/85 - Complementary IGFETs, e.g. CMOS
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
• H10D 30/01 - Manufacture or treatment
• H10D 30/43 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 1D charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
• H10D 30/67 - Thin-film transistors [TFT]
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology

Abstract

A method of manufacturing a semiconductor device includes: forming first through fourth active regions extending in parallel in a substrate; forming a first gate electrode and a first conductive pattern each extending across each of the first through fourth active regions; forming a first plurality of vias overlying the first gate electrode; forming a second plurality of vias overlying the first conductive pattern; and electrically connecting the first gate electrode in parallel with the first conductive pattern through the first and second pluralities of vias.

IPC Classes  ?

• H01L 23/528 - Layout of the interconnection structure
• G03F 1/36 - Masks having proximity correction featuresPreparation thereof, e.g. optical proximity correction [OPC] design processes
• G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
• G06F 119/12 - Timing analysis or timing optimisation
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials

Abstract

A package includes a package substrate, the package substrate having a first side and a second side opposite to the first side, a package component bonded to the first side of the package substrate, a front-side warpage control structure attached to the first side of the package substrate, and a backside warpage control structure embedded in the package substrate from the second side of the package substrate. The front-side warpage control structure includes a first disconnected structure and a second disconnected structure laterally separated from each other by a gap. The backside warpage control structure includes a third disconnected structure and a fourth disconnected structure laterally separated from each other.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/498 - Leads on insulating substrates
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

Package structures and methods of forming package structures are discussed. A package structure, in accordance with some embodiments, includes a package component with one or more integrated circuits adhered to a package substrate, a hybrid thermal interface material utilizing a combination of polymer based material with high elongation values and metal based material with high thermal conductivity values. The polymer based thermal interface material placed on the edge of the package component contains the metal based thermal interface material in liquid form.

IPC Classes  ?

• H01L 23/427 - Cooling by change of state, e.g. use of heat pipes
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/498 - Leads on insulating substrates
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

Embodiments of the present disclosure provide a magnetic tunnel junction (MTJ) structure for storing a data. In one embodiment, the MJT structure includes a first ferromagnetic layer, a second ferromagnetic layer disposed above the first ferromagnetic layer, a first dielectric layer disposed between and in contact with the first ferromagnetic layer and the second ferromagnetic layer, a plurality of metal particles disposed in contact with the second ferromagnetic layer, wherein the metal particles are distributed in a discrete and non-continuous manner, and a second dielectric layer disposed over the plurality of metal particles.

IPC Classes  ?

• H10N 50/80 - Constructional details
• H01F 10/32 - Spin-exchange-coupled multilayers, e.g. nanostructured superlattices
• H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• H10N 50/01 - Manufacture or treatment

Abstract

A method includes forming a pad layer. The pad layer includes a first portion over a first part of a semiconductor substrate, and a second portion over a second part of the semiconductor substrate. The first portion has a first thickness, and the second portion has a second thickness smaller than the first thickness. The semiconductor substrate is then annealed to form a first oxide layer over the first part of the semiconductor substrate, and a second oxide layer over the second part of the semiconductor substrate. The pad layer, the first oxide layer, and the second oxide layer are removed. A semiconductor layer is epitaxially grown over and contacting the first part and the second part of the semiconductor substrate.

IPC Classes  ?

• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
• H01L 21/266 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation using masks
• H01L 21/311 - Etching the insulating layers
• H01L 21/66 - Testing or measuring during manufacture or treatment
• H10D 84/01 - Manufacture or treatment
• H10D 84/85 - Complementary IGFETs, e.g. CMOS

Abstract

A semiconductor structure is provided. The semiconductor structure includes a first gate stack wrapping around first nanostructures, a second gate stack wrapping around second nanostructures, a gate isolation structure interposing between the first gate stack and the second gate stack, a first source/drain feature adjoining the first nanostructures, a second source/drain feature adjoining the second nanostructures, and a source/drain spacer structure interposing between the first source/drain feature and the second source/drain feature. The gate isolation structure covers a sidewall of the source/drain spacer structure.

IPC Classes  ?

• H10D 30/67 - Thin-film transistors [TFT]
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H10D 30/01 - Manufacture or treatment
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 64/01 - Manufacture or treatment