An apparatus (100) may include a first node (104) coupled to a first terminal, the first terminal to receive a first control signal (S_IN); a second node (102) coupled to a second terminal, the second terminal to receive a second control signal (H_IN); a first capacitor (CO) having a first plate coupled to the first node and a second plate coupled to a first output terminal (H); a second capacitor (Cl) having a first plate coupled to the second node and a second plate coupled to a second output terminal (S); a first stack of transistors (M223, M24, M25) coupled between a positive supply terminal (POS through M2, X0) and a common mode terminal (CM), the first stack operable to divide voltage: and a second stack of transistors (M5, M4, M3) coupled between a negative supply terminal (NEG through M1, X10) and the common mode terminal (CM), the second stack operable to divide voltage.
An apparatus may include a first node coupled to a first terminal, the first terminal to receive a first control signal; a second node coupled to a second terminal, the second terminal to receive a second control signal; a first capacitor having a first plate coupled to the first node and a second plate coupled to a first output terminal; a second capacitor having a first plate coupled to the second node and a second plate coupled to a second output terminal; a first stack of transistors coupled between a positive supply terminal and a common mode terminal, the first stack operable to divide voltage; and a second stack of transistors coupled between a negative supply terminal and the common mode terminal, the second stack operable to divide voltage.
A job manager may receive a request for a design of a semiconductor device to be verified by a set of computing devices, wherein the request comprises design parameters regarding the design of the semiconductor device. The job manager may provide the design parameters as inputs to a machine learning model trained to predict amounts of computational resources and amounts of compute time for verifying designs of semiconductor devices. The job manager may obtain, as an output from the machine learning model, a predicted amount of computational resources and a predicted amount of compute time for verifying the design of the semiconductor device. The job manager may determine an availability of resources, of the set of computing devices, for verifying the design of the semiconductor device. The job manager may cause the design of the semiconductor device to be verified by one or more computing devices.
G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
4.
APPARATUS FORMED FROM ELECTRONIC COMPONENTS HAVING DIFFERENT RESPECTIVE THICKNESSES AND METHODS OF FORMING AN APPARATUS FROM ELECTRONIC COMPONENTS HAVING DIFFERENT RESPECTIVE THICKNESSES
An apparatus includes a pair of substrates with conductive material formed on portions of inwardly facing surfaces thereof, and a step formed in or on the conductive material on one of the pair of substrates. A lead frame having leads and electronic components having different respective thicknesses are mounted between the conductive materials on the pair of substrates. The step has a step thickness dimensioned to facilitate electrical contact between a thickest one of the electronic components or the leads with the step in the conductive material on one of the pair of substrates and the conductive material on the one other of the pair of substrates. An electrical signal path is formed between the electronic components or the leads disposed in electrical contact with the step and the conductive material on the one other of the pair of substrates.
H01L 23/373 - Cooling facilitated by selection of materials for the device
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
5.
APPARATUS FORMED FROM ELECTRONIC COMPONENTS HAVING DIFFERENT RESPECTIVE THICKNESSES AND METHODS OF FORMING AN APPARATUS FROM ELECTRONIC COMPONENTS HAVING DIFFERENT RESPECTIVE THICKNESSES
An apparatus includes a pair of substrates with conductive material formed on portions of inwardly facing surfaces thereof, and a step formed in or on the conductive material on one of the pair of substrates. A lead frame having leads and electronic components having different respective thicknesses are mounted between the conductive materials on the pair of substrates. The step has a step thickness dimensioned to facilitate electrical contact between a thickest one of the electronic components or the leads with the step in the conductive material on one of the pair of substrates and the conductive material on the one other of the pair of substrates. An electrical signal path is formed between the electronic components or the leads disposed in electrical contact with the step and the conductive material on the one other of the pair of substrates.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
A FinFET device that may include a substrate (20). A drain layer (30) on a first side of the substrate. A drift layer (40) on a second side of the substrate. The drift layer having a fin-shaped portion (50) and a recessed portion. A doped-well layer (70) over the recessed portion of the drift layer and along sides of the fin-shaped portion of the drift layer. A body layer (80) and a source layer (90) formed over a portion of the doped-well layer over the recessed portion of the drift layer. An insulating layer (75) over the doped-well layer. A gate electrode (110) over the insulating layer.
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
A FinFET device that may include a substrate. A drain layer on a first side of the substrate. A drift layer on a second side of the substrate. The drift layer having a fin-shaped portion and a recessed portion. A doped-well layer over the recessed portion of the drift layer and along sides of the fin-shaped portion of the drift layer. A body layer and a source layer formed over a portion of the doped-well layer over the recessed portion of the drift layer. An insulating layer over the doped-well layer. A gate electrode over the insulating layer.
A FinFET device that may include a substrate. A drain layer on a first side of the substrate. A drift layer on a second side of the substrate. The drift layer having a fin-shaped portion and a recessed portion. A doped-well layer over the fin-shaped portion of the drift layer. An insulating layer over the doped-well layer and over the recessed portion of the drift layer. A gate electrode over the insulating layer.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 21/336 - Field-effect transistors with an insulated gate
9.
SYSTEM AND METHODS FOR PHYSICAL IDENTIFICATION OF MANUFACTURED PRODUCTS
A manufactured product may include a machine-readable physical identifier and the machine-readable physical identifier may be stored in a tracking file. The machine-readable physical identifier may be encoded with manufacturing information related to the manufactured product, including but not limited to manufacturing location, lot number and manufacturing date. The tracking file may be updated based on one or more supply chain operations, including but not limited to a testing operation, a shipping operation or a delivery operation. The tracking file may include information on testing results, shipping origin and destinations and delivery locations. The tracking file may be delivered to a customer along with the manufactured products listed in the tracking file.
A FinFET device that may include a substrate. A drain layer on a first side of the substrate. A drift layer on a second side of the substrate. The drift layer having a fin-shaped portion and a recessed portion. A doped-well layer over the fin-shaped portion of the drift layer. An insulating layer over the doped-well layer and over the recessed portion of the drift layer. A gate electrode over the insulating layer.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
A manufactured product may include a machine-readable physical identifier and the machine-readable physical identifier may be stored in a tracking file. The machine-readable physical identifier may be encoded with manufacturing information related to the manufactured product, including but not limited to manufacturing location, lot number and manufacturing date. The tracking file may be updated based on one or more supply chain operations, including but not limited to a testing operation, a shipping operation or a delivery operation. The tracking file may include information on testing results, shipping origin and destinations and delivery locations. The tracking file may be delivered to a customer along with the manufactured products listed in the tracking file.
G06Q 10/06 - Resources, workflows, human or project managementEnterprise or organisation planningEnterprise or organisation modelling
G06K 19/06 - Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
G06Q 10/08 - Logistics, e.g. warehousing, loading or distributionInventory or stock management
A circuit to suppress ringing in a Controller Area Network (CAN) bus having a CAN high (CANH) wire and a CAN low (CANL) wire is provided. The circuit may include processing circuitry to generate a CAN control signal, and a transconductance amplifier to receive a first input signal corresponding to the CAN control signal and a voltage signal from the CANL wire, and to generate an output current signal based on a difference between the first input signal and the voltage signal from the CANL wire. An output terminal of the transconductance amplifier may be coupled to the CANH wire to source current to or sink current from the CANH wire.
A system includes one or more processing units adapted to generate, using a first encryption key, a first set of round keys for rounds of an advanced encryption standard (AES) algorithm; generate, using a second encryption key, a second set of round keys; and determine different addresses, of a plurality of memory devices, for the first and second sets of round keys; and store the first and second sets of round keys in the different addresses, wherein the first round key is stored in a memory device, of the plurality of memory devices, using a first port of the memory device, and wherein the memory device is a dual port memory device that includes the first port and a second port.
H04L 9/06 - Arrangements for secret or secure communicationsNetwork security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
14.
High Electron Mobility Transistor and Method for Manufacturing Same
A High-Electron-Mobility-Transistor that may include a substrate with a buffer layer formed on the substrate. A recess formed in the buffer layer. A barrier layer formed on the buffer layer. A gate recess formed in the barrier layer, the gate recess overlaps the recess in the buffer layer. A drain terminal formed at a first side of the barrier layer. A source terminal formed at a second side of the barrier layer. An isolation structure formed within the gate recess proximate the drain terminal. A doped structure formed adjacent to the isolation structure within the gate recess proximate the source terminal. A gate terminal formed on the doped structure.
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
15.
TERMINATION STRUCTURE FOR A SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
A termination structure for a semiconductor device that may include a substrate having a first type dopant. A plurality of doped-wells having a second type dopant formed in the substrate. A plurality of trenches formed into the plurality of doped-wells, respective ones of the formed trenches exposing a bottom surface of the doped-well, and exposing side surfaces of the doped-well, and a material within respective ones of the formed trenches, wherein the material in respective ones of the formed trenches is surrounded by the exposed bottom surface of the doped-well of the respective formed trench and the exposed side surfaces of the doped-well of the respective formed trench.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
16.
HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD FOR MANUFACTURING SAME
A High-Electron-Mobility-Transistor includes a substrate (20) with a buffer layer (30) formed on the substrate. A recess (50) is formed in the buffer layer. A barrier layer (40) is formed on the buffer layer. A gate recess (55) is formed in the barrier layer, wherein the gate recess overlaps the recess in the buffer layer. A drain terminal (60) is formed at a first side of the barrier layer. A source terminal (70) is formed at a second side of the barrier layer. An isolation structure (80) is formed within the gate recess proximate the drain terminal. A doped structure (90) is formed adjacent to the isolation structure within the gate recess proximate the source terminal. A gate terminal (100) is formed on the doped structure.
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H10D 62/17 - Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
17.
DETERMINING PHYSICAL ADDRESSES OF MEMORY DEVICES USING DIVISION BY PRIME NUMBERS
A processing unit, associated with a host device, adapted to receive a request to calculate a first physical address of an external device based on a second physical address of the host device; determine a tree of parallel adders corresponding to the division operation; obtain an output value from the tree of parallel adders based on the input values; and calculate the first physical address using the output value. The first physical address of the external device is to be calculated based on a division operation that divides the second physical address by a divisor. The tree of parallel adders is determined based on input values that include a number of bits of the second physical address and a divisor.
A Controller Area Network (CAN) bus driver for driving a CAN bus is provided. The bus driver may include a first translinear loop circuit to receive an input voltage and output a first output current signal corresponding to an exponential function, a second translinear loop circuit to receive the input voltage and output a second output current signal corresponding to a hyperbolic function, a divider circuit to output a divided output current signal corresponding to the first output current signal divided by the second output current signal, a CAN Lo driver circuit to output the divided output current signal to a CAN Lo wire of the CAN bus, and a CAN Hi driver circuit to output the divided output current signal to a CAN Hi wire of the CAN bus.
A transistor comprising a drain layer, a drift layer over the drain layer, a channel layer over the drift layer, and a source layer over the channel layer. A trench formed through the source layer, through the channel layer and into at least partially the drift layer. A gate formed within the trench.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 21/266 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation using masks
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A termination structure for a semiconductor device that may include a substrate having a first type dopant. A plurality of doped-wells having a second type dopant formed in the substrate. A plurality of trenches formed into the plurality of doped-wells, respective ones of the formed trenches exposing a bottom surface of the doped-well, and exposing side surfaces of the doped-well, and a material within respective ones of the formed trenches, wherein the material in respective ones of the formed trenches is surrounded by the exposed bottom surface of the doped-well of the respective formed trench and the exposed side surfaces of the doped-well of the respective formed trench.
A processing unit, associated with a host device, adapted to receive a request to calculate a first physical address of an external device based on a second physical address of the host device; determine a tree of parallel adders corresponding to the division operation; obtain an output value from the tree of parallel adders based on the input values; and calculate the first physical address using the output value. The first physical address of the external device is to be calculated based on a division operation that divides the second physical address by a divisor. The tree of parallel adders is determined based on input values that include a number of bits of the second physical address and a divisor.
A transistor comprising a drain layer, a drift layer over the drain layer, a channel layer over the drift layer, and a source layer over the channel layer. A trench formed through the source layer, through the channel layer and into at least partially the drift layer. A gate formed within the trench.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 21/336 - Field-effect transistors with an insulated gate
23.
STORING AND PROVIDING ACCESS TO ROUND KEYS OF ADVANCED ENCRYPTION STANDARD USING DUAL PORT MEMORY DEVICES
A system includes one or more processing units adapted to generate, using a first encryption key, a first set of round keys for rounds of an advanced encryption standard (AES) algorithm; generate, using a second encryption key, a second set of round keys; and determine different addresses, of a plurality of memory devices, for the first and second sets of round keys; and store the first and second sets of round keys in the different addresses, wherein the first round key is stored in a memory device, of the plurality of memory devices, using a first port of the memory device, and wherein the memory device is a dual port memory device that includes the first port and a second port.
G06F 21/79 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
24.
CONTROLLER AREA NETWORK (CAN) BUS DRIVER USING TRANSLINEAR LOOPS
A Controller Area Network (CAN) bus driver for driving a CAN bus is provided. The bus driver may include a first translinear loop circuit to receive an input voltage and output a first output current signal corresponding to an exponential function, a second translinear loop circuit to receive the input voltage and output a second output current signal corresponding to a hyperbolic function, a divider circuit to output a divided output current signal corresponding to the first output current signal divided by the second output current signal, a CAN Lo driver circuit to output the divided output current signal to a CAN Lo wire of the CAN bus, and a CAN Hi driver circuit to output the divided output current signal to a CAN Hi wire of the CAN bus.
H03K 17/60 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being bipolar transistors
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
25.
TRANSMISSION OF SIGNALS FOR RANGING, TIMING, AND DATA TRANSFER
A method is disclosed. In various examples, the method may include receiving an instruction for generating a ranging signal, and transmitting the ranging signal at least partially responsive to the instruction. In various examples the ranging signal may be transmitted via a terrestrial transmitter for transmitting radio waves having encoded messaging information and timing information for one or more of positioning, navigation and timing. In various examples, the ranging signal may exhibit a first ranging pulse and a second ranging pulse of a pulse group and an encoded transmitter identifier, the transmitter identifier encoded by modulating an inter-pulse interval defined between a start of the first ranging pulse and a start of the second ranging pulse.
G01S 1/04 - Beacons or beacon systems transmitting signals having a characteristic or characteristics capable of being detected by non-directional receivers and defining directions, positions, or position lines fixed relatively to the beacon transmittersReceivers co-operating therewith using radio waves Details
26.
TRENCH POWER SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
A trench power semiconductor device comprising a silicon carbide drain layer, a silicon carbide drift layer over the silicon carbide drain layer and a first silicon layer over the silicon carbide drift layer. A second silicon layer over the first silicon layer with a source silicon carbide layer over the second silicon layer. A trench formed through the source silicon carbide layer, through the second silicon layer and into at least partially the first silicon layer. A gate terminal contact formed on the trench with a drain terminal contact formed on the silicon carbide drain layer.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/165 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group in different semiconductor regions
27.
IDENTIFYING WORDLINES SUSCEPTIBLE TO DEEPER ERASE CONDITIONS
In some implementations, a controller may identify a block of a memory device that is scheduled for an erase operation. The controller may determine, using a machine learning model or a data structure, whether a wordline of the block is susceptible to a deeper erase condition before the erase operation. The data structure identifies wordlines that are susceptible to deeper erase conditions. The controller may perform a programming operation, on the wordline, to program a predetermined bit pattern on the wordline based on the wordline being susceptible to the deeper erase condition. The controller may perform the erase operation on the block after performing the programming operation.
An apparatus includes a clock signal input, a sampling circuit, and an estimation circuit. The clock signal input receives N time measurements. A time measurement denotes a respective portion of a given cycle of a clock signal. The sampling circuit is to generate a first and second sampled window from the clock signal input. The first sampled window includes a sum of a plurality of a first m of the N time measurements. The second sampled window includes a sum of a plurality of a last m of the N time measurements. The estimation circuit is to estimate the frequency or period of the clock signal based upon the first sampled window and the second sampled window.
A trench power semiconductor device comprising a silicon carbide drain layer, a silicon carbide drift layer over the silicon carbide drain layer and a first silicon layer over the silicon carbide drift layer. A second silicon layer over the first silicon layer with a source silicon carbide layer over the second silicon layer. A trench formed through the source silicon carbide layer, through the second silicon layer and into at least partially the first silicon layer. A gate terminal contact formed on the trench with a drain terminal contact formed on the silicon carbide drain layer.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/167 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form further characterised by the doping material
A gate driver circuit to receive an input drive signal and output an output drive signal is provided. The gate driver circuit may include a first capacitor having first and second terminals, a second capacitor having first and second terminals, a first set of switches to selectively couple the first terminals of the first and second capacitors to the input drive signal and a power supply voltage, a second set of switches to selectively couple the second terminals of the first and second capacitors to a reference voltage and a high impedance node, and a comparator having a first terminal coupled to the reference voltage and a second terminal coupled to the high impedance node. The comparator may output the output drive signal based on a comparison of the reference voltage and a voltage at the high impedance node.
H03K 17/567 - Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
31.
CONTROLLING AN AIR FLOW RATE PROVIDED TO A BURNER BASED ON A CONCENTRATION OF GAS PROVIDED TO THE BURNER
Systems and methods for controlling an air flow rate provided to a burner based on the concentration of one or more gases provided to the burner are disclosed. A method for controlling a burner including receiving a gas concentration value indicating a concentration of one or more gases in a gas mixture provided to a burner; determining, using the gas concentration value, an air flow rate to input to the burner; and controlling the air flow rate provided to the burner based on the determined air flow rate.
NN time measurements. The sampling circuit is to generate a second sampled window from the clock signal input including an accumulation of a plurality of products. The estimation circuit is to estimate the frequency or period of the clock signal based upon the first sampled window and the second sampled window.
A method is provided that may include receiving an identifier of a permanent magnet synchronous motor (PMSM), and mapping the identifier to electrical parameters of the PMSM. The method may include determining one or more coefficients of a sliding mode observer (SMO) based on the electrical parameters. The method may include providing the determined coefficients to the SMO to estimate the rotor position and speed of the PMSM.
An apparatus includes a clock signal input, a sampling circuit, and an estimation circuit. The clock signal input receives N time measurements. A time measurement denotes a respective portion of a given cycle of a clock signal. The sampling circuit is to generate a first sampled window from the clock signal input. The first sampled window includes an accumulation of the N time measurements. The sampling circuit is to generate a second sampled window from the clock signal input including an accumulation of a plurality of products. The estimation circuit is to estimate the frequency or period of the clock signal based upon the first sampled window and the second sampled window.
An apparatus includes a clock signal input, a sampling circuit, and an estimation circuit. The clock signal input receives N time measurements. A time measurement denotes a respective portion of a given cycle of a clock signal. The sampling circuit is to generate a first sampled window based upon a first time measurement and a first previous time measurement received m time measurements earlier than the first time measurement. The sampling circuit is to generate a second sampled window based upon a second time measurement and a second previous time measurement received m time measurements earlier than the second time measurement. The estimation circuit is to estimate the frequency or period of the clock signal based upon the first sampled window and the second sampled window.
In some implementations, a controller may identify a block of a memory device that is scheduled for an erase operation. The controller may determine, using a machine learning model or a data structure, whether a wordline of the block is susceptible to a deeper erase condition before the erase operation. The data structure identifies wordlines that are susceptible to deeper erase conditions. The controller may perform a programming operation, on the wordline, to program a predetermined bit pattern on the wordline based on the wordline being susceptible to the deeper erase condition. The controller may perform the erase operation on the block after performing the programming operation.
A method comprises generating a wireless power signal in one or more transmit coils of a transmitter which inductively couple with one or more receive coils of a receiver for wireless power transfer; terminating the wireless power transfer at least partially responsive to detecting a power loss of the wireless power transfer to be greater than a power loss threshold when a power factor of the wireless power transfer is greater than a power factor threshold; and refraining from terminating the wireless power transfer at least partially based on the power factor being less than the power factor threshold.
H02J 50/10 - Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling
H02J 50/40 - Circuit arrangements or systems for wireless supply or distribution of electric power using two or more transmitting or receiving devices
H02J 50/60 - Circuit arrangements or systems for wireless supply or distribution of electric power responsive to the presence of foreign objects, e.g. detection of living beings
38.
TUNING A SLIDING MODE OBSERVER FOR A PERMANENT MAGNET SYNCHRONOUS MOTOR
A method is provided that may include receiving an identifier of a permanent magnet synchronous motor (PMSM), and mapping the identifier to electrical parameters of the PMSM. The method may include determining one or more coefficients of a sliding mode observer (SMO) based on the electrical parameters. The method may include providing the determined coefficients to the SMO to estimate the rotor position and speed of the PMSM.
N m m m time measurements earlier than the second time measurement. The estimation circuit is to estimate the frequency or period of the clock signal based upon the first sampled window and the second sampled window.
N m m m of the N time measurements. The estimation circuit is to estimate the frequency or period of the clock signal based upon the first sampled window and the second sampled window.
In some implementations, a controller may perform, on one or more wordlines of a block of a non-volatile memory device, read operations using default threshold voltages associated with two overlapped charge states. The controller may determine, using a machine learning model, a distribution of threshold voltages for the two overlapped charge states based on read errors associated with the threshold voltages. The controller may determine, based on the determined distribution of threshold voltages, a health of the block. The controller may perform a block refresh operation for the block based on the health of the block. The block refresh operation may be performed when the health satisfies a health threshold. The block refresh operation may not be performed when the health does not satisfy the health threshold.
A method comprises generating a wireless power signal in one or more transmit coils of a transmitter which inductively couple with one or more receive coils of a receiver for wireless power transfer; terminating the wireless power transfer at least partially responsive to detecting a power loss of the wireless power transfer to be greater than a power loss threshold when a power factor of the wireless power transfer is greater than a power factor threshold; and refraining from terminating the wireless power transfer at least partially based on the power factor being less than the power factor threshold.
H02J 50/12 - Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling of the resonant type
H02J 50/60 - Circuit arrangements or systems for wireless supply or distribution of electric power responsive to the presence of foreign objects, e.g. detection of living beings
H02J 50/90 - Circuit arrangements or systems for wireless supply or distribution of electric power involving detection or optimisation of position, e.g. alignment
43.
SILICON CARBIDE DRIVER USING HIGH VOLTAGE CAPACITORS FOR ISOLATION AND SIGNAL TRANSMISSION
A gate driver circuit to receive an input drive signal and output an output drive signal is provided. The gate driver circuit may include a first capacitor having first and second terminals, a second capacitor having first and second terminals, a first set of switches to selectively couple the first terminals of the first and second capacitors to the input drive signal and a power supply voltage, a second set of switches to selectively couple the second terminals of the first and second capacitors to a reference voltage and a high impedance node, and a comparator having a first terminal coupled to the reference voltage and a second terminal coupled to the high impedance node. The comparator may output the output drive signal based on a comparison of the reference voltage and a voltage at the high impedance node.
H03K 17/06 - Modifications for ensuring a fully conducting state
H03K 17/689 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors with galvanic isolation between the control circuit and the output circuit
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
44.
DIAGNOSIS OF A SHARED BUS USING INDICATORS APPLIED TO A VECTOR BASED ON THE AMPLITUDE OF AN OBSERVED SIGNAL
Systems and methods for diagnosing a shared bus based on an indicator applied to a vector of amplitudes of signals transmitted over the bus. An aspect provides a method comprising: transmitting a pulse signal over a shared bus; capturing an observed signal, wherein the observed signal is a superimposition of the pulse signal and a reflection signal; comparing an amplitude of the observed signal to a plurality of threshold values; creating a vector indicating a given threshold at which the amplitude of the observed signal first exceeds one of the plurality of threshold values at a plurality of sampling times; applying an indicator to the vector; and diagnosing the shared bus based on the indicator.
A controller may determine, using a machine learning model, reliability characteristic data associated with memory cells of a non-volatile memory device. The machine learning model may be trained using characterization data that identifies different reliability characteristic of one or more non-volatile memory devices. The controller may group, based on the reliability characteristic data, a first portion of the memory cells of the non-volatile memory device in a first management group, and a second portion of the memory cells of the non-volatile memory device in a second management group. The controller may manage, based on the reliability characteristic data, background scanning and logical to physical mapping of the first management group of memory cells, and the second management group of memory cells.
Systems and methods for controlling an air flow rate provided to a burner based on the concentration of one or more gases provided to the burner are disclosed. A method for controlling a burner including receiving a gas concentration value indicating a concentration of one or more gases in a gas mixture provided to a burner; determining, using the gas concentration value, an air flow rate to input to the burner; and controlling the air flow rate provided to the burner based on the determined air flow rate.
F23D 14/02 - Premix gas burners, i.e. in which gaseous fuel is mixed with combustion air upstream of the combustion zone
F23D 14/22 - Non-premix gas burners, i.e. in which gaseous fuel is mixed with combustion air on arrival at the combustion zone with separate air and gas feed ducts, e.g. with ducts running parallel or crossing each other
47.
DETERMINING HEALTH OF A BLOCK OF A NON-VOLATILE MEMORY DEVICE BASED ON A DISTRIBUTION OF THRESHOLD VOLTAGES
In some implementations, a controller may perform, on one or more wordlines of a block of a non-volatile memory device, read operations using default threshold voltages associated with two overlapped charge states. The controller may determine, using a machine learning model, a distribution of threshold voltages for the two overlapped charge states based on read errors associated with the threshold voltages. The controller may determine, based on the determined distribution of threshold voltages, a health of the block. The controller may perform a block refresh operation for the block based on the health of the block. The block refresh operation may be performed when the health satisfies a health threshold. The block refresh operation may not be performed when the health does not satisfy the health threshold.
In some implementations, a controller may receive a request for an inference. The controller may determine, based on the received request for the inference, a first inference model of a plurality of inference models, to generate the inference. The controller may obtain, from a memory associated with an inference cache, first attribute data regarding first attributes of the first inference model. A location of the first attribute data, in the memory, may be determined using the inference cache. The attributes may include weights associated with the first inference model, biases associated with the first inference model, and a structure of the first inference model. The controller may utilize the first attribute data to generate the inference based on the request.
Systems and methods for communicating brain waves or control signals via body communication from the brain to body extremities to control or activate body parts or even external devices. An EEG coupler/transceiver couples to a person's scalp, wherein the EEG coupler/transceiver comprises an EEG electrode to receive a brain wave from the person, an EEG body communication coupler and an EEG antenna to transmit a signal via the EEG body communication coupler. An activator coupler/transceiver couples to the person's body to stimulate a muscle of the person's body, wherein the activator coupler/transceiver comprises a muscle activator, an activator body communication coupler, and an activator antenna to receive the signal via the activator body communication coupler.
A controller, of a solid state drive (SSD), may perform, on one or more blocks of a non-volatile memory device of the SSD, read operations using pre-determined threshold voltages associated with two overlapped charge states. The read operations may be performed after a power-on condition following a power-off condition on the non-volatile memory device. The controller may determine, using a machine learning model, a change in threshold voltages associated with the two overlapped charge states, after the power-off condition. The machine learning model may determine the change in threshold voltages using bit error rates associated with the read operations. The machine learning model may be trained to determine changes in threshold voltages for the two overlapped charge states, after power-off conditions. The controller may determine adjusted threshold voltages associated with the two overlapped charge states based on the change in threshold voltages.
G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
G11C 16/26 - Sensing or reading circuitsData output circuits
51.
DIAGNOSIS OF A SHARED BUS USING INDICATORS APPLIED TO A VECTOR BASED ON THE AMPLITUDE OF AN OBSERVED SIGNAL
Systems and methods for diagnosing a shared bus based on an indicator applied to a vector of amplitudes of signals transmitted over the bus. An aspect provides a method comprising: transmitting a pulse signal over a shared bus; capturing an observed signal, wherein the observed signal is a superimposition of the pulse signal and a reflection signal; comparing an amplitude of the observed signal to a plurality of threshold values; creating a vector indicating a given threshold at which the amplitude of the observed signal first exceeds one of the plurality of threshold values at a plurality of sampling times; applying an indicator to the vector; and diagnosing the shared bus based on the indicator.
A controller, of a solid state drive (SSD), may perform, on one or more blocks of a non-volatile memory device of the SSD, read operations using pre-determined threshold voltages associated with two overlapped charge states. The read operations may be performed after a power-on condition following a power-off condition on the non-volatile memory device. The controller may determine, using a machine learning model, a change in threshold voltages associated with the two overlapped charge states, after the power-off condition. The machine learning model may determine the change in threshold voltages using bit error rates associated with the read operations. The machine learning model may be trained to determine changes in threshold voltages for the two overlapped charge states, after power-off conditions. The controller may determine adjusted threshold voltages associated with the two overlapped charge states based on the change in threshold voltages.
A controller may determine, using a machine learning model, reliability characteristic data associated with memory cells of a non-volatile memory device. The machine learning model may be trained using characterization data that identifies different reliability characteristic of one or more non-volatile memory devices. The controller may group, based on the reliability characteristic data, a first portion of the memory cells of the non-volatile memory device in a first management group, and a second portion of the memory cells of the non-volatile memory device in a second management group. The controller may manage, based on the reliability characteristic data, background scanning and logical to physical mapping of the first management group of memory cells, and the second management group of memory cells.
An ADC system may include an ADC, a comparator, a voltage source, a comparator output polarity control circuit and a comparator output counter. An analog input signal may be input to a first input of the comparator, and an output of the voltage source may be input to a second input of the comparator. The comparator may generate an output to the comparator output polarity control circuit, and the comparator output counter may count clock cycles while the comparator output is asserted and may assert a monitor output based on the comparator output counter value. The monitor output may be an interrupt, an alarm or other system alerts and may control system operation.
In some implementations, a controller may receive a request for an inference. The controller may determine, based on the received request for the inference, a first inference model of a plurality of inference models, to generate the inference. The controller may obtain, from a memory associated with an inference cache, first attribute data regarding first attributes of the first inference model. A location of the first attribute data, in the memory, may be determined using the inference cache. The attributes may include weights associated with the first inference model, biases associated with the first inference model, and a structure of the first inference model. The controller may utilize the first attribute data to generate the inference based on the request.
G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
G06F 12/0864 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
G06F 12/123 - Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
G06F 12/0875 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
56.
MULTI-TURN COIL STRUCTURE INCLUDING CROSSOVER CONNECTIONS FOR INDUCTIVE ANGULAR-POSITION SENSOR
An apparatus includes a support structure and a sense coil comprising conductive traces on, or in, multiple layers of the support structure. The sense coil includes a first coil portion, a second coil portion, and first and second crossover connections. The first coil portion has M turns defining one or more in-phase lobes and the second coil portion has N turns defining one or more out-of-phase lobes. The first crossover connection connects an ending portion of an Mth turn of the first coil portion of an in-phase lobe to a starting portion of a first turn of the second coil portion of an out-of-phase lobe. The second crossover connection connects an ending portion of an Nth turn of the second coil portion of the out-of-phase lobe to a starting portion of a first turn of the first coil portion of the in-phase lobe.
G01D 5/20 - Mechanical means for transferring the output of a sensing memberMeans for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for convertingTransducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying inductance, e.g. by a movable armature
57.
GS) VOLTAGE OF A SILICON CARBIDE (SIC) FIELD-EFFECT TRANSISTOR (FET)
An apparatus may include a Silicon Carbide, SiC, Field-Effect Transistor, FET (110), and a sense buffer circuit (102). The sense buffer circuit may sense a gate-to-source voltage, VGS, of the SiC FET. The sense buffer circuit may include a buffer circuit (104) at an input of the sense buffer circuit. The buffer circuit may have a smaller input voltage range than the sense buffer circuit.
H03K 17/0412 - Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the control circuit
H03K 17/16 - Modifications for eliminating interference voltages or currents
H03K 19/003 - Modifications for increasing the reliability
A method may include obtaining samples associated with one or more symbols of a packet; determining at least one down-sampling point in a sequence of samples associated with a header portion of the packet; and utilizing samples associated with the determined down-sampling point to recover the one or more symbol and subsequent symbols.
An apparatus includes a support structure and a sense coil comprising conductive traces on, or in, multiple layers of the support structure. The sense coil includes a first coil portion, a second coil portion, and first and second crossover connections. The first coil portion has M turns defining one or more in-phase lobes and the second coil portion has N turns defining one or more out-of-phase lobes. The first crossover connection connects an ending portion of an Mth turn of the first coil portion of an in-phase lobe to a starting portion of a first turn of the second coil portion of an out-of-phase lobe. The second crossover connection connects an ending portion of an Nth turn of the second coil portion of the out-of-phase lobe to a starting portion of a first turn of the first coil portion of the in-phase lobe.
H01F 27/00 - Details of transformers or inductances, in general
G01B 7/30 - Measuring arrangements characterised by the use of electric or magnetic techniques for measuring angles or tapersMeasuring arrangements characterised by the use of electric or magnetic techniques for testing the alignment of axes
H01F 5/04 - Arrangements of electric connections to coils, e.g. leads
H01F 17/02 - Fixed inductances of the signal type without magnetic core
60.
DEVICE AND METHODS FOR RECONFIGURABLE ANALOG INPUT MONITORING
An ADC system may include an ADC, a comparator, a voltage source, a comparator output polarity control circuit and a comparator output counter. An analog input signal may be input to a first input of the comparator, and an output of the voltage source may be input to a second input of the comparator. The comparator may generate an output to the comparator output polarity control circuit, and the comparator output counter may count clock cycles while the comparator output is asserted and may assert a monitor output based on the comparator output counter value. The monitor output may be an interrupt, an alarm or other system alerts and may control system operation.
A multi-channel ADC system may include a plurality of input channels coupled to input signals. A multiplexer may couple one or more of the plurality of input channels to one or more multiplexer output channels. A control circuit may be coupled between the multiplexer output channels and an ADC. In operation, a configuration setting may configure the multi-channel ADC system in one of a plurality of configurations, including but not limited to single-ended, differential, pseudo-differential and hybrid configurations. The ADC may convert the plurality of input channels based on the configuration setting.
An apparatus may include a Silicon Carbide (SiC) Field-Effect Transistor (PET) and a sense buffer circuit. The sense buffer circuit may sense a gate-to-source voltage (VGS) of the SiC PET. The sense buffer circuit may include a buffer circuit at an input of the sense buffer circuit. The buffer circuit may have a smaller input voltage range than the sense buffer circuit.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
63.
EMI Reduction in PLCA-Based Networks Through Beacon Temporal Spreading
An apparatus may be communicatively coupled to other nodes in a network. The apparatus may include a control circuit configured to repeatedly issue transmission cycles to the other nodes. A given transmission cycle may include a least one send slot for each of the other nodes to send data. The control circuit may be configured to initiate transmission cycles by issuing beacon signals to the other nodes. The control circuit may be configured to determine when to issue a beacon signal in a given transmission cycle by determining that all of the other nodes have completed all associated send slots in an immediately previous transmission cycle and based upon a determination of the completion of the other nodes' transmission, delaying transmission of the beacon signal for the given transmission cycle.
A method may include obtaining samples associated with one or more symbols of a packet; determining at least one down-sampling point in a sequence of samples associated with a header portion of the packet; and utilizing samples associated with the determined down-sampling point to recover the one or more symbol and subsequent symbols
A smart cable for backplane storage management is provided. The cable may include a microcontroller, a power conditioning circuitry to regulate an input voltage from a power supply and provide an output voltage to the microcontroller, a storage device coupled to the microcontroller, a first end to be coupled to one or more storage devices, and a second end to be coupled to a storage controller. The microcontroller may receive sideband signals from the one or more storage drives, and may transmit connection topology information to the storage controller based at least in part on the sideband signals.
A multi-channel ADC system may include a plurality of input channels coupled to input signals. A multiplexer may couple one or more of the plurality of input channels to one or more multiplexer output channels. A control circuit may be coupled between the multiplexer output channels and an ADC. In operation, a configuration setting may configure the multi-channel ADC system in one of a plurality of configurations, including but not limited to single-ended, differential, pseudo-differential and hybrid configurations. The ADC may convert the plurality of input channels based on the configuration setting.
A smart cable for backplane storage management is provided. The cable may include a microcontroller, a power conditioning circuitry to regulate an input voltage from a power supply and provide an output voltage to the microcontroller, a storage device coupled to the microcontroller, a first end to be coupled to one or more storage devices, and a second end to be coupled to a storage controller. The microcontroller may receive sideband signals from the one or more storage drives, and may transmit connection topology information to the storage controller based at least in part on the sideband signals.
In one example, a method of a transceiver comprises receiving a first communication signal including a first message; detecting a signal strength of the first communication signal; generating a preamble having a preamble bit length that is adjusted at least partially based on the detected signal strength of the first communication signal; and transmitting a second communication signal including a second message, the second message including the preamble having the preamble bit length.
An apparatus including a power circuit to receive power from a power supply of a life safety device, and at least one control circuit powered by the power circuit. The control circuit to, in a calibration mode, receive a signal from an ambient light sensor and determine a baseline ambient light level based on the signal from the ambient light sensor. The control circuit to, in a proximity detection mode, receive another signal from the ambient light sensor, compare the other signal from the ambient light sensor to the baseline ambient light level, determine with an analysis that a difference in ambient light from the baseline ambient light level indicates a presence of an object in proximity to the life safety device, and issue an alert indicating the presence of the object in proximity to the life safety device based at least in part on the analysis.
A moisture resistant semiconductor device may include a substrate and a plurality of terminations in the substrate of the semiconductor device, wherein the plurality of terminations are laterally adjacent to an active region of the semiconductor device. A first insulating layer which overlays the plurality of terminations and the substrate. A trench into the substrate located laterally beyond an edge of the plurality of terminations. A contact layer which overlays the first insulating layer. A second insulating layer which overlays the contact layer. The second insulating layer which overlays the trench. A third insulating layer which overlays the second insulating layer.
An apparatus including a power circuit to receive power from a power supply of a life safety device, and at least one control circuit powered by the power circuit. The control circuit to, in a calibration mode, receive a signal from an ambient light sensor and determine a baseline ambient light level based on the signal from the ambient light sensor. The control circuit to, in a proximity detection mode, receive another signal from the ambient light sensor, compare the other signal from the ambient light sensor to the baseline ambient light level, determine with an analysis that a difference in ambient light from the baseline ambient light level indicates a presence of an object in proximity to the life safety device, and issue an alert indicating the presence of the object in proximity to the life safety device based at least in part on the analysis.
In one example, a method of a transceiver comprises receiving a first communication signal including a first message; detecting a signal strength of the first communication signal; generating a preamble having a preamble bit length that is adjusted at least partially based on the detected signal strength of the first communication signal; and transmitting a second communication signal including a second message, the second message including the preamble having the preamble bit length.
A moisture resistant semiconductor device (10) may include a substrate (15) and a plurality of terminations (20) in the substrate of the semiconductor device, wherein the plurality of terminations are laterally adjacent to an active region (18) of the semiconductor device. A first insulating layer (30) which overlays the plurality of terminations and the substrate. A trench (70) into the substrate located laterally beyond an edge of the plurality of terminations. A contact layer (40) which overlays the first insulating layer. A second insulating layer (50) which overlays the contact layer. The second insulating layer which overlays the trench. A third insulating layer (60) which overlays the second insulating layer.
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
A device may have a reference divider circuit to divide a reference clock, a phase-frequency detector circuit to detect a detected phase difference and a detected frequency difference based on the reference divider output and a feedback clock, a loop filter circuit to filter the detector output, a voltage controlled oscillator (VCO) control output pin coupled to the loop filter output, a VCO clock divider control output pin to select a divisor of an external clock divider circuit, a divided VCO clock input pin for coupling to an output of the external clock divider circuit, a pulse-width modulation (PWM) circuit having a PWM clock input coupled to the divided VCO clock input pin, a period register to store a period value, a duty cycle register to store a duty cycle value and a pulse-width modulated output based on the period value and the duty cycle value.
H03L 7/193 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider
H03L 7/18 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
H03L 7/089 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
H03L 7/091 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
H03L 7/093 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
H03L 7/14 - Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail
A bias circuit may generate a one or more bias outputs for a crystal oscillator. The bias circuit may include a first current mirror, a second current mirror and a third current mirror. A capacitor may be coupled between the second current mirror and the third current mirror. In operation, a first bias output may be generated by the third current mirror, and a second bias output may be generated by the second current mirror. The first bias output and second bias output may be coupled to a crystal oscillator.
H03B 5/36 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator active element in amplifier being semiconductor device
A bias circuit may generate a one or more bias outputs for a crystal oscillator. The bias circuit may include a first current mirror, a second current mirror and a third current mirror. A capacitor may be coupled between the second current mirror and the third current mirror. In operation, a first bias output may be generated by the third current mirror, and a second bias output may be generated by the second current mirror. The first bias output and second bias output may be coupled to a crystal oscillator.
H03B 5/32 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator
77.
PREDICTIVE BEAMFORMING ANTENNA AND METHOD OF CONTROLLING SAME
An apparatus that includes a beamforming antenna is provided. The apparatus may include a predictive calculator processing unit to receive position information of one or more airborne receivers, determine future position information of the one or more airborne receivers as a function of time based on the received position information, and determine beamforming antenna parameters. The apparatus may include an antenna instruction processing unit to receive the beamforming antenna parameters and generate beamforming instructions based on the beamforming antenna parameters, a beamforming antenna to receive the beamforming instructions, and to generate a beam at a specified time based on the beamforming instructions to enable communication with at least one of the one or more airborne receivers, and a receiver processing unit to receive airborne receiver data from the at least one of the one or more airborne receivers, and generate output data based on the airborne receiver data.
H04B 7/08 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station
H04B 7/06 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
H04W 64/00 - Locating users or terminals for network management purposes, e.g. mobility management
78.
PULSE WIDTH MODULATION CIRCUIT TO GENERATE A FEEDBACK CLOCK
A device may have a reference divider circuit to divide a reference clock, a phase-frequency detector circuit to detect a detected phase difference and a detected frequency difference based on the reference divider output and a feedback clock, a loop filter circuit to filter the detector output, a voltage controlled oscillator (VCO) control output pin coupled to the loop filter output, a VCO clock divider control output pin to select a divisor of an external clock divider circuit, a divided VCO clock input pin for coupling to an output of the external clock divider circuit, a pulse-width modulation (PWM) circuit having a PWM clock input coupled to the divided VCO clock input pin, a period register to store a period value, a duty cycle register to store a duty cycle value and a pulse-width modulated output based on the period value and the duty cycle value.
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H03K 5/156 - Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
H03L 7/093 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
H03L 7/18 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
79.
PREDICTIVE BEAMFORMING ANTENNA AND METHOD OF CONTROLLING SAME
An apparatus that includes a beamforming antenna is provided. The apparatus may include a predictive calculator processing unit to receive position information of one or more airborne receivers, determine future position information of the one or more airborne receivers as a function of time based on the received position information, and determine beamforming antenna parameters. The apparatus may include an antenna instruction processing unit to receive the beamforming antenna parameters and generate beamforming instructions based on the beamforming antenna parameters, a beamforming antenna to receive the beamforming instructions, and to generate a beam at a specified time based on the beamforming instructions to enable communication with at least one of the one or more airborne receivers, and a receiver processing unit to receive airborne receiver data from the at least one of the one or more airborne receivers, and generate output data based on the airborne receiver data.
H04W 4/02 - Services making use of location information
H01Q 3/26 - Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the relative phase or relative amplitude of energisation between two or more active radiating elementsArrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the distribution of energy across a radiating aperture
H04B 7/06 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
H04B 7/08 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station
B64G 1/10 - Artificial satellitesSystems of such satellitesInterplanetary vehicles
80.
INDUCTIVE SENSOR DEVICE WITH INDUCTOR COIL FORMED IN REDISTRIBUTION LAYER (RDL) REGION
An inductive sensor device includes at least one die mounted in or on a substrate, a redistribution layer (RDL) region formed over the at least one die and including multiple RDL metal layers, and at least one inductive coil formed in the RDL region and including at least one conductive coil element formed in at least one RDL metal layer of the multiple RDL metal layers, wherein the at least one die includes sensor circuitry connected to the at least one inductive coil to perform sensor measurements.
G01D 5/20 - Mechanical means for transferring the output of a sensing memberMeans for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for convertingTransducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying inductance, e.g. by a movable armature
G01B 7/30 - Measuring arrangements characterised by the use of electric or magnetic techniques for measuring angles or tapersMeasuring arrangements characterised by the use of electric or magnetic techniques for testing the alignment of axes
An input signal may be converted into a first PWM signal and a second PWM signal at a PWM controller circuit. The first PWM signal and second signal output may drive a driver circuit. The driver circuit may receive a high-voltage supply from a boost converter or other power circuit. The driver circuit may include a high-side device and a low-side device. The output of the driver circuit may drive a filter circuit, the filter circuit comprising a filter capacitor, an inductor and a haptic actuator. The haptic actuator may produce a desired haptic response at the haptic actuator.
An inductive sensor device includes at least one die mounted in or on a substrate, a redistribution layer (RDL) region formed over the at least one die and including multiple RDL metal layers, and at least one inductive coil formed in the RDL region and including at least one conductive coil element formed in at least one RDL metal layer of the multiple RDL metal layers, wherein the at least one die includes sensor circuitry connected to the at least one inductive coil to perform sensor measurements.
G01D 5/20 - Mechanical means for transferring the output of a sensing memberMeans for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for convertingTransducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying inductance, e.g. by a movable armature
An input signal may be converted into a first PWM signal and a second PWM signal at a PWM controller circuit. The first PWM signal and second signal output may drive a driver circuit. The driver circuit may receive a high-voltage supply from a boost converter or other power circuit. The driver circuit may include a high-side device and a low-side device. The output of the driver circuit may drive a filter circuit, the filter circuit comprising a filter capacitor, an inductor and a haptic actuator. The haptic actuator may produce a desired haptic response at the haptic actuator.
A method for using a LIDAR-equipped projectile for three-dimensional mapping including sending a signal to a light source to cause the light source to emit a plurality of light pulses, the light source located on a spinning projectile proceeding along a predetermined path; receiving, at the spinning projectile, a plurality of reflected light pulses responsive to the plurality of light pulses reflecting off an object or a terrain portion; determining a distance of the object or the terrain portion from the light source; and generating a three-dimensional map of the object based on the determined distance of the object or the terrain portion from the light source.
A method includes performing a pressing operation on a volume of silicon carbide (SiC) powder to form a polycrystalline SiC (poly-SiC) ingot, and divide the poly-SiC ingot into a plurality of poly-SiC wafer bases. The method further includes, for a respective poly-SiC wafer base, bonding a silicon (Si) wafer structure to the respective poly-SiC wafer base to define a hybrid Si/poly-SiC stack structure, and performing a dividing process to remove a partial thickness of the Si wafer structure from the hybrid Si/poly-SiC stack structure to provide a hybrid Si/poly-SiC wafer comprising a remaining portion of the Si wafer structure bonded to the respective poly-SiC wafer base.
A transistor that may include a substrate, a drain layer formed within the substrate at a first side of the substrate. A first well implant having a first implant depth, a second well implant having a second implant depth and a third well implant having a third implant depth. The first well implant, the second well implant and the third well implant formed within the substrate at the second side of the substrate. The second implant depth is greater than the first implant depth and the third implant depth is greater than the second implant depth. A gate formed at the second side of the substrate. The gate overlaps the first well implant by a first distance, the gate overlaps the second well implant by a second distance and the gate overlaps the third well implant by a third distance.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A method for distress signal monitoring with EMS and public notification in crowded public spaces. The method includes receiving a distress signal from a first personal device in a crowded public space; locating the first personal device closest to an EMS unit indicating that a user of the first personal device is in distress; transmitting a location of the first personal device to the EMS unit; identifying a second personal device proximate to the first personal device; and transmitting a notification signal to the second personal device indicating that a person is in distress.
G08B 25/01 - Alarm systems in which the location of the alarm condition is signalled to a central station, e.g. fire or police telegraphic systems characterised by the transmission medium
G08B 27/00 - Alarm systems in which the alarm condition is signalled from a central station to a plurality of substations
88.
THREE-DIMENSIONAL MAPPING USING A LIDAR-EQUIPPED SPINNING PROJECTILE
A method for using a LIDAR-equipped projectile for three-dimensional mapping including sending a signal to a light source to cause the light source to emit a plurality of light pulses, the light source located on a spinning projectile proceeding along a predetermined path; receiving, at the spinning projectile, a plurality of reflected light pulses responsive to the plurality of light pulses reflecting off an object or a terrain portion; determining a distance of the object or the terrain portion from the light source; and generating a three-dimensional map of the object based on the determined distance of the object or the terrain portion from the light source.
F41G 3/02 - Aiming or laying means using an independent line of sight
F42B 12/36 - Projectiles, missiles or mines characterised by the warhead, the intended effect, or the material characterised by the warhead or the intended effect for dispensing materialsProjectiles, missiles or mines characterised by the warhead, the intended effect, or the material characterised by the warhead or the intended effect for producing chemical or physical reactionProjectiles, missiles or mines characterised by the warhead, the intended effect, or the material characterised by the warhead or the intended effect for signalling
F42B 12/38 - Projectiles, missiles or mines characterised by the warhead, the intended effect, or the material characterised by the warhead or the intended effect for dispensing materialsProjectiles, missiles or mines characterised by the warhead, the intended effect, or the material characterised by the warhead or the intended effect for producing chemical or physical reactionProjectiles, missiles or mines characterised by the warhead, the intended effect, or the material characterised by the warhead or the intended effect for signalling of tracer type
F42B 30/00 - Projectiles or missiles, not otherwise provided for, characterised by the ammunition class or type, e.g. by the launching apparatus or weapon used
G01S 1/00 - Beacons or beacon systems transmitting signals having a characteristic or characteristics capable of being detected by non-directional receivers and defining directions, positions, or position lines fixed relatively to the beacon transmittersReceivers co-operating therewith
G01S 3/00 - Direction-finders for determining the direction from which infrasonic, sonic, ultrasonic, or electromagnetic waves, or particle emission, not having a directional significance, are being received
G01S 17/86 - Combinations of lidar systems with systems other than lidar, radar or sonar, e.g. with direction finders
G01S 17/89 - Lidar systems, specially adapted for specific applications for mapping or imaging
A transistor that may include a substrate, a drain layer formed within the substrate at a first side of the substrate. A first well implant having a first implant depth, a second well implant having a second implant depth and a third well implant having a third implant depth. The first well implant, the second well implant and the third well implant formed within the substrate at the second side of the substrate. The second implant depth is greater than the first implant depth and the third implant depth is greater than the second implant depth. A gate formed at the second side of the substrate. The gate overlaps the first well implant by a first distance, the gate overlaps the second well implant by a second distance and the gate overlaps the third well implant by a third distance.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 21/336 - Field-effect transistors with an insulated gate
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
90.
METHOD AND APPARATUS FOR PRECHARGING DC-LINK CAPACITOR IN HIGH-VOLTAGE DC DISTRIBUTION SYSTEM
A pre-charging circuit for charging a DC-link capacitor is provided. The pre-charging circuit may include a first semiconductor switch to be coupled to a first terminal of a high voltage source, a first inductor to be coupled to the first semiconductor switch and a first terminal of a capacitor, a second semiconductor switch to be coupled to a second terminal of the high voltage source, a second inductor to be coupled to the second semiconductor switch and a second terminal of the capacitor, and a diode coupled to the first semiconductor switch, the second semiconductor switch, the first inductor, and the second inductor, and coupled in parallel with the capacitor.
A method includes performing a pressing operation on a volume of silicon carbide (SiC) powder to form a polycrystalline SiC (poly-SiC) ingot, and divide the poly-SiC ingot into a plurality of poly-SiC wafer bases. The method further includes, for a respective poly-SiC wafer base, bonding a silicon (Si) wafer structure to the respective poly-SiC wafer base to define a hybrid Si/poly-SiC stack structure, and performing a dividing process to remove a partial thickness of the Si wafer structure from the hybrid Si/poly-SiC stack structure to provide a hybrid Si/poly-SiC wafer comprising a remaining portion of the Si wafer structure bonded to the respective poly-SiC wafer base.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 29/04 - Semiconductor bodies characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
92.
DEVICE AND METHODS FOR FUNCTIONAL DESCRIPTOR-BASED DMA CONTROLLER
A microcontroller may include a DMA controller, a pattern matching circuit and a memory. The DMA controller may read a first descriptor word in the memory at a location addressed by a first descriptor pointer, and may move an input word from a location in the memory addressed by a source payload pointer to a location in the memory addressed by a destination payload pointer. The pattern matching circuit may perform a pattern matching operation based on the input word and one or more register values. The first descriptor pointer may be modified based on the results of the pattern matching circuit and may generate a second descriptor pointer value.
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
93.
DEVICE AND METHOD FOR PIPELINED MULTIPLY-ACCUMULATOR
A circuit may include a vector arithmetic logic unit (ALU), the vector ALU comprising a multiplier, a first multiplexer, a second multiplexer and an accumulator. The vector ALU may compute a dot product of two or more vector inputs. A system may include two or more vector ALUs, and may partition a vector input into multiple segments. Each segment may be input to a respective vector ALU via a multiplexer, and a controller may route the partial sums of respective ALUs via one or more feedback paths and the system may compute the complete dot product of the vector inputs.
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
94.
METHOD AND APPARATUS FOR PRE-CHARGING DC-LINK CAPACITOR IN HIGH VOLTAGE DC DISTRIBUTION SYSTEM
A pre-charging circuit for charging a DC-link capacitor is provided. The pre-charging circuit may include a first semiconductor switch to be coupled to a first terminal of a high voltage source, a first inductor to be coupled to the first semiconductor switch and a first terminal of a capacitor, a second semiconductor switch to be coupled to a second terminal of the high voltage source, a second inductor to be coupled to the second semiconductor switch and a second terminal of the capacitor, and a diode coupled to the first semiconductor switch, the second semiconductor switch, the first inductor, and the second inductor, and coupled in parallel with the capacitor.
H02M 1/36 - Means for starting or stopping converters
H02M 3/156 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
95.
LOCATING AN EMS UNIT CLOSEST TO A SOURCE OF A DISTRESS SIGNAL AND NOTIFYING PROXIMATE PERSONAL DEVICES
A method for distress signal monitoring with EMS and public notification in crowded public spaces. The method includes receiving a distress signal from a first personal device in a crowded public space; locating the first personal device closest to an EMS unit indicating that a user of the first personal device is in distress; transmitting a location of the first personal device to the EMS unit; identifying a second personal device proximate to the first personal device; and transmitting a notification signal to the second personal device indicating that a person is in distress.
G08B 27/00 - Alarm systems in which the alarm condition is signalled from a central station to a plurality of substations
G08B 5/36 - Visible signalling systems, e.g. personal calling systems, remote indication of seats occupied using electric transmissionVisible signalling systems, e.g. personal calling systems, remote indication of seats occupied using electromagnetic transmission using visible light sources
96.
DEVICE AND METHOD FOR PIPELINED MULTIPLY-ACCUMULATOR
A circuit may include a vector arithmetic logic unit (ALU), the vector ALU comprising a multiplier, a first multiplexer, a second multiplexer and an accumulator. The vector ALU may compute a dot product of two or more vector inputs. A system may include two or more vector ALUs, and may partition a vector input into multiple segments. Each segment may be input to a respective vector ALU via a multiplexer, and a controller may route the partial sums of respective ALUs via one or more feedback paths and the system may compute the complete dot product of the vector inputs.
G06F 7/57 - Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups or for performing logical operations
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
97.
TELEMETRY SYSTEM INCLUDING A SENSOR STATION ARRAY AND AN AERIAL DATA COLLECTION SYSTEM
A telemetry system includes an array of sensor stations arranged in a spaced apart arrangement, wherein respective sensor stations include a respective sensor to generate respective sensor data regarding a respective sensed parameter, a respective sensor station memory to store the respective sensor data, a respective sensor station antenna, a respective sensor station wireless transmitter, and a respective sensor station processor to periodically activate the respective sensor station wireless transmitter to transmit the respective sensor data via the respective sensor station antenna. The telemetry system includes an aerial data collection system including an aerial data collection system antenna, and an aerial data collection system receiver to receive the respective sensor data transmitted by the respective sensor station antenna.
G05D 1/00 - Control of position, course, altitude or attitude of land, water, air or space vehicles, e.g. using automatic pilots
H04L 67/12 - Protocols specially adapted for proprietary or special-purpose networking environments, e.g. medical networks, sensor networks, networks in vehicles or remote metering networks
A microcontroller may include a DMA controller, a pattern matching circuit and a memory. The DMA controller may read a first descriptor word in the memory at a location addressed by a first descriptor pointer, and may move an input word from a location in the memory addressed by a source payload pointer to a location in the memory addressed by a destination payload pointer. The pattern matching circuit may perform a pattern matching operation based on the input word and one or more register values. The first descriptor pointer may be modified based on the results of the pattern matching circuit and may generate a second descriptor pointer value.
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 7/76 - Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
99.
SILICON CARBIDE POWER MOSFET AND METHOD FOR MANUFACTURING SAME
A method of manufacturing a semiconductor device is provided. The method may include implanting a silicon-rich layer on a surface of a silicon carbide substrate, and growing a gate oxide layer on the silicon-rich layer on the surface of the silicon carbide substrate.
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
100.
HYBRID CHANNEL POWER SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
A semiconductor device is provided. The semiconductor device may include a silicon carbide substrate, a silicon layer formed at a first side of the silicon carbide substrate, a gate oxide layer formed on the silicon layer, a gate terminal formed on the gate oxide layer, a drain terminal formed at a second side of the silicon carbide substrate opposite the first side, and a source terminal formed at the first side of the silicon carbide substrate, and at opposite ends of the silicon layer.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/808 - Field-effect transistors with field effect produced by a PN or other rectifying junction gate with a PN junction gate
