An apparatus comprising an interposer to couple conductive contacts of a substrate to conductive contacts of an integrated circuit device, wherein the interposer comprises a cavity proximate conductive contacts of the interposer, the conductive contacts of the interposer to couple to conductive contacts of a photonics integrated circuit (PIC).
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des groupes principaux , ou dans une seule sous-classe de , , p.ex. circuit hybrides
G02B 6/12 - OPTIQUE ÉLÉMENTS, SYSTÈMES OU APPAREILS OPTIQUES - Détails de structure de dispositions comprenant des guides de lumière et d'autres éléments optiques, p.ex. des moyens de couplage du type guide d'ondes optiques du genre à circuit intégré
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
2.
N-TYPE TRANSISTOR FABRICATION IN COMPLEMENTARY FET (CFET) DEVICES
N-type gate-all-around (nanosheet, nanoribbon, nanowire) field-effect transistors (GAAFETs) vertically stacked on top of p-type GAAFETs in complementary FET (CFET) devices comprise non-crystalline silicon layers that form the n-type transistor source, drain, and channel regions. The non-crystalline silicon layers can be formed via deposition, which can provide for a simplified processing flow to form the middle dielectric layer between the n-type and p-type GAAFETs relative to processing flows where the silicon layers forming the n-type transistor source, drain, and channel regions are grown epitaxially.
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
3.
A CAPACITIVE DIGITAL-TO-ANALOG CONVERTER FOR MULTI-BAND RADIO FREQUENCY COMMUNICATION
Disclosed herein are devices, methods, and systems that relate to wireless communications architectures and, in particular, multi-band radio-frequency circuitry. Disclosed herein is a capacitive digital-to-analog converter (CDAC). The CDAC may include a plurality of circuits configured to receive a digital signal to be converted into an analog signal, wherein each circuit of the plurality of circuits may include: a variable capacitive element; and a driver configured to cause the variable capacitive element to be charged or discharged to convert the received digital signal into the analog signal.
Methods, apparatus, systems, and articles of manufacture to generate a timestamp are disclosed. Examples disclosed herein generate a correction factor based on a first timestamp and a second timestamp, the first timestamp generated before a first data packet is obtained by ethernet physical coding sublayer (PCS), the second timestamp generated before the first data packet is obtained by a physical ethernet port coupled to the ethernet PCS; and generate a third timestamp for a second data packet based on the correction factor and a fourth timestamp, the fourth timestamp generated by network interface circuitry for the second data packet.
H04L 43/106 - Surveillance active, p.ex. battement de cœur, utilitaire Ping ou trace-route en utilisant des informations liées au temps dans des paquets, p.ex. en ajoutant des horodatages
H04L 43/0823 - Erreurs, p.ex. erreurs de transmission
H04L 43/067 - Génération de rapports en utilisant des rapports de délai
Disclosed herein are systems, devices, and methods for real-time motion and path planning. The real-time motion and path planner may generate occupancy information about an environment around a robot. The occupancy information represents defined volumes of space of the environment, and each defined volume of space is associated with a corresponding occupancy probability. The motion/path planner also determines a sequence of robot configurations between a starting and a target configuration based on the occupancy information, wherein the sequence of robot configurations defines poses of the robot that occupy selected ones of the defined volumes of space. The motion/path planner also generates an instruction for the robot based on the sequence of robot configurations, wherein the instruction includes trajectory information to control the robot to move from the starting configuration to the target configuration through the sequence of robot configurations.
G10K 11/178 - Procédés ou dispositifs de protection contre le bruit ou les autres ondes acoustiques ou pour amortir ceux-ci, en général utilisant des effets d'interférence; Masquage du son par régénération électro-acoustique en opposition de phase des ondes acoustiques originales
H04R 1/40 - Dispositions pour obtenir la fréquence désirée ou les caractéristiques directionnelles pour obtenir la caractéristique directionnelle désirée uniquement en combinant plusieurs transducteurs identiques
A non-transitory computer readable medium is provided having instructions stored therein that when executed by a processor cause the processor to select a device interface component layout from a plurality of device interface component layouts based on a set of parameters, wherein each device interface component layout corresponds to an interface structure of a shared integrated circuit semiconductor device component; perform at least one compatibility verification process for the selected device interface component layout with regard to an environment of the device interface component at a predetermined position in the integrated circuit semiconductor device; and output a compatibility verification information indicating a result of the at least one compatibility verification process for the selected device interface component layout.
G06F 30/398 - Vérification ou optimisation de la conception, p.ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
G06F 30/392 - Conception de plans ou d’agencements, p.ex. partitionnement ou positionnement
7.
METHOD AND SYSTEM FOR ERROR CHECK AND SCRUB ERROR DATA COLLECTION AND REPORTING FOR A MEMORY DEVICE
A method and system for error check and scrub (ECS) error data collection and reporting for a memory device. A controller includes circuitry and a buffer. The circuitry may be configured to read ECS error data from a register of a memory device and calculate an ECS error increase rate based on the ECS error data. The circuitry may be configured to inform basic input output system (BIOS) by interrupt if a total number of ECS errors reaches or exceeds an ECS error number threshold or if the ECS error increase rate reaches or exceeds an ECS error rate threshold. The controller may be an out-of-band device, e.g., a baseboard management controller or a memory micro controller.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
An apparatus and method for a reused-data cache. For example, a processor comprises: a plurality of processing cores; a first cache of a cache level shared by the plurality of processing cores, the first cache to store cache lines associated with data that is not specifically identified as data likely to be reused; a second cache of the cache level coupled to the plurality of processing cores, the second cache to store cache lines associated with data that is specifically identified as data likely to be reused; a cache controller configured to: receive an address associated with a load operation for first data; perform a lookup in at least one of the first cache and the second cache using the address; read the second data from at least one cache line of the first cache or the second cache if the lookup results in a hit in the first cache or the second cache, respectively; load the first data from the memory if the lookup results in a miss in the first cache and the second cache; store the first data in one or more cache lines of the first cache if the first data is not specifically identified as data likely to be reused; and store the first data in one or more cache lines of the second cache if the first data is specifically identified as data likely to be reused.
Microelectronic integrated circuit package structures include a package substrate with a first die over the package substrate, and a second die adjacent to the first die, such that first sides of the first die and the second die are on a thermal solution. A bridge structure is directly on a portion of each of second sides of the first and second dies, such that the second sides include integrated circuit contact structures. Bridge via structures couple the integrated circuit contact structures to the bridge structure.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
10.
SYSTEMS AND METHODS FOR RECEIVE-SIDE CUSTOMIZATION OF PRESENTATION OF MIXED MEDIA DATA
Systems and methods for receive-side customization of presentation of mixed media data. Systems and methods focus on the receive path so that each participant in a video conference or other mixed media application can, as a receiver of mixed media data signals, customize the individual incoming mixed media data signals for display on the receiver's user device. User customization options include blocking video or avatars, converting (to avatars), and filtering distracting behavior. Embodiments enable all participating users (not just a host user) to respectively receive-side customize the presentation/display of the mixed media data. Additionally, systems and methods can be implemented in an existing server
H04N 21/4788 - Services additionnels, p.ex. affichage de l'identification d'un appelant téléphonique ou application d'achat communication avec d'autres utilisateurs, p.ex. discussion en ligne
H04N 21/222 - Serveurs secondaires, p.ex. serveur proxy ou tête de réseau de télévision par câble
11.
COLLABORATIVE HUMAN-ROBOT ERROR CORRECTION AND FACILITATION
Techniques are disclosed for task error correction for robots, such as collaborative robots (cobots). A controller of a robot may include an error detector to detect an error in a performance of a human-robot collaborative task, and an error corrector to correct the detected error. The error corrector may include a correction planner and a facilitator. The correction planner may determine an error correction plan based on the detected error. The error correction plan may include corrective subtasks to control the cobot to correct the detected error. The facilitator may determine a facilitation plan based on the determined error correction plan. The facilitation plan including an assistance subtask configured to control the cobot to assist a human operator in correcting the detected error. The error corrector may generate a control signal to control the cobot based on the correction plan and the facilitation plan.
Disclosed herein are microelectronic assemblies, related apparatuses, and methods. In some embodiments, a microelectronic assembly may include a first die in a first layer; and a second and third die in a second layer, the second layer coupled to the first layer by hybrid bond interconnects having a first pad and a second pad, wherein the first pad is coupled to a first via in the second die and the first pad is offset from the first via by a first dimension, and the second pad is coupled to a second via in the third die and the second pad is offset from the second via by a second dimension different than the first dimension. In some embodiments, the first pad is offset from the first via in a first direction and the second pad is offset from the second via in a second direction different than the first direction.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/544 - Marques appliquées sur le dispositif semi-conducteur, p.ex. marques de repérage, schémas de test
13.
EDGE-BASED END DEVICE CONTROL USING ASYNCHRONOUS ADAPTIVE MOTION PRIMITIVES
A component of an edge server, including: processor circuitry; and a non-transitory computer-readable storage medium including instructions that, when executed by the processor circuitry, cause the processor circuitry to: distribute, to a client device, tokens that enable its end device to execute respective asynchronous adaptive motion primitives (A2MPs) of a task graph of a task, wherein an A2MP is a motion primitive of encoded motion factoring in motion updates from the end device; receive A2MP task execution status messages during execution of the A2MPs; and dynamically update the distribution of the token or the task graph based on the A2MP task execution status messages to modify a trajectory of the end device.
H04L 67/125 - Protocoles spécialement adaptés aux environnements propriétaires ou de mise en réseau pour un usage spécial, p.ex. les réseaux médicaux, les réseaux de capteurs, les réseaux dans les véhicules ou les réseaux de mesure à distance en impliquant la commande des applications des terminaux par un réseau
14.
INTEGRATED CIRCUIT STRUCTURES HAVING VERTICAL-TRANSPORT TRANSISTOR WITH BOTTOM SOURCE CONNECTION
Structures having vertical-transport field effect transistors (FETs) with bottom source connection are described. In an example, an integrated circuit structure includes a channel structure above a substrate. A gate structure is laterally surrounding the channel structure. A drain structure is above the gate structure and on the channel structure. A metal source structure is below the substrate and vertically beneath the channel structure. A conductive via is through the substrate, the conductive via coupling the metal source structure to the channel structure.
H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
15.
METHODS AND APPARATUS TO INCREASE PRIVACY FOR FOLLOW-ME SERVICES
Methods, apparatus, systems, and articles of manufacture to migrate cloud-based workloads are disclosed. An example instructions cause programmable circuitry to at least cause transmission of anonymized information corresponding to a user device to a network device; and cause migration of a virtual execution environment from a first compute device to a second compute device based on a response from the network device, the virtual execution environment to execute at least a portion of a workload for an end user device.
A rotatable circular waveguide structure is described that may comprise circular waveguide sections configured to propagate electromagnetic radiation. The circular waveguide sections may enable data signals to be transmitted between portions of an electronic device, such as a chassis and display portion, which may be rotatable with respect to one another. The rotatable circular waveguide structure may comprise one or more circular waveguide sections that are routed through a hinge of the electronic device, as well as one or more rotatable junctions. The rotatable junctions enable a rotation of circular waveguide sections with respect to one another as the coupled portions of the electronic device are also rotated. The rotatable circular waveguide structure may replace the use of data cables that are conventionally used to carry data signals between portions of an electronic device.
Technologies for hybrid optical chip-to-chip coupling are disclosed. In an illustrative embodiment, light from a waveguide in a photonic integrated circuit (PIC) die is collimated using a micromirror and directed towards a glass substrate. Another micromirror in the glass substrate focuses the light into a waveguide defined in a bulk layer of the glass substrate. In the illustrative embodiment, the waveguide is directly written into the bulk layer using an ultrafast laser. The glass substrate also has waveguides with a large difference in the index of refraction in a layer above the bulk substrate, such as silicon nitride waveguides in silicon oxide cladding. The directly-written waveguides can be evanescently coupled to the silicon nitride waveguides. The silicon nitride waveguides can then be used for two-dimensional routing throughout the glass substrate. The light can be coupled back into a directly-written waveguide before it is transmitted to another PIC die.
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des groupes principaux , ou dans une seule sous-classe de , , p.ex. circuit hybrides
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
G02B 6/12 - OPTIQUE ÉLÉMENTS, SYSTÈMES OU APPAREILS OPTIQUES - Détails de structure de dispositions comprenant des guides de lumière et d'autres éléments optiques, p.ex. des moyens de couplage du type guide d'ondes optiques du genre à circuit intégré
G02B 6/42 - Couplage de guides de lumière avec des éléments opto-électroniques
18.
METHODS AND DEVICES FOR MULTI-CELL RADIO RESOURCE MANAGEMENT ALGORITHMS
A device may include a memory configured to store an artificial intelligence or machine learning model (AI/ML) configured to provide an output used in radio resource management of a plurality of cells; and a processor configured to: obtain cell-specific parameters of the plurality of cells of a mobile communication network; select a subset of the plurality of cells based on obtained cell-specific parameters; and cause the AI/ML to be trained with radio access network (RAN)-related data of the subset of the plurality of cells.
H04W 28/18 - Négociation des paramètres de télécommunication sans fil
H04W 72/542 - Critères d’affectation ou de planification des ressources sans fil sur la base de critères de qualité en utilisant la qualité mesurée ou perçue
H04L 41/16 - Dispositions pour la maintenance, l’administration ou la gestion des réseaux de commutation de données, p.ex. des réseaux de commutation de paquets en utilisant l'apprentissage automatique ou l'intelligence artificielle
Integrated circuit structures having differential epitaxial source or drain dent are described. For example, an integrated circuit structure includes a first sub-fin structure beneath a first stack of nanowires or fin. A second sub-fin structure is beneath a second stack of nanowires or fin. A first epitaxial source or drain structure is at an end of the first stack of nanowires of fin, the first epitaxial source or drain structure having no dent or a shallower dent therein. A second epitaxial source or drain structure is at an end of the second stack of nanowires or fin, the second epitaxial source or drain structure having a deeper dent therein.
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
20.
THIN HAFNIUM-ZIRCONIUM OXIDE FILMS HAVING LARGE GRAIN SIZE FOR FERROELECTRIC CAPACITORS
Apparatuses, memory systems, capacitor structures, and techniques related to ferroelectric capacitors having a hafnium-zirconium oxide film between the electrodes of the capacitor are discussed. The hafnium-zirconium oxide film is thin and has large crystallite grains. The thin large grain hafnium-zirconium oxide film having large grains is formed by depositing a thick hafnium-zirconium oxide film and annealing the thick hafnium-zirconium oxide film to establish the large grain size, and etching back the hafnium-zirconium oxide film to the desired thickness for deployment in the ferroelectric capacitor.
H10N 97/00 - Dispositifs électriques à l’état solide à film mince ou à film épais, non prévus ailleurs
H10B 53/30 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par la région noyau de mémoire
H10B 53/20 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur
G11C 11/22 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des éléments ferro-électriques
21.
SELF-ALIGNED MEMORY CELL WITH REPLACEMENT METAL GATE VERTICAL ACCESS TRANSISTOR AND STACKED 3D CAPACITORS
An integrated circuit device includes a stack of capacitors with a vertical first electrode coupled to a stack of individual second electrodes by an insulating storage material between first and second electrodes, and an access transistor coaxially aligned with, and coupled to, the vertical first electrode. The storage material may be a ferroelectric material. A gate dielectric of the access transistor may be around, and coaxial with, a channel region. The channel region may be vertically oriented and coaxial with the first electrode. A second access transistor may be similarly aligned with the first electrode and the stack of capacitors with the capacitor stack between the transistors. A channel of the second transistor may be around, and coaxial with, a gate dielectric. The transistors and capacitor stack may be in arrays of transistors and capacitor stacks. A self-aligned process may be used to form the capacitor and transistor arrays.
H10B 53/20 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur
H10B 53/30 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par la région noyau de mémoire
H10B 53/10 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par la configuration vue du dessus
H10N 97/00 - Dispositifs électriques à l’état solide à film mince ou à film épais, non prévus ailleurs
22.
ENQUEUE COMMAND POWER MANAGEMENT AND SERVICE REQUEST PROCESSING LATENCY IMPROVEMENTS
Methods and apparatus relating to power management and service request processing latency improvements for an enqueue command are described. In one embodiment, a storage device stores a request reference count, which is updated in response to receipt of a job request from a process at a device and in response to completion of a job corresponding to the received job request. The device enters into, remains in, or exits an active/idle power state in response to a value of the request reference count. In another embodiment, a job request with a job descriptor is issued to a target device. Device power management logic causes the target device to transition from an idle power state to an active power state in response to receipt of the job descriptor prior to the job descriptor being stored in a work queue of the target device. Other embodiments are also disclosed and claimed.
Examples include techniques to mitigate or prevent cache-based side-channel attacks to a cache. Examples include use of assigned class of service (COS) assigned to cores of a process to determine whether to notify an OS of a potential malicious application attempting to access a cache line cached to a processor cache. Examples also include marking pages in an application memory address space of a processor cache as unflushable to prevent a potentially malicious application from accessing sensitive data loaded to the application memory address space of the processor cache.
In one embodiment, a processor includes a power controller having a resource allocation circuit. The resource allocation circuit may: receive a power budget for a first core and at least one second core and scale the power budget based at least in part on at least one energy performance preference value to determine a scaled power budget; determine a first maximum operating point for the first core and a second maximum operating point for the at least one second core based at least in part on the scaled power budget; determine a first efficiency value for the first core based at least in part on the first maximum operating point for the first core and a second efficiency value for the at least one second core based at least in part on the second maximum operating point for the at least one second core; and report a hardware state change to an operating system scheduler based on the first efficiency value and the second efficiency value. Other embodiments are described and claimed.
G06F 1/3296 - Gestion de l’alimentation, c. à d. passage en mode d’économie d’énergie amorcé par événements Économie d’énergie caractérisée par l'action entreprise par diminution de la tension d’alimentation ou de la tension de fonctionnement
G06F 1/324 - Gestion de l’alimentation, c. à d. passage en mode d’économie d’énergie amorcé par événements Économie d’énergie caractérisée par l'action entreprise par réduction de la fréquence d’horloge
Methods and apparatus relating to techniques for multi-tile memory management. In an example, a graphics processor includes an interposer, a first chiplet coupled with the interposer, the first chiplet including a graphics processing resource and an interconnect network coupled with the graphics processing resource, cache circuitry coupled with the graphics processing resource via the interconnect network, and a second chiplet coupled with the first chiplet via the interposer, the second chiplet including a memory-side cache and a memory controller coupled with the memory-side cache. The memory controller is configured to enable access to a high-bandwidth memory (HBM) device, the memory-side cache is configured to cache data associated with a memory access performed via the memory controller, and the cache circuitry is logically positioned between the graphics processing resource and a chiplet interface.
G06F 15/78 - Architectures de calculateurs universels à programmes enregistrés comprenant une seule unité centrale
G06F 7/544 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p.ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul
G06F 7/575 - Unités arithmétiques et logiques de base, c. à d. dispositifs pouvant être sélectionnés pour accomplir soit l'addition, soit la soustraction, soit une parmi plusieurs opérations logiques, utilisant, au moins partiellement, les mêmes circuits
G06F 7/58 - Générateurs de nombres aléatoires ou pseudo-aléatoires
G06F 9/30 - Dispositions pour exécuter des instructions machines, p.ex. décodage d'instructions
G06F 9/50 - Allocation de ressources, p.ex. de l'unité centrale de traitement [UCT]
G06F 12/02 - Adressage ou affectation; Réadressage
G06F 12/06 - Adressage d'un bloc physique de transfert, p.ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
G06F 12/0802 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache
G06F 12/0804 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache avec mise à jour de la mémoire principale
G06F 12/0811 - Systèmes de mémoire cache multi-utilisateurs, multiprocesseurs ou multitraitement avec hiérarchies de mémoires cache multi-niveaux
G06F 12/0862 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache avec pré-lecture
G06F 12/0866 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache pour les systèmes de mémoire périphérique, p.ex. la mémoire cache de disque
G06F 12/0871 - Affectation ou gestion d’espace de mémoire cache
G06F 12/0875 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache avec mémoire cache dédiée, p.ex. instruction ou pile
G06F 12/0891 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p.ex. mémoires cache utilisant des moyens d’effacement, d’invalidation ou de réinitialisation
G06F 12/0893 - Mémoires cache caractérisées par leur organisation ou leur structure
G06F 12/0895 - Mémoires cache caractérisées par leur organisation ou leur structure de parties de mémoires cache, p.ex. répertoire ou matrice d’étiquettes
G06F 12/0897 - Mémoires cache caractérisées par leur organisation ou leur structure avec plusieurs niveaux de hiérarchie de mémoire cache
G06F 12/1009 - Traduction d'adresses avec tables de pages, p.ex. structures de table de page
G06F 12/128 - Commande de remplacement utilisant des algorithmes de remplacement adaptée aux systèmes de mémoires cache multidimensionnelles, p.ex. associatives d’ensemble, à plusieurs mémoires cache, multi-ensembles ou multi-niveaux
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p.ex. plusieurs processeurs de données à instruction unique
H03M 7/46 - Conversion en, ou à partir de codes à longueur de série, c. à d. par représentation du nombre de chiffres successifs ou groupes de chiffres de même type à l'aide d'un mot-code et d'un chiffre représentant ce type
Some embodiments include a voltage regulator including a clock node to receive an input clock signal, and first and second power switching blocks coupled to the clock node. The first power switching block includes a first clock generator and first switched capacitor circuitry. The first clock generator includes clock output nodes to provide first clock signals based on the input clock signal. The first switched capacitor circuitry includes input nodes to receive first control signals generated based on the first clock signals. The second power switching block includes a second clock generator and second switched capacitor circuitry. The second clock generator includes clock output nodes to provide second clock signals based on the input clock signal. The second switched capacitor circuitry includes input nodes to receive second control signals generated based on the second clock signals.
H02M 3/07 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des résistances ou des capacités, p.ex. diviseur de tension utilisant des capacités chargées et déchargées alternativement par des dispositifs à semi-conducteurs avec électrode de commande
H02M 1/00 - APPAREILS POUR LA TRANSFORMATION DE COURANT ALTERNATIF EN COURANT ALTERNATIF, DE COURANT ALTERNATIF EN COURANT CONTINU OU VICE VERSA OU DE COURANT CONTINU EN COURANT CONTINU ET EMPLOYÉS AVEC LES RÉSEAUX DE DISTRIBUTION D'ÉNERGIE OU DES SYSTÈMES D'ALI; TRANSFORMATION D'UNE PUISSANCE D'ENTRÉE EN COURANT CONTINU OU COURANT ALTERNATIF EN UNE PUISSANCE DE SORTIE DE CHOC; LEUR COMMANDE OU RÉGULATION - Détails d'appareils pour transformation
Embodiments herein relate to systems, apparatuses, techniques or processes for reducing the capacitance of a package that includes a die by at least partially surrounding the die within a mold compound and a dielectric material with different dielectric constants. Other embodiments may be described and/or claimed.
H01L 23/31 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par leur disposition
H01L 21/56 - Capsulations, p.ex. couches de capsulation, revêtements
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/42 - Choix ou disposition de matériaux de remplissage ou de pièces auxiliaires dans le conteneur pour faciliter le chauffage ou le refroidissement
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/552 - Protection contre les radiations, p.ex. la lumière
28.
INTEGRATED CIRCUIT DEVICES WITH FLIPPED STAIRCASE INTERCONNECT STRUCTURES
An example IC device includes a support structure; a device layer over or at least partially in the support structure, the device layer comprising transistors; and an interconnect layer. The device layer is between the support structure and the interconnect layer, and the interconnect layer includes a first conductive line and a second conductive line stacked above the first conductive line. A first end of the first conductive line is substantially aligned with a first end of the second conductive line along a plane perpendicular to the substrate, and a second end of the first conductive line is closer to the plane than a second end of the second conductive line. Such an arrangement of conductive lines may be referred to as “flipped staircase.”
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
29.
MEMORY CELL WITH TRANSISTOR HAVING INCREASED LEAKAGE CURRENT
A transistor may include a source region, a drain region, a channel region between the source region and the drain region in a first direction, a gate electrode, a source contact, and a drain contact. A first portion of the gate electrode is over the channel region in a second direction substantially perpendicular to the first direction. A second portion of the gate electrode is over a first portion of the drain region in the second direction. The source contact is over at least part of the source region. The drain contact is over a second portion of the drain region. A distance from an edge of the first portion of the drain region to an edge of the gate electrode or to an edge the first trench electrode in the first direction is greater than a fourth of a length of the gate electrode in the first direction.
An example IC device includes a substrate comprising a plurality of areas and one or more scribe lines defining boundaries of individual areas of the plurality of areas. The plurality of areas includes a first area and a second area. The IC device further includes a scribe line between the first area and the second area, a first device layer over the first area of the substrate and a first metallization stack over the first device layer, a second device layer over the second area of the substrate and a second metallization stack over the second device layer, and a conductive line extending (e.g., being materially and electrically continuous) between the first metallization stack and the second metallization stack, where a projection of the conductive line onto a plane parallel to the substrate and containing the scribe line intersects the scribe line.
Systems, apparatus, articles of manufacture, and methods are disclosed to self-align batch pick and place die bonding. Disclosed is an apparatus comprising a fluid dispensing assembly to dispense first amounts of water onto first hydrophilic regions of a first semiconductor wafer at a first point in time, the first hydrophilic regions having a first arrangement, and dispense second amounts of water onto second hydrophilic regions of a second semiconductor wafer at a second point in time, the second hydrophilic regions having a second arrangement, and a pick-and-place assembly to simultaneously position, at the first point in time, a first batch of dies corresponding to the first arrangement onto the first amounts of water dispensed on the first semiconductor wafer, and simultaneously position, at the second point in time, a second batch of dies corresponding to the second arrangement onto the second amounts of water dispensed on the second semiconductor wafer.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 21/67 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitement; Appareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants
H01L 21/68 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitement; Appareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le positionnement, l'orientation ou l'alignement
H01L 21/683 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitement; Appareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension
32.
TECHNIQUES FOR RESONANT ROTARY CLOCKING FOR DIE-TO-DIE COMMUNICATION
Various embodiments provide apparatuses, systems, and methods for resonant rotary clocking for die-to-die (D2D) communication in a multi-die system. A base die may include a resonant ring structure to form a plurality of rotary traveling wave oscillators (RTWOs) coupled to one another in a rotary oscillator array (ROA). The ROA may provide synchronized clock signals at deterministic phase points that are tapped from the resonant ring structure. Multiple dies may be coupled to the base die and may receive the tapped clock signals from respective tap points. The clock signals may be used for die-to-die communication and/or other purposes. Other embodiments may be described and claimed.
H03B 9/08 - Production d'oscillations par utilisation des effets du temps de transit utilisant des tubes à décharge utilisant un tube à onde progressive
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
33.
MULTI-CHIP PACKAGE AND METHOD OF PROVIDING DIE-TO-DIE INTERCONNECTS IN SAME
A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 21/683 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitement; Appareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/13 - Supports, p.ex. substrats isolants non amovibles caractérisés par leur forme
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
34.
FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING ADDITIVE METAL GATES
Gate-all-around integrated circuit structures having additive metal gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack having a P-type conductive layer with a first portion surrounding the nanowires of the first vertical arrangement of horizontal nanowires and a second portion extending laterally beside and spaced apart from the first portion. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack having an N-type conductive layer with a first portion surrounding the nanowires of the second vertical arrangement of horizontal nanowires and a second portion adjacent to and in contact with the second portion of the P-type conductive layer.
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
35.
VARIABLE GAIN AMPLIFIER WITH COMPLEMENTARILY SWITCHED NEUTRALIZED DIFFERENTIAL PAIR
An integrated circuit device includes a variable gain amplifier with multiple gain circuits coupled in parallel, where one or more of the multiple gain circuits comprises a first differential pair of transistors, and a complementarily switched second differential pair of transistors cross-connected to the first differential pair of transistors with a sign inversion relative to the first differential pair of transistors. Other examples are disclosed and claimed.
An integrated circuit device includes an electrostatic discharge (ESD) protection circuit comprising a plurality of P+/N-well diodes (P-diodes) and a plurality of N+/P-well (N-diodes) arranged in a stripe geometry, a p-tap anode stripe of the ESD protection circuit shared between a first P-diode and a second P-diode of the ESD protection circuit, and a n-tap cathode stripe of the ESD protection circuit shared between a first N-diode and a second N-diode of the ESD protection circuit. Other examples are disclosed and claimed.
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
H02H 9/04 - Circuits de protection de sécurité pour limiter l'excès de courant ou de tension sans déconnexion sensibles à un excès de tension
37.
APPARATUS AND METHOD FOR SECURE RESOURCE ALLOCATION
An apparatus and method for securely reserving resources for trusted execution. For example, one embodiment of a processor comprises: a plurality of cores, each core of the plurality of cores to provide at least one logical processor of a plurality of logical processors; a first plurality of registers, each register of the first plurality of registers to associate a class of service (CLOS) value with a corresponding logical processor of the plurality of logical processors; a second plurality of registers, each register of the second plurality of registers to indicate a portion of a shared resource to be allocated to a corresponding CLOS value; a first control register of a first logical processor of the plurality of logical processors to be configured with a reserved CLOS value associated with a trusted control structure; resource reservation circuitry configurable by secure firmware or software to indicate a reserved portion of the shared resource associated with the reserved CLOS value; and enforcement circuitry to limit access to the reserved portion of the shared resource to threads or logical processors associated with the reserved CLOS value.
An apparatus includes a clock monitoring circuit and a multiplexing circuit. The clock monitoring circuit includes an output terminal. The clock monitoring circuit is configured to generate a control signal based on monitoring a plurality of clock signals. The multiplexing circuit is coupled to the output terminal of the clock monitoring circuit and is configured to receive the control signal. The multiplexing circuit includes a first input terminal to receive a first signal generated based on a first clock signal of the plurality of clock signals. The multiplexing circuit includes a second input terminal to receive a second signal generated based on a second clock signal of the plurality of clock signals. The multiplexing circuit includes an output terminal to output one of the first signal or the second signal based on the control signal.
Integrated capacitors are described. In an example, an integrated capacitor structure includes alternating first metal lines and second metal lines in a dielectric layer of a metallization layer in a stack of metallization layers, the first metal lines coupled together, and the second metal lines coupled together. A metal plate is over or beneath the alternating first metal lines and second metal lines. A dielectric liner layer is between the alternating first metal lines and second metal lines and the metal plate.
Integrated circuit structures having backside source or drain contact selectivity are described. In an example, an integrated circuit structure includes a first epitaxial source or drain structure at an end of a first plurality of horizontally stacked nanowires or fin, with a first conductive source or drain contact vertically beneath and in contact with a bottom of the first epitaxial source or drain structure, and with a first hardmask material beneath and in contact with the first conductive source or drain contact. A second epitaxial source or drain structure is at an end of a second plurality of horizontally stacked nanowires or fin, with a second conductive source or drain contact vertically beneath and in contact with a bottom of the second epitaxial source or drain structure, and a second hardmask material beneath and in contact with the second conductive source or drain contact.
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
Described herein is a graphics processor including a plurality of processing clusters coupled with a host interface, each processing cluster comprising a plurality of multiprocessors, the plurality of multiprocessors interconnected via a data interconnect, and each multiprocessor comprising sparse matrix multiply acceleration hardware including a systolic processing array with feedback inputs.
G06F 9/30 - Dispositions pour exécuter des instructions machines, p.ex. décodage d'instructions
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p.ex. plusieurs processeurs de données à instruction unique
42.
MEMORY WITH ONE ACCESS TRANSISTOR COUPLED TO MULTIPLE CAPACITORS
IC devices implementing memory with one access transistor coupled to multiple capacitors are disclosed. An example IC device includes a support structure (e.g., a substrate), an access transistor over the support structure, the access transistor having a region that is either a source region or a drain region, and a plurality of capacitors where at least two or more of the capacitors are in different layers above the access transistor. First capacitor electrodes of the plurality of capacitors are coupled to the region, and second capacitor electrodes of the plurality of capacitors are coupled to respective electrically conductive lines. IC devices implementing memory with one access transistor coupled to multiple capacitors as described herein may be used to address the scaling challenges of conventional 1T-1C memory technology and enable high-density embedded memory compatible with advanced CMOS processes.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
H10B 53/30 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par la région noyau de mémoire
H10B 53/20 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par les agencements tridimensionnels, p ex. avec des cellules à des niveaux différents de hauteur
H10N 97/00 - Dispositifs électriques à l’état solide à film mince ou à film épais, non prévus ailleurs
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
43.
METHODS AND APPARATUS FOR SELF-ALIGNING BATCH PICK AND PLACE DIE BONDING
Systems, apparatus, articles of manufacture, and methods are disclosed to self-align batch pick and place die bonding. Disclosed is an apparatus comprising a fluid dispensing assembly to dispense first amounts of water onto first hydrophilic regions of a first semiconductor wafer at a first point in time, the first hydrophilic regions having a first arrangement, and dispense second amounts of water onto second hydrophilic regions of a second semiconductor wafer at a second point in time, the second hydrophilic regions having a second arrangement, and a pick-and-place assembly to simultaneously position, at the first point in time, a first batch of dies corresponding to the first arrangement onto the first amounts of water dispensed on the first semiconductor wafer, and simultaneously position, at the second point in time, a second batch of dies corresponding to the second arrangement onto the second amounts of water dispensed on the second semiconductor wafer.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 21/683 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitement; Appareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension
H01L 21/677 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitement; Appareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le transport, p.ex. entre différents postes de travail
44.
COMPLEMENTARY FIELD-EFFECT TRANSISTOR WITH FORKED SEMICONDUCTOR STRUCTURE
A CFET may include two or more transistors stacked over each other. A transistor may be a FET including a forked semiconductor structure. The source region and drain region of a transistor may have a forked shape including a body and one or more branches protruding from the body. A branch may include a fin, nanoribbon, etc. The channel region may be between a branch of the source region and a branch of the drain region. The body of the source region and the body of the drain region may be on opposite sides of the channel region in two perpendicular directions. The two bodies may be diagonally arranged with respect to the channel region. The body of the source region or drain region may be over a contact that is electrically coupled to a frontside metal layer or a backside metal layer for signal transmission or power delivery.
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 23/528 - Configuration de la structure d'interconnexion
45.
DEEP NEURAL NETWORK ACCELERATOR WITH MEMORY HAVING TWO-LEVEL TOPOLOGY
A deep neural network (DNN) accelerator includes one or more compute blocks that perform deep learning operations in DNNs. A compute block includes a memory and one or more processing elements. The memory may include bank groups, each of which includes memory banks. The memory may also include a group selection module, buffers, interconnects, and bank selection modules. The group selection module may select a bank group for a data transfer request from a processing element and store the data transfer request in a buffer associated with the bank group. The memory address in the data transfer request may be transmitted from the buffer to a bank selection module associated with the bank group through an interconnect. The bank selection module may select a memory bank in the bank group based on the memory address. Data can be read from or written into the selected memory bank.
Systems or methods of the present disclosure may provide a library (102) including multiple regional bitstreams (112) that may be pre-generated by a manufacturer and/or custom generated by a designer that may be used to implement a design onto an integrated circuit device (12). The design may be decomposed into one or more regional bitstreams (112) and stitched to form a larger combined bitstream to be implemented as coarse-grained operations on the integrated circuit device (12), thereby decreasing compilation time experienced by the designer. The combined bitstreams may be loaded into all or a portion of the integrated circuit device (12) to realize the design. Additionally or alternatively, the integrated circuit device (12) may include hardened networks-on-chip (NOCs) (224) to improve data routing within the combined bitstream.
An apparatus of a New Radio (NR) User Equipment (UE), includes the processing circuitry to: detect a synchronization signal block (SSB) from a NR Node B (gNB); determine a number of multiple physical random access channel (PRACH) transmissions, wherein respective PRACH transmissions of the multiple PRACH transmissions correspond to repetitions of each other and to a preamble; determine a set of valid PRACH occasions associated with the SSB, wherein respective ones of the valid PRACH occasions of the set: are in sequential respective time instances; and use same frequency resources as any immediately prior PRACH occasion of the set; and send the multiple PRACH transmissions in the set for transmission to the gNB.
A CFET may include two or more transistors stacked over each other. A transistor may be a FET including a forked semiconductor structure. The source region and drain region of a transistor may have a forked shape including a body and one or more branches protruding from the body. A branch may include a fin, nanoribbon, etc. The channel region may be between a branch of the source region and a branch of the drain region. The body of the source region and the body of the drain region may be on opposite sides of the channel region in two perpendicular directions. The two bodies may be diagonally arranged with respect to the channel region. The body of the source region or drain region may be over a contact that is electrically coupled to a frontside metal layer or a backside metal layer for signal transmission or power delivery.
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
IC devices implementing memory with one access transistor coupled to multiple capacitors are disclosed. An example IC device includes a support structure (e.g., a substrate), an access transistor over the support structure, the access transistor having a region that is either a source region or a drain region, and a plurality of capacitors where at least two or more of the capacitors are in different layers above the access transistor. First capacitor electrodes of the plurality of capacitors are coupled to the region, and second capacitor electrodes of the plurality of capacitors are coupled to respective electrically conductive lines. IC devices implementing memory with one access transistor coupled to multiple capacitors as described herein may be used to address the scaling challenges of conventional 1T-1C memory technology and enable high-density embedded memory compatible with advanced CMOS processes.
H10B 53/30 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par la région noyau de mémoire
50.
GLASS LAYERS AND CAPACITORS FOR USE WITH INTEGRATED CIRCUIT PACKAGES
Glass layers and capacitors for use with integrated circuit packages are disclosed. An example integrated circuit (IC) package includes a semiconductor die, a glass layer, and a capacitor electrically coupled to the semiconductor die, at least one side of the capacitor enclosed by the glass layer, the capacitor positioned closer to the glass layer than the semiconductor die is to the glass layer.
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
H01L 23/31 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par leur disposition
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 27/01 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant uniquement des éléments à film mince ou à film épais formés sur un substrat isolant commun
H01Q 1/22 - Supports; Moyens de montage par association structurale avec d'autres équipements ou objets
Heat exchange apparatuses and methods for hyperbaric cooling fan applications such as computing devices. The apparatus comprises a material with high thermal conductivity and is configured to be overlaid on an internal surface of the housing, such that an internal surface of the apparatus is exposed to the hot air flowing inside the housing, and an external surface of the apparatus occludes at least some of the existing through-holes of the housing. In operation, the apparatus converts the through-holes into passive heat exchanging regions that passively transfer heat from inside the housing to outside the housing, which brings the internal air temperature and junction temperature (Tj) of the heat generating components down. Provided embodiments do not require reworking of the original industrial design (ID) of the housing.
Methods, systems, apparatus, and articles of manufacture to validate timing constraints for an integrated circuit are disclosed. An example apparatus disclosed herein includes programmable circuitry to obtain an assumption property associated with a system on a chip (SoC) architecture, obtain a timing assertion associated with the SoC architecture, determine, using a formal property verification (FPV) tool, valid functional vectors and counter examples for the SoC architecture based on the assumption property and the timing assertion, and determine whether to accept a timing constraint based on at least one of the valid functional vectors or the counter examples, the timing constraint corresponding to the timing assertion.
Embodiments herein relate to a multi-bit flip-flop circuit which uses unidirectional transistors to allow sharing of transistors among a set of flip-flops, while avoiding charge sharing within or between the flip-flops. Clock devices in the circuit can be shared to reduce the clock transistor gate capacitance and associated power consumption. The shared transistors can provide keeper circuits and/or tri-state inverters in a primary latch and a secondary latch in each flip-flop. One example implementation uses tri-state keeper sharing. Another example implementation uses tri-state keeper and/or pass gate sharing. Another example implementation uses pass gate sharing and no keeper.
H03K 17/687 - Commutation ou ouverture de porte électronique, c. à d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
54.
METHODS AND APPARATUS TO PHOTOLITHOGRAPHICALLY PATTERN MATERIALS IN INTEGRATED CIRCUIT PACKAGES
Systems, apparatus, articles of manufacture, and methods to photolithographically pattern materials in integrated circuit packages are disclosed. An example photolithography mask includes: a transparent substrate, and an opaque material supported by the transparent substrate. The opaque material covers a first area of the transparent substrate. The example photolithography mask further includes an optical filter supported by the transparent substrate. The optical filter covers a second area of the transparent substrate. The second area is distinct from the first area. Both the opaque material and the optical material are spaced apart from a third area of the transparent substrate
G03F 1/38 - Masques à caractéristiques supplémentaires, p.ex. marquages pour l'alignement ou les tests, ou couches particulières; Leur préparation
H01L 21/48 - Fabrication ou traitement de parties, p.ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes
55.
PEROVSKITE-BASED FIELD EFFECT TRANSISTOR (FET) DEVICES ENABLED BY EPITAXIAL LATERAL OVERGROWTH
A transistor device may be formed with a doped perovskite material as a channel region. The doped perovskite material may be formed via an epitaxial growth process from a seed layer, and the channel regions of the transistor device may be formed from lateral overgrowth from the epitaxial growth process.
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/66 - Types de dispositifs semi-conducteurs
A device for detecting a dynamic object, comprising a processor configured to determine a first point density of a first volume around a first point in a first image, the first image being an image of an environment of a robot, the image including image 3D data; determine one or more second point densities, wherein each second point density is a point density of a second volume about a second point, wherein the second point corresponds to the first point in each of one or more second images, the one or more second images of the environment being one or more images taken prior to the first image and including image data corresponding to the three dimensions; and classify the first point as dynamic or static based on a comparison of the first point density and the one or more second point densities.
G06V 10/764 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant la classification, p.ex. des objets vidéo
G06V 20/70 - RECONNAISSANCE OU COMPRÉHENSION D’IMAGES OU DE VIDÉOS Éléments spécifiques à la scène Étiquetage du contenu de scène, p.ex. en tirant des représentations syntaxiques ou sémantiques
Technology providing in-memory neural network protection can include a memory to store a neural network, and a processor executing instructions to generate a neural network memory structure having a plurality of memory blocks in the memory, scatter the neural network among the plurality of memory blocks based on a randomized memory storage pattern, and reshuffle the neural network among the plurality of memory blocks based on a neural network memory access pattern. Scattering the neural network model can include dividing each layer of the neural network into a plurality of chunks, for each layer, selecting, for each chunk of the plurality of chunks, one of the plurality of memory blocks based on the randomized memory storage pattern, and storing each chunk in the respective selected memory block. The plurality of memory blocks can be organized into a groups of memory blocks and be divided between stack space and heap space.
Described herein is a generic hardware/software communication (HSC) channel that facilitates the re-use of pre-silicon DPI methods to enable FPGA-based post-silicon validation. The HSC channel translates a DPI interface into a hardware FIFO based mechanism. This translation allows the reuse of the methods without having to re-implement the entire flow in pure hardware. The core logic for the transactor remains the same, while only a small layer of the transactor is converted into the FIFO based mechanism.
Systems, apparatuses and methods may provide for technology that conducts, in accordance with a first instruction, a load of a block of data into a register, wherein the block of data is to include a plurality of lanes, conducts, in accordance with a second instruction, a first bitwise mask application to each lane in the plurality of lanes, and extracts a set of vector dimensions from the block of data based on the first bitwise mask application.
Disclosed herein are components for millimeter-wave communication, as well as related methods and systems. In one aspect, a microelectronic support for millimeter-wave communication includes a millimeter-wave communication transmission line, wherein the transmission line includes a trace in a metal layer, wherein the trace is electrically coupled to a via by a via pad in the metal layer; and a ground plane in the metal layer, wherein one or more metal portions contact the via pad and the ground plane.
An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des groupes principaux , ou dans une seule sous-classe de , , p.ex. circuit hybrides
62.
STANDOFF-SPRING COMBINATION FITTING FOR THERMAL SOLUTIONS
Example fittings that combine standoffs and springs for supporting thermal solutions are disclosed herein. An example electronic device includes a chassis; a substrate; a thermal solution; and a fitting to separate the substrate from the chassis and to separate the thermal solution from the substrate, the fitting including a standoff end and a spring end.
This disclosure describes systems, methods, and devices related to block acknowledgment (ACK) overhead reduction. A device may receive a soliciting physical layer convergence protocol data unit (PPDU). The device may encode a multiple station device (Multi-STA) block acknowledgment (BA) as a response to the soliciting PPDU. The device may transmit the Multi-STA BA in response to the PPDU. The device may manage multiple Per Association Identification (AID) Traffic Identifier (TID) Information (Per AID TID Info) entries with the same AID and TID in the same Multi-STA BA. The device may set the Per AID TID Info entries with the same AID and TID to be consecutive.
H04W 28/06 - Optimisation, p.ex. compression de l'en-tête, calibrage des informations
H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue
H04L 1/1607 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue en utilisant un canal de retour dans lesquelles le canal de retour transporte des signaux de contrôle, p.ex. répétition de signaux de demande - Détails du signal de contrôle
H04L 5/00 - Dispositions destinées à permettre l'usage multiple de la voie de transmission
64.
VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF
A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.
A compute node coupled to a computer network via a computing device that includes communications for communicating with the computer network and persistent instructions for providing control functions to the computing device, wherein the control functions are defined by protocol data. An update control module of the computing device may receive update data from a remote node in the computer network via the communications, wherein the update data includes new protocol data for the persistent instructions. A protocol parser module may parse the update data and generate metadata relating to the update data. A classifier module may receive rules for the control functions, wherein the rules are based at least in part on the update data and metadata. A compiler may compile the parsed update data to the persistent instructions for providing new control functions to the computing device based at least in part on the received rules.
H04L 41/082 - Réglages de configuration caractérisés par les conditions déclenchant un changement de paramètres la condition étant des mises à jour ou des mises à niveau des fonctionnalités réseau
H04L 67/00 - Dispositions ou protocoles de réseau pour la prise en charge de services ou d'applications réseau
H04L 67/04 - Protocoles spécialement adaptés à la portabilité du terminal
66.
FORKSHEET DEVICES WITH DIELECTRIC SPINE AT CELL BOUNDARY
Techniques are provided herein to form semiconductor devices having cells that include forksheet devices with source or drain regions of the same dopant type on both sides of the forksheet dielectric spine. The techniques can be used in any number of integrated circuit applications and are particularly useful with respect to logic and memory cells. The forksheet devices may include all p-type source or drain regions on both sides of the dielectric spine or all n-type source or drain regions on both sides of the dielectric spine. Using forksheet devices with the same dopant type allows for both forksheet transistors and gate-all-around (GAA) transistors to be included within the same cell. The cell boundaries may also be placed along the forksheet dielectric spines rather than along gate cuts, which provides greater flexibility when designing multi-height cells.
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
Integrated circuit structures having deep via bar isolation are described. For example, an integrated circuit structure includes a plurality of gate lines. A plurality of trench contacts extends over a plurality of source or drain structures, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines. A backside metal routing layer is extending beneath one or more of the plurality of gate lines and beneath one or more of the plurality of trench contacts. A conductive structure couples the backside metal routing layer to one of the one or more of the plurality of trench contacts. The conductive structure includes has a cut between first and second conductive structure portions. A cut in a first one of the plurality of gate lines adjacent to the cut in the conductive structure is smaller than a cut in a second one of the plurality of gate lines adjacent to the first or second conductive structure portions.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
A system, article, device, apparatus, and method of binaural audio emulation comprises receiving, by processor circuitry, multiple audio signals from multiple microphones and overlapping in a same time and associated with a same at least one audio source. The method also comprises generating binaural audio signals comprising inputting at least one version of the multiple audio signals into a neural network.
Integrated circuit structures having backside plug last approach are described. In an example, an integrated circuit structure includes a plurality of horizontally stacked nanowires or a fin. A gate stack is over the plurality of horizontally stacked nanowires or the fin. A conductive trench contact structure is at a level below the plurality of horizontally stacked nanowires or the fin, the conductive trench contact structure having outwardly tapered sidewalls from a top of the conductive trench contact structure to a bottom of the conductive trench contact structure.
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
Some embodiments relate generally to memory arrays having complementary bitlines. With some implementations, charge sharing to facilitate midrail read operations may be incorporated therein.
G06F 12/084 - Systèmes de mémoire cache multi-utilisateurs, multiprocesseurs ou multitraitement avec mémoire cache partagée
G11C 11/412 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules avec réaction positive, c. à d. des cellules ne nécessitant pas de rafraîchissement ou de régénération de la charge, p.ex. multivibrateur bistable, déclencheur de Schmitt utilisant uniquement des transistors à effet de champ
71.
ANALOG-TO-DIGITAL CONVERSION USING DIFFERENTIAL OSCILLATOR TECHNIQUES
An apparatus includes a pair of voltage-controlled oscillators (VCOs). The pair includes a first VCO with a first biasing stage receiving an input voltage signal and a first output stage coupled to the first biasing stage. The first output stage generates a first output frequency signal based on the input voltage signal. The pair also includes a second VCO. The second VCO includes a second biasing stage receiving the input voltage signal and a second output stage coupled to the second biasing stage. The second output stage generates a second output frequency signal based on the input voltage signal.
Techniques are described for designing and forming cells having transistor devices. In an example, an integrated circuit structure includes a plurality of cells where adjacent cells have a decreased distance between them along their height and a staggered via arrangement. Accordingly, a first cell may be adjacent to a second cell along a shared cell boundary. A first via is provided between a first gate structure of the first cell adjacent to the cell boundary and a first metal layer above the first gate structure, and a second via is provided between a second gate structure of the second cell adjacent to the cell boundary and a second metal layer above the second gate structure. No part of the first via is aligned with any part of the second via along the first direction.
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
Some embodiments include an apparatus having a first node to receive a connection from a gate of a first transistor of a voltage converter; a second node to receive a connection from a gate of a second transistor of the voltage converter; a third node to receive a connection from a node between the first and second transistors; a capacitor including a first plate coupled to the third node; a first driver including an output node coupled to the first node, a first voltage node coupled to the first plate of the capacitor, and a second voltage node coupled to a second plate of the capacitor; a second driver including an output node coupled to the second node; and a circuit including third transistors coupled in series between the second voltage node and a third voltage node.
H02M 3/155 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
H02M 1/088 - Circuits spécialement adaptés à la production d'une tension de commande pour les dispositifs à semi-conducteurs incorporés dans des convertisseurs statiques pour la commande simultanée de dispositifs à semi-conducteurs connectés en série ou en parallèle
Integrated capacitors are described. In an example, an integrated capacitor structure includes alternating first metal lines and second metal lines in a dielectric layer of a metallization layer in a stack of metallization layers, the first metal lines coupled together, and the second metal lines coupled together. A metal plate is over or beneath the alternating first metal lines and second metal lines. The metal plate is coupled to the first metal lines or the second metal lines by vias.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
G06F 30/367 - Vérification de la conception, p.ex. par simulation, programme de simulation avec emphase de circuit intégré [SPICE], méthodes directes ou de relaxation
75.
CONDUCTIVE LINES HAVING MOLYBDENUM LINER AND TUNGSTEN FILL FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION
Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes a plurality of conductive lines, individual ones of the plurality of conductive lines having a liner including molybdenum (Mo), and a fill including tungsten (W). The integrated circuit structure also includes an inter-layer dielectric (ILD) structure having portions between adjacent ones of the plurality of conductive lines.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
H01L 23/498 - Connexions électriques sur des substrats isolants
76.
PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS TO ATOMICALLY STORE TO MEMORY DATA WIDER THAN A NATIVELY SUPPORTED DATA WIDTH
A processor includes a widest set of data registers that corresponds to a given logical processor. Each of the data registers of the widest set have a first width in bits. A decode unit that corresponds to the given logical processor is to decode instructions that specify the data registers of the widest set, and is to decode an atomic store to memory instruction. The atomic store to memory instruction is to indicate data that is to have a second width in bits that is wider than the first width in bits. The atomic store to memory instruction is to indicate memory address information associated with a memory location. An execution unit is coupled with the decode unit. The execution unit, in response to the atomic store to memory instruction, is to atomically store the indicated data to the memory location.
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p.ex. plusieurs processeurs de données à instruction unique
G06F 9/30 - Dispositions pour exécuter des instructions machines, p.ex. décodage d'instructions
An apparatus to facilitate machine learning matrix processing is disclosed. The apparatus comprises a memory to store matrix data one or more processors to execute an instruction to examine a message descriptor included in the instruction to determine a type of matrix layout manipulation operation that is to be executed, examine a message header included in the instruction having a plurality of parameters that define a two-dimensional (2D) memory surface that is to be retrieved, retrieve one or more blocks of the matrix data from the memory based on the plurality of parameters and a register file including a plurality of registers, wherein the one or more blocks of the matrix data is stored within a first set of the plurality of registers.
G06F 7/78 - Dispositions pour le réagencement, la permutation ou la sélection de données selon des règles prédéterminées, indépendamment du contenu des données pour changer l'ordre du flux des données, p.ex. transposition matricielle ou tampons du type pile d'assiettes [LIFO]; Gestion des occurrences du dépassement de la capacité du système ou de sa sous-alimentation à cet effet
G06F 9/30 - Dispositions pour exécuter des instructions machines, p.ex. décodage d'instructions
G06N 3/044 - Réseaux récurrents, p.ex. réseaux de Hopfield
G06N 3/084 - Rétropropagation, p.ex. suivant l’algorithme du gradient
78.
ENHANCING TEMPERATURE STABILITY IN REFERENCE CLOCK APPLICATIONS USING RESONATOR ARRAYS
Embodiments herein relate to a reference clock that includes an array of resonators with different turnover temperatures. The resonators may be Microelectromechanical Systems (MEMS) resonators with different doping concentrations, or quartz crystal resonators with different cut angles, for example. For MEMS resonators in particular, the turnover temperature can be adjusted by providing an overlying oxide layer with different thicknesses. In another approach, the resonators are piezoelectric-on-silicon resonators with different finger pitch-to-thickness ratios. A control circuit obtains a sensed temperature from a temperature sensor and selects one of the resonators having a turnover temperature in a temperature range corresponding to the sensed temperature. Each resonator may have a turnover temperature in a different temperature range. The resonators may have separate drivers or have a common driver.
H03B 5/04 - Modifications du générateur pour compenser des variations dans les grandeurs physiques, p.ex. alimentation, charge, température
H03B 5/36 - Production d'oscillation au moyen d'un amplificateur comportant un circuit de réaction entre sa sortie et son entrée l'élément déterminant la fréquence étant un résonateur électromécanique un résonateur piézo-électrique l'élément actif de l'amplificateur comportant un dispositif semi-conducteur
79.
ACCESS POINT CONFIGURED FOR UNAVAILABILITY ADVERTISEMENT WITH TARGET WAKE-UP TIME (TWT)
An access point (AP) operating as a Target Wake-up Time (TWT) scheduling AP may encode a broadcast TWT element for transmission to advertise a broadcast TWT with one or more broadcast TWT Service Periods (SPs). When the broadcast TWT element carries one or more broadcast TWT parameter set fields with a broadcast TWT ID subfield equal to zero and has a Responder Power Management (PM) Mode subfield equal to one, the AP may set a NDP Paging Indicator/Unavailability Mode subfield of a Control Field of the broadcast TWT element to a value of zero to indicate that the AP is unavailable outside of the one or more broadcast TWT SPs except for other TWT SPs that are setup with the AP or advertised by the AP. The AP may set the NDP Paging Indicator/Unavailability Mode subfield of the Control field to a value of one to indicate that the AP is unavailable outside of the one or more broadcast TWT SPs including unavailable during any time that falls within the other TWT SPs that are setup with the AP or advertised by the AP.
An example method includes, based on a request from the third-party entity to join the edge network, initiating a Zero-Knowledge Proof (ZKP) protocol by generating a common reference string (CRS) to establish public parameters within the edge network; transmitting the CRS to the third-party entity and an authorization server; obtaining an authorization of the third-party entity from the authorization server, the authorization server authenticating the third-party entity based on a ZKP proof constructed by the third-party entity using the CRS and a private credential of the third-party entity; authorizing the third-party entity to join the edge network based on the authorization; and deploying a smart contract on a distributed ledger, wherein the smart contract specifies conditions under which the third-party entity is granted access to the edge network, and wherein the distributed ledger records transactions related to access permissions of the third-party entity.
H04L 9/32 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
H04L 41/5003 - Gestion des accords de niveau de service [SLA]; Interaction entre l'accord de niveau de service et la qualité de service [QoS]
81.
ENHANCED I/O SEMICONDUCTOR CHIP PACKAGE AND COOLING ASSEMBLY HAVING SIDE I/OS
A semiconductor chip package is described. The semiconductor chip package has a substrate. The substrate has side I/Os on the additional surface area of the substrate. The side I/Os are coupled to I/Os of a semiconductor chip within the semiconductor chip package. A cooling assembly has also been described. The cooling assembly has a passageway to guide a cable to connect to a semiconductor chip's side I/Os that are located between a base of a cooling mass and an electronic circuit board that is between a bolster plate and a back plate and that is coupled to second I/Os of the semiconductor chip through a socket that the semiconductor chip's package is plugged into.
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
An IC device includes a gate electrode having multiple lengths. The length of a first portion of the gate electrode, which is over a channel region in a semiconductor structure, may be longer (e.g., about 0.5-3 nm longer) than the length of a second portion of the gate electrode, which is over a channel region in another semiconductor structure. The pitches at the two portions of the gate electrode may be the same or substantially similar. The lengths of the gate electrode can be differentiated by using dry clean based removal of a dielectric material surrounding the semiconductor structures. A larger amount of the dielectric material may be removed at a first region than a second region so that the gap at the first region can be longer than the gap at the second region. A conductive material may be provided to fill the gaps to form the gate electrode.
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
83.
SUBSTRATES INCLUDING MICRO-STRUCTURED THIN FILM CAPACITORS
Disclosed herein are microelectronic assemblies including strengthened glass cores, as well as related devices and methods. In some embodiments, a microelectronic substrate with an in situ capacitor, the capacitor may include a first conductive layer having first microstructures at a first surface, a second conductive layer on the first conductive layer and having second microstructures at a second surface, where the second microstructures vertically interlock with the first microstructures, and a high-k dielectric material between the first microstructures and the second microstructures.
H01L 27/01 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant uniquement des éléments à film mince ou à film épais formés sur un substrat isolant commun
H01G 4/33 - Condensateurs à film mince ou à film épais
84.
WIRELESS INTERCONNECTS IN INTEGRATED CIRCUIT PACKAGE SUBSTRATES WITH GLASS CORES
Wireless interconnects in integrated circuit package substrates with glass cores are disclosed. An example apparatus includes a semiconductor die. The example apparatus further includes a package substrate supporting the semiconductor die. The package substrate includes a glass core. The example apparatus also includes an antenna within the glass core.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a first die having a first surface, an opposing second surface, and a first footprint; a second die electrically coupled to the second surface of the first die and having a second footprint, wherein the second footprint is smaller than the first footprint; and a mold material on the second surface of the first die and surrounding the second die, the mold material including a trench.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/16 - Matériaux de remplissage ou pièces auxiliaires dans le conteneur, p.ex. anneaux de centrage
H01L 23/31 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par leur disposition
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
86.
TRENCH CONNECTION OVER DISCONNECTED EPITAXIAL STRUCTURE USING DIRECTED SELF-ASSEMBLY
Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for creating flyover trench connectors within a transistor structure, where a first portion of the trench connector is electrically coupled with a first epitaxial structure and where a second portion of the trench connector extends above but is not electrically coupled with a second epitaxial structure. Other embodiments may be described and/or claimed.
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
Described herein is a graphics processor comprising a plurality of processing elements associated with performance monitoring circuitry. The performance monitoring circuitry is configurable to generate performance data for multiple concurrently executed workloads via flexible event filtering hardware that can isolate a data stream of performance events and display performance monitoring data that is specific to each of the multiple concurrently executed workloads. In one embodiment, performance monitoring for the separate workloads can be configured, for example, by filtering based on the respective contexts used to execute the workloads, the specific instructions executed respectively by the workloads, or the datatypes used respectively by the workloads.
Some demonstrative aspects include radar apparatuses, devices, systems and methods. In one example, an apparatus may include a plurality of Transmit (Tx) antennas to transmit radar Tx signals, and a plurality of Receive (Rx) antennas to receive radar Rx signals. For example, the radar Rx signals may be based on the radar Tx signals. The apparatus may be implemented, for example, as part of a radar device, for example, as part of a vehicle including the radar device. In other aspects, the apparatus may include any other additional or alternative elements and/or may be implemented as part of any other device.
G01S 7/35 - DÉTERMINATION DE LA DIRECTION PAR RADIO; RADIO-NAVIGATION; DÉTERMINATION DE LA DISTANCE OU DE LA VITESSE EN UTILISANT DES ONDES RADIO; LOCALISATION OU DÉTECTION DE LA PRÉSENCE EN UTILISANT LA RÉFLEXION OU LA RERADIATION D'ONDES RADIO; DISPOSITIONS ANALOGUES UTILISANT D'AUTRES ONDES - Détails des systèmes correspondant aux groupes , , de systèmes selon le groupe - Détails de systèmes non impulsionnels
B60W 60/00 - Systèmes d’aide à la conduite spécialement adaptés aux véhicules routiers autonomes
G01S 13/89 - Radar ou systèmes analogues, spécialement adaptés pour des applications spécifiques pour la cartographie ou la représentation
H01Q 1/32 - Adaptation pour l'utilisation dans ou sur les véhicules routiers ou ferroviaires
H01Q 21/22 - Réseaux d'unités d'antennes, de même polarisation, excitées individuellement et espacées entre elles les unités d'antennes du réseau étant excitées d'une façon non uniforme en amplitude ou en phase, p.ex. réseau à prises ou réseau bidirectionnel
89.
METHODS AND APPARATUS TO DETECT ANOMALIES IN VIDEO DATA
Methods and apparatus to detect anomalies in video data are disclosed. An example apparatus disclosed herein generates a reconstructed feature vector corresponding to an input feature vector representative of a video segment, the reconstructed feature vector based on a transformation applied to the input feature vector and an inverse of the transformation applied to an output of the transformation, the input feature vector and the reconstructed feature vector including features associated with a plurality of dimensions including a time dimension. The disclosed example apparatus also generates an error vector based on a difference between the input feature vector and the reconstructed feature vector. The disclosed example apparatus further generates an anomaly map based on sums of elements of the error vector across at least the time dimension, the anomaly map corresponding to the video segment.
G06V 20/40 - RECONNAISSANCE OU COMPRÉHENSION D’IMAGES OU DE VIDÉOS Éléments spécifiques à la scène dans le contenu vidéo
G06V 10/25 - Détermination d’une région d’intérêt [ROI] ou d’un volume d’intérêt [VOI]
G06V 10/77 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant l’intégration et la réduction de données, p.ex. analyse en composantes principales [PCA] ou analyse en composantes indépendantes [ ICA] ou cartes auto-organisatrices [SOM]; Séparation aveugle de source
90.
DEVICE, METHOD AND SYSTEM FOR IMPROVED ELECTROSTATIC DISCHARGE PROTECTION
Techniques and mechanisms for a DC-DC voltage converter to mitigate a risk of damage to circuitry due to electrostatic discharge (ESD). In an embodiment, a protection circuit of the DC-DC voltage converter comprises a pull-up circuit and a pull-down circuit which are coupled in series between a first interconnect and a second interconnect, which are to receive a first supply voltage and a second supply voltage, respectively. A voltage divider comprises capacitors which are coupled in series with each other between the first interconnect and the second interconnect. Control circuitry is coupled with the voltage divider, and is further coupled to automatically configure a first operational mode based on an ESD event. During the first mode, the pull-up circuit is disabled and the pull-down circuit is enabled. In another embodiment, a resistor-capacitor (RC) circuit automatically transitions the protection circuit from the first mode.
H02H 9/04 - Circuits de protection de sécurité pour limiter l'excès de courant ou de tension sans déconnexion sensibles à un excès de tension
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
H03K 19/003 - Modifications pour accroître la fiabilité
Disclosed is an integrated circuit with a metallization stack that has thermal tower assemblages formed from wires in two or more metal layers to assist in dissipating heat out of the metallization stack.
A processor of an aspect includes decoder circuitry to decode an instruction indicating a source floating-point operand, having a floating-point data element, and indicating a destination register. The element has a sign bit, an N-bit first exponent value, and M bits. Execution circuitry of the processor is to interpret the M bits as an M-bit significand, when the N-bit first exponent value is not all zeroes or all ones, and interpret the M bits as including a second exponent value in at least one of the M bits, and a less than M-bit significand in at least one other of the M bits, when the N-bit first exponent value is either all zeroes or all ones. The execution unit is to perform an operation on the source floating-point operand to generate a result floating-point operand, and to store the result floating-point operand in the destination register.
Guard rings are described. In an example, a semiconductor die includes an active device layer including a plurality of nanoribbon devices. A dielectric structure is over the active device layer. A first die-edge metal guard ring is in the dielectric structure and around an outer perimeter of the plurality of nanoribbon devices. A plurality of metallization layers is in the dielectric structure and within the first die-edge metal guard ring. A plurality of direct backside contacts extend to the active device layer. A plurality of backside metallization structures is beneath the plurality of direct backside contacts. The plurality of direct backside contacts are connected to the plurality of backside metallization structures. A second die-edge metal guard ring is laterally around the plurality of backside metallization structures.
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/50 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes pour des dispositifs à circuit intégré
H01L 23/58 - Dispositions électriques structurelles non prévues ailleurs pour dispositifs semi-conducteurs
A system that includes a graphics processing unit (GPU) that includes at least one processor and multiple registers. In some examples, based on execution of an instruction by at least one of the at least one processor to allocate a particular number of registers to a thread, assign the number of registers to the thread. In some examples, a compiler is to consider register demands for a code segment and number of available registers in determining a number of registers to allocate to the code segment.
Provided is a power estimation tool for estimating power from an RTL simulation waveform. The tool may use an inference engine that uses an ML trained power estimation model.
G06F 30/327 - Synthèse logique; Synthèse de comportement, p.ex. logique de correspondance, langage de description de matériel [HDL] à liste d’interconnections [Netlist], langage de haut niveau à langage de transfert entre registres [RTL] ou liste d’interconnections [Netlist]
G06F 30/31 - Saisie informatique, p.ex. éditeurs spécifiquement adaptés à la conception de circuits
96.
SUBSTRATE PROCESS FLOW FOR ENABLING SUBSTRATE TO DIE HYBRID BONDING
Various embodiments disclosed relate to methods of making hybrid bonds for semiconductor assemblies, such as including substrate, semiconductor dies, and/or interconnects. The present disclosure includes a hybrid bond assembly having a via and a dielectric layer, each of the via and the dielectric layer bonding two or more components to each other.
Disclosed herein are IC devices with 3D interlocked corrugated capacitor structures. An example IC device includes a support structure (e.g., a substrate, a die, a wafer, or a chip), an insulator material over the support structure, and a first and a second corrugated capacitor structures extending into the insulator material, where a projection of at least one of the protrusions of the first corrugated capacitor structure onto a plane parallel to the support structure overlaps with a projection of at least one of the protrusions of the second corrugated capacitor structure onto the plane.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
Provided is a power estimation tool for estimating power from an RTL simulation waveform. The tool may use an inference engine that uses an ML trained power estimation model. A method comprising: for an integrated circuit partition, dividing one or more RTL simulation waveform files into a plurality of windows; processing the windows to generate activity and power values for each window; and creating an ML generated power estimation model for the partition using the processed windows.
G06F 30/327 - Synthèse logique; Synthèse de comportement, p.ex. logique de correspondance, langage de description de matériel [HDL] à liste d’interconnections [Netlist], langage de haut niveau à langage de transfert entre registres [RTL] ou liste d’interconnections [Netlist]
G06F 30/27 - Optimisation, vérification ou simulation de l’objet conçu utilisant l’apprentissage automatique, p.ex. l’intelligence artificielle, les réseaux neuronaux, les machines à support de vecteur [MSV] ou l’apprentissage d’un modèle
G06F 119/06 - Analyse de puissance ou optimisation de puissance
99.
MITIGATION OF INTERFERENCE FROM SUPPLEMENTAL COVERAGE FROM SPACE (SCS) NETWORKING
Various approaches for detecting and mitigating interference in a supplemental coverage from space (SCS) networking arrangement are disclosed, using an SCS zone for a geographic area in connection with exclusion, coordination, or inclusion of SCS communications in the geographic area. In an example, an approach for dynamically mitigating interference includes: obtaining orbital position data for at least one satellite vehicle (e.g., low-earth orbit (LEO) SV), which can perform SCS network communications to a geographic area that includes a terrestrial network (e.g., 5G network); determining operational parameters to mitigate terrestrial interference of the SCS network communications in the geographic area, with the geographic area identified based on the orbital position data; and modifying operation of the SCS network communications in the geographic area, based on the determined operational parameters.
G01S 19/39 - Détermination d'une solution de navigation au moyen des signaux émis par un système de positionnement satellitaire à radiophares le système de positionnement satellitaire à radiophares transmettant des messages horodatés, p.ex. GPS [Système de positionnement global], GLONASS [Système mondial de satellites de navigation] ou GALILEO
The application relates to an Access Point (AP) and an apparatus used therein, wherein the apparatus includes processor circuitry configured to cause the AP to: receive, from a sharing AP, a Single User Trigger Frame (SU-TF), wherein the SU-TF is used to allocate time within a Transmission Opportunity (TXOP) of the sharing AP to multiple communication stations including the AP and includes a Duration field indicating a competition allowed duration in which only the multiple communication stations are allowed to contend for a communication channel; and send, to the sharing AP, a Clear To Send (CTS) frame upon receiving the SU-TF and before contending for a communication channel, wherein the CTS frame comprises a Receiver Address (RA) field set to a Media Access Control (MAC) address of the sharing AP.
