Self-aligned gate endcap (SAGE) architectures with improved caps, and methods of fabricating self-aligned gate endcap (SAGE) architectures with improved caps, are described. In an example, an integrated circuit structure includes a first gate structure over a first semiconductor fin. A second gate structure is over a second semiconductor fin. A gate endcap isolation structure is between the first gate structure and the second gate structure. The gate endcap isolation structure has a higher-k dielectric cap layer on a lower-k dielectric wall. The higher-k dielectric cap layer includes hafnium and oxygen and has 70% or greater monoclinic crystallinity.
H10D 64/68 - Électrodes ayant un conducteur couplé capacitivement à un semi-conducteur par un isolant, p. ex. électrodes du type métal-isolant-semi-conducteur [MIS] caractérisées par l’isolant, p. ex. par l’isolant de grille
H10D 64/27 - Électrodes ne transportant pas le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. grilles
H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
2.
INTEGRATED CIRCUIT STRUCTURES HAVING CUT METAL GATES
Integrated circuit structures having cut metal gates, and methods of fabricating integrated circuit structures having cut metal gates, are described. For example, an integrated circuit structure includes a fin having a portion protruding above a shallow trench isolation (STI) structure. A gate dielectric material layer is over the protruding portion of the fin and over the STI structure. A conductive gate layer is over the gate dielectric material layer. A conductive gate fill material is over the conductive gate layer. A dielectric gate plug is laterally spaced apart from the fin, the dielectric gate plug on but not through the STI structure. The gate dielectric material layer and the conductive gate layer are not along sides of the dielectric gate plug, and the conductive gate fill material is in contact with the sides of the dielectric gate plug.
A cross-domain device includes a memory with a shared memory region. The device further includes a first interface to couple to a first device over a first interconnect, where the first device implements a first domain, and includes a second interface to couple to a second device over a second interconnect, where the second device implements a second domain, and the first domain is independent of the second domain. The cross-domain device is to create a buffer in the shared memory region to allow writes by a first software module in the first domain and reads by a second software module in the second domain, and use the buffer to implement a memory-based communication link between the first software module and the second software module.
Glass cores with embedded power delivery components are disclosed. An example apparatus includes a glass layer including an opening, a dielectric material within the opening, a first cluster of inductors extending through the dielectric material, and a second cluster of inductors extending through the dielectric material, the second cluster spaced apart from the first cluster, the dielectric material extending continuously from around the first cluster to around the second cluster.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate, having a surface, including a first conductive pathway electrically coupled to a power source; a first microelectronic component, having an active side electrically coupled to the surface of the package substrate and an opposing back side, surrounded by an insulating material; a second microelectronic component, having an active side electrically coupled to the surface of the package substrate and an opposing back side, surrounded by the insulating material and including a through-substrate via (TSV) electrically coupled to the first conductive pathway; and a redistribution layer (RDL), on the insulating material, including a second conductive pathway electrically coupling the TSV, the second surface of the second microelectronic component, and the second surface of the first microelectronic component.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 23/50 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes pour des dispositifs à circuit intégré
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
6.
PERSONALIZED SKIN TONE ADAPTATION FOR IMAGES AND VIDEO
Systems, apparatus, articles of manufacture, and methods are disclosed to implement personalized skin tone adaptation for images and video. An example apparatus disclosed herein obtains an initial skin tone group distribution for an identified user depicted in an input image. The example apparatus also determines, based on the input image, a plurality of skin tone measurements associated respectfully with a plurality of skin tone groups corresponding to the initial skin tone group distribution. The example apparatus further outputs a revised skin tone group distribution based on the skin tone measurements, the initial skin tone group distribution, and a transition model.
G06V 10/84 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant les modèles graphiques de probabilités à partir de caractéristiques d’images ou de vidéos, p. ex. les modèles de Markov ou les réseaux bayésiens
G06T 7/90 - Détermination de caractéristiques de couleur
G06T 11/60 - Édition de figures et de texteCombinaison de figures ou de texte
G06V 10/56 - Extraction de caractéristiques d’images ou de vidéos relative à la couleur
An electronic device is provided that implements thermally conductive plastic supports that may replace the typical use of “feet” used in conventional electronic devices. The thermally conductive supports may extend through the bottom chassis cover (e.g. the “D cover”) of the electronic device, and be mechanically and thermally coupled to a heat pipe that is in turn coupled to a heat source for which thermal regulation is utilized. The thermally conductive plastic supports may provide a heat path from the heat source to the bottom chassis cover and, when the electronic device is disposed on a surface, an additional heat path may be provided from the heat source to this surface.
The present disclosure is related to framework for automatically and efficiently finding machine learning (ML) architectures that are optimized to one or more specified performance metrics and/or hardware platforms. This framework provides ML architectures that are applicable to specified ML domains and are optimized for specified hardware platforms in significantly less time than could be done manually and in less time than existing ML model searching techniques. Furthermore, a user interface is provided that allows a user to search for different ML architectures based on modified search parameters, such as different hardware platform aspects and/or performance metrics. Other embodiments may be described and/or claimed.
Integrated circuitry comprising a ribbon or wire (RoW) transistor stack within which the transistors have different threshold voltages (Vt). In some examples, a gate electrode of the transistor stack may include only one workfunction metal. A metal oxide may be deposited around one or more channels of the transistor stack as a solid-state source of a metal oxide species that will diffuse toward the channel region(s). As diffused, the metal oxide may remain (e.g., as a silicate, or hafnate) in close proximity to the channel region, thereby altering the dipole properties of the gate insulator material. Different channels of a transistor stack may be exposed to differing amounts or types of the metal oxide species to provide a range of Vt within the stack. After diffusion, the metal oxide may be stripped as sacrificial, or retained.
H10D 84/03 - Fabrication ou traitement caractérisés par l'utilisation de technologies basées sur les matériaux utilisant une technologie du groupe IV, p. ex. technologie au silicium ou au carbure de silicium [SiC]
10.
MICROMETER METAL PARTICLE REINFORCED TIN-BISMUTH LOW TEMPERATURE SOLDER MATERIALS
Solder materials and microelectronic devices and systems deploying the solder materials are discussed. The solder material includes a bulk material of tin and bismuth and particles interspersed in the tin and bismuth bulk material. The particles are a metal other than tin and bismuth, and an intermetallic compound is formed around the particles. The intermetallic compound includes the metal of the particles and tin or bismuth. The solder materials are deployed as interconnect structures to interconnect components, such as electrically coupling an integrated circuit package to a motherboard.
B23K 35/26 - Emploi de matériaux spécifiés pour le soudage ou le brasage dont le principal constituant fond à moins de 400°C
B23K 35/02 - Baguettes, électrodes, matériaux ou environnements utilisés pour le brasage, le soudage ou le découpage caractérisés par des propriétés mécaniques, p. ex. par la forme
An apparatus to facilitate barrier state save and restore for preemption in a graphics environment is disclosed. The apparatus includes processing resources to execute a plurality of execution threads that are comprised in a thread group (TG) and mid-thread preemption barrier save and restore hardware circuitry to: initiate an exception handling routine in response to a mid-thread preemption event, the exception handling routine to cause a barrier signaling event to be issued; receive indication of a valid designated thread status for a thread of a thread group (TG) in response to the barrier signaling event; and in response to receiving the indication of the valid designated thread status for the thread of the TG, cause, by the thread of the TG having the valid designated thread status, a barrier save routine and a barrier restore routine to be initiated for named barriers of the TG.
Porous liners for through-glass vias and associated methods are disclosed. An example apparatus includes a glass layer having a through-hole. The example apparatus further includes a conductive material within the through-hole. The example apparatus also includes a porous material between at least a portion of the conductive material and at least a portion of a sidewall of the through-hole.
A transport system, including: a plurality of self-lifting wheel units individually controllable and mounted to a transport platform; one or more sensors mounted to the transport platform and configured to detect a floor obstacle, floor elevation change, or floor surface irregularity; a control system operatively connected to the plurality of self-lifting wheel units and the one or more sensors, wherein the control system is configured to: receive floor obstacle, elevation change, or surface irregularity detection data from the one or more sensors; plan and control the plurality of self-lifting wheel units to selectively lift or lower to maintain stability of the transport platform when traversing the floor obstacle, the floor elevation change, or the floor surface irregularity; and regulate movement of the transport platform to traverse the floor obstacle, the floor elevation change, or the floor surface irregularity based the plan and control.
B60G 17/0165 - Suspensions élastiques permettant d'ajuster les caractéristiques des ressorts ou des amortisseurs de vibrations, de réguler la distance entre la surface porteuse et la partie suspendue du véhicule ou de bloquer la suspension pendant l'utilisation pour s'adapter aux conditions variables du véhicule ou du terrain, p. ex. en fonction de la vitesse ou de la charge les moyens de régulation comportant des éléments électriques ou électroniques caractérisés par leur réponse à un mouvement ou une condition donnés ou à l'action du conducteur, lors du déplacement du véhicule à une condition externe, p. ex. un mauvais état de la route, un vent latéral
G01S 17/08 - Systèmes déterminant les données relatives à la position d'une cible pour mesurer la distance uniquement
G01S 17/931 - Systèmes lidar, spécialement adaptés pour des applications spécifiques pour prévenir les collisions de véhicules terrestres
Systems, apparatus, articles of manufacture, and methods are disclosed to partition a boot drive for two or more processor circuits. An example apparatus includes at least one first processor circuit to determine at least one first parameter for a first namespace and at least one second parameter for a second namespace to be configured for a non-volatile memory (NVM) boot drive, cause a first controller of the NVM boot drive to create the first namespace based on the at least one first parameter, and cause the first controller to create the second namespace based on the at least one second parameter. Also, the example at least one first processor circuit is to attach the first namespace to the first controller of the NVM boot drive, attach the second namespace to a second controller of the NVM boot drive, and attach the second controller to a bootloader of a second processor circuit.
A cold plate comprises a plurality of fins. The individual fins have an opening, and the openings collectively define a first channel through the plurality of fins. During operation of an integrated circuit component attached to the cold plate, coolant is pumped through the cold plate. The coolant flows in a first direction through the first channel and then in a second through second channels located between the fins. The first direction is substantially orthogonal to the second direction. The first channel can comprise a tube that has openings that direct coolant to flow into the second channels. The first channel is located close to the base plate of the cold plate so that there is a high degree of heat transfer between an integrated circuit component attached to the cold plate and coolant flowing through the cold plate.
An apparatus for a user equipment (UE) is configured for operation in a Next Generation Radio Access Network (RAN). The apparatus includes processing circuitry to encode a radio resource control (RRC) setup request message for transmission to a distributed unit (DU) function of a base station. The processing circuitry is to decode an RRC setup message received from the DU function. The RRC setup message is responsive to the RRC setup request message. The processing circuitry is to perform a selection of a public land mobile network (PLMN) based on the RRC setup message. The processing circuitry is to encode an RRC setup complete message for transmission to the DU function. The RRC setup complete message includes a global unique temporary identifier (GUTI) of the UE, an access and mobility management function (AMF) identification (ID) of a previously contacted AMF, and an ID of the PLMN.
H04W 76/12 - Établissement de tunnels de transport
H04W 76/11 - Attribution ou utilisation d'identifiants de connexion
H04W 48/10 - Distribution d'informations relatives aux restrictions d'accès ou aux accès, p. ex. distribution de données d'exploration utilisant des informations radiodiffusées
Examples to determine a dynamic batch size of a layer are disclosed herein. An example apparatus to determine a dynamic batch size of a layer includes a layer operations controller to determine a layer ratio between a number of operations of a layer and weights of the layer, a comparator to compare the layer ratio to a number of operations per unit of memory size performed by a computation engine, and a batch size determination controller to, when the layer ratio is less than the number of operations per unit of memory size, determine the dynamic batch size of the layer.
G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
G06N 3/04 - Architecture, p. ex. topologie d'interconnexion
This disclosure describes systems, methods, and devices related to enhanced service period updates. A device may receive, from a station (STA), a negotiation request that identifies a service period and one or more transmission and reception (Tx/Rx) parameters to be updated during the service period. The device may define the service period based on the received negotiation request, wherein the service period is determined using a target wake time (TWT) element. The device may adjust, based on the negotiation request, the one or more Tx/Rx parameters for operation during the service period, wherein the one or more Tx/Rx parameters include at least a maximum modulation and coding scheme (Max MCS). The device may transmit a confirmation to the STA after updating the one or more Tx/Rx parameters. The device may revert the one or more Tx/Rx parameters to default values outside the service period.
A fabrication method and associated integrated circuit (IC) structures and devices that include one or more self-insulated vias is described herein. In one example, an IC structure includes a via surrounded by an insulator material and a layer of insulator material between a conductive material of the via and the surrounding insulator material. In one example, the layer of insulator material has one or more material properties that are different than the surrounding insulator material, including one or more of a different density, a different dielectric constant, and a different material composition.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
20.
INFRASTRUCTURE-BASED COLLABORATIVE AUTOMATED PARKING AND LOCATION MANAGEMENT
Systems and techniques for location management are described herein. In an example, a system may include at least one processor and at least one memory with instructions stored thereon that when executed by the processor, cause the processor to obtain data originating from one or more sensors proximate to the location. A trained activity-based detection model may identify an activity at the location and perform a determination of a service to be offered at the location based on the detected activity. The system may then send a message to a user offering the service to the user, and in response to receiving an authorization accepting the service from the user, cause the service to be implemented at the location, which may include classifying the service as a service type, matching the service type to a service provider, and sending a notification to the service provider.
B60W 30/06 - Manœuvre automatique de stationnement
B60L 53/36 - Moyens pour l’ajustement automatique ou assisté de la position relative des dispositifs de charge et des véhicules par le positionnement du véhicule
B60L 53/63 - Surveillance et commande des stations de charge en réponse à la capacité du réseau
B60L 55/00 - Dispositions relatives à la fourniture d'énergie emmagasinée dans un véhicule à un réseau électrique, c.-à-d. du véhicule au réseau [V2G]
G06Q 20/40 - Autorisation, p. ex. identification du payeur ou du bénéficiaire, vérification des références du client ou du magasinExamen et approbation des payeurs, p. ex. contrôle des lignes de crédit ou des listes négatives
G06Q 30/0283 - Estimation ou détermination de prix
G08G 1/0967 - Systèmes impliquant la transmission d'informations pour les grands axes de circulation, p. ex. conditions météorologiques, limites de vitesse
G08G 1/14 - Systèmes de commande du trafic pour véhicules routiers indiquant des places libres individuelles dans des parcs de stationnement
21.
APPARATUS INCLUDING SPEAKERS PORTED THROUGH KEYS OF A KEYBOARD
Apparatus including speakers ported through keys of a keyboard are disclosed. An example electronic device includes a housing, and a keyboard carried by the housing. The keyboard includes a key having a keycap that covers an associated switch. The example electronic device further includes a speaker within the housing underneath the keyboard. The keycap includes an opening to define a port through which sound from the speaker is able to pass.
H01H 13/7065 - Interrupteurs ayant un organe moteur à mouvement rectiligne ou des organes adaptés pour pousser ou tirer dans une seule direction, p. ex. interrupteur à bouton-poussoir ayant une pluralité d'éléments moteurs associés à différents jeux de contacts, p. ex. claviers avec des contacts portés par ou formés à partir de couches dans une structure multicouche, p. ex. interrupteurs à membrane caractérisés par la structure, le montage ou l'agencement des organes d'actionnement, p. ex. des boutons-poussoirs ou des touches caractérisés par le mécanisme entre les touches et les claviers multicouches
H04R 1/02 - BoîtiersMeublesMontages à l'intérieur de ceux-ci
A cross-domain device includes a first interface to couple to a first device and a second interface to couple to a second device, where the first device is to implement a first component in a radio access network (RAN) system in a first computing domain, and the second device is to implement a second component in the RAN system in a second computing domain. The first component is to interface within the second component in a RAN processing pipeline. The cross-domain device further comprises hardware to implement a communication channel between the first device and the second device to pass data from the first component to the second component, where the communication channel enforces isolation of the first computing domain from the second computing domain.
Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.
Examples described herein relate to performing source routing of a packet to route the packet from a source to a destination through multiple routers by specification of a path of logical port identifiers through the multiple routers. In some examples, multiple routers are to translate the logical port identifiers into physical ports based on configurations. In some examples, the path of the packet through the multiple routers is based on a topology of the routers.
Methods and apparatus for DDR5 DIMM power fail monitor to prevent I/O reverse-bias current. An apparatus is configured to be implemented in a host system including a processor having an integrated memory controller (iMC) coupled to one or more DIMMs having an onboard Power Management Integrated Circuit (PMIC). The apparatus includes circuitry to monitor an operating state for a host voltage regulator (VR) providing input power to the processor and monitor an operating state of the PMIC for each of the one or more DIMMs. In response to detecting a fault condition of the host VR or a PMIC for a DIMM, the apparatus prevents reverse bias voltage in circuitry in at least one of the iMC and the one or more DIMMs. The apparatus may implement a finite state machine (FSN) having a plurality of defined states including a fault state used to indicate detection of the fault condition.
Examples described herein relate to processing packets. In some examples, based on receipt of a Hypertext Transfer Protocol (HTTP) packet at a network interface device, the HTTP packet comprising an HTTP body and HTTP header: provide the HTTP header, but not the HTTP body, for processing in user space; modify solely the HTTP header in user space; and in kernel space, combine the modified HTTP header and the HTTP body prior to transmission of the HTTP packet with modified HTTP header to a client.
In one embodiment, an apparatus comprises a log circuit to: identify an input associated with a logarithm operation, wherein the logarithm operation is to be performed by the log circuit using piecewise linear approximation; identify a first range that the input falls within, wherein the first range is identified from a plurality of ranges associated with a plurality of piecewise linear approximation (PLA) equations for the logarithm operation, and wherein the first range corresponds to a first equation of the plurality of PLA equations; compute a result of the first equation based on a plurality of operands associated with the first equation; and return an output associated with the logarithm operation, wherein the output is generated based at least in part on the result of the first equation.
G06F 7/499 - Maniement de valeur ou d'exception, p. ex. arrondi ou dépassement
G06F 7/556 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs n'établissant pas de contact, p. ex. tube, dispositif à l'état solideMéthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul de fonctions logarithmiques ou exponentielles
G06F 17/11 - Opérations mathématiques complexes pour la résolution d'équations
G06F 17/17 - Évaluation de fonctions par des procédés d'approximation, p. ex. par interpolation ou extrapolation, par lissage ou par le procédé des moindres carrés
G06N 3/044 - Réseaux récurrents, p. ex. réseaux de Hopfield
G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
G06N 3/084 - Rétropropagation, p. ex. suivant l’algorithme du gradient
28.
MULTI-VARIATE STRIDED READ OPERATIONS FOR ACCESSING MATRIX OPERANDS
In one embodiment, a matrix processor comprises a memory to store a matrix operand and a strided read sequence, wherein: the matrix operand is stored out of order in the memory; and the strided read sequence comprises a sequence of read operations to read the matrix operand in a correct order from the memory. The matrix processor further comprises circuitry to: receive a first instruction to be executed by the matrix processor, wherein the first instruction is to instruct the matrix processor to perform a first operation on the matrix operand; read the matrix operand from the memory based on the strided read sequence; and execute the first instruction by performing the first operation on the matrix operand.
G06F 9/345 - Adressage de l'opérande d'instruction ou du résultat ou accès à l'opérande d'instruction ou au résultat d'opérandes ou de résultats multiples
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
Embodiments are directed to providing integrity-protected command buffer execution. An embodiment of an apparatus includes a computer-readable memory comprising one or more command buffers and a processing device communicatively coupled to the computer-readable memory to read, from a command buffer of the computer-readable memory, a first command received from a host device, the first command executable by one or more processing elements on the processing device, the first command comprising an instruction and associated parameter data, compute a first authentication tag using a cryptographic key associated with the host device, the instruction and at least a portion of the parameter data, and authenticate the first command by comparing the first authentication tag with a second authentication tag computed by the host device and associated with the command.
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
A component of a computing system, including: processor circuitry; and a non-transitory computer-readable storage medium including instructions that, when executed by the processor circuitry, cause the processor circuitry to: dynamically monitor runtime metrics across processor cores of the computing system, wherein the runtime metrics comprise a measure of system-critical task residency and a measure of user-critical foreground application utilization; and initiate a power optimization action configured to transition the computing system into a power efficiency mode when the system-critical task residency is below a system-critical task residency threshold and the user-critical foreground application utilization is below a user-critical foreground application utilization threshold.
Systems, apparatus, articles of manufacture, and methods are disclosed to dynamically manage input/output (I/O) transactions. An example apparatus includes circuitry to determine at least one of a first parameter assigned to an VO transaction by a user, a second parameter for the I/O transaction based on at least a class of an I/O device, or a third parameter for the I/O transaction based on a usage pattern for a compute device coupled to the I/O device. Additionally, the example apparatus includes parameter management circuitry to determine a dynamic parameter to assign to the I/O transaction based on at least one of the first parameter, the second parameter, or the third parameter and cause scheduler circuitry to at least one of adjust a default bandwidth to be allocated to the I/O transaction based on the dynamic parameter or adjust a latency associated with the I/O transaction based on the dynamic parameter.
Systems, apparatus, articles of manufacture, and methods to save power during conference calls are disclosed. An example first client device includes interface circuitry; machine readable instructions; and at least one processor circuit to at least one of instantiate or execute the machine readable instructions to: determine whether a first attendee of a conference call is absent from the first client device; and cause transmission of a notification to at least one of a server for the conference call or a second client device associated with the conference call and different from the first client device, the notification to cause the second client device to change an operating state associates with the conference call.
A method and system of neural network dynamic noise suppression (DNS) is provided for audio processing. The system is a down-scaled DNS model that uses grouping techniques at pointwise convolutional layers to reduce the number of network parameters. According to one technique, audio signal data can be coded into an input vector that that is split into multiple groups, each groups having multiple channels. At a pointwise convolution layer, an output is generated for each group. The outputs can be concatenated to form a single input vector for a next layer of the model. Each group is treated as a channel, such that the reduction in the number of channels reduces the number of parameters used by the neural network. In some examples, the groups are weight sharing groups.
G10L 21/0232 - Traitement dans le domaine fréquentiel
G10L 25/30 - Techniques d'analyse de la parole ou de la voix qui ne se limitent pas à un seul des groupes caractérisées par la technique d’analyse utilisant des réseaux neuronaux
G10L 25/78 - Détection de la présence ou de l’absence de signaux de voix
H04R 3/04 - Circuits pour transducteurs pour corriger la fréquence de réponse
34.
SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH GATE-ALL-AROUND DEVICES
Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.
H10D 30/62 - Transistors à effet de champ à ailettes [FinFET]
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 62/13 - Régions semi-conductrices connectées à des électrodes transportant le courant à redresser, amplifier ou commuter, p. ex. régions de source ou de drain
H10D 84/03 - Fabrication ou traitement caractérisés par l'utilisation de technologies basées sur les matériaux utilisant une technologie du groupe IV, p. ex. technologie au silicium ou au carbure de silicium [SiC]
35.
EPITAXIAL SOURCE OR DRAIN STRUCTURES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION
Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon, the fin having a lower fin portion and an upper fin portion. A gate electrode is over the upper fin portion of the fin, the gate electrode having a first side opposite a second side. A first epitaxial source or drain structure is embedded in the fin at the first side of the gate electrode. A second epitaxial source or drain structure is embedded in the fin at the second side of the gate electrode, the first and second epitaxial source or drain structures comprising silicon and germanium and having a match-stick profile.
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
H01L 21/033 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou comportant des couches inorganiques
H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
H01L 21/285 - Dépôt de matériaux conducteurs ou isolants pour les électrodes à partir d'un gaz ou d'une vapeur, p. ex. condensation
H01L 21/308 - Traitement chimique ou électrique, p. ex. gravure électrolytique en utilisant des masques
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
H10B 10/00 - Mémoires statiques à accès aléatoire [SRAM]
H10D 1/47 - Résistances n’ayant pas de barrières de potentiel
H10D 30/62 - Transistors à effet de champ à ailettes [FinFET]
H10D 30/69 - Transistors IGFET ayant des isolateurs de grille à piégeage de charges, p. ex. transistors MNOS
H10D 62/00 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 62/13 - Régions semi-conductrices connectées à des électrodes transportant le courant à redresser, amplifier ou commuter, p. ex. régions de source ou de drain
H10D 62/822 - Hétérojonctions comprenant uniquement des hétérojonctions de matériaux du groupe IV, p. ex. des hétérojonctions Si/Ge
H10D 62/834 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe IV, p. ex. Si dopé B ou Ge non dopé caractérisés en outre par les dopants
H10D 64/23 - Électrodes transportant le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. sources, drains, anodes ou cathodes
H10D 64/68 - Électrodes ayant un conducteur couplé capacitivement à un semi-conducteur par un isolant, p. ex. électrodes du type métal-isolant-semi-conducteur [MIS] caractérisées par l’isolant, p. ex. par l’isolant de grille
H10D 84/03 - Fabrication ou traitement caractérisés par l'utilisation de technologies basées sur les matériaux utilisant une technologie du groupe IV, p. ex. technologie au silicium ou au carbure de silicium [SiC]
H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
H10D 84/85 - Transistors IGFET complémentaires, p. ex. CMOS
Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
H10D 30/69 - Transistors IGFET ayant des isolateurs de grille à piégeage de charges, p. ex. transistors MNOS
H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
37.
MULTI-CHIP PACKAGE WITH HIGH DENSITY INTERCONNECTS
An apparatus is provided which comprises: a plurality of first conductive contacts having a first pitch spacing on a substrate surface, a plurality of second conductive contacts having a second pitch spacing on the substrate surface, and a plurality of conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first groupings are present in a layer of the substrate above the conductive interconnects to couple the second groupings. Other embodiments are also disclosed and claimed.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
38.
EMIB ARCHITECTURE WITH DEDICATED METAL LAYERS FOR IMPROVING POWER DELIVERY
Embodiments disclosed herein include electronic packages with a bridge that comprise improved power delivery architectures. In an embodiment, a bridge comprises a substrate and a routing stack over the substrate. In an embodiment, the routing stack comprises first routing layers, where individual ones of the first routing layers have a first thickness, and a second routing layer, where the second routing layer has a second thickness that is greater than the first thickness.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
Examples described herein relate to a network interface device. The network interface device includes a host interface; a network interface; and a direct memory access (DMA) circuitry. In some examples, the host interface includes circuitry to: apply a first configuration of Peripheral Component Interconnect Express (PCIe) upstream ports and downstream ports and without reboot of the network interface device, apply a second configuration to adjust routing of communication among devices coupled to the PCIe upstream ports and downstream ports.
Systems and methods include establishing a cryptographically secure communication between an application module and an audio module. The application module is configured to execute on an information-handling machine, and the audio module is coupled to the information-handling machine. The establishment of the cryptographically secure communication may be at least partially facilitated by a mutually trusted module.
G06F 21/44 - Authentification de programme ou de dispositif
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p. ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
G06F 21/83 - Protection des dispositifs de saisie, d’affichage de données ou d’interconnexion dispositifs de saisie de données, p. ex. claviers, souris ou commandes desdits claviers ou souris
G06F 21/84 - Protection des dispositifs de saisie, d’affichage de données ou d’interconnexion dispositifs d’affichage, p. ex. écrans ou moniteurs
This disclosure describes systems, methods, and devices related to NAV timeout. A device may transmit, during a transmission opportunity (TxOP), an initial control frame (ICF) trigger frame including user information fields identifying one or more target stations (STAs). The device may receive from the one or more target STAs, an initial control response (ICR) frame, wherein the ICR frame includes feedback information and padding. The device may calculate a network allocation vector (NAV) timeout period based on a transmission time of a maximum-sized ICR frame at a lowest transmission rate. The device may adjust NAV settings based on the NAV timeout period.
H04W 24/02 - Dispositions pour optimiser l'état de fonctionnement
H04W 74/0816 - Accès non planifié, p. ex. ALOHA utilisant une détection de porteuse, p. ex. accès multiple par détection de porteuse [CSMA] avec évitement de collision
Write filter hardware is provided with circuitry to receive a signal to switch the write filter from a disabled state to an enabled state for a given range of addresses in a shared memory. A write attempt by a host processor to the range of addresses is identified, where access to the shared memory is shared with an accelerator device. The write filter hardware causes the write attempt to be dropped when the hardware write filter is in the enabled state for the given range of addresses.
Techniques are disclosed to implement a mathematical framework to model a mechanical actuator such as robotic arm and compute the differential kinematics of an end effector represented by a circle in a three-dimensional space, described as a bi-vector of conformal geometric algebra. Additionally, by using a circle to describe the grasping pose on the object, a differential kinematics-based control scheme is implemented to guide the actuator and minimize the error between the end effector circle and the target circle. The circle has 3 degrees of freedom for the center, two degrees for the orientation, and one more for the radius, which may be used to describe the end effector pose, with the differential kinematics-based control scheme law adjusting the position and the orientations simultaneously.
Key-value (KV) caching accelerates inference in large language models (LLMs) by allowing the attention operation to scale linearly rather than quadratically with the total sequence length. Due to large context lengths in modern LLMs, KV cache size can exceed the model size, which can negatively impact throughput. To address this issue, KVCrush, which stands for KEY-VALUE CACHE SIZE REDUCTION USING SIMILARITY IN HEAD-BEHAVIOR, is implemented. KVCrush involves using binary vectors to represent tokens, where the vector indicates which attention heads attend to the token and which attention heads disregard the token. The binary vectors are used in a hardware-efficient, low-overhead process to produce representatives for unimportant tokens to be pruned, without having to implement k-means clustering techniques.
Systems, apparatus, articles of manufacture, and methods are disclosed to utilize large language artificial intelligence models to convert computer code. An example apparatus includes instructions and processor circuitry to execute the instructions to at least: train a large language model based on a computer instructions repository that includes code of a first type; utilize the large language model to convert an input set of instructions of the first type into output code of a second type; cause execution of the output code; determine if the execution is successful; and when the execution is not successful, utilize the output code for fine-tuning training of the large language model with incorrect data.
A legacy virtual machine (a virtual machine not operating in a secure environment) can be converted to a confidential virtual machine (a virtual that operates in a secure environment) on the fly, with little downtime experienced by the legacy virtual machine (VM) owner. A legacy VM operating either on a legacy platform (a platform not having confidential computing capabilities) or a confidential computing-capable platform can be converted to a confidential VM (CVM). The legacy VM can be migrated to another computing device as part of the conversion or be converted into a CVM that executes on the same computing device on which the legacy VM was running. A trusted security module can be responsible for starting a VM-to-CVM conversion session, validating the state of legacy virtual machine to be converted, provision a CVM with the state of the legacy virtual machine, and end a VM-to-CVM conversion session.
G06F 9/455 - ÉmulationInterprétationSimulation de logiciel, p. ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
47.
EAPOL-KEY ENCRYPTION KEY DERIVATION AND ENCRYPTION IN AUTHENTICATION FRAME
This disclosure describes systems, methods, and devices related to KEK frame encryption. A device may identify, within a received authentication frame, a capability bit in a Robust Security Network Extension Element (RSNXE) indicating peer device support for Key Encryption Key (KEK) derivation during an authentication frame exchange. The device may derive the KEK during the authentication frame exchange based on mutual support for KEK derivation and derivation of a Pairwise Transient Key Security Association (PTKSA) during the exchange. The device may use a cryptographic key protection process for deriving the KEK. The device may encrypt a portion of the authentication frame using the derived KEK.
Examples described herein relate to partitioning of processor sockets. A first processor socket includes first communication circuitry associated with a first partition identifier and a second processor socket includes a second communication circuitry associated with a second partition identifier. In some examples, based on a boot operation associated with the first processor socket: the first communication circuitry is to permit communication with the second communication circuitry based on a first partition identifier matching the second partition identifier and the first communication circuitry is to disable communication with the second communication circuitry based on the first partition identifier not matching the second partition identifier.
Particular embodiments described herein provide for an electronic device that can be configured to include a chassis, where the chassis includes a first chassis portion and a second chassis portion, a flexible display supported by the chassis, and a hinge. The hinge includes a first chassis attachment housing coupled to the first chassis portion, a first chassis portion lift arm coupled to the first chassis attachment housing, a first hinge pivot coupled to the first chassis portion lift arm, a second chassis attachment housing coupled to the second chassis portion, a second chassis portion lift arm coupled to the second chassis attachment housing, and a second hinge pivot coupled to the second chassis portion lift arm. The first chassis portion lift arm extends to increase a first distance between the first chassis attachment housing and the first hinge pivot and the second chassis portion lift arm extends to increase a second distance between the second chassis attachment housing and the second hinge pivot as the flexible display is bent.
Disclosed herein are methods for fabricating IC structures that include stacked vias providing electrical connectivity between metal lines of different layers of a metallization stack, as well as resulting IC structures. An example IC structure includes a first and a second metallization layers, including, respectively, a bottom metal line and a top metal line. The IC structure further includes a via that has a bottom via portion and a top via portion, where the top via portion is stacked over the bottom via portion (hence, the via may be referred to as a “stacked via”). The bottom via portion is coupled and self-aligned to the bottom electrically conductive line, while the top via portion is coupled and self-aligned to the top electrically conductive line. The bottom via portion is formed using selective growth, e.g., assisted by a self-assembled monolayer (SAM) material.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/528 - Configuration de la structure d'interconnexion
51.
PACKAGE SUBSTRATES WITH COMPONENTS INCLUDED IN CAVITIES OF GLASS CORES
Package substrates with components included in cavities of glass cores are disclosed. An example apparatus includes: a glass core having a first through-hole and a second through-hole, the first through-hole spaced apart from and smaller than the second through-hole; and a conductive material within the first through-hole, the conductive material to extend a full length of the first through-hole. The example apparatus further includes a dielectric material within the second through-hole, the dielectric material between an electronic component within the second through-hole and a sidewall of the second through-hole.
H01L 23/18 - Matériaux de remplissage caractérisés par le matériau ou par ses propriétes physiques ou chimiques, ou par sa disposition à l'intérieur du dispositif complet
H01L 23/498 - Connexions électriques sur des substrats isolants
Package substrates with components included in cavities of glass cores are disclosed. An example apparatus includes: a glass layer having an opening between opposing first and second surfaces of the glass layer; an electronic component within the opening; a dielectric material within the opening between the electronic component and a sidewall of the opening; and a through-glass via including a conductive material that extends through the glass layer.
H01L 23/18 - Matériaux de remplissage caractérisés par le matériau ou par ses propriétes physiques ou chimiques, ou par sa disposition à l'intérieur du dispositif complet
H01L 23/498 - Connexions électriques sur des substrats isolants
Package substrates with components included in cavities of glass cores are disclosed. An example apparatus includes: a glass layer having a first hole and a second hole, the second hole larger than an electronic component disposed therein, a width of the electronic component larger than a width of the first hole. The example apparatus further includes a conductive material that substantially fills the first hole; and a dielectric material that substantially fills a space within the second hole surrounding the electronic component.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
54.
MICROELECTRONIC ASSEMBLIES INCLUDING INTERCONNECTS WITH DIFFERENT SOLDER MATERIALS
Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface, in a first layer; a redistribution layer (RDL) on the first layer, wherein the RDL includes conductive vias having a greater width towards a first surface of the RDL and a smaller width towards an opposing second surface of the RDL; wherein the first surface of the RDL is electrically coupled to the second surface of the first die by first solder interconnects having a first solder; and a second die in a second layer on the RDL, wherein the second die is electrically coupled to the RDL by second solder interconnects having a second solder, wherein the second solder is different than the first solder.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
Disclosed herein are via plug resistors for incorporation into electronic substrates, and related methods and devices. Exemplary via plug resistor structures include a resistive element within and on a surface of a via extending at least partially through an electronic substrate and first and second electrodes coupled to the resistive element.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H05K 1/11 - Éléments imprimés pour réaliser des connexions électriques avec ou entre des circuits imprimés
H05K 1/16 - Circuits imprimés comprenant des composants électriques imprimés incorporés, p. ex. une résistance, un condensateur, une inductance imprimés
Techniques related to adaptive quantization matrix selection using machine learning for video coding are discussed. Such techniques include applying a machine learning model to generate an estimated quantization parameter for a frame and selecting a set of quantization matrices for encode of the frame from a number of sets of quantization matrices based on the estimated quantization parameter.
H04N 19/149 - Débit ou quantité de données codées à la sortie du codeur par estimation de la quantité de données codées au moyen d’un modèle, p. ex. un modèle mathématique ou un modèle statistique
H04N 19/172 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage adaptatif caractérisés par l’unité de codage, c.-à-d. la partie structurelle ou sémantique du signal vidéo étant l’objet ou le sujet du codage adaptatif l’unité étant une zone de l'image, p. ex. un objet la zone étant une image, une trame ou un champ
Voice anonymization systems and methods are provided. Voice anonymization is done on the speaker's computing device and can prevent voice theft. The voice anonymization systems and methods are lightweight and run efficiently in real time on a computing device, allowing for speaker anonymity without diminishing system performance during a teleconference or VoIP meeting. The anonymization system outputs a transformed speaker voice. The anonymization system can also generate a voice embedding that can be used to reconstruct the original speaker voice. The voice embedding can be encrypted and transmitted to another device. Sometimes, the voice embedding is not transmitted and the listener receives the anonymized voice. Systems and methods are provided for the detection of voice transformations in received audio. Thus, a listener can be informed whether the speaker voice output from the listener's computing device is the original speaker's voice or a transformed version of the original speaker voice.
G06F 21/62 - Protection de l’accès à des données via une plate-forme, p. ex. par clés ou règles de contrôle de l’accès
G10L 15/02 - Extraction de caractéristiques pour la reconnaissance de la paroleSélection d'unités de reconnaissance
G10L 21/007 - Changement de la qualité de la voix, p. ex. de la hauteur tonale ou des formants caractérisé par le procédé utilisé
G10L 25/30 - Techniques d'analyse de la parole ou de la voix qui ne se limitent pas à un seul des groupes caractérisées par la technique d’analyse utilisant des réseaux neuronaux
A memory subsystem performs error correction through erasure decoding instead of ECC (error correction code) polynomial computation. An error correction module of the memory controller receives a data word and calculates a syndrome using the data word. The error correction module generates multiple correctable error pattern candidates for bounded fault regions based on erasure decoding. The error correction module selects one correctable error pattern candidate to apply error correction.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
Systems, apparatus, articles of manufacture, and methods are disclosed to estimate a pose of a head of a user of an electronic device. An example apparatus to estimate a head pose includes at least one processor circuit to be programmed by instructions to: identify a plurality of facial landmarks in a plurality of images; identify initial image data based on the plurality of facial landmarks; augment the initial image data with a transformation operation; and train a neural network based on the initial image data and the augmented image data to: infer three-dimensional model parameters; and infer a confidence metric.
Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/535 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions internes, p. ex. structures d'interconnexions enterrées
H10B 10/00 - Mémoires statiques à accès aléatoire [SRAM]
H10D 84/85 - Transistors IGFET complémentaires, p. ex. CMOS
61.
SYSTEMS, APPARATUS, AND METHODS FOR ENERGY HARVESTING IN DATA CENTERS
Systems, apparatus, and methods for energy harvesting in data centers are disclosed. An example apparatus includes interface circuitry; machine-readable instructions; and at least one processor circuit to at least one of instantiate or execute the machine-readable instructions to estimate first power consumption values for electronic components of a first rack; estimate second power consumption values for electronic components of a second rack; determine a first selection score for the first rack based on the first power consumption values and a second selection score for the second rack based on the second power consumption values; select a first electronic component of the first rack or a second electronic component of the second rack to receive a workload based on the first selection score and the second selection score; and cause the selected one of the first electronic component or the second electronic component to perform the workload.
Methods, apparatus, systems and articles of manufacture are disclosed to map workloads. An example apparatus includes a constraint definer to define performance characteristic targets of the neural network, an action determiner to apply a first resource configuration to candidate resources corresponding to the neural network, a reward determiner to calculate a results metric based on (a) resource performance metrics and (b) the performance characteristic targets, and a layer map generator to generate a resource mapping file, the mapping file including respective resource assignments for respective corresponding layers of the neural network, the resource assignments selected based on the results metric.
G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
G06F 9/50 - Allocation de ressources, p. ex. de l'unité centrale de traitement [UCT]
G06F 18/21 - Conception ou mise en place de systèmes ou de techniquesExtraction de caractéristiques dans l'espace des caractéristiquesSéparation aveugle de sources
A foundation layer and methods of forming a conductive via are described. A die pad is formed over a die. A seed layer is deposited over the die pad and the foundation layer. A first photoresist layer is deposited over the seed layer, and the first layer is patterned to form a conductive line opening over the die pad. A conductive material is deposited into the conductive line opening to form a conductive line. A second photoresist layer is deposited over the first layer, and the second layer is patterned to form a via opening over the conductive line. The conductive material is deposited into the via opening to form the conductive via, where the conductive material only deposits on portions of exposed conductive line. The second and first layers are removed. Portions of exposed seed layer are recessed, and then a top surface of the conductive via is exposed.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
64.
METHODS AND APPARATUS FOR REGION-OF-INTEREST (ROI) CROPPING
Systems, apparatus, articles of manufacture, and methods are disclosed for high quality and low power dynamic region of interest (ROI) cropping. An example apparatus disclosed herein provides a first image to image signal processor (ISP) circuitry, the ISP circuitry to implement an image processing pipeline to process the first image. The example apparatus also downscales the first image to generate a second image having lower resolution than the first image and identifies a region of interest (ROI) in the second image. The example apparatus further provides coordinates of the ROI to the ISP circuitry, the ISP circuitry to crop the first image based on the coordinates and to output a third image based on the cropped first image.
Examples described herein relate to a timing source. In some examples, the timing source generates a clock signal by synchronization with a second clock signal from a crystal source and subsequent synchronization with a third clock signal. In some examples, the third clock signal is synchronized to timing signals received in Ethernet packets. In some examples, the crystal source is to provide the second clock signal to the circuitry via the interface.
Examples described herein relate to hot page detection. Some examples include circuitry to provide a number of pages with access counts within a bucket of a histogram, wherein the bucket of the histogram is associated with a configured access count range; based on a distribution of access counts in the histogram being a first level, reduce the configured access count ranges of the different buckets of the histogram; determine a second level indicative of page access counts; and migrate data of pages from a far memory to a near memory based on the second level.
Systems, apparatus, articles of manufacture, and methods are disclosed to manage network notifications. An example apparatus includes interface circuitry, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to cause transmission of a first signal based on a packet, the first signal including characteristics of the packet, and cause transmission of a second signal after the first signal, the second signal including a payload of the packet.
This disclosure describes systems, methods, and devices related to extended enhanced multi-link single-radio (EMLSR) with more than two links. A multi-link device may send, to a second multi-link device, an indication that the multi-link device supports an extended enhanced multi-link single-radio (EMLSR) mode using a first enhanced EMLSR link, a second EMLSR link, and an auxiliary EMLSR link; identify a time when at least one of the first EMLSR link or the second EMLSR link are busy due to overlapping basic service set (OBSS) traffic; initiate, during the time, a transmit opportunity on the auxiliary EMLSR link; and cause to send one or more frames to the second multi-link device using the auxiliary EMLSR link during the time.
H04W 74/0816 - Accès non planifié, p. ex. ALOHA utilisant une détection de porteuse, p. ex. accès multiple par détection de porteuse [CSMA] avec évitement de collision
69.
ON-PACKAGE MEMORY WITH UNIVERSAL CHIPLET INTERCONNECT EXPRESS
This disclosure describes systems, methods, and devices related to enhanced memory integration. The device may include a compute chiplet configured as a System-on-a-Chip (SoC). The device may include a logic die circuitry coupled to the compute chiplet through a high-speed link. The device may include a memory interface that connects the logic die circuitry to on-package memory. The device may include control circuitry within the logic die circuitry configured to treat the on-package memory as a memory-side cache for an off-package memory. The device may dynamically migrate memory pages between the on-package memory and the off-package memory based on memory access patterns. The device may facilitate efficient data management, optimize memory utilization, and support scalable memory architectures for improved performance.
For example, a non Access Point (AP) (non-AP) Multi-Link Device (MLD) may process a multi-link processing delay value in a first frame from an AP MLD to identify a multi-link processing delay time for the AP MLD; transmit a second frame from a first non-AP station (STA) affiliated with the non-AP MLD to the AP MLD over a first link, the second frame including a multi-link power management field to change a power management mode for at least one second non-AP STA from a first power management mode to a second power management mode, wherein the at least one second non-AP STA is affiliated with the non-AP MLD and is operative over at least one second link with the AP MLD; and change the power management mode for the at least one second non-AP STA based on the multi-link processing delay time for the AP MLD.
A method and system for implementing a virtual trusted platform module (vTPM). Software components are sequentially loaded and measured from a core root of trust for measurement (CRTM) in a user confidential virtual machine (CVM). The measurements of the software components are recorded in a runtime measurement register (RTMR) log and a digest of each entry of the RTMR log is extended into an RTMR configured for the user CVM. A signed quote and corresponding measurement entries of the RTMR log are provided to a verifier. The signed quote includes a value of the RTMR. A state of the user CVM may be verified based on the RTMR value and the RTMR log entries. The measurement entries of the RTMR log may be replayed to calculate platform configuration register (PCR) values and the TCG event log may be verified using the PCR values.
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p. ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
72.
MECHANISM TO SIGNAL ACCESS POINT SCHEDULING UPFRONT RESOURCE ALLOCATION INFORMATION TO ANOTHER AP IN C-TDMA
This disclosure describes systems, methods, and devices related to enhanced AP scheduling. A device may transmit a schedule allocation frame during a transmission opportunity (TXOP), wherein the schedule allocation frame includes time allocation information for a plurality of shared access points (APs) or stations (STAs). The device may determine a time allocation for each shared AP or STA based on the information included in the schedule allocation frame. The device may adjust the transmission schedule of the TXOP to align with the determined time allocation for each shared AP or STA, wherein the AP does not set a network allocation vector (NAV) for its own BSS upon transmitting the schedule allocation frame. The device may initiate a transmission from shared APs or STAs during respective time allocations within the TXOP.
H04W 74/0816 - Accès non planifié, p. ex. ALOHA utilisant une détection de porteuse, p. ex. accès multiple par détection de porteuse [CSMA] avec évitement de collision
The application relates to an Access Point (AP) and an apparatus used therein, wherein the apparatus includes processor circuitry configured to cause the AP to send a management frame, wherein: the management frame includes a Ultra High Reliability (UHR) max operation information field and a UHR dynamic operation information field, the UHR max operation information field containing information about a maximum UHR Basic Service Set (BSS) bandwidth applicable by the AP, the UHR dynamic operation information field containing information about a dynamic UHR BSS bandwidth that is used right now by the AP.
Embodiments herein describe techniques for a semiconductor device including a three dimensional capacitor. The three dimensional capacitor includes a pole, and one or more capacitor units stacked around the pole. A capacitor unit of the one or more capacitor units includes a first electrode surrounding and coupled to the pole, a dielectric layer surrounding the first electrode, and a second electrode surrounding the dielectric layer. Other embodiments may be described and/or claimed.
Various embodiments herein provide techniques for uplink control information (UCI) multiplexing in multi—transmission-reception point (TRP) multi-panel operation. For example, the UCI may be multiplexed on a physical uplink shared channel (PUSCH) and/or a physical uplink control channel (PUCCH). Embodiments further include techniques for handling collision between PUSCH and PUCCH with different priorities. Additionally, embodiments include techniques for timing control for multi-TRP multi-panel operation. Other embodiments may be described and claimed.
Methods, apparatus, systems and articles of manufacture for loss-error-aware quantization of a low-bit neural network are disclosed. An example apparatus includes a network weight partitioner to partition unquantized network weights of a first network model into a first group to be quantized and a second group to be retrained. The example apparatus includes a loss calculator to process network weights to calculate a first loss. The example apparatus includes a weight quantizer to quantize the first group of network weights to generate low-bit second network weights. In the example apparatus, the loss calculator is to determine a difference between the first loss and a second loss. The example apparatus includes a weight updater to update the second group of network weights based on the difference. The example apparatus includes a network model deployer to deploy a low-bit network model including the low-bit second network weights.
G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
G06F 18/21 - Conception ou mise en place de systèmes ou de techniquesExtraction de caractéristiques dans l'espace des caractéristiquesSéparation aveugle de sources
G06F 18/214 - Génération de motifs d'entraînementProcédés de Bootstrapping, p. ex. ”bagging” ou ”boosting”
G06N 3/047 - Réseaux probabilistes ou stochastiques
G06N 3/084 - Rétropropagation, p. ex. suivant l’algorithme du gradient
77.
TECHNOLOGIES FOR TRUSTED I/O PROTECTION OF I/O DATA WITH HEADER INFORMATION
Technologies for trusted I/O include a computing device having a hardware cryptographic agent, a cryptographic engine, and an I/O controller. The hardware cryptographic agent intercepts a message from the I/O controller and identifies boundaries of the message. The message may include multiple DMA transactions, and the start of message is the start of the first DMA transaction. The cryptographic engine encrypts the message and stores the encrypted data in a memory buffer. The cryptographic engine may skip and not encrypt header data starting at the start of message or may read a value from the header to determine the skip length. In some embodiments, the cryptographic agent and the cryptographic engine may be an inline cryptographic engine. In some embodiments, the cryptographic agent may be a channel identifier filter, and the cryptographic engine may be processor-based. Other embodiments are described and claimed.
Techniques to improve performance of matrix multiply operations are described in which a compute kernel can specify one or more element-wise operations to perform on output of the compute kernel before the output is transferred to higher levels of a processor memory hierarchy.
One embodiment provides an apparatus comprising a memory stack including multiple memory dies and a parallel processor including a plurality of multiprocessors. Each multiprocessor has a single instruction, multiple thread (SIMT) architecture, the parallel processor coupled to the memory stack via one or more memory interfaces. At least one multiprocessor comprises a multiply-accumulate circuit to perform multiply-accumulate operations on matrix data in a stage of a neural network implementation to produce a result matrix comprising a plurality of matrix data elements at a first precision, precision tracking logic to evaluate metrics associated with the matrix data elements and indicate if an optimization is to be performed for representing data at a second stage of the neural network implementation, and a numerical transform unit to dynamically perform a numerical transform operation on the matrix data elements based on the indication to produce transformed matrix data elements at a second precision.
G06F 7/544 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs n'établissant pas de contact, p. ex. tube, dispositif à l'état solideMéthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul
A processing apparatus described herein includes a general-purpose parallel processing engine comprising a systolic array having multiple pipelines, each of the multiple pipelines including multiple pipeline stages, wherein the multiple pipelines include a first pipeline, a second pipeline, and a common input shared between the first pipeline and the second pipeline.
An apparatus to facilitate exception handling for debugging in a graphics environment is disclosed. The apparatus includes load store pipeline hardware circuitry to: in response to a page fault exception being enabled for a memory access request received from a thread of the plurality of threads, allocate a memory dependency token correlated to a scoreboard identifier (SBID) that is included with the memory access request; send, to memory fabric of the graphics processor, the memory access request comprising the memory dependency token; receive, from the memory fabric in response to the memory access request, a memory access response comprising the memory dependency token and indicating occurrence of a page fault error condition and fault details associated with the page fault error condition; and return the SBID associated with the memory access response and fault details of the page fault error condition to a debug register of the thread.
Disclosed embodiments relate to systems and methods for performing instructions to convert to 16-bit floating-point format. In one example, a processor includes fetch circuitry to fetch an instruction having fields to specify an opcode and locations of a first source vector comprising N single-precision elements, and a destination vector comprising at least N 16-bit floating-point elements, the opcode to indicate execution circuitry is to convert each of the elements of the specified source vector to 16-bit floating-point, the conversion to include truncation and rounding, as necessary, and to store each converted element into a corresponding location of the specified destination vector, decode circuitry to decode the fetched instruction, and execution circuitry to respond to the decoded instruction as specified by the opcode.
Techniques for converting FP16 to BF8 using bias are described. An exemplary embodiment utilizes decoder circuitry to decode a single instruction, the single instruction to include one or more fields to identify a first source operand, one or more fields to identify a second source operand, one or more fields to identify a source/destination operand, and one or more fields for an opcode, wherein the opcode is to indicate that execution circuitry is to convert packed half-precision data from the identified first and second sources to packed bfloat8 data using bias terms from the identified source/destination operand and store the packed bfloat8 data into corresponding data element positions of the identified source/destination operand; and execution circuitry to execute the decoded instruction according to the opcode to convert packed half-precision data from the identified first and second sources to packed bfloat8 data using bias terms from the identified source/destination operand and store the packed bfloat8 data into corresponding data element positions of the identified source/destination operand.
Techniques for scalable virtualization of an Input/Output (I/O) device are described. An electronic device composes a virtual device comprising one or more assignable interface (AI) instances of a plurality of AI instances of a hosting function exposed by the I/O device. The electronic device emulates device resources of the I/O device via the virtual device. The electronic device intercepts a request from the guest pertaining to the virtual device, and determines whether the request from the guest is a fast-path operation to be passed directly to one of the one or more AI instances of the I/O device or a slow-path operation that is to be at least partially serviced via software executed by the electronic device. For a slow-path operation, the electronic device services the request at least partially via the software executed by the electronic device.
G06F 9/455 - ÉmulationInterprétationSimulation de logiciel, p. ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
G06F 9/48 - Lancement de programmes Commutation de programmes, p. ex. par interruption
G06F 15/17 - Communication entre processeurs utilisant une connexion de type entrée/sortie, p. ex. canal, point d'accès entrée/sortie
85.
Instruction and Micro-Architecture Support for Decompression on Core
Methods and apparatus relating to an instruction and/or micro-architecture support for decompression on core are described. In an embodiment, decode circuitry decodes a decompression instruction into a first micro operation and a second micro operation. The first micro operation causes one or more load operations to fetch data into one or more cachelines of a cache of a processor core. Decompression Engine (DE) circuitry decompresses the fetched data from the one or more cachelines of the cache of the processor core in response to the second micro operation. Other embodiments are also disclosed and claimed.
G06F 12/0893 - Mémoires cache caractérisées par leur organisation ou leur structure
G06F 12/0875 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache avec mémoire cache dédiée, p. ex. instruction ou pile
86.
METHODS AND APPARATUS TO IMPROVE USER EXPERIENCE ON COMPUTING DEVICES
Methods and apparatus to improve user experience on computing devices are disclosed. An example computing device includes a microphone to capture audio corresponding to spoken words. The example computing device further includes a speech analyzer to: detect a keyword prompt from among the spoken words, the keyword prompt to precede a query statement of a user of the computing device; and identify topics associated with a subset of the spoken words, the subset of the spoken words captured by the microphone before the keyword prompt. The example computing device also includes a communications interface to, in response to detection of the keyword prompt, transmit information indicative of the query statement and ones of the identified topics to a remote server.
In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive an input from one or more detectors proximate a display to present an output from a graphics pipeline, determine that a user is not interacting with the display, and in response to a determination that the user is not interacting with the display, to reduce a frame rendering rate of the graphics pipeline. Other embodiments are also disclosed and claimed.
Examples described herein relate to switch circuitry that is to: based on receipt of a packet at the first input port and based on allocation of a first memory region in the memory to the first input port: based on capability of a first buffer for the first output port to store the packet, store the packet into the first buffer and egress the packet from the first buffer to the first output port and based on incapability of the first buffer to store the packet, store the packet into the first memory region and associate the packet with the first buffer prior to egress from the first output port.
H04L 49/253 - Routage ou recherche de route dans une matrice de commutation en utilisant l'établissement ou la libération de connexions entre les ports
H04L 49/112 - Commande de la commutation, p. ex. par arbitrage
89.
TECHNOLOGIES TO ADJUST LINK EFFICIENCY AND BUFFER SIZE
Examples described herein relate to a switch or router. In some examples, the switch or router is to: based on receipt of a control packet associated with a first link, store the control packet into a first region of memory associated with the first link; based on receipt of a data packet associated with the first link, store the data packet into a second region of memory associated with the first link; based on the control packet and data packet to egress from a same output port, insert a strict subset of content of the control packet into the data packet to form a second data packet; and cause transmission of the second data packet to a device from the output port.
Memory management for wireless networks is described. A method, includes accessing an operational parameter for a network slice of a wireless network, determining a first memory region of a plurality of memory regions in the memory pool based on the operational parameter, and encoding configuration information to allocate the first memory region to the network slice. Other embodiments are described and claimed.
Described herein are gate-all-around (GAA) transistors with extended drains, where the drain region extends through a well region below the GAA transistor. A high voltage can be applied to the drain, and the extended drain region provides a voltage drop. The transistor length (and, specifically length of the extended drain) can be varied based on the input voltage to the device, e.g., providing a longer drain for higher input voltages. The extended drain transistors can be implemented in devices that include CFETs, either by implementing the extended drain transistor across both CFET layers, or by providing a sub-fin pedestal with the well regions in the lower layer.
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
92.
SYSTEMS, METHODS, AND APPARATUSES FOR TILE TRANSPOSE
Embodiments detailed herein relate to matrix operations. In particular, support for a matrix transpose instruction is detailed. In some embodiments, decode circuitry to decode an instruction having fields for an opcode, a source matrix operand identifier, and a destination matrix operand identifier; and execution circuitry to execute the decoded instruction to transpose each row of elements of the identified source matrix operand into a corresponding column of the identified destination matrix operand are detailed.
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
G06F 7/78 - Dispositions pour le réagencement, la permutation ou la sélection de données selon des règles prédéterminées, indépendamment du contenu des données pour changer l'ordre du flux des données, p. ex. transposition matricielle ou tampons du type pile d'assiettes [LIFO]Gestion des occurrences du dépassement de la capacité du système ou de sa sous-alimentation à cet effet
93.
SYSTEMS, METHODS, AND APPARATUSES FOR TILE MATRIX MULTIPLICATION AND ACCUMULATION
Embodiments detailed herein relate to matrix operations. In particular, matrix (tile) multiply accumulate and negated matrix (tile) multiply accumulate are discussed. For example, in some embodiments decode circuitry to decode an instruction having fields for an opcode, an identifier for a first source matrix operand, an identifier of a second source matrix operand, and an identifier for a source/destination matrix operand; and execution circuitry to execute the decoded instruction to multiply the identified first source matrix operand by the identified second source matrix operand, add a result of the multiplication to the identified source/destination matrix operand, and store a result of the addition in the identified source/destination matrix operand and zero unconfigured columns of identified source/destination matrix operand are detailed.
The disclosed embodiments are generally directed to inline encryption of data at line speed at a chip interposed between two memory components. The inline encryption may be implemented at a System-on-Chip (“SOC” or “SOC”). The memory components may comprise Non-Volatile Memory express (NVMe) and a dynamic random access memory (DRAM). An exemplary device includes an SOC to communicate with a Non-Volatile Memory NVMe circuitry to provide direct memory access (DMA) to an external memory component. The SOC may include: a cryptographic controller circuitry; a cryptographic memory circuitry in communication with the cryptographic controller, the cryptographic memory circuitry configured to store instructions to encrypt or decrypt data transmitted through the SOC; and an encryption engine in communication with the crypto controller circuitry, the encryption engine configured to encrypt or decrypt data according to instructions stored at the crypto memory circuitry. Other embodiments are also disclosed and claimed.
G06F 21/79 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du stockage de données dans les supports de stockage à semi-conducteurs, p. ex. les mémoires adressables directement
G06F 12/14 - Protection contre l'utilisation non autorisée de mémoire
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p. ex. acces direct à la mémoire, vol de cycle
G06F 21/62 - Protection de l’accès à des données via une plate-forme, p. ex. par clés ou règles de contrôle de l’accès
G06F 21/85 - Protection des dispositifs de saisie, d’affichage de données ou d’interconnexion dispositifs d’interconnexion, p. ex. les dispositifs connectés à un bus ou les dispositifs en ligne
95.
SYSTOLIC ARRAY OF ARBITRARY PHYSICAL AND LOGICAL DEPTH
A processing apparatus includes a processing resource including a general-purpose parallel processing engine and a matrix accelerator. The matrix accelerator includes first circuitry to receive a command to perform operations associated with an instruction, second circuitry to configure the matrix accelerator according to a physical depth of a systolic array within the matrix accelerator and a logical depth associated with the instruction, third circuitry to read operands for the instruction from a register file associated with the systolic array, fourth circuitry to perform operations for the instruction via one or more passes through one or more physical pipeline stages of the systolic array based on a configuration performed by the second circuitry, and fifth circuitry to write output of the operations to the register file associated with the systolic array.
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p. ex. plusieurs processeurs de données à instruction unique
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
96.
HIGH THROUGHPUT CONTROL INFORMATION AND FIELD EXTENSION
This disclosure describes systems, methods, and devices related to high throughput (HT) control information. A device may determine a frame comprising HT control information. The device may determine to extend a size of the HT control information. The device may cause to generate a management or data frame for sending to a first station device of one or more station devices, the management or data frame comprising extended high throughput (HT) control information, define a new control identification (ID) associated with the extended HT control information, and cause to send the management or data frame to the first station device.
In one embodiment, an apparatus includes: an integrity circuit to receive data and generate a protection code based at least in part on the data; a cryptographic circuit coupled to the integrity circuit to encrypt the data into encrypted data and encrypt the protection code into an encrypted protection code; a message authentication code (MAC) circuit coupled to the cryptographic circuit to compute a MAC comprising a tag using header information, the encrypted data, and the encrypted protection code; and an output circuit to send the header information, the encrypted data, and the tag to a receiver via a link. Other embodiments are described and claimed.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
H04L 69/22 - Analyse syntaxique ou évaluation d’en-têtes
98.
HIGH AVAILABILITY AI VIA A PROGRAMMABLE NETWORK INTERFACE DEVICE
Techniques described herein address the above challenges that arise when using host executed software to manage vector databases by providing a vector database accelerator and shard management offload logic that is implemented within hardware and by software executed on device processors and programmable data planes of a programmable network interface device. In one embodiment, a programmable network interface device includes infrastructure management circuitry configured to facilitate data access for a neural network inference engine having a distributed data model via dynamic management of a node associated with the neural network inference engine, the node including a database shard of a vector database.
Described herein are stacked photonic integrated circuit (PIC) assemblies that include multiple layers of waveguides. The waveguides are formed of substantially monocrystalline materials, which cannot be repeatedly deposited. Layers of monocrystalline material are fabricated and repeatedly transferred onto the PIC structure using a layer transfer process, which involves bonding a monocrystalline material using a non-monocrystalline bonding material. Layers of isolation materials are also deposited or layer transferred onto the PIC assembly.
G02B 6/132 - Circuits optiques intégrés caractérisés par le procédé de fabrication par le dépôt de couches minces
G02B 6/12 - Guides de lumièreDétails de structure de dispositions comprenant des guides de lumière et d'autres éléments optiques, p. ex. des moyens de couplage du type guide d'ondes optiques du genre à circuit intégré
G02B 6/136 - Circuits optiques intégrés caractérisés par le procédé de fabrication par gravure
A datacenter including a plurality of racks. The racks associated with a motorized and/or automated system to move the racks between first and second positions. In the first position, the racks are arranged in a side-by-side fashion in one or more rows. In the second position, a rack is moved so that a lateral side of the rack is accessible. In some embodiments, the racks include a motor and gear system for interacting with tracks. In some embodiments, each of the racks includes a plurality of chassis, each chassis including a plurality of input/output (I/O) connectors to receive a connector of a cable, the plurality of I/O connectors are arranged along a lateral side of the chassis so that they are accessible when the rack is in the second position. In use, the racks may be moved between the first and second positions while the chassis remain in normal operation.
