A computer model is trained with an architecture including additional training layers relative to the inference architecture. The architecture of a computer model to be used in inference includes a convolutional layer with a number of K×K convolutional filters. For training, the convolutional filters are expanded to a plurality of training layers including a layer with 1×1 and K×K filters. The expanded layers may include additional layers than the number of expanded filters in the layer of the inference model. The 1×1 expanded layer in training may learn weights for combining the K×K expanded layers, providing a weighted combination of the K×K filters for the respective channel of the layer of the inference layer.
A system that includes a graphics processing unit (GPU) that includes first circuitry to based on a configuration: count a number of transactions; count a time to receive the transactions; count a number of clock cycles for the time for transactions; and output, to a testing equipment, the number of transactions, the time to receive the transactions, and the number of clock cycles for the time for the counted number of transactions. The GPU can include second circuitry that is to cause adjustment of a number of transaction entries in the cache based on a received instruction, wherein the adjust the number of transaction entries in the cache is based on the number of transactions, the time to receive the transactions, and the number of clock cycles for the time for transactions.
Techniques are provided herein for forming one or more capacitors between backside power rails using backside contacts to the backside power rails. In one example, a capacitor includes a first plurality of plate-like electrodes that alternate with a second plurality of plate-like electrodes. Backside contacts are used to contact bottom surfaces of the first plurality of plate-like electrodes and bottom surfaces of the second plurality of plate-like electrodes. In another example, a capacitor includes a first plurality of plate-like electrodes and one or more second plate-like electrodes. A dielectric layer is present over the first plurality of plate-like electrodes. A conductive layer is present on the dielectric layer and also contacting at least one of the one or more second plate-like electrodes. Backside contacts are used to contact bottom surfaces of the first plurality of plate-like electrodes and bottom surfaces of the one or more second plate-like electrodes.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a first die having a first surface and an opposing second surface embedded in a first dielectric layer, where the first surface of the first die is coupled to the second surface of the package substrate by first interconnects; a second die having a first surface and an opposing second surface embedded in a second dielectric layer, where the first surface of the second die is coupled to the second surface of the first die by second interconnects; and a third die having a first surface and an opposing second surface embedded in a third dielectric layer, where the first surface of the third die is coupled to the second surface of the second die by third interconnects.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
5.
STRIPPED REDISTRUBUTION-LAYER FABRICATION FOR PACKAGE-TOP EMBEDDED MULTI-DIE INTERCONNECT BRIDGE
An embedded multi-die interconnect bridge (EMIB) is fabricated on a substrate using photolithographic techniques, and the EMIB is separated from the substrate and placed on the penultimate layer of an integrated-circuit package substrate, below the top solder-resist layer. A low Z-height of the EMIB, allows for useful trace and via real estate below the EMIB, to be employed in the package substrate.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
6.
APPARATUS, SYSTEM, AND METHOD OF LOW LATENCY TRAFFIC
For example, an Access Point (AP) may be configured to set a predefined indication field to a predefined setting configured to indicate a request for a non-AP station (STA) to provide a current Enhanced Distributed Channel Access (EDCA) retry count for one or more low latency traffic flows. For example, the AP may be configured to transmit a Buffer Status Report Poll (BSRP) trigger frame to solicit a Buffer Status Report (BSR) from the non-AP STA. For example, the BSRP trigger frame may be configured to include the predefined indication field. For example, the non-AP STA may be configured to process the BSRP trigger frame, and to transmit to the AP a frame including a reported current EDCA retry count corresponding to a reported low latency traffic flow, for example, based on a determination that the predefined indication field is set to the predefined setting.
An apparatus to facilitate accelerating mutation testing for simulation and formal verification is disclosed. The apparatus includes processing circuitry to define a set of mutations and a set of verification properties for an original design under test (DUT); utilize a conditional input bit to conditionally activate the set of mutations in the original DUT; generate a conditional DUT comprising the original DUT having the conditional input bit applied to the set of mutations; for each verification property, inspect a query associated with the verification property and the conditional DUT to determine whether the verification property has at least one mutation of the set of mutations that has a corresponding conditional input bit that is present; and run a verification sign-off tool that executes the verification properties that are determined to have the at least one mutation of the set of mutations with the corresponding conditional input bit that is present.
G06F 30/3323 - Vérification de la conception, p. ex. simulation fonctionnelle ou vérification du modèle utilisant des méthodes formelles, p. ex. vérification de l’équivalence ou vérification des propriétés
G06F 30/333 - Conception en vue de la testabilité [DFT], p. ex. chaîne de balayage ou autotest intégré [BIST]
Examples described herein relate to an interface and a circuitry, coupled to the interface. In some examples, the circuitry is to translate an interrupt from system management interrupt (SMI) format to a second interrupt in System Control Interrupt (SCI) format and transmit the second interrupt, by the interface, to an SCI interrupt handler to perform event handling. In some examples, the SCI interrupt handler is to execute on a single thread.
Described herein is a technique for automatic detection of defects via formal verification bug hunting of floating-point designs. In one embodiment the technique specifies a method including loading a hardware definition into an automatic bug fixing tool configured to automatically generate input constraints for formal verification of a device under test (DUT), querying for operational constraints defined for portions of the hardware definition directed towards floating-point operations, adjusting formal verification proofs based on the operational constraints, and performing formal verification of the hardware definition based on adjusted formal verification proofs.
G06F 30/333 - Conception en vue de la testabilité [DFT], p. ex. chaîne de balayage ou autotest intégré [BIST]
G06F 30/3323 - Vérification de la conception, p. ex. simulation fonctionnelle ou vérification du modèle utilisant des méthodes formelles, p. ex. vérification de l’équivalence ou vérification des propriétés
10.
Concept for Software Application Container Hardware Resource Allocation
Examples relate to a concept for software application container hardware resource allocation, and in particular to sidecar apparatuses, sidecar devices, methods for a software application container sidecars, a resource management controller apparatus, a resource management controller device, and corresponding computer programs and computer systems. A sidecar apparatus comprises interface circuitry, machine-readable instructions and processing circuitry to execute the machine-readable instructions to obtain information on hardware resources desired by a software application container from the software application container, and to provide a request for changing the hardware resources allocated to the software application container to another entity capable of influencing an allocation of hardware resources to the software application container.
An apparatus is described. The apparatus includes a module to be inserted into an electronic system. The module includes a first heat exchanger at one end of the module and second heat exchanger at another end of the module. The module also includes a first vapor chamber that runs along respective integrated heat spreaders of semiconductor chips disposed on a first side of the module and a second vapor chamber that runs along respective integrated heat spreaders of semiconductor chips disposed on a second side of the module. The first heat exchanger is in thermal contact with at least one of the first and second vapor chambers, and, the second heat exchanger is in thermal contact with at least one of the first and second vapor chambers.
Techniques are disclosed for reducing or eliminating loop overhead caused by function calls in processors that form part of a pipeline architecture. The processors in the pipeline process data blocks in an iterative fashion, with each processor in the pipeline completing one of several iterations associated with a processing loop for a commonly-executed function. The described techniques leverage the use of message passing for pipelined processors to enable an upstream processor to signal to a downstream processor when processing has been completed, and thus a data block is ready for further processing in accordance with the next loop processing iteration. The described techniques facilitate a zero loop overhead architecture, enable continuous data block processing, and allow the processing pipeline to function indefinitely within the main body of the processing loop associated with the commonly-executed function where efficiency is greatest.
Methods, apparatus, systems, and articles of manufacture are disclosed for real-time interactive performances. An example apparatus includes at least one memory, machine readable instructions, and processor circuitry to at least one of instantiate or execute the machine readable instructions to capture an image of a performance area, detect one or more performers in the performance area using the image, estimate locations of the one or more detected performers, smooth the estimated locations of the one or more detected performers based on prior estimated locations, and provide the smoothed estimated locations to display controller circuitry for generation of an interactive effect based on the smoothed estimated locations
Disclosed herein are NEMS switches embedded in backend layers of IC structures (backend NEMS switches). A backend NEMS switch includes one or more moveable nanoscale cantilevers that can be actuated to make or break electrical connections, thus controlling the flow of electrical current. Cantilevers may be suspended or anchored between electrodes and can be moved or deflected by applying electrical, mechanical, or thermal stimuli. An example IC structure may include an insulator material, first and second interconnects embedded in the insulator material, and a backend NEMS switch. The backend NEMS switch may include a middle element, a cantilever extending from the middle element, and one or more control elements. The middle element is connected to the first interconnect and, depending on a stimulus applied to the one or more control elements, the cantilever is either electrically connected to or electrically disconnected from the second interconnect.
Technologies for allocating resources across data centers include a compute device to obtain resource utilization data indicative of a utilization of resources for a managed node to execute a workload. The compute device is also to determine whether a set of resources presently available to the managed node in a data center in which the compute device is located satisfies the resource utilization data. Additionally, the compute device is to allocate, in response to a determination that the set of resources presently available to the managed node does not satisfy the resource utilization data, a supplemental set of resources to the managed node. The supplemental set of resources are located in an off-premises data center that is different from the data center in which the compute device is located. Other embodiments are also described.
G06F 12/06 - Adressage d'un bloc physique de transfert, p. ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
G06F 12/0802 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache
G06F 12/1045 - Traduction d'adresses utilisant des moyens de traduction d’adresse associatifs ou pseudo-associatifs, p. ex. un répertoire de pages actives [TLB] associée à une mémoire cache de données
G06F 12/14 - Protection contre l'utilisation non autorisée de mémoire
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
G06F 13/42 - Protocole de transfert pour bus, p. ex. liaisonSynchronisation
G06F 15/16 - Associations de plusieurs calculateurs numériques comportant chacun au moins une unité arithmétique, une unité programme et un registre, p. ex. pour le traitement simultané de plusieurs programmes
G06F 15/173 - Communication entre processeurs utilisant un réseau d'interconnexion, p. ex. matriciel, de réarrangement, pyramidal, en étoile ou ramifié
G06F 15/78 - Architectures de calculateurs universels à programmes enregistrés comprenant une seule unité centrale
G06F 16/11 - Administration des systèmes de fichiers, p. ex. détails de l’archivage ou d’instantanés
G06F 16/22 - IndexationStructures de données à cet effetStructures de stockage
G06F 16/248 - Présentation des résultats de requêtes
G06F 16/25 - Systèmes d’intégration ou d’interfaçage impliquant les systèmes de gestion de bases de données
G06F 16/901 - IndexationStructures de données à cet effetStructures de stockage
G06F 21/10 - Protection de programmes ou contenus distribués, p. ex. vente ou concession de licence de matériel soumis à droit de reproduction
G06F 30/34 - Conception de circuits pour circuits reconfigurables, p. ex. réseaux de portes programmables [FPGA] ou circuits logiques programmables [PLD]
G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
G06Q 10/0631 - Planification, affectation, distribution ou ordonnancement de ressources d’entreprises ou d’organisations
G06Q 30/0283 - Estimation ou détermination de prix
G11C 8/12 - Circuits de sélection de groupe, p. ex. pour la sélection d'un bloc de mémoire, la sélection d'une puce, la sélection d'un réseau de cellules
G11C 29/02 - Détection ou localisation de circuits auxiliaires défectueux, p. ex. compteurs de rafraîchissement défectueux
G11C 29/36 - Dispositifs de génération de données, p. ex. inverseurs de données
G11C 29/38 - Dispositifs de vérification de réponse
G11C 29/44 - Indication ou identification d'erreurs, p. ex. pour la réparation
H04L 41/0213 - Protocoles de gestion de réseau normalisés, p. ex. protocole de gestion de réseau simple [SNMP]
H04L 41/0668 - Gestion des fautes, des événements, des alarmes ou des notifications en utilisant la reprise sur incident de réseau par sélection dynamique des éléments du réseau de récupération, p. ex. le remplacement par l’élément le plus approprié après une défaillance
H04L 41/149 - Analyse ou conception de réseau pour la prédiction de la maintenance
H04L 41/34 - Canaux de signalisation pour la communication dédiée à la gestion du réseau
H04L 41/40 - Dispositions pour la maintenance, l’administration ou la gestion des réseaux de commutation de données, p. ex. des réseaux de commutation de paquets en utilisant la virtualisation des fonctions réseau ou ressources, p. ex. entités SDN ou NFV
H04L 41/5019 - Pratiques de respect de l’accord du niveau de service
H04L 41/5025 - Pratiques de respect de l’accord du niveau de service en réagissant de manière proactive aux changements de qualité du service, p. ex. par reconfiguration après dégradation ou mise à niveau de la qualité du service
H04L 43/20 - Dispositions pour la surveillance ou le test de réseaux de commutation de données le système de surveillance ou les éléments surveillés étant des entités virtualisées, abstraites ou définies par logiciel, p. ex. SDN ou NFV
H04L 45/28 - Routage ou recherche de routes de paquets dans les réseaux de commutation de données en utilisant la reprise sur incident de routes
H04L 45/7453 - Recherche de table d'adressesFiltrage d'adresses en utilisant le hachage
H04L 49/351 - Interrupteurs spécialement adaptés à des applications spécifiques pour des réseaux locaux [LAN], p. ex. des commutateurs Éthernet
H04L 49/40 - Détails de construction, p. ex. alimentation électrique, construction mécanique ou fond de panier
H04L 49/9005 - Dispositions de mémoires tampon en utilisant une allocation dynamique de l'espace des mémoires tampon
H04L 67/1001 - Protocoles dans lesquels une application est distribuée parmi les nœuds du réseau pour accéder à un serveur parmi une pluralité de serveurs répliqués
H04L 67/1008 - Sélection du serveur pour la répartition de charge basée sur les paramètres des serveurs, p. ex. la mémoire disponible ou la charge de travail
H04L 69/22 - Analyse syntaxique ou évaluation d’en-têtes
H04L 69/32 - Architecture des piles de protocoles du type interconnexion de systèmes ouverts en 7 couches, p. ex. interfaces entre le niveau liaison et le niveau physique
H04L 69/321 - Protocoles de communication inter-couches ou définitions d'unité de données de service [SDU]Interfaces entre les couches
H05K 7/14 - Montage de la structure de support dans l'enveloppe, sur cadre ou sur bâti
A system that includes a graphics processing unit (GPU) comprising multiple processors and circuitry to: store compressed first data into the at least one memory based on a first address; store meta data associated with the compressed first data into the at least one memory; store compressed second data into the at least one memory based on a second address; copy the meta data into a cache of the at least one cache; and decompress the compressed first data and compressed second data based on at least one read of the stored meta data from the cache of the at least one cache.
G06F 12/0811 - Systèmes de mémoire cache multi-utilisateurs, multiprocesseurs ou multitraitement avec hiérarchies de mémoires cache multi-niveaux
G06F 12/1027 - Traduction d'adresses utilisant des moyens de traduction d’adresse associatifs ou pseudo-associatifs, p. ex. un répertoire de pages actives [TLB]
G06T 1/20 - Architectures de processeursConfiguration de processeurs p. ex. configuration en pipeline
09 - Appareils et instruments scientifiques et électriques
Produits et services
Computer hardware; semi-conductors; semi-conductor packaging; interconnect bridges; embedded silicon bridges; substrate packages; computer hardware for interconnecting multiple dies within a single chip package
18.
MEMORY CELLS WITH SEMICONDUCTOR LAYERS OF DIFFERENT DOPING LEVELS
Disclosed herein are memory cells with semiconductor layers of different doping levels, and related devices and techniques. In some embodiments, a memory cell may include a first semiconductor layer, a second semiconductor layer on the first semiconductor layer, a third semiconductor layer on the second semiconductor layer, a fourth semiconductor layer on the third semiconductor layer, a fifth semiconductor layer on the fourth semiconductor layer, and a sixth semiconductor layer on the fifth semiconductor layer, wherein dopant concentrations of the first semiconductor layer, the fourth semiconductor layer, and the sixth semiconductor layer are higher than dopant concentrations of the second semiconductor layer, the third semiconductor layer, and the fifth semiconductor layer.
For example, a STA may transmit a Fast Basic Service Set (BSS) Transition (FT) request to a target AP via a current AP with which the STA is associated, wherein the FT request is configured to request an FT from the current AP to the target AP; process an FT response from the target AP after the FT request, the FT response received by the STA via the current AP; transmit a reassociation request to the target AP via the current AP after the FT response, the reassociation request to request to associate between the STA and the target AP; process a reassociation response from the target AP after the reassociation request, the reassociation response received by the STA via the current AP; and switch the STA from the current AP to the target AP for communication via an associated session between the STA and the target AP.
For example, a millimeterWave (mmWave) wireless communication station (STA) may be configured to transmit a preamble of a packet via a plurality of antennas of the mmWave STA over a mmWave wireless communication channel; and to transmit a Multiple-Input-Multiple-Output (MIMO) Training (TRN) field of the packet over the mmWave wireless communication channel, the MIMO TRN field is after the preamble, the MIMO TRN field including a sequence of a plurality of MIMO TRN subfields transmitted via the plurality of antennas of the mmWave STA. For example, a MIMO TRN subfield of the plurality of MIMO TRN subfields may include a plurality of TRN sequences simultaneously transmitted via the plurality of antennas, respectively.
H04B 7/08 - Systèmes de diversitéSystèmes à plusieurs antennes, c.-à-d. émission ou réception utilisant plusieurs antennes utilisant plusieurs antennes indépendantes espacées à la station de réception
H04B 7/06 - Systèmes de diversitéSystèmes à plusieurs antennes, c.-à-d. émission ou réception utilisant plusieurs antennes utilisant plusieurs antennes indépendantes espacées à la station d'émission
H04L 25/03 - Réseaux de mise en forme pour émetteur ou récepteur, p. ex. réseaux de mise en forme adaptatifs
H04L 27/26 - Systèmes utilisant des codes à fréquences multiples
21.
ENHANCED DESIGN AND USE OF LONGER LOW-DENSITY PARITY-CHECK WI-FI CODEWORDS
This disclosure describes systems, methods, and devices related to for low-density parity-check (LDPC) Wi-Fi coding and decoding. A device may identify a first base matrix to generate LDPC codewords of 1944 bits; identify a mask matrix to generate a second base matrix based on the first base matrix used to generate LDPC codewords of 3888 bits, the entries of the mask matrix having values of 0, 1, and −1; generate the second base matrix by multiplying each the first base matrix by the mask matrix, the entries of the second base matrix indicative of respective cyclic shifts to apply to an identity matrix; generate a parity check matrix by multiplying the second base matrix by the identity matrix; generate a LDPC codeword of 3888 bits based on the parity check matrix; and transmit a frame including the LDPC codeword.
H03M 13/25 - Détection d'erreurs ou correction d'erreurs transmises par codage spatial du signal, c.-à-d. en ajoutant une redondance dans la constellation du signal, p. ex. modulation codée en treillis [TMC]
H03M 13/00 - Codage, décodage ou conversion de code pour détecter ou corriger des erreursHypothèses de base sur la théorie du codageLimites de codageMéthodes d'évaluation de la probabilité d'erreurModèles de canauxSimulation ou test des codes
H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue
22.
DIFFERENTIATED CONTAINERIZATION AND EXECUTION OF WEB CONTENT BASED ON TRUST LEVEL AND OTHER ATTRIBUTES
Systems and methods may provide for receiving web content and determining a trust level associated with the web content. Additionally, the web content may be mapped to an execution environment based at least in part on the trust level. In one example, the web content is stored to a trust level specific data container.
G06F 21/51 - Contrôle des utilisateurs, des programmes ou des dispositifs de préservation de l’intégrité des plates-formes, p. ex. des processeurs, des micrologiciels ou des systèmes d’exploitation au stade du chargement de l’application, p. ex. en acceptant, en rejetant, en démarrant ou en inhibant un logiciel exécutable en fonction de l’intégrité ou de la fiabilité de la source
G06F 21/53 - Contrôle des utilisateurs, des programmes ou des dispositifs de préservation de l’intégrité des plates-formes, p. ex. des processeurs, des micrologiciels ou des systèmes d’exploitation au stade de l’exécution du programme, p. ex. intégrité de la pile, débordement de tampon ou prévention d'effacement involontaire de données par exécution dans un environnement restreint, p. ex. "boîte à sable" ou machine virtuelle sécurisée
H04L 67/02 - Protocoles basés sur la technologie du Web, p. ex. protocole de transfert hypertexte [HTTP]
23.
HIGH FIDELITY INTERACTIVE SEGMENTATION FOR VIDEO DATA WITH DEEP CONVOLUTIONAL TESSELLATIONS AND CONTEXT AWARE SKIP CONNECTIONS
Techniques related to automatically segmenting video frames into per pixel fidelity object of interest and background regions are discussed. Such techniques include applying tessellation to a video frame to generate feature frames corresponding to the video frame and applying a segmentation network implementing context aware skip connections to an input volume including the feature frames and a context feature volume corresponding to the video frame to generate a segmentation for the video frame.
G06V 10/26 - Segmentation de formes dans le champ d’imageDécoupage ou fusion d’éléments d’image visant à établir la région de motif, p. ex. techniques de regroupementDétection d’occlusion
G06V 10/764 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant la classification, p. ex. des objets vidéo
G06V 20/40 - ScènesÉléments spécifiques à la scène dans le contenu vidéo
24.
TECHNOLOGIES FOR RE-PROGRAMMABLE HARDWARE IN AUTONOMOUS VEHICLES
Techniques are disclosed herein for reconfiguring reprogrammable hardware in an autonomous vehicle system. According to an embodiment, an autonomous driving system includes sensors and a configurable circuit having physical logic units. The autonomous driving system aggregates data observed from each of the sensors. The autonomous driving system detects a trigger indicative of a defect in the configurable circuit. The defect is identified as a function of the aggregated data. The autonomous driving system performs, in response to the trigger, a reconfiguration action on the configurable circuit to repair the defect.
G06F 11/07 - Réaction à l'apparition d'un défaut, p. ex. tolérance de certains défauts
B60W 60/00 - Systèmes d’aide à la conduite spécialement adaptés aux véhicules routiers autonomes
G06F 11/00 - Détection d'erreursCorrection d'erreursContrôle de fonctionnement
G06F 11/20 - Détection ou correction d'erreur dans une donnée par redondance dans le matériel en utilisant un masquage actif du défaut, p. ex. en déconnectant les éléments défaillants ou en insérant des éléments de rechange
G06F 11/22 - Détection ou localisation du matériel d'ordinateur défectueux en effectuant des tests pendant les opérations d'attente ou pendant les temps morts, p. ex. essais de mise en route
G07C 5/00 - Enregistrement ou indication du fonctionnement de véhicules
G07C 5/08 - Enregistrement ou indication de données de marche autres que le temps de circulation, de fonctionnement, d'arrêt ou d'attente, avec ou sans enregistrement des temps de circulation, de fonctionnement, d'arrêt ou d'attente
25.
CONTEXT-AWARE MEMORY TIERING FOR MACHINE LEARNING TRAINING
Techniques for training machine learning models are described. In particular, some examples describe the use of storing out a tensor after a training forward pass if conditions warrant this storage. For example, if the tensor can be stored to a different memory, but still be pre-fetched before it is needed in a backward training pass, then the tensor is stored out in some examples. By storing out tensors, memory is freed for computation of subsequent forward and backward passes. This helps improve page swapping, etc. of data.
A method, apparatus, and non-transitory computer-readable medium for packaging and deploying applications using virtualized execution units (VEUs). A development apparatus instantiates a development environment, captures changes to identify build elements, and packages the build elements into a VEU. An execution apparatus receives and parses the VEU to obtain build elements, determines corresponding deployment actions, and applies these actions to instantiate the application in a deployment environment, automating application deployment while preserving state.
G06F 9/455 - ÉmulationInterprétationSimulation de logiciel, p. ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
Example systems, apparatus, articles of manufacture, and methods to perform data flow metering on a fixed rate link interface are disclosed. An example apparatus disclosed herein increments a first pointer to track a first number of data characters to be written to a fixed rate link interface in a clock period of the fixed rate link interface, the fixed rate link associated with a first clock frequency. The example apparatus also increments a second pointer to track a second number of data characters to be read from the fixed rate link interface in the clock period, the second pointer incremented based on integer and fractional components of a ratio between a second clock frequency and the first clock frequency, the second clock frequency associated with a data source. The example apparatus further meters data transmission on the fixed rate link interface based on the first pointer and the second pointer.
Examples include techniques associated for multiple isolations for shared memory. Examples include the shared memory being included on or at an externally-attached shared memory device. The shared memory at the externally-attached shared memory device can be shared between multiple domains hosted by one or more host computing platforms. The multiple isolations to be established for memory access transactions to the shared memory by one or more domains that can access the shared memory.
Examples include techniques associated with enumeration of a shared memory device. Examples include the shared memory device is an externally-attached shared memory device configured to maintain one or more shared memory regions that can be shared between multiple host computing platforms. The externally-attached shared memory device can communicate with a host computing platform's basic input/output operating system (BIOS) to provide device capabilities to facilitate enumeration of the externally-attached shared memory device.
Examples include techniques associated for use of in-memory compute circuitry in shared memory. Examples include the shared memory being included on or at an externally attached shared memory device. The shared memory at the externally attached shared memory device can be shared between multiple domains hosted by one or more host computing platforms. Examples include establishment of multiple isolations for in-memory compute requests for in-memory compute operations to the shared memory by one or more domains that can access the shared memory.
Examples include allocation of a memory region of memory that is accessible to multiple processes of a tenant. In some examples, based on receipt of a first request to access Mixture of Experts (MoE) artificial intelligence (AI) trained weight data from a process associated with a first tenant, apply a configuration to determine whether to permit the access to the trained weight data from a memory and based on a determination to permit the access to the trained weight data, permit the memory to provide trained weight data to the process.
Examples described herein include shared reserved memory regions providing communications among network functions for isolation among network slices. In some examples, circuitry is configured to: based on receipt of a first request, allocate a first region of one or more memory regions of a memory to store data reserved for access by a first network slice for communication between an Open Radio Access Network (ORAN) Centralized Unit (CU) and a Distributed Unit (DU) of the first network slice; report telemetry data indicative of access to the first region; and based on a first command, selectively adjust resources of the memory allocated to the first network slice.
H04W 28/16 - Gestion centrale des ressourcesNégociation de ressources ou de paramètres de communication, p. ex. négociation de la bande passante ou de la qualité de service [QoS Quality of Service]
Examples described herein include shared reserved memory regions providing communications among network functions for isolation among network slices. In some examples, circuitry is configured to: based on receipt of a first request, allocate a first region of one or more memory regions of memory to store data reserved for access by a first network function of a radio access network (RAN) and reserved for access by a second network function of the RAN, access telemetry data of the first network function to indicate isolation of the first region for the first network function, and based on the accessed telemetry data, reserve a second region of one or more memory regions of the memory for the first network function and also release the reservation of the first region to store data for the first network function and second network function of the RAN.
H04W 48/16 - ExplorationTraitement d'informations sur les restrictions d'accès ou les accès
34.
MICROELECTRONICS PACKAGE COMPRISING A PACKAGE-ON-PACKAGE (POP) ARCHITECTURE WITH INKJET BARRIER MATERIAL FOR CONTROLLING BONDLINE THICKNESS AND POP ADHESIVE KEEP OUT ZONE
Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.
H01L 23/373 - Refroidissement facilité par l'emploi de matériaux particuliers pour le dispositif
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
35.
FAST ANGULAR SEARCH AND ADAPTIVE SKIP DECISION IN INTRA-PREDICTION FOR VIDEO ENCODING
It is a technical challenge to find an encoding solution that can reduce complexity for intra-prediction encoding while maintaining the quality gains from the added available block partitioning structures and available coding tools for coding the blocks. In some embodiments, the complexity associated with block partitioning structures is reduced by performing intra-prediction decision for blocks larger than 4x4 pixels only in certain scenarios. In some embodiments, the complexity associated with added coding tools is reduced by modifying intra-prediction decision making (for blocks where intra-prediction decision making is to be applied or not skipped) to include fast angular candidate selection based on a reduce set of angular candidates and rate-distortion optimization (RDO) on 4 or 5 intra-prediction modes.
H04N 19/11 - Sélection du mode de codage ou du mode de prédiction parmi plusieurs modes de codage prédictif spatial
H04N 19/176 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage adaptatif caractérisés par l’unité de codage, c.-à-d. la partie structurelle ou sémantique du signal vidéo étant l’objet ou le sujet du codage adaptatif l’unité étant une zone de l'image, p. ex. un objet la zone étant un bloc, p. ex. un macrobloc
H04N 19/103 - Sélection du mode de codage ou du mode de prédiction
36.
APPARATUS, SYSTEM, AND METHOD OF COMMUNICATING A SHORT TRAINING FIELD (STF) OVER A MILLIMETERWAVE (MMWAVE) CHANNEL
For example, a wireless communication device may be configured to generate a Short Training Field (STF) according to a millimeter Wave (mmWave) Physical layer (PHY) Protocol Data Unit (PPDU) format. For example, the STF may include a plurality of repetitions of an STF structure. For example, the STF structure may include a plurality of repetitions of a short training Orthogonal Frequency Division Multiplexing (OFDM) symbol, which may include a training sequence over a plurality of OFDM tones. For example, the wireless communication device may be configured to transmit an mm Wave PPDU including the STF according to the mmWave PPDU format over an mmWave wireless communication channel in an mmWave frequency band.
Various systems and methods are described implementing a multi-access edge computing (MEC) based system to realize MEC application registration and application data functions for MEC frameworks. In an example, operations are performed at a MEC orchestrator to maintain a registry of applications within a MEC system or among a federation of MEC systems, with the MEC orchestrator performing operations including: identifying, based on the communications with a plurality of MEC hosts, a plurality of applications provided by the MEC hosts in the MEC system (or, by applications provided by a plurality of MEC hosts in a federation); storing and synchronizing application information for the plurality of applications in a registry; and communicating the application information from the registry to an entity of the MEC system or to an entity federated with the MEC system.
H04W 60/04 - Rattachement à un réseau, p. ex. enregistrementSuppression du rattachement à un réseau, p. ex. annulation de l'enregistrement utilisant des événements déclenchés
G06F 9/455 - ÉmulationInterprétationSimulation de logiciel, p. ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
H04L 67/10 - Protocoles dans lesquels une application est distribuée parmi les nœuds du réseau
38.
INTEGRATED CIRCUIT STRUCTURES HAVING CUT METAL GATES
Integrated circuit structures having cut metal gates, and methods of fabricating integrated circuit structures having cut metal gates, are described. For example, an integrated circuit structure includes a fin having a portion protruding above a shallow trench isolation (STI) structure. A gate dielectric material layer is over the protruding portion of the fin and over the STI structure. A conductive gate layer is over the gate dielectric material layer. A conductive gate fill material is over the conductive gate layer. A dielectric gate plug is laterally spaced apart from the fin, the dielectric gate plug on but not through the STI structure. The gate dielectric material layer and the conductive gate layer are not along sides of the dielectric gate plug, and the conductive gate fill material is in contact with the sides of the dielectric gate plug.
Provided is an apparatus comprising interface circuitry, machine-readable instructions and processing circuitry to execute the machine-readable instructions. The machine-readable instructions include instructions to store a first plurality of cryptographic authentication credentials configured to authenticate the apparatus, wherein each of the plurality of authentication credentials is provisioned to a second plurality of different apparatuses and to select a first authentication credential from the first plurality of authentication credentials for authenticating the apparatus to a verifier. The machine-readable instructions further include instructions to transmit a certificate of the selected first authentication credential to the verifier for authentication and to receive revocation information from the verifier. The machine-readable instructions further include instructions to select a second cryptographic credential from the first plurality of cryptographic credentials based on a stored counting index if the received revocation information indicates that the selected first authentication credential is revoked.
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
Systems, apparatus, articles of manufacture, and methods are disclosed. An example apparatus includes interface circuitry, machine-readable instructions, and programmable circuitry to at least one of instantiate or execute the machine-readable instructions to generate potential actions to, if implemented, re-assign a client device in the wireless network from a first base station device in the wireless network to another base station device in the wireless network, wherein the re-assignment is to cause the first base station device to stop communications with the client device and is to cause the another base station device to begin communications with the client device; execute a first machine learning model to predict which of the potential actions would satisfy a quality of service (QoS) threshold; execute a second machine learning model to select one of the potential actions predicted to satisfy the QoS threshold; and implement the selected action within the wireless network.
Methods and apparatus for variable chunk size memory compression. A physical address space for system memory is partitioned into an uncompressed partition in which data are stored without compression and a compressed partition in which compressed data are stored using a plurality of chunk sizes. In response to a memory Read request, when it is determined that the requested data are stored in a compressed partition, the location of a compressed chunk on a memory device containing the data is determined, the data are retrieved and decompressed, and the decompressed data are returned to the core issuing the memory Read request. A compressed page table (CPT) is maintained containing entries having fields encoding a chunk size, a device address corresponding to a start of the compressed page, and one or more fields denoting sizes of each chunk in the compressed page.
Examples described herein include shared reserved memory regions providing communications among network functions for isolation among network slices. In some examples, circuitry is configured to: based on receipt of a first request, allocate a first region of one or more memory regions of a memory to store data reserved for access by a first network function of a radio access network (RAN) and shared for access by a second network function of the RAN and allocate a processor to perform operations of the first network function, wherein the first network function and the second network function perform operations of Open Radio Access Network (ORAN) components.
Examples described herein include shared reserved memory regions providing communications among network functions for isolation among network slices. In some examples, circuitry is configured to: based on receipt of a first request, allocate a first region of one or more memory regions of a memory to store data reserved for access by a first network function, wherein the first network function comprises an Open Radio Access Network (ORAN) Control Unit (CU) of a radio access network (RAN) and wherein an ORAN Distributed Unit (DU) is to provide the data and based on receipt of a second request, allocate a second region of one or more memory regions of the memory to store second data reserved for access by a second network function, wherein the second network function comprises a second ORAN CU of the RAN, the DU is to provide the second data, and the DU is shared among the first CU and the second CU.
For example, an Ultra High Reliability (UHR) Access Point (AP) may be configured to configure a UHR parameters update element. For example, the UHR parameters update element may include an updated setting of one or more UHR parameters to be updated by the UHR AP in a critical update event. For example, the UHR AP may be configured to transmit a plurality of protected beacon frames during a critical update period before a time at which the one or more UHR parameters are to be updated. For example, a protected beacon frame of the plurality of protected beacon frames may include the UHR parameters update element.
Various systems and methods are described implementing a multi-access edge computing (MEC) based system to realize MEC federation management and broker functions for MEC frameworks. In an example, performing edge federation management functions of edge computing systems, to establish a partnership among multiple edge federation managers as a federation, include: using system data attributes to establish the partnership; using authentication data attributes to enable the edge federation managers to securely authenticate; using authorization data attributes to enable the edge federation managers to perform authorization; using availability zone data attributes to define zones in the federation; and using management and settlement information data attributes to enable management of resources in the federation. Further operations include communicating the data attributes via respective connections with the edge federation managers, and the use of defined interfaces and operations.
H04L 67/288 - Dispositifs intermédiaires distribués, c.-à-d. dispositifs intermédiaires pour l'interaction avec d'autres dispositifs intermédiaires de même niveau
An apparatus to facilitate supporting 8-bit floating point format operands in a computing architecture is disclosed. The apparatus includes a processor comprising: a decoder to decode an instruction fetched for execution into a decoded instruction, wherein the decoded instruction is a matrix instruction that operates on 8-bit floating point operands to cause the processor to perform a parallel dot product operation; a controller to schedule the decoded instruction and provide input data for the 8-bit floating point operands in accordance with an 8-bit floating data format indicated by the decoded instruction; and systolic dot product circuitry to execute the decoded instruction using systolic layers, each systolic layer comprises one or more sets of interconnected multipliers, shifters, and adder, each set of multipliers, shifters, and adders to generate a dot product of the 8-bit floating point operands.
In one embodiment, an apparatus includes: a first link layer circuit to perform link layer functionality for a first communication protocol; and a logical physical (logPHY) circuit coupled to the first link layer circuit via a logical PHY interface (LPIF) link, the logPHY circuit to communicate with the first link layer circuit in a flit mode in which the first information is communicated in a fixed width size and to communicate with another link layer circuit in a non-flit mode. Other embodiments are described and claimed.
G06F 13/38 - Transfert d'informations, p. ex. sur un bus
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
Systems and apparatus are disclosed for cooling configuration for memory devices. An example cooling device includes a heat sink further including a longitudinal length having a left end, a right end, and a first planar orientation, a transverse height having a top, a bottom, and a second planar orientation orthogonal to the first planar orientation, and an inner side and an outer side, the outer side including at least one channel having the second planar orientation. The example cooling device also includes a first heat pipe further including a first heat pipe portion having a left end, a right end, and the second planar orientation, the first heat pipe portion seated into the at least one channel, a heat pipe transition portion coupled to the left end of the first heat pipe portion, the transition portion including a first end having the second planar orientation and a second end having the first planar orientation, and a heat dissipation portion coupled to the second end of the heat pipe transition portion.
Examples herein relate to an interface selectively providing access to a memory region for a work request from an entity by providing selective access to a physical address of the memory region and selective access to a cryptographic key for use by a memory controller to access the memory region. In some examples, providing selective access to a physical address conversion is based on one or more of: validation of a certificate received with the work request and an identifier of the entity being associated with a process with access to the memory region. Access to the memory region can be specified. A memory region can be a page or sub-page sized region. Different access rights can be associated with different sub-portions of the memory region, wherein the access rights comprise one or more of: create, read, update, delete, write, or notify.
G06F 15/173 - Communication entre processeurs utilisant un réseau d'interconnexion, p. ex. matriciel, de réarrangement, pyramidal, en étoile ou ramifié
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
An infrastructure for a platform immersive experience is described. An example of an apparatus includes a microcontroller to receive control parameters for platform lighting options for a computing system and information regarding current system conditions for the computing system, and generate control instructions for a lighting pattern for a set of lights based at least in part on the control parameters and the information regarding current system conditions; and host control circuitry to receive the control instructions for the lighting pattern from the microcontroller, and provide control signals to control the set of lights.
Methods and apparatus relating to one or more delayed cache writeback instructions for improved data sharing in manycore processors are described. In an embodiment, a delayed cache writeback instruction causes a cache block in a modified state in a Level 1 (L1) cache of a first core of a plurality of cores of a multi-core processor to a Modified write back (M.wb) state. The M.wb state causes the cache block to be written back to LLC upon eviction of the cache block from the L1 cache. Other embodiments are also disclosed and claimed.
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
G06F 12/0804 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache avec mise à jour de la mémoire principale
52.
SYSTEM AND METHOD FOR BALANCING SPARSITY IN WEIGHTS FOR ACCELERATING DEEP NEURAL NETWORKS
An apparatus is provided to access a weight vector of a layer in a sequence of layers in the DNN. The weight vector includes a first sequence of weights having different values. A bitmap is generated based on the weight vector. The bitmap includes a second sequence of bitmap elements. Each bitmap element corresponds to a different weight and has a value determined based at least on the value of the corresponding weight. The index of each bitmap element in the second sequence matches the index of the corresponding weight in the first sequence. A new bitmap is generated by rearranging the bitmap elements in the second sequence based on the values of the bitmap elements. The weight vector is rearranged based on the new bitmap. The rearranged weight vector is divided into subsets, each of which is assigned to a different PE for a MAC operation.
G06F 7/76 - Dispositions pour le réagencement, la permutation ou la sélection de données selon des règles prédéterminées, indépendamment du contenu des données
53.
LITHOGRAPHIC CAVITY FORMATION TO ENABLE EMIB BUMP PITCH SCALING
Embodiments include an electronic package with an embedded multi-interconnect bridge (EMIB) and methods of making such packages. Embodiments include a first layer, that is an organic material and a second layer disposed over the first layer. In an embodiment, a cavity is formed through the second layer to expose a first surface of the first layer. A bridge substrate is in the cavity and is supported by the first surface of the first layer. Embodiments include a first die over the second layer that is electrically coupled to a first contact on the bridge substrate, and a second die over the second layer that is electrically coupled to a second contact on the bridge substrate. In an embodiment the first die is electrically coupled to the second die by the bridge substrate.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
54.
IC PACKAGE INCLUDING MULTI-CHIP UNIT WITH BONDED INTEGRATED HEAT SPREADER
A multi-chip unit suitable for chip-level packaging may include multiple IC chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. Bonding of the integrated heat spreader to the multiple IC chips may be direct so that no thermal interface material (TIM) is needed, resulting in a reduced bond line thickness (BLT) and lower thermal resistance. The integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. The redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing IC chips of differing thickness prior to bonding the heat spreader. The sacrificial interposer may be removed to expose the RDL for further interconnection to a substrate without the use of through-substrate vias.
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
55.
SEMI-RANDOM MEMORY RETRIEVAL FOR IMAGE REGISTRATION BASED ON K-MEANS
Systems and methods are provided for image registration, which is used in video noise reduction and other multi-frame processing applications, such as remote sensing, medical imaging, and computer vision. Image registration can include geometrically transforming a current image to align with a reference image, ensuring that objects, patterns, and/or features in the images appear in the same spatial location. Memory is accessed for image retrieval for mapping pixels in the main image to corresponding pixels in a reference image. To minimize overhead in memory-bandwidth and achieve a high retrieval rate, the two-dimensional plane is split into vertical stripes, and, for each vertical stripe, an independent one-dimensional fetch-mechanism is formulated based on tracking two clusters of source-pixels using a simplified K-means algorithm. Using two clusters of source pixels enables fetching pixels from across discontinuities in the motion-field The systems and methods allow for power-efficient multi-frame processing and high-quality video noise reduction.
G06T 7/33 - Détermination des paramètres de transformation pour l'alignement des images, c.-à-d. recalage des images utilisant des procédés basés sur les caractéristiques
Systems, apparatus, articles of manufacture, and methods to distribute workloads in server farms based on temperature are disclosed. An example first compute device includes at least one programmable circuit to at least one of instantiate or execute machine readable instructions to: analyze temperature data indicative of a first temperature of a first compute device and a second temperature of a second compute device; and cause an adjustment in at least one of a first workload executed by the first compute device or a second workload executed by the second compute device based on the temperature data, the adjustment to reduce a difference between the first and second temperatures.
A system-in-package apparatus includes a semiconductive bridge that uses bare-die pillars to couple with a semiconductive device such as a processor die. The apparatus achieves a thin form factor.
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides
Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
An integrated circuit package is disclosed. The integrated circuit package includes a first integrated circuit die, a second integrated circuit die, an organic substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the organic substrate, a multi-die interconnect bridge (EMIB) embedded within the organic substrate, and a termination resistor associated with a circuit in the first integrated circuit die, wherein the termination resistor is located within the multi-die interconnect bridge embedded within the organic substrate.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
An apparatus, including: a simulator configured to estimate signal propagation delays for a plurality of conductive trace structures, wherein the conductive trace structures include at least one tabbed routing structure; a compensator configured to determine trace-specific delay compensation values based on measured actual signal propagation delays obtained from PCB test coupons that include the tabbed routing structure and calculate compensated physical trace lengths using the trace-specific delay compensation values to achieve signal timing alignment; and a correlator configured to correlate estimated signal propagation delays with the measured actual signal propagation delays.
Methods, apparatus, systems, and articles of manufacture are disclosed to debug a hardware accelerator such as a neural network accelerator for executing Artificial Intelligence computational workloads. An example apparatus includes a core with a core input and a core output to execute executable code based on a machine-learning model to generate a data output based on a data input, and debug circuitry coupled to the core. The debug circuitry is configured to detect a breakpoint associated with the machine-learning model, compile executable code based on at least one of the machine-learning model or the breakpoint. In response to the triggering of the breakpoint, the debug circuitry is to stop the execution of the executable code and output data such as the data input, data output and the breakpoint for debugging the hardware accelerator.
G06F 11/277 - Matériel de test, c.-à-d. circuits de traitement de signaux de sortie avec une comparaison entre la réponse effective et la réponse connue en l'absence d'erreur
Systems, apparatus, articles of manufacture, and methods are disclosed to implement memory sparing. An example memory controller includes first logic circuitry to: determine a first bank index for a bank of a memory that is to be moved; and determine if a first row index hash of an element in the bank of memory matches the first bank index; and second logic circuitry to: when the first row index hash matches the first bank index, move the element to a reserved row of the memory in the memory based on the first row index; and when the first row index hash does not match the first bank index, move the element to a bank in the reserved row that has a second bank index based on the first row index.
Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 23/50 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes pour des dispositifs à circuit intégré
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
Through gate fin isolation for non-planar transistors in a microelectronic device, such as an integrated circuit (IC). In embodiments, ends of adjacent semiconductor fins are electrically isolated from each other with an isolation region that is self-aligned to gate electrodes of the semiconductor fins enabling higher transistor packing density and other benefits. In an embodiment, a single mask is employed to form a plurality of sacrificial placeholder stripes of a fixed pitch, a first subset of placeholder stripes is removed and isolation cuts made into the semiconductor fins in openings resulting from the first subset removal while a second subset of the placeholder stripes is replaced with gate electrodes.
H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
H10D 84/03 - Fabrication ou traitement caractérisés par l'utilisation de technologies basées sur les matériaux utilisant une technologie du groupe IV, p. ex. technologie au silicium ou au carbure de silicium [SiC]
H10D 84/85 - Transistors IGFET complémentaires, p. ex. CMOS
H10D 86/00 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre
Provided is a computer-readable medium including computer-readable instructions. When the instructions are executed by a computer, the computer may implement a method. According to this method, a reference time value and a real time value are obtained based on hash calculation to positional information respectively, and a time-related verification on the positional information is performed based on the two time values.
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
An application workload is performed on data by a plurality of processor devices, where the data is stored in a first memory associated with a first one of the processor devices and a second memory is associated with a second one of the processor devices. Accesses of the data from the first memory by the plurality of processor devices are monitored. The data is transformed from a first form to a second form based on the accesses, and the data is transformed in the second form to the second memory based on the accesses.
A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.
G06F 13/22 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le balayage successif, p. ex. l'appel sélectif
G06F 1/3287 - Économie d’énergie caractérisée par l'action entreprise par la mise hors tension d’une unité fonctionnelle individuelle dans un ordinateur
G06F 8/71 - Gestion de versions Gestion de configuration
G06F 9/46 - Dispositions pour la multiprogrammation
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
G06F 12/0806 - Systèmes de mémoire cache multi-utilisateurs, multiprocesseurs ou multitraitement
G06F 12/0808 - Systèmes de mémoire cache multi-utilisateurs, multiprocesseurs ou multitraitement avec moyen d'invalidation de mémoires cache
G06F 12/0813 - Systèmes de mémoire cache multi-utilisateurs, multiprocesseurs ou multitraitement avec configuration en réseau ou matrice
G06F 12/0815 - Protocoles de cohérence de mémoire cache
G06F 12/0831 - Protocoles de cohérence de mémoire cache à l’aide d’un schéma de bus, p. ex. avec moyen de contrôle ou de surveillance
G06F 13/42 - Protocole de transfert pour bus, p. ex. liaisonSynchronisation
H04L 9/06 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p. ex. système DES
A UE is configured for power boosting in the NR network. The processing circuitry of the UE is to encode capability reporting signaling for transmission to a base station. The capability reporting signaling includes a parameter indicating the UE supports power boosting in an uplink transmission when using pi -over- two BPSK modulation or QPSK modulation. The processing circuitry is to decode configuration signaling received from the base station. The configuration signaling is to configure an uplink carrier aggregation band for uplink transmission. The processing circuitry is to decode the configuration signaling to determine the power boosting is enabled for the UE. The processing circuitry encodes uplink data for the uplink transmission using the pi-over-two BPSK modulation or the QPSK modulation with power boosting when the uplink carrier aggregation band includes one uplink component carrier.
This disclosure describes systems, methods, and devices for measuring carriers in a frequency band within 24250 – 52600 MHz. A user equipment (UE) device may identify a reference signal (RS) received from a base station; measure a target carrier frequency of the RS in a frequency band within 24250 – 52600 MHz; set a carrier specific scaling factor, associated with measurement delays for additional target carrier frequencies in the frequency band, to one; and signal to the base station that the measurement of the target carrier frequency applies to the additional target carrier frequencies in the frequency band based on setting the carrier specific scaling factor to one.
This disclosure describes systems, methods, and devices related to enhanced null data packet (NDP) for 60 GHz BBT. A device may establish two or more links with a non-AP multi-link device (MLD). The device may cause to send on a first link of the two or more links a trigger discovery frame to a first station device (STA) in the non-AP MLD. The device may select a beamforming training sequence mode. The device may cause to send a training frame, based on the beamforming training sequence mode, during a beamforming phase, on a second link of the two or more links with a second STA in the non-AP MLD. The device may identify a feedback frame received from the first STA on the first link.
H04B 7/06 - Systèmes de diversitéSystèmes à plusieurs antennes, c.-à-d. émission ou réception utilisant plusieurs antennes utilisant plusieurs antennes indépendantes espacées à la station d'émission
H04W 8/00 - Gestion de données relatives au réseau
H04W 76/15 - Établissement de connexions à liens multiples sans fil
In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to receive a plurality of data inputs for training a neural network, wherein the data inputs comprise training data and weights inputs; represent the data inputs in a first form; and represent the weight inputs in a second form. Other embodiments are also disclosed and claimed.
An apparatus and method for dynamic reassignment of resources. For example, an example method comprises: executing a plurality of threads on a plurality of cores and/or functional circuit blocks, the cores and/or functional circuit blocks coupled to an interconnect; associating, by resource management circuitry, a class of service (CLOS) level of a plurality of CLOS levels with each thread of the plurality of threads, the resource management circuitry to detect one or more inactive CLOS levels corresponding to inactive threads; remapping, by the resource management circuitry, active threads from corresponding active CLOS levels to the one or more inactive CLOS levels, the remapping to provide the active threads with a larger allocation of resources than provided at the corresponding active CLOS levels; and allocating any remaining resources to the active threads in accordance with the respective active CLOS levels of the active threads.
Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 23/50 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes pour des dispositifs à circuit intégré
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
74.
METHODS AND APPARATUS FOR COOLING OF DUAL IN-LINE MEMORY MODULES
Methods and apparatus for cooling of dual in-line memory modules are disclosed. An example apparatus includes: a heat pipe, and a first base to house the heat pipe. The first base is to be thermally coupled to a first side of a dual in-line memory module (DIMM). The example apparatus further includes a second base to be thermally coupled to a second side of a DIMM. The second side is opposite the first side. The second base is to be thermally coupled to the first base.
Integrated circuit structures having deep via bar width tuning are described. For example, an integrated circuit structure includes a plurality of gate lines extending over first and second semiconductor nanowire stack channel structures or fin structures. A plurality of trench contacts is intervening with the plurality of gate lines. A conductive structure is between the first and second semiconductor nanowire stack channel structures or fin structures, the conductive structure having a first width in a first region and a second width in a second region between the first and second semiconductor nanowire stack channel structures or fin structures, the second width different than the first width.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H10D 30/43 - Transistors FET ayant des canaux à gaz de porteurs de charge de dimension nulle [0D], à une dimension [1D] ou à deux dimensions [2D] ayant des canaux à gaz de porteurs de charge à une dimension, p. ex. transistors FET à fil quantique ou transistors ayant des canaux à confinement quantique à une dimension
Techniques for the use of verbal commands in human-robot communication. The number of tasks the robot can perform is limited to a specific set, while providing syntactic flexibility to users. The system includes two components: a speech recognizer for speech-to-text conversion and a natural language understanding module that maps the text to a command for the robot. After speech is transcribed to text, a nearest neighbor classifier can be applied in the high dimensional space of embedding tokens. Multiple variants of each command are provided in a database of reference embeddings, and the classifier can identify the k nearest reference embedding tokens to determine the command. The text similarity model allows for quick detection solutions to be deployed locally on a robot or other device. Local deployment reduces potential latency caused by a cloud connection, which can be important in many assistant robot applications.
G10L 15/10 - Classement ou recherche de la parole utilisant des mesures de distance ou de distorsion entre la parole inconnue et les gabarits de référence
Embodiments disclosed herein include electronic packages and methods of forming electronic packages. In an embodiment, an electronic package comprises an interposer, where the interposer comprises a cavity that passes through the interposer, a through interposer via (TIV), and an interposer pad electrically coupled to the TIV. In an embodiment, the electronic package further comprises a nested component in the cavity, where the nested component comprises a component pad, and a die coupled to the interposer pad by a first interconnect and coupled to the component pad by a second interconnect. In an embodiment, the first interconnect and the second interconnect each comprise an intermediate pad, and a bump over the intermediate pad.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
78.
DEVICE AND METHOD OF VERY HIGH DENSITY ROUTING USED WITH EMBEDDED MULTI-DIE INTERCONNECT BRIDGE
A device and method for providing enhanced bridge structures is disclosed. A set of conducting and insulating layers are deposited and lithographically processed. The conducting layers have uFLS routing. A bridge with uFLS contacts and die disposed on the underlying structure such that the die are connected with the uFLS contacts and uFLS routing. For core-based structures, the layers are formed after the bridge is placed on the underlying structure and the die connected to the bridge through intervening conductive layers. For coreless structures, the layers are formed over the bridge and carrier, which is removed prior to bonding the die to the bridge, and the die bonded directly to the bridge.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 21/683 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 23/50 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes pour des dispositifs à circuit intégré
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
80.
NANORIBBON-BASED TRANSISTORS WITH ETCH STOP LAYER TO ASSIST SUBFIN REMOVAL
Fabrication methods that employ an etch stop layer to assist subfin removal during fabrication of nanoribbon-based transistors are disclosed. An example fabrication method includes providing a stack of nanoribbons above a subfin, where the nanoribbons and the subfin include one or more semiconductor materials; depositing an etch stop layer over a top of the subfin and around portions of the nanoribbons; removing the etch stop layer from around the portions of the nanoribbons; providing a gate dielectric material around the portions of the nanoribbons and over the etch stop layer over the top of the subfin; depositing a gate electrode material around the portions of the nanoribbons; and performing an etch to remove the subfin without substantially removing the etch stop layer.
H10D 84/03 - Fabrication ou traitement caractérisés par l'utilisation de technologies basées sur les matériaux utilisant une technologie du groupe IV, p. ex. technologie au silicium ou au carbure de silicium [SiC]
H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
Disclosed herein are IC structures and devices that aim to mitigate proximity effects of deep trench vias. An example IC structure may include a device region having a first face and a second face, the second face being opposite the first face, and further include a conductive via extending between the first face and the second face, wherein the conductive via includes an electrically conductive material, and wherein a concentration of titanium at sidewalls of the conductive via is below about 1015 atoms per cubic centimeter.
H10D 62/83 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe IV, p. ex. Si dopé B ou Ge non dopé
H01L 21/285 - Dépôt de matériaux conducteurs ou isolants pour les électrodes à partir d'un gaz ou d'une vapeur, p. ex. condensation
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
H10D 30/43 - Transistors FET ayant des canaux à gaz de porteurs de charge de dimension nulle [0D], à une dimension [1D] ou à deux dimensions [2D] ayant des canaux à gaz de porteurs de charge à une dimension, p. ex. transistors FET à fil quantique ou transistors ayant des canaux à confinement quantique à une dimension
High-density socket connectors are disclosed herein. An example socket connector includes a first housing to be coupled to a substrate, The first housing has a first side, a second side opposite the first side, and a first opening extending through the first housing between the first side and the second side. The socket connector includes a socket pin disposed in the first opening. The socket connector further includes a second housing moveably coupled to the first housing. The second housing has a third side, a fourth side opposite the third side, and a second opening extending through the second housing between the third side and the fourth side. The socket pin extends into the second opening of the second housing. The second housing is moveable relative to the first housing between a first position and a second position.
In one embodiment, an apparatus includes a host controller to implement one or more layers of a Universal Serial Bus (USB)-based protocol to provide an interconnect for a plurality of devices. The host controller is to monitor control plane messages on the interconnect, detect, in the control plane messages, a power state change command for a device coupled to the interconnect, wherein the devices utilizes a tunneled protocol on the interconnect, and modify power distribution for one or more other devices of the interconnect based on detecting the power state change command.
G06F 1/3228 - Surveillance d’exécution de tâches, p. ex. par utilisation de temporisations d’attente, de commandes d’arrêt ou de commandes d’attente
G06F 1/3212 - Surveillance du niveau de charge de la batterie, p. ex. un mode d’économie d’énergie étant activé lorsque la tension de la batterie descend sous un certain niveau
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
G06F 13/38 - Transfert d'informations, p. ex. sur un bus
In various embodiments, disclosed herein are systems and methods directed to the fabrication of a coreless semiconductor package (e.g., a millimeter (mm)-wave antenna package) having an asymmetric build-up layer count that can be fabricated on both sides of a temporary substrate (e.g., a core). The asymmetric build-up layer count can reduce the overall layer count in the fabrication of the semiconductor package and can therefore contribute to fabrication cost reduction. In further embodiments, the semiconductor package (e.g., a millimeter (mm)-wave antenna packages) can further comprise dummification elements disposed near one or more antenna layers. Further, the dummification elements disposed near one or more antenna layers can reduce image current and thereby increasing the antenna gain and efficiency.
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/498 - Connexions électriques sur des substrats isolants
H01Q 1/36 - Forme structurale pour éléments rayonnants, p. ex. cône, spirale, parapluie
A machine-readable storage medium includes instructions stored thereupon, which when executed by processing circuitry of a computing node operable to implement a V2X information service (VIS) in a MEC network, cause the processing circuitry to perform operations comprising detecting a subscription request to an information service. The subscription request originates from a MEC application instantiated on a MEC host and includes at least one filtering criterion indicative of an information-processing configuration of the MEC application. The subscription request with the at least one filtering criterion is forwarded to a plurality of providers of the information service. A response message received from at least one of the providers is decoded. The response message indicates an acceptance of the subscription request by the at least one provider. An acknowledgment message is encoded for transmission to the MEC application, indicating the acceptance of the subscription request by the at least one provider.
H04W 4/44 - Services spécialement adaptés à des environnements, à des situations ou à des fins spécifiques pour les véhicules, p. ex. communication véhicule-piétons pour la communication entre véhicules et infrastructures, p. ex. véhicule à nuage ou véhicule à domicile
H04L 67/60 - Ordonnancement ou organisation du service des demandes d'application, p. ex. demandes de transmission de données d'application en utilisant l'analyse et l'optimisation des ressources réseau requises
H04L 69/08 - Protocoles d’interopérabilitéConversion de protocole
H04W 4/20 - Signalisation de servicesSignalisation de données auxiliaires, c.-à-d. transmission de données par un canal non destiné au trafic
H04W 60/04 - Rattachement à un réseau, p. ex. enregistrementSuppression du rattachement à un réseau, p. ex. annulation de l'enregistrement utilisant des événements déclenchés
86.
SYSTEM, APPARATUS AND METHODS FOR PERFORMANT READ AND WRITE OF PROCESSOR STATE INFORMATION RESPONSIVE TO LIST INSTRUCTIONS
In one embodiment, a processor includes: a front end circuit to fetch and decode a read list instruction, the read list instruction to cause storage to a memory of a software-provided list of processor state information; and an execution circuit coupled to the front end circuit. The execution circuit, in response to the decoded read list instruction, is to read the processor state information stored in the processor and store each datum of the processor state information into an entry of a data table in the memory. Other embodiments are described and claimed.
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
G06F 9/455 - ÉmulationInterprétationSimulation de logiciel, p. ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
G06F 9/48 - Lancement de programmes Commutation de programmes, p. ex. par interruption
Systems and devices can include a controller and a command queue to buffer incoming write requests into the device. The controller can receive, from a client across a link, a non-posted write request (e.g., a deferred memory write (DMWr) request) in a transaction layer packet (TLP) to the command queue; determine that the command queue can accept the DMWr request; identify, from the TLP, a successful completion (SC) message that indicates that the DMWr request was accepted into the command queue; and transmit, to the client across the link, the SC message that indicates that the DMWr request was accepted into the command queue. The controller can receive a second DMWr request in a second TLP; determine that the command queue is full; and transmit a memory request retry status (MRS) message to be transmitted to the client in response to the command queue being full.
Disclosed herein are integrated circuit (IC) packages, antenna boards, antenna modules, and communication devices (e.g., for millimeter wave communications). For example, in some embodiments, an antenna module may include: a logic die; a radio frequency front-end (RFFE) die in electrical communication with the logic die; and an antenna patch, wherein the RFFE die is closer to the antenna patch than the logic die is to the antenna patch.
In various embodiments, disclosed herein are systems and methods directed to the fabrication of a coreless semiconductor package (e.g., a millimeter (mm)-wave antenna package) having an asymmetric build-up layer count that can be fabricated on both sides of a temporary substrate (e.g., a core). The asymmetric build-up layer count can reduce the overall layer count in the fabrication of the semiconductor package and can therefore contribute to fabrication cost reduction. In further embodiments, the semiconductor package (e.g., a millimeter (mm)-wave antenna packages) can further comprise dummification elements disposed near one or more antenna layers. Further, the dummification elements disposed near one or more antenna layers can reduce image current and thereby increasing the antenna gain and efficiency.
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/498 - Connexions électriques sur des substrats isolants
H01Q 1/36 - Forme structurale pour éléments rayonnants, p. ex. cône, spirale, parapluie
A fan impeller, including: a hub; an annular structure positioned radially outward of the hub and defining a peripheral surface lying in a first plane; and a plurality of blades extending radially between the hub and the annular structure, each blade having a main surface lying in a second plane that is perpendicular to the first plane, wherein each of the plurality of blades includes an edge region proximate the annular structure, the edge region tapering to define an inclination angle between a top edge and a bottom edge of the blade, the inclination angle being configured to reduce turbulence during operation. Each of the plurality of blades may additionally define a slot formed through the main surface of the blade, the slot being configured to interrupt turbulent boundary layer growth towards a trailing edge of the respective blade.
F04D 29/28 - Rotors spécialement adaptés aux fluides compressibles pour pompes centrifuges ou hélicocentrifuges
F04D 17/02 - Pompes à flux radial spécialement adaptées aux fluides compressibles, p. ex. pompes centrifugesPompes hélicocentrifuges spécialement adaptées aux fluides compressibles ayant des étages non centrifuges, p. ex. centripètes
F04D 29/42 - Carters d'enveloppeTubulures pour le fluide énergétique pour pompes radiales ou hélicocentrifuges
F04D 29/66 - Lutte contre la cavitation, les tourbillons, le bruit, les vibrations ou phénomènes analoguesÉquilibrage
91.
TECHNIQUES FOR DECOUPLED ACCESS-EXECUTE NEAR-MEMORY PROCESSING
Techniques for decoupled access-execute near-memory processing include examples of first or second circuitry of a near-memory processor receiving instructions that cause the first circuitry to implement system memory access operations to access one or more data chunks and the second circuitry to implement compute operations using the one or more data chunks.
Methods, apparatuses, and computer readable media for polling APs for time allocation requests, where a first AP comprises processing circuitry configured to: decode, from a second AP, a BSRP trigger frame, the BSRP trigger frame comprising a user information field, the user information field comprising an AID field, the AID field indicating a first AP ID, and the BSRP trigger frame comprising a field, the field indicating a format for a response from the first AP, in response to the field indicating the format of the response from the first AP is to be a HT duplicate PPDU or a non-HT PPDU, encode, for transmission to the second AP, the non-HT duplicate PPDU or the non-HT PPDU, and in response to the field indicating the format of the response from the first AP is to be a PPDU, encode, for transmission to the second AP, the PPDU.
H04W 74/0816 - Accès non planifié, p. ex. ALOHA utilisant une détection de porteuse, p. ex. accès multiple par détection de porteuse [CSMA] avec évitement de collision
H04W 28/02 - Gestion du trafic, p. ex. régulation de flux ou d'encombrement
H04W 72/0446 - Ressources du domaine temporel, p. ex. créneaux ou trames
H04W 74/06 - Accès planifié utilisant une invitation à émettre
93.
METHODS AND APPARATUS TO INCREASE ROBUSTNESS IN RADIO ACCESS NETWORK - ARTIFICIAL INTELLIGENCE (RAN-AI) LIFE-CYCLE MANAGEMENT
A disclosed example includes identifying an event in a radio access network (RAN) based on RAN metrics data; accessing a machine learning (ML) model of the RAN; generating predictions of the ML model of the RAN based on a calibration dataset; determining uncertainty scores corresponding to the predictions of the ML model of the RAN; determining a conformity threshold based on the uncertainty scores; and updating a robustness protection layer in an inference pipeline to include the conformity threshold.
H04L 41/16 - Dispositions pour la maintenance, l’administration ou la gestion des réseaux de commutation de données, p. ex. des réseaux de commutation de paquets en utilisant l'apprentissage automatique ou l'intelligence artificielle
H04B 17/309 - Mesure ou estimation des paramètres de qualité d’un canal
94.
INITIAL CONTROL FRAMES WITH BLOCK ACKNOWLEDGMENT REQUEST
Methods, apparatuses, and computer readable media for initial control frames with block acknowledgement request, where a STA comprises processing circuitry configured to: decode, from an access point (AP), an ultra-high reliability (UHR) buffer status report poll (BSRP) trigger frame, the BSRP trigger frame including a user information field, the user information field comprising an association identification (AID) field, the AID field indicating an AID of the STA, and the BSRP trigger frame including a common information field, the common information field comprising a field, the field indicating a format of a response from the STA, in response to the field indicating the format of the response from the STA is a non-HT duplicate PPDU, encode, for transmission to the AP, the non-HT duplicate PPDU, and in response to the field indicating the format of the response from the STA is a PPDU, encode, for transmission to the AP, the PPDU.
An integrated circuit (IC) device may implement a speech recognition model with a transformer-based architecture. The IC device may include an embedder unit, etched mind unit(s), a layer normalizer unit, a sampler unit, and a flow control unit. The embedder unit may be a hardware implementation of an embedder in the model. The etched mind unit(s) may be a hardware implementation of matrix multiplications and additions in the model. The layer normalizer unit may implement a layer normalizer in the model. The sampler unit may implement a sampler in the model. The sampler unit may use comparators to find the largest value of a vector received from the etched mind unit(s). The sampler unit may determine the index of the largest value and output a predicted token. The flow contour unit may orchestrate the other components of the IC device based on a timing sequence of the model.
Building on the models-on-silicon (model-on-chip or model-on-die) architecture and design, multiple models-on-silicon chips/dies can be arranged in a stacked formation to form a single cube, referred to herein as AI cube. Each of these chips or dies can embed one or more transformer blocks, such as one or more consecutive transformer blocks of a transformer-based neural network. This stacked configuration enables processing of data in a feedforward manner, effectively performing processing for an inference task of a transformer-based neural network, e.g., an entire large language model, within one compact semiconductor integrated circuit package. For example, a 70 billion parameter LLM can be arranged and implemented onto an AI cube, where different groups of transformer blocks are distributed to different chips in the AI cube in a feedforward manner.
G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
Embodiments disclosed herein include photonics systems with a dual polarization module. In an embodiment, a photonics patch comprises a patch substrate, and a photonics die over a first surface of the patch substrate. In an embodiment, a multiplexer is over a second surface of the patch substrate. In an embodiment, a first optical path from the photonics die to the multiplexer is provided for propagating a first optical signal, and a second optical path from the photonics die to the multiplexer is provided for propagating a second optical signal. In an embodiment, a Faraday rotator is provided along the second optical path to convert the second optical signal from a first mode to a second mode before reaching the multiplexer.
G02B 27/28 - Systèmes ou appareils optiques non prévus dans aucun des groupes , pour polariser
G02F 1/01 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p. ex. commutation, ouverture de porte ou modulationOptique non linéaire pour la commande de l'intensité, de la phase, de la polarisation ou de la couleur
G02F 1/09 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p. ex. commutation, ouverture de porte ou modulationOptique non linéaire pour la commande de l'intensité, de la phase, de la polarisation ou de la couleur basés sur des éléments magnéto-optiques, p. ex. produisant un effet Faraday
An apparatus is provided which comprises: a first die having a first surface and a second surface, the first die comprising: a first layer formed on the first surface of the first die, and a second layer formed on the second surface of the first die; a second die coupled to the first layer; and a plurality of structures to couple the apparatus to an external component, wherein the plurality of structures is coupled to the second layer.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 21/683 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
Systems and methods are disclosed for Ambient Internet of Things (A- loT) devices that have at most a few hundred pW peak power consumption. Carrier wave (CW) transmission and collision handling for A-IoT applications are described for direct communication between A-IoT devices and base stations and indirect communications in which a reader is used. A user equipment (UE) provides the CW and, in indirect topologies, the same UE or a different UE may be used to transmit signals between the A-IoT device and base station. When scheduled CW and uplink transmissions from the UE overlap, one of the CW or uplink transmission may be predetermined to be canceled while the other is transmitted, or the transmission with a higher assigned priority may be transmitted.
H04W 72/23 - Canaux de commande ou signalisation pour la gestion des ressources dans le sens descendant de la liaison sans fil, c.-à-d. en direction du terminal
H04L 5/00 - Dispositions destinées à permettre l'usage multiple de la voie de transmission
H04W 72/563 - Critères d’affectation ou de planification des ressources sans fil sur la base de critères de priorité des ressources sans fil
H04W 88/04 - Dispositifs terminaux adapté à la retransmission à destination ou en provenance d'un autre terminal ou utilisateur
UE is configured for a physical uplink shared channel (PUSCH) transmission in a Fifth Generation New Radio (5G NR) network. The UE comprises front-end circuitry coupled to three or more antennas and processing circuitry coupled to the front-end circuitry. The processing circuitry is to decode control information received from a base station in a downlink control information (DCI) format. The control information includes an indicator of an association between a phase tracking reference signal (PTRS) and a demodulation reference signal (DMRS) for scheduling the PUSCH transmission with 3 transmit antenna ports. The processing circuitry is to configure transmission of the DMRS and the PTRS for the PUSCH transmission, a position of the PTRS in relation to the DMRS based on the association.
H04L 5/00 - Dispositions destinées à permettre l'usage multiple de la voie de transmission
H04W 72/1268 - Jumelage du trafic à la planification, p. ex. affectation planifiée ou multiplexage de flux de flux de données en liaison ascendante
H04W 72/232 - Canaux de commande ou signalisation pour la gestion des ressources dans le sens descendant de la liaison sans fil, c.-à-d. en direction du terminal les données de commande provenant de la couche physique, p. ex. signalisation DCI
H04B 7/024 - Utilisation coopérative d’antennes sur plusieurs sites, p. ex. dans les systèmes à plusieurs points coordonnés ou dans les systèmes coopératifs à "plusieurs entrées plusieurs sorties" [MIMO]
H04B 7/0404 - Systèmes de diversitéSystèmes à plusieurs antennes, c.-à-d. émission ou réception utilisant plusieurs antennes utilisant plusieurs antennes indépendantes espacées la station mobile comprenant plusieurs antennes, p. ex. pour mettre en œuvre une diversité en voie ascendante
