Logic may send information on cross-link interference reference signal (CLI-RS) resource and measurement configuration via an interface to a second base station, the CLI-RS resource and measurement configuration to comprise an identification of a communication resource within which to measure the CLI-RS. Logic may cause transmission of the CLI-RS. Logic may receive the CLI-RS measurement report based on measurement of the CLI-RS based on a definition for a CLI-RS measurement report from the second base station via the interface. Logic may decode information on CLI-RS resource and measurement configuration received via the interface from a first base station. Logic may measure the CLI-RS based on identification of the communication resource. Logic may generate the CLI-RS measurement report based on measurement of the CLI-RS. And logic may send the CLI-RS measurement report to the first base station.
Integrated circuit structures having sub-fin isolation, and methods of fabricating integrated circuit structures having sub-fin isolation, are described. For example, an integrated circuit structure includes a channel structure, and an oxide sub-fin structure over the channel structure, the oxide sub-fin structure including silicon and oxygen and aluminum.
H10D 30/43 - Transistors FET ayant des canaux à gaz de porteurs de charge de dimension nulle [0D], à une dimension [1D] ou à deux dimensions [2D] ayant des canaux à gaz de porteurs de charge à une dimension, p. ex. transistors FET à fil quantique ou transistors ayant des canaux à confinement quantique à une dimension
H10D 30/62 - Transistors à effet de champ à ailettes [FinFET]
H10D 84/03 - Fabrication ou traitement caractérisés par l'utilisation de technologies basées sur les matériaux utilisant une technologie du groupe IV, p. ex. technologie au silicium ou au carbure de silicium [SiC]
3.
METHODS AND ARRANGEMENTS FOR CROSS-LINK INTERFERENCE MITIGATION
Logic may decode information on cross-link interference (CLI) measurement and report configuration received via a first downlink (DL) control information (DCI) from a first base station to comprise an identification of a communication resource within which to measure a sounding reference signal (SRS) or other uplink transmission and a definition for a CLI measurement report. Logic may measure the SRS or other uplink transmission based on the identification of the communication resource. Logic may generate the CLI measurement report based on measurement of the SRS or other uplink transmission. Logic may send the CLI measurement report. Logic may generate a CLI measurement and report configuration to comprise an identification of a communication resource within which to measure a SRS and a definition for a CLI measurement report. And logic may send the CLI measurement and report configuration via a DCI transmission to a first user equipment.
In one embodiment, an apparatus includes a port to transmit and receive data over a link; and protocol stack circuitry to implement one or more layers of a load-store input/output (I/O)-based protocol (e.g., PCIe or CXL) across the link. The protocol stack circuitry constructs memory write request transaction layer packets (TLPs) for memory write transactions, wherein fields of the memory write request TLPs indicate a virtual channel (VC) other than VC0, that a completion is required in response to the memory write transaction, and a stream identifier associated with the memory write transaction. The memory write request TLP is transmitted over the link and a completion TLP is received over the link in response, indicating a completion for the memory write request TLP.
An example apparatus includes interface circuitry to obtain a power draw of a node, telemetry data of a core in the node, and an application characteristic of an application, and a programmable circuit to determine a first weight based on the telemetry data and the application characteristic, the first weight indicative of an impact the application has on a power consumption of the core, determine a second weight based on the application characteristic, the second weight indicative of an impact the application has on a power consumption of resources accessible by the core and by different cores of the node, determine a power estimate value for the application based on the first weight, the second weight, the power consumption of the core, and the power consumption of the resources, the power estimate value indicative of how much power of the power draw of the node that the application draws.
Disclosed herein are integrated circuit (IC) structures including backside vias, as well as related methods and devices. In some embodiments, an IC structure may include: a device layer, wherein the device layer includes a plurality of active devices; a first metallization layer over the device layer, wherein the first metallization layer includes a first conductive pathway in conductive contact with at least one of the active devices in the device layer; a second metallization layer under the device layer, wherein the second metallization layer includes a second conductive pathway; and a conductive via in the device layer, wherein the conductive via is in conductive contact with at least one of the active devices in the device layer and also in conductive contact with the second conductive pathway.
H10D 89/60 - Dispositifs intégrés comprenant des dispositions pour la protection électrique ou thermique, p. ex. circuits de protection contre les décharges électrostatiques [ESD].
An apparatus and system of supporting simultaneous transmission over multi-panel (STxMP) uplink (UL) transmissions are described. At least one downlink control information (DCI) is used to schedule STxMP UL transmission to multiple transmit-receive points (TRPs). The DCI indicates whether time domain (TD) repetition is to be applied, in addition to time domain and/or frequency domain resource location for different multiplexing schemes. Aperiodic-channel state information (A-CSI) or semi-persistent CSI (SP-CSI) multiplexing is multiplexed within one or more of the repetitions. One or more sounding reference signal (SRS) resource indication (SRI) fields in the DCI indicate the SRS resources to use for the transmission. Mechanisms of physical uplink control channel (PUCCH) resource configuration are described for STxMP operation.
H04W 72/1268 - Jumelage du trafic à la planification, p. ex. affectation planifiée ou multiplexage de flux de flux de données en liaison ascendante
H04B 7/06 - Systèmes de diversitéSystèmes à plusieurs antennes, c.-à-d. émission ou réception utilisant plusieurs antennes utilisant plusieurs antennes indépendantes espacées à la station d'émission
H04L 5/00 - Dispositions destinées à permettre l'usage multiple de la voie de transmission
H04W 72/0446 - Ressources du domaine temporel, p. ex. créneaux ou trames
H04W 72/0453 - Ressources du domaine fréquentiel, p. ex. porteuses dans des AMDF [FDMA]
H04W 72/231 - Canaux de commande ou signalisation pour la gestion des ressources dans le sens descendant de la liaison sans fil, c.-à-d. en direction du terminal les données de commande provenant des couches au-dessus de la couche physique, p. ex. signalisation RRC ou MAC-CE
8.
TECHNOLOGIES FOR PROVIDING ATTESTATION OF FUNCTION AS A SERVICE FLAVORS
Technologies for providing attestation for function as a service flavors include a compute device including circuitry configured to obtain function definition data indicative of a set of operations to be performed in a function and a set of hardware resources to be utilized by the function, execute a benchmark operation to produce benchmark data indicative of a measured performance of the function, and sign the function definition data and the benchmark data to produce function flavor data. The circuitry is also configured to provide the function flavor data to one or more other compute devices for validation that the function, when executed on the hardware resources, provides the measured performance and write, to a distributed ledger, the function flavor data.
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
G06F 9/455 - ÉmulationInterprétationSimulation de logiciel, p. ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
G06F 9/48 - Lancement de programmes Commutation de programmes, p. ex. par interruption
G06F 9/50 - Allocation de ressources, p. ex. de l'unité centrale de traitement [UCT]
G06F 16/27 - Réplication, distribution ou synchronisation de données entre bases de données ou dans un système de bases de données distribuéesArchitectures de systèmes de bases de données distribuées à cet effet
G06F 21/62 - Protection de l’accès à des données via une plate-forme, p. ex. par clés ou règles de contrôle de l’accès
H04L 9/00 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité
H04L 9/06 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p. ex. système DES
H04L 12/66 - Dispositions pour la connexion entre des réseaux ayant différents types de systèmes de commutation, p. ex. passerelles
H04L 41/12 - Découverte ou gestion des topologies de réseau
H04L 47/70 - Contrôle d'admissionAllocation des ressources
H04L 47/83 - Contrôle d'admissionAllocation des ressources basée sur la prédiction d'utilisation
H04L 67/52 - Services réseau spécialement adaptés à l'emplacement du terminal utilisateur
H04L 67/60 - Ordonnancement ou organisation du service des demandes d'application, p. ex. demandes de transmission de données d'application en utilisant l'analyse et l'optimisation des ressources réseau requises
9.
CINEMATIC SPACE-TIME VIEW SYNTHESIS FOR ENHANCED VIEWING EXPERIENCES IN COMPUTING ENVIRONMENTS
A mechanism is described for facilitating cinematic space-time view synthesis in computing environments according to one embodiment. A method of embodiments, as described herein, includes capturing, by one or more cameras, multiple images at multiple positions or multiple points in times, where the multiple images represent multiple views of an object or a scene, where the one or more cameras are coupled to one or more processors of a computing device. The method further includes synthesizing, by a neural network, the multiple images into a single image including a middle image of the multiple images and representing an intermediary view of the multiple views.
G06T 3/18 - Déformation d’images, p. ex. réarrangement de pixels individuellement
G06T 3/4007 - Changement d'échelle d’images complètes ou de parties d’image, p. ex. agrandissement ou rétrécissement basé sur l’interpolation, p. ex. interpolation bilinéaire
G06T 3/4046 - Changement d'échelle d’images complètes ou de parties d’image, p. ex. agrandissement ou rétrécissement utilisant des réseaux neuronaux
G06T 7/246 - Analyse du mouvement utilisant des procédés basés sur les caractéristiques, p. ex. le suivi des coins ou des segments
A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.
G06F 13/22 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le balayage successif, p. ex. l'appel sélectif
G06F 1/3287 - Économie d’énergie caractérisée par l'action entreprise par la mise hors tension d’une unité fonctionnelle individuelle dans un ordinateur
G06F 8/71 - Gestion de versions Gestion de configuration
G06F 9/46 - Dispositions pour la multiprogrammation
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
G06F 12/0806 - Systèmes de mémoire cache multi-utilisateurs, multiprocesseurs ou multitraitement
G06F 12/0808 - Systèmes de mémoire cache multi-utilisateurs, multiprocesseurs ou multitraitement avec moyen d'invalidation de mémoires cache
G06F 12/0813 - Systèmes de mémoire cache multi-utilisateurs, multiprocesseurs ou multitraitement avec configuration en réseau ou matrice
G06F 12/0815 - Protocoles de cohérence de mémoire cache
G06F 12/0831 - Protocoles de cohérence de mémoire cache à l’aide d’un schéma de bus, p. ex. avec moyen de contrôle ou de surveillance
G06F 13/42 - Protocole de transfert pour bus, p. ex. liaisonSynchronisation
H04L 9/06 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p. ex. système DES
Integrated circuit structures having a dielectric gate wall and a dielectric gate plug, and methods of fabricating integrated circuit structures having a dielectric gate wall and a dielectric gate plug, are described. For example, an integrated circuit structure includes a sub-fin having a portion protruding above a shallow trench isolation (STI) structure. A plurality of horizontally stacked nanowires is over the sub-fin. A gate dielectric material layer is over the protruding portion of the sub-fin, over the STI structure, and surrounding the horizontally stacked nanowires. A conductive gate layer is over the gate dielectric material layer. A conductive gate fill material is over the conductive gate layer. A dielectric gate wall is laterally spaced apart from the sub-fin and the plurality of horizontally stacked nanowires, the dielectric gate wall on the STI structure. A dielectric gate plug is on the dielectric gate wall.
H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
H10D 30/62 - Transistors à effet de champ à ailettes [FinFET]
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
12.
MULTI VERSION LIBRARY CELL HANDLING AND INTEGRATED CIRCUIT STRUCTURES FABRICATED THEREFROM
Multi version library cell handling and integrated circuit structures fabricated therefrom are described. In an example, an integrated circuit structure includes a plurality of gate lines parallel along a first direction of a substrate and having a pitch along a second direction orthogonal to the first direction. A first version of a cell type is over a first portion of the plurality of gate lines, the first version of the cell type including a first plurality of interconnect lines having a second pitch along the second direction, the second pitch less than the first pitch.
Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 23/367 - Refroidissement facilité par la forme du dispositif
14.
FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING ADDITIVE METAL GATES
Gate-all-around integrated circuit structures having additive metal gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack having a P-type conductive layer with a first portion surrounding the nanowires of the first vertical arrangement of horizontal nanowires and a second portion extending laterally beside and spaced apart from the first portion. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack having an N-type conductive layer with a first portion surrounding the nanowires of the second vertical arrangement of horizontal nanowires and a second portion adjacent to and in contact with the second portion of the P-type conductive layer.
H10D 84/85 - Transistors IGFET complémentaires, p. ex. CMOS
H10D 30/43 - Transistors FET ayant des canaux à gaz de porteurs de charge de dimension nulle [0D], à une dimension [1D] ou à deux dimensions [2D] ayant des canaux à gaz de porteurs de charge à une dimension, p. ex. transistors FET à fil quantique ou transistors ayant des canaux à confinement quantique à une dimension
H10D 84/03 - Fabrication ou traitement caractérisés par l'utilisation de technologies basées sur les matériaux utilisant une technologie du groupe IV, p. ex. technologie au silicium ou au carbure de silicium [SiC]
Through gate fin isolation for non-planar transistors in a microelectronic device, such as an integrated circuit (IC). In embodiments, ends of adjacent semiconductor fins are electrically isolated from each other with an isolation region that is self-aligned to gate electrodes of the semiconductor fins enabling higher transistor packing density and other benefits. In an embodiment, a single mask is employed to form a plurality of sacrificial placeholder stripes of a fixed pitch, a first subset of placeholder stripes is removed and isolation cuts made into the semiconductor fins in openings resulting from the first subset removal while a second subset of the placeholder stripes is replaced with gate electrodes.
H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
H10D 84/03 - Fabrication ou traitement caractérisés par l'utilisation de technologies basées sur les matériaux utilisant une technologie du groupe IV, p. ex. technologie au silicium ou au carbure de silicium [SiC]
H10D 84/85 - Transistors IGFET complémentaires, p. ex. CMOS
H10D 86/00 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre
A high-voltage transistor structure is provided that includes a self-aligned isolation feature between the gate and drain. Normally, the isolation feature is not self-aligned. The self-aligned isolation process can be integrated into standard CMOS process technology. In one example embodiment, the drain of the transistor structure is positioned one pitch away from the active gate, with an intervening dummy gate structure formed between the drain and active gate structure. The dummy gate structure is sacrificial in nature and can be utilized to create a self-aligned isolation recess, wherein the gate spacer effectively provides a template for etching the isolation recess. This self-aligned isolation forming process eliminates a number of the variation and dimensional constraints attendant non-aligned isolation forming techniques, which in turn allows for smaller footprint and tighter alignment so as to reduce device variation. The structure and forming techniques are compatible with both planar and non-planar transistor architectures.
H10D 30/60 - Transistors à effet de champ à grille isolée [IGFET]
H10D 30/62 - Transistors à effet de champ à ailettes [FinFET]
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 62/13 - Régions semi-conductrices connectées à des électrodes transportant le courant à redresser, amplifier ou commuter, p. ex. régions de source ou de drain
Some aspects of the present disclosure relate to a non-transitory computer-readable medium storing instructions that, when executed by one or more processing circuitries, cause the one or more processing circuitries to perform a method for a controller of a shared device, the method comprising obtaining (130), from a requester device connected to the shared device via an interconnect fabric, a request for using a functionality of the shared device, and providing (140) access to the functionality of the shared device using a share of performance of the shared device defined by a data structure mapping one or more requester devices to one or more shares of performance of the shared device for the requester device.
Integrated circuit structures having front-side-guided backside source or drain contacts are described. In an example, an integrated circuit structure includes first, second and third pluralities of horizontally stacked nanowires or fins, and first, second and third gate stacks. A first epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, and has a backside contact structure thereon. A second epitaxial source or drain structure is between the second plurality of horizontally stacked nanowires or fin and the third plurality of horizontally stacked nanowires or fin, and has a backside dielectric structure thereon, the backside dielectric structure laterally spaced apart from the backside contact structure. A dielectric gate cut plug is in contact with an end of the backside dielectric structure and with an end of the backside contact structure.
H10D 86/60 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT] les transistors TFT étant dans des matrices actives
H10D 86/40 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre caractérisés par de multiples transistors en couches minces [TFT]
19.
OPTIMIZING DIRTY PAGE COPYING FOR A WORKLOAD RECEIVED DURING LIVE MIGRATION THAT MAKES USE OF HARDWARE ACCELERATOR VIRTUALIZATION
Embodiments described herein are generally directed to an improved workload submission handling strategy for workloads received during live migration and targeting VFs of a hardware accelerator. In an example, while performing a live migration of a source VM running on a source host to a destination VM of a destination host, a new workload targeting a VF of a first HW accelerator of the source host is identified by a HW status manager of the source host by trapping the workload submission channel. Based on a nature of the new workload, the HW status manager determines whether to transfer the new workload to the destination host. Responsive to an affirmative determination, the HW status manager causes the new workload to be submitted to a VF of a second HW accelerator of the destination host by incorporating information regarding the new workload within a migration stream associated with the live migration.
G06F 9/455 - ÉmulationInterprétationSimulation de logiciel, p. ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
20.
METHODS AND ARRANGEMENTS FOR APPLICATION SERVICE DISCOVERY
Logic to generate an extremely high throughput (EHT) physical layer protocol data unit (PPDU) comprising a medium access control (MAC) management frame, the MAC management frame comprising a QoS management field. the QoS management field comprising at least one bit value to indicate quality of service (QOS) management capability associated with links associated with more than one frequency bands. Logic to cause the transmission of the EHT PPDU. And logic to receive and decode the EHT PPDU.
Systems, methods, and apparatuses can include transmission-side protocol stack circuitry comprising first cyclic redundancy check (CRC) circuitry to determine first CRC code for a first set of information and to determine second CRC code for a second set of information; and Flit encoding circuitry to encode a first portion of a Flit with the first set of information and the first CRC code, the Flit encoding circuitry to encode a second portion of the Flit with the second set of information and the second CRC code. Receiver-side protocol stack circuitry can include a low-latency path comprising first CRC check circuitry to perform a CRC check on a first portion of a received Flit. Receiver-side protocol stack circuitry can include a non-low-latency path comprising forward error correction (FEC) decoder circuitry to perform FEC on received Flits, and second CRC check circuitry to perform CRC check on received Flits that pass FEC.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue
22.
TRACKING CRC (CYCLIC REDUNDANCY CHECK) ERRORS PER MEMORY WRITE TRANSACTION
A memory device includes CRC (cyclic redundance check) circuitry to detect CRC errors in write transactions. The CRC circuitry computes CRC for a data block to compare with CRC bits that were computed and sent by the memory controller. The memory device records the pass/fail status of write transactions in an error status register readable by the memory controller. The memory device can trigger the ALERT_n signal in response to an error.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
G06F 11/07 - Réaction à l'apparition d'un défaut, p. ex. tolérance de certains défauts
Examples described herein relate to a network interface device. In some examples, the network interface device is configured to determine routing information for a packet by: access a content addressable memory (CAM) to retrieve an Internet Protocol (IP) subnetwork identifier based on a portion of a destination address of the packet; determine a starting memory address of a subnetwork in a memory based on the subnetwork identifier; determine an offset from the starting memory address based on a second portion of the destination address; access the memory to retrieve the routing information for the packet based on the offset and the starting memory address.
Integrated circuit structures having backside power delivery are described. In an example, an integrated circuit structure includes a device layer within a cell boundary, the device layer having a front side and a backside, and the device layer including a source or drain structure. A source or drain trench contact structure is on the front side of the device layer. The source or drain trench contact structure is coupled to the source or drain structure. A metal layer is on the backside of the device layer. A via structure couples the metal layer to the source or drain trench contact structure. The via structure is overlapping and parallel with a cell row boundary of the cell boundary.
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
Integrated circuit structures having backside self-aligned penetrating conductive source or drain contacts, and methods of fabricating integrated circuit structures having backside self-aligned penetrating conductive source or drain contacts, are described. For example, an integrated circuit structure includes a sub-fin structure over a vertical stack of horizontal nanowires. An epitaxial source or drain structure is laterally adjacent and coupled to the vertical stack of horizontal nanowires. A conductive source or drain contact is laterally adjacent to the sub-fin structure and extends into the epitaxial source or drain structure. The conductive source or drain contact does not extend around the epitaxial source or drain structure.
H10D 84/03 - Fabrication ou traitement caractérisés par l'utilisation de technologies basées sur les matériaux utilisant une technologie du groupe IV, p. ex. technologie au silicium ou au carbure de silicium [SiC]
H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
For example, a first device may calibrate a reference channel estimation based on a plurality of first channel estimation measurements, the plurality of first channel estimation measurements corresponding to first PPDUs received from a second device over a wireless channel, wherein two consecutive channel estimation measurements of the plurality of first channel estimation measurements are separated by no more than a first time interval; and determine a plurality of second channel estimation measurements for detection of a change in an environment of the wireless channel based on the reference channel estimation, wherein the plurality of second channel estimation measurements corresponds to a plurality of second PPDUs received from the second device over the wireless channel, wherein two consecutive channel estimation measurements of the plurality of second channel estimation measurements are separated by at least a second time interval, the second time interval is longer than the first time interval.
Some challenges to using analog compute-in-memory circuits for machine learning hardware relate to the overhead and non-idealities associated with data converters at the input and output of the analog compute-in-memory circuits. To address at least some of these challenges, a digital-to-analog converter having binary-weighted resistances can be used to drive the analog compute-in-memory circuits. The resulting digital-to-analog converter is sparsity-aware with low average power consumption. A calibration engine can perform analog tuning and/or digital post-correction to mitigate the non-idealities of the digital-to-analog converter.
Systems, apparatus, articles of manufacture, and methods are disclosed to configure content-addressable memory resources. An example apparatus includes interface circuitry to access parameters to be used to configure content-addressable memory (CAM) of a compute device to implement a packet flow table, machine-readable instructions, and at least one programmable circuit to be programmed by the machine-readable instructions. The at least one programmable circuit is to convert the parameters into a hardware representation of the packet flow table, generate, based on the hardware representation, candidate configurations of two or more CAM slices of the compute device that satisfy the parameters, select one of the candidate configurations of the two or more CAM slices to implement the packet flow table based on respective performance characteristics of the candidate configurations, and configure the two or more CAM slices based on the selected one of the candidate configurations.
H04L 45/745 - Recherche de table d'adressesFiltrage d'adresses
H04L 41/0816 - Réglages de configuration caractérisés par les conditions déclenchant un changement de paramètres la condition étant une adaptation, p. ex. en réponse aux événements dans le réseau
H04L 45/655 - Interaction entre les entités de calcul de routes et les entités de transmission, p. ex. pour la détermination de la route ou pour la mise à jour des tables de flux
29.
COLLISION HANDLING IN AND HARQ-ACK CODEBOOK GENERATION FOR SIDELINK CARRIER AGGREGATION
An apparatus and system of supporting sidelink carrier aggregation are described. Mechanisms for Type 1 and Type 2 sidelink hybrid automatic repeat request-acknowledgement (HARQ-ACK) codebook generation for carrier aggregation are described. A sidelink carrier index is included in downlink control information (DCI) format 3 0 received by a user equipment. The sidelink carrier index indicates the sidelink carrier used for resource allocation of a physical sidelink shared channel (PSSCH) and physical sidelink control channel (PSCCH). The HARQ-ACK for a sidelink serving cell is generated and the sidelink HARQ-ACK information bits are concatenated in accordance with ascending order of sidelink serving cell index. Collision handling and prioritization among sidelink transmissions and reception, as well as uplink transmissions during sidelink carrier aggregation are described.
H04L 1/1812 - Protocoles hybridesDemande de retransmission automatique hybride [HARQ]
H04W 72/1273 - Jumelage du trafic à la planification, p. ex. affectation planifiée ou multiplexage de flux de flux de données en liaison descendante
H04W 72/40 - Gestion des ressources pour la communication en mode direct, p. ex. D2D ou liaison secondaire
H04W 72/566 - Critères d’affectation ou de planification des ressources sans fil sur la base de critères de priorité de l’information, de la source d’information ou du destinataire
H04W 92/18 - Interfaces entre des dispositifs hiérarchiquement similaires entre des dispositifs terminaux
30.
PHYSICAL DOWNLINK CONTROL CHANNEL (PDCCH) MONITORING CAPABILITY FOR MULTI-CELL SCHEDULING
An apparatus of a New Radio (NR) Node B (gNB), a method, and a storage medium. The apparatus is to identify a downlink control information (DCI) size budget related to a DCI format for multi-cell scheduling; generate a physical downlink control channel (PDCCH) transmission to schedule, in a plurality of cells, shared channel (SCH) transmissions, the PDCCH transmission including an indication of the DCI size budget; and send the PDCCH transmission for transmission to a User Equipment (UE) within a scheduling cell of the plurality of cells.
H04W 72/232 - Canaux de commande ou signalisation pour la gestion des ressources dans le sens descendant de la liaison sans fil, c.-à-d. en direction du terminal les données de commande provenant de la couche physique, p. ex. signalisation DCI
H04W 72/1263 - Jumelage du trafic à la planification, p. ex. affectation planifiée ou multiplexage de flux
Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate including a dielectric material having a first surface and an opposing second surface, a first material on at least a portion of the second surface, and a second material on at least a portion of the first material, wherein the second material has a different material composition than the first material.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/13 - Supports, p. ex. substrats isolants non amovibles caractérisés par leur forme
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides
32.
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING INSULATOR FIN ON INSULATOR SUBSTRATE
Gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, and methods of fabricating gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, are described. For example, an integrated circuit structure includes an insulator fin on an insulator substrate. A vertical arrangement of horizontal semiconductor nanowires is over the insulator fin. A gate stack surrounds a channel region of the vertical arrangement of horizontal semiconductor nanowires, and the gate stack is overlying the insulator fin. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires and at first and second ends of the insulator fin.
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
H10D 30/62 - Transistors à effet de champ à ailettes [FinFET]
H10D 30/69 - Transistors IGFET ayant des isolateurs de grille à piégeage de charges, p. ex. transistors MNOS
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 62/13 - Régions semi-conductrices connectées à des électrodes transportant le courant à redresser, amplifier ou commuter, p. ex. régions de source ou de drain
H10D 62/17 - Régions semi-conductrices connectées à des électrodes ne transportant pas de courant à redresser, amplifier ou commuter, p. ex. régions de canal
H10D 62/822 - Hétérojonctions comprenant uniquement des hétérojonctions de matériaux du groupe IV, p. ex. des hétérojonctions Si/Ge
H10D 84/03 - Fabrication ou traitement caractérisés par l'utilisation de technologies basées sur les matériaux utilisant une technologie du groupe IV, p. ex. technologie au silicium ou au carbure de silicium [SiC]
33.
INTEGRATED CIRCUIT STRUCTURES WITH BACKSIDE GATE PARTIAL CUT OR TRENCH CONTACT PARTIAL CUT
Integrated circuit structures having backside gate partial cut or backside trench contact partial cut and/or spit epitaxial structure are described. For example, an integrated circuit structure includes a first sub-fin structure over a first stack of nanowires. A second sub-fin structure is over a second stack of nanowires. A first portion of a gate electrode is around the first stack of nanowires, a second portion of the gate electrode is around the second stack of nanowires, and a third portion of the gate electrode bridges the first and second portions of the gate electrode. A dielectric structure is between the first portion of the gate electrode and the second portion of the gate electrode, the dielectric structure over the third portion of the gate electrode. The dielectric structure is continuous along the first and second portions of the gate electrode and the first and second sub-fin structures.
Systems and methods for a skin segmentation framework that leverages facial crop as prior knowledge. In particular, the system employs a cross-attention mechanism to transfer features extracted from the face region to guide the main segmentation network. By utilizing the face as a reference point for skin tone and lighting conditions, the model learns to adapt to diverse environmental scenarios and varying skin appearances. This approach significantly enhances skin segmentation accuracy and robustness compared to traditional color-based and deep learning methods, particularly in challenging lighting conditions. Any changes to pixels representing skin (e.g., white balance, auto exposure) are consistent with the changes in the face crop, and thus skin segmentation colors can be updated to reflect the changes. The model results in consistent and robust skin pixel detection across diverse lighting conditions and image processing variations, significantly enhancing the performance and reliability of applications that depend on accurate skin segmentation.
G06V 10/26 - Segmentation de formes dans le champ d’imageDécoupage ou fusion d’éléments d’image visant à établir la région de motif, p. ex. techniques de regroupementDétection d’occlusion
G06V 10/75 - Organisation de procédés de l’appariement, p. ex. comparaisons simultanées ou séquentielles des caractéristiques d’images ou de vidéosApproches-approximative-fine, p. ex. approches multi-échellesAppariement de motifs d’image ou de vidéoMesures de proximité dans les espaces de caractéristiques utilisant l’analyse de contexteSélection des dictionnaires
G06V 10/82 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant les réseaux neuronaux
G06V 40/16 - Visages humains, p. ex. parties du visage, croquis ou expressions
35.
LOW LATENCY AND DETERMINISTIC NODE FAILURE DETECTION
Embodiments described herein are generally directed to a flexible mechanism for performing low latency and deterministic node failure detection. In an example, an agent, running on a monitor node of a distributed system, receives from a process, running within a user space of an operating system (OS) of the monitor node, a request to send a probe to a monitored node of the distributed system. The agent is interposed between a networking stack of a kernel of the OS and a transmission media coupling the nodes in communication. The agent causes the probe to be transmitted to the monitored node via the transmission media at a time specified by the request utilizing a time-based packet scheduling feature of a network interface associated with the monitor node. When a time period elapses prior to receipt of a response to the probe, the agent notifies the process of a failure relating to the monitored node.
H04L 43/0817 - Surveillance ou test en fonction de métriques spécifiques, p. ex. la qualité du service [QoS], la consommation d’énergie ou les paramètres environnementaux en vérifiant la disponibilité en vérifiant le fonctionnement
H04L 43/106 - Surveillance active, p. ex. battement de cœur, utilitaire Ping ou trace-route en utilisant des informations liées au temps dans des paquets, p. ex. en ajoutant des horodatages
36.
METHODS AND APPARATUS TO INCREASE NUMBER OF DIMMs PER SOCKET AND/OR ENHANCE COOLING OF DIMMs
Systems, apparatus, articles of manufacture, and methods to increase number of DIMMs per socket and/or enhance cooling of DIMMs are disclosed. An example apparatus includes a circuit board including a first end, a second end opposite the first end, a first lateral edge, and a second lateral edge opposite the first lateral edge. The example apparatus includes a first bank of memory slots to extend between the first and second ends of the circuit board. The first bank of memory slots is a first distance from the first end. The example apparatus also includes a second bank of memory slots to extend between the first and second ends of the circuit board. The second bank of memory slots is a second distance from the first end. The second distance is greater than the first distance.
Integrated circuit structures having fin isolation regions bound by gate cuts are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires over a first sub-fin. A gate structure is over the vertical stack of horizontal nanowires and on the first sub-fin. A dielectric structure is laterally spaced apart from the gate structure. The dielectric structure is not over a channel structure but is on a second sub-fin. A gate cut is between the gate structure and the dielectric structure.
H10D 30/43 - Transistors FET ayant des canaux à gaz de porteurs de charge de dimension nulle [0D], à une dimension [1D] ou à deux dimensions [2D] ayant des canaux à gaz de porteurs de charge à une dimension, p. ex. transistors FET à fil quantique ou transistors ayant des canaux à confinement quantique à une dimension
H10D 30/62 - Transistors à effet de champ à ailettes [FinFET]
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 84/03 - Fabrication ou traitement caractérisés par l'utilisation de technologies basées sur les matériaux utilisant une technologie du groupe IV, p. ex. technologie au silicium ou au carbure de silicium [SiC]
H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
38.
CONTACT RESISTANCE REDUCTION IN TRANSISTOR DEVICES WITH METALLIZATION ON BOTH SIDES
Embodiments disclosed herein include transistor devices and methods of making such devices. In an embodiment, the transistor device comprises a stack of semiconductor channels with a first source/drain region on a first end of the semiconductor channels and a second source/drain region on a second end of the semiconductor channels. In an embodiment, the first source/drain region and the second source/drain region have a top surface and a bottom surface. In an embodiment, the transistor device further comprises a first source/drain contact electrically coupled to the top surface of the first source/drain region, and a second source/drain contact electrically coupled to the bottom surface of the second source/drain region. In an embodiment, the second source/drain contact is separated from the second source/drain region by an interfacial layer.
Methods and apparatus to implement always-on context sensor hubs for processing multiple different types of data inputs are disclosed. An examples apparatus includes a first processor core to implement a host controller, and a second processor core to implement an offload engine. The host controller includes first logic to process sensor data associated with an electronic device when the electronic device is in a low power mode. The host controller is to offload a computational task associated with the sensor data to the offload engine. The offload engine includes second logic to execute the computational task.
In accordance with disclosed embodiments, there is an antenna package using a ball attach array to connect an antenna and base substrates of the package. One example is an RF module package including an RF antenna package having a stack material in between a top and a bottom antenna layer to form multiple antenna plane surfaces, a base package having alternating patterned conductive and dielectric layers to form routing through the base package, and a bond between a bottom surface of the antenna package and to a top surface of the base package.
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/498 - Connexions électriques sur des substrats isolants
Generally this disclosure describes a video communication system that replaces actual live images of the participating users with animated avatars. A method may include selecting an avatar; initiating communication; detecting a user input; identifying the user input; identifying an animation command based on the user input; generating avatar parameters; and transmitting at least one of the animation command and the avatar parameters.
G06F 3/0482 - Interaction avec des listes d’éléments sélectionnables, p. ex. des menus
G06F 3/04883 - Techniques d’interaction fondées sur les interfaces utilisateur graphiques [GUI] utilisant des caractéristiques spécifiques fournies par le périphérique d’entrée, p. ex. des fonctions commandées par la rotation d’une souris à deux capteurs, ou par la nature du périphérique d’entrée, p. ex. des gestes en fonction de la pression exercée enregistrée par une tablette numérique utilisant un écran tactile ou une tablette numérique, p. ex. entrée de commandes par des tracés gestuels pour l’entrée de données par calligraphie, p. ex. sous forme de gestes ou de texte
G06T 13/40 - Animation tridimensionnelle [3D] de personnages, p. ex. d’êtres humains, d’animaux ou d’êtres virtuels
G06V 40/16 - Visages humains, p. ex. parties du visage, croquis ou expressions
G10L 21/003 - Changement de la qualité de la voix, p. ex. de la hauteur tonale ou des formants
G10L 21/013 - Adaptation à la hauteur tonale ciblée
H04M 1/72439 - Interfaces utilisateur spécialement adaptées aux téléphones sans fil ou mobiles avec des moyens de soutien local des applications accroissant la fonctionnalité avec des moyens interactifs de gestion interne des messages pour la messagerie visuelle ou vidéo
Various embodiments herein provide techniques for sidelink (SL) communication on unlicensed spectrum. For example, embodiments provide techniques for a physical sidelink feedback channel (PSFCH) and/or a SL synchronization signal block (S-SSB), such as techniques related to a listen-before-talk (LBT) procedure and/or occupied channel bandwidth (OCB) requirements. Other embodiments may be described and claimed.
Systems, apparatus, articles of manufacture, and methods to provide interface data compression for hybrid data processing architectures are disclosed. An example apparatus disclosed herein includes communicates with a device to determine interface compression capability information, The disclosed example apparatus also determines, based on the interface compression capability information, whether a host and the device implement one or more interface compression algorithms in common, the one or more interface compression algorithms to provide data compression over a bus interface between a host and the device. The disclosed example apparatus further configures, in response to a determination that the host and the device implement one or more interface compression algorithms in common, a first interface compression algorithm of the one or more interface compression algorithms to operate on the host and on the device to compress data communicated over the bus interface.
System and techniques to map a workspace for a robotic device are described herein. The robotic device has a movable portion with a sensor that is used to capture readings from part of the workspace. These readings are used to map a portion of the workspace and then to plot a new position of the movable portion to get readings for another part of the workspace. As the technique iterates, the robotic device is able to safely and efficiently map the entirety of the workspace.
In embodiments herein, circuit components are embedded within a core layer of a substrate. The circuit components are vertically oriented within a cavity or hole of the core layer of the substrate, e.g., with conductive contacts on an edge of the component that is substantially orthogonal to a plane of the core layer. The edge that is substantially orthogonal to a plane of the core layer may be the longest edge of the component.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/498 - Connexions électriques sur des substrats isolants
46.
RATELESS CODING AND FEEDBACK SCHEME FOR COMMUNICATION SYSTEMS
A device can include memory to store source packets and coded packets. The device can include processing circuitry to perform a first coding phase and a second coding phase. In the first coding phase, the processing circuitry can combine the source packets to generate a first set of coded packets, where a coded packet can be defined according to a degree, the degree being a count of the source packets used to generate the coded packet. In the second coding phase, the same source packets into a second set of coded packets, such that a total number of coded packets generated in the first encoding phase and in the second encoding phase is greater than a total number of source packets. In another aspects, broadcasters can receive feedback beacons and modify broadcast accordingly.
A system includes a first chiplet that includes at least one demodulator for demodulating at least one received signal from a receiver to generate hard bits and soft information from the received signal and a second chiplet coupled to exchange information with the first chiplet. The second chiplet includes at least one correlator to detect a symbol pattern indicating frame boundaries of frames having a known frame symbol period length in an acquisition state and transitioning the first and second chiplets to a connected state in response to a threshold number of successful frame boundary detections. The at least one correlator uses soft bit representations to correlate and deduce the frame boundaries in a windowed mode using the known frame length and previous frame boundary information while in the connected state and transitions the first and second chiplets out of the connected state and back to the acquisition state in response to at least one unsuccessful frame boundary detection.
An integrated circuit device includes (i) a first interconnect feature extending within a first dielectric material, and (ii) a second interconnect feature extending within the first dielectric material, and landing on the first interconnect feature. The integrated circuit device further includes a layer having a first section and a second section, wherein the layer includes a second dielectric material that is compositionally different from the first dielectric material. An opening between the first section and the second section is above, and vertically aligned to, the first interconnect feature. The second interconnect feature extends through the opening. In an example, each of the first section and the second section is vertically separated from the first interconnect feature by at least 2 nanometers (nm). In an example, a dielectric constant of the second dielectric material is higher than a dielectric constant of the first dielectric material by at least 5%.
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
49.
COHERENT RECEPTION OF ON/OFF KEYING AND PULSE POSITION MODULATIONS
An optical receiver implements a method to provide a digital output of a received on-off keyed optical signal. The method includes receiving an on-off keyed optical signal via a coherent optical front-end receiver utilizing a locally mixed laser LO for a reference signal to perform quadrature detection of the optical signal to generate an electrical signal, performing symbol/slot timing recovery on the electrical signal using a timing error detector, performing carrier frequency and phase recovery on a symbol/slot signal to generate a frequency and phase recovered signal, and demodulating the frequency and phase recovered signal via a demodulation circuit to provide a digital output representative of the received on-off keyed optical signal.
Integrated circuit (IC) devices with non-planar transistors may be formed from a material stack having a sacrificial layer between one or more mask material layers and a top surface of a channel material. An IC device may include a non-planar transistor with a gate spacer layer having portions with a same or consistent composition, both over an upper surface of the channel material and under a lower surface of the channel material. The gate spacer layer may have a different composition than a gate endcap spacer layer.
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
A system of a vehicle having access to a network, includes a communication controller to interface with at least one of: a mobile device, the vehicle, and sensors coupled to the vehicle; and a vehicle controller to perform a responsive operation at the vehicle; where the system is to: identify a target vehicle operating in proximity of the vehicle; determine a trust metric, the trust metric indicating a measurement of risk to operate the vehicle in the proximity of the target vehicle; and initiate the responsive operation at the vehicle, using the vehicle controller, based on the trust metric.
B60W 60/00 - Systèmes d’aide à la conduite spécialement adaptés aux véhicules routiers autonomes
B60W 30/09 - Entreprenant une action automatiquement pour éviter la collision, p. ex. en freinant ou tournant
B60W 40/08 - Calcul ou estimation des paramètres de fonctionnement pour les systèmes d'aide à la conduite de véhicules routiers qui ne sont pas liés à la commande d'un sous-ensemble particulier liés aux conducteurs ou aux passagers
B60W 50/14 - Moyens d'information du conducteur, pour l'avertir ou provoquer son intervention
G06V 20/58 - Reconnaissance d’objets en mouvement ou d’obstacles, p. ex. véhicules ou piétonsReconnaissance des objets de la circulation, p. ex. signalisation routière, feux de signalisation ou routes
52.
ENCAPSULATION TECHNIQUES FOR COMPONENTS EMBEDDED IN A CORE LAYER OF A PACKAGE SUBSTRATE
In embodiments herein, a circuit component (e.g., a deep trench capacitor) is embedded within a core layer of a substrate. The circuit component may be encapsulated by multiple (e.g., two) layers of dielectrics or by a polymer material.
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 23/498 - Connexions électriques sur des substrats isolants
A method comprising forming a first layer, forming a second layer over the first layer, and applying an etch material to concurrently form a first interconnect line and a second interconnect line in the first layer and side surfaces of a first via and a second via in the second layer, wherein a side surface of the first via is seamless with a side surface of the first interconnect line, wherein a side surface of the second via is seamless with a side surface of the second interconnect line, wherein the first via is adjacent to the second via.
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
54.
VAPOR COMPRESSION ASSISTED LIQUID COOLING SYSTEM FOR ELECTRONIC COMPONENTS
Disclosed herein are devices, methods, and systems for cooling an electronic component. The cooling device includes a liquid cooling loop with a heat exchanger, wherein the liquid cooling loop thermally conductively connects to the electronic component. The cooling device also includes a vapor compression cooling loop with a compressor and an expansion nozzle. The cooling device also includes an intermediate heat exchanger between the liquid cooling loop and the vapor compression cooling loop for exchanging heat between the liquid cooling loop and the vapor compression cooling loop. The cooling device also includes a controller configured to selectively activate the vapor compression cooling loop based on a power consumption of the electronic component.
A device may include a plurality of carriers, wherein each carrier includes a plurality of communication processors, each communication processor disposed over or in a respective carrier of the plurality of carriers and configured to provide a wireless broadcasting communication channel, and a plurality of antennas, each antenna disposed on or in a respective carrier and coupled to a respective communication processor, wherein each antenna extends into a corner of the respective carrier, and wherein the antennas of each pair of adjacent carriers are positioned at a distance from each other at less than about 1 wavelength corresponding to the lowest operating frequency.
Disclosed herein are devices, methods, and systems for encoding data packets for transmitting over at least two transmission paths, which may include a sub-6 GHz link and multiple high frequency band links. The system may divide an upper layer packet into a predefined number of equal-sized segments, encode the segments with linear packet network coding to generate a set of network coded packets, allocate for transmission to a destination node over two or more transmission paths subsets of the set of network coded packets to corresponding ones of the two or more transmission paths, and transmit to the destination node each subset of the subsets of network coded packets on its corresponding transmission path of the two or more transmission paths. The linear packet network coding may be optimized using a recursive method to allocate packets using decoding success probability and/or through a steepest decent or equalized distribution algorithm
A server includes a memory on which a map is stored, wherein the map represents locations of a plurality of mobile units; and a processor, configured to generate an emergency response plan based on sensor data and the map, wherein the emergency response plan comprises actions to be taken by a plurality of robots within a vicinity of the mobile units; and instruct a transceiver to send a signal representing the emergency response plan.
G05D 1/617 - Sécurité ou protection, p. ex. définition de zones de protection autour d’obstacles ou évitement de zones dangereuses
G05D 101/00 - Détails des architectures logicielles ou matérielles utilisées pour la commande de la position
G05D 105/55 - Applications spécifiques des véhicules commandés pour les opérations d’urgence, p. ex. recherche et sauvetage, interventions en cas d’accidents de la circulation ou lutte contre les incendies
G08B 7/06 - Systèmes de signalisation selon plus d'un des groupes Systèmes d'appel de personnes selon plus d'un des groupes utilisant une transmission électrique
58.
RECONSTITUTED PASSIVE WITH MECHANICAL SUPPORT STRUCTURES
Embodiments disclosed herein include components that include passive electrical devices with a thickness augmentation. In an embodiment, such an apparatus comprises a substrate with a first material composition, and a liner on a sidewall of the substrate. In an embodiment, a layer is on the substrate, where the layer has a second material composition that is different than the first material composition. In an embodiment, the layer directly contacts at least a portion of a surface of the substrate.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/13 - Supports, p. ex. substrats isolants non amovibles caractérisés par leur forme
Assemblies and methods of manufacturing assemblies comprising semiconductor chips and package substrates wherein the semiconductor chips are operably coupled to the package substrate through a solderless direct metal-to-metal bond region. The solderless direct metal-to-metal bond region also comprises a dielectric polymer. Package substrates can comprise interconnect bridges and the semiconductor chips can be operably coupled to the interconnect bridges and can also be operably coupled to each other through the interconnect bridges.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
60.
PATTERNED MOLD UNDERFILL (MUF) FILMS FOR DEEP TRENCH FILLING
Embodiments disclosed herein include components that are embedded in the core of a package substrate. In an embodiment, such an apparatus comprises a substrate with a cavity through a thickness of the substrate. In an embodiment, a component is in the cavity, and a first layer is in the cavity. In an embodiment the first layer is a dielectric material. In an embodiment, a second layer is in the cavity, and the second layer is a dielectric material that is a different material than the second layer.
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides
61.
PASSIVE COMPONENT ASSEMBLY FOR THICKNESS MODIFICATION TO MATCH CORE THICKNESS
Embodiments disclosed herein include passive electrical components with thickness modifications. In an embodiment, such an apparatus may comprise a first substrate with a first material composition, where the first substrate comprises a passive electrical device. In an embodiment, a second substrate is coupled to the first substrate, where the second substrate has a second material composition. In an embodiment, a layer is over a surface of the second substrate opposite from the first substrate, and the layer is electrically insulating.
Pedestals for semiconductors embedded in package substrates and related methods are disclosed. An example package substrate for an integrated circuit package disclosed herein includes core having a first surface, a second surface, and a cavity formed in the first surface, a semiconductor component disposed in the cavity, and a pedestal disposed in the cavity, the pedestal having a third surface coupled to the semiconductor component, and a fourth surface adjacent to the first surface, the pedestal dimensioned such that a first thickness of the pedestal and semiconductor is substantially equal to a second thickness of the core.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
63.
MICROELECTRONIC ASSEMBLIES INCLUDING CAVITY-LESS ENCAPSULATED DIES
Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a substrate having a material and conductive pathways through the material, wherein the material includes an organic dielectric material; and a microelectronic component having a first surface and an opposing second surface, wherein the first surface of the microelectronic component is electrically coupled to the conductive pathways in the material by interconnects, wherein the interconnects include solder and are surrounded by a capillary underfill material, and wherein the microelectronic component and the capillary underfill material are surrounded by the material of the substrate.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/10 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs ayant des conteneurs séparés
64.
PAD DESIGN FOR EMBEDDED INTERCONNECT BRIDGES IN PACKAGE SUBSTRATES
Semiconductor chip package substrates having interconnect bridges, assemblies including these semiconductor chip package substrates, and methods of manufacturing interconnect-bridge-containing semiconductor package chip substrates are provided. The interconnect bridges can include through-bridge vias that are electrically coupled to the semiconductor package substrate. The embedded bridges can be aligned to fiducials within the semiconductor package substrate.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
A method comprising receiving, at a computing system, a request for design rules of an integrated circuit technology node; and providing, by the computing system, a plurality of design rule entries for display in a tabular format by an interface, the plurality of design rule entries selected based on the request, a design rule entry of the plurality of design rule entries corresponding to a design rule of the plurality of design rules, the design rule entry comprising a first cell designated for a label of the design rule, a second cell designated for a description of the design rule, and a third cell designated for a numerical dimension for the design rule.
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
G06F 30/392 - Conception de plans ou d’agencements, p. ex. partitionnement ou positionnement
G06F 119/18 - Analyse de fabricabilité ou optimisation de fabricabilité
G06F 119/20 - Conception de réutilisation, analyse de réutilisabilité ou optimisation de réutilisabilité
66.
METHODS AND APPARATUS TO EMBED SEMICONDUCTOR DEVICES IN CORES OF PACKAGE SUBSTRATES
Systems, apparatus, articles of manufacture, and methods to embed semiconductor devices in cores of package substrates are disclosed. An example package substrate includes a core having a first surface and a second surface. The core includes a cavity extending between the first and second surfaces. The example package substrate further includes a semiconductor die within the cavity; a pedestal within the cavity; and an adhesive within the cavity. The adhesive surrounds the semiconductor die and the pedestal. A material of the pedestal different from a material of the adhesive.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
67.
METHODS AND APPARATUS TO FACILITATE SEMICONDUCTOR DEVICE ALIGNMENT IN AN INTEGRATED CIRCUIT PACKAGE
An apparatus includes a package substrate comprising a core having a first surface along a first plane and a second surface along a second plane, a semiconductor device disposed within an opening in the core, the semiconductor device having a third surface along a third plane and a fourth surface along a fourth plane, the third plane substantially parallel to the first plane, a first dielectric material disposed on the first surface of the core, the first dielectric material extends into the opening to fill a first gap between a wall of the opening and a lateral surface of the semiconductor device, and a second dielectric material disposed on the second surface of the core, the second dielectric material extends into the opening to fill a second gap between the second plane and the fourth plane.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 21/52 - Montage des corps semi-conducteurs dans les conteneurs
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
68.
GATE-ALL-AROUND DEVICES WITH DIFFERENT GATE LENGTHS
Techniques are provided herein to form semiconductor devices having different gate lengths on the same die. In an example, any number of first semiconductor devices includes first gate structures around first semiconductor regions and any number of second semiconductor devices include second gate structures around second semiconductor regions. The first gate structures have a first gate length around the first semiconductor regions and the second gate structures have a second gate length around the second semiconductor regions with the second gate length being greater than the first gate length. An upper thickness of each the first and second gate structures may be the same, despite the gate length diversity. The first semiconductor devices include first inner spacer structures around ends of the first semiconductor regions that have a greater lateral thickness compared to second inner spacer structures around ends of the second semiconductor regions of the second semiconductor devices.
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
An apparatus includes a substrate core, which has a first height between a first surface and a second surface opposite the first surface. A die is within the substrate core. The die may include a deep trench capacitor. The die has a second height between a first side of the die and a second side opposite the first side. The first height is greater than the second height. A plurality of conductive vias extend from a plurality of conductive contacts at the first side of the die to the first surface of the substrate core. A material comprising a dielectric is disposed over the die and encapsulates the plurality of conductive vias. In some embodiments, a bond film is in contact with the second side of the die.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
Solder materials, solder balls, and solder features, and microelectronic devices and systems deploying the solders are discussed. A solder ball includes an inner core that is an alloy of tin, silver, and copper, which has a relatively high melting point. Surrounding the inner core is a shell or cladding of a tin-bismuth alloy having a lower melting point. An optional nickel coating is on the inner core and between the inner core and the shell or cladding. During surface mount, the lower melting point the tin-bismuth alloy is used as the reflow temperature.
Technologies for memory and power components embedded in a substrate core are disclosed. In one embodiment, memory components such as a high-bandwidth memory stack and power components such as deep trench capacitors are disposed in a cavity defined in a substrate core for a circuit board of an integrated circuit package, such as a processor. The components are stacked on top of each other, allowing for the stack of components to match the height of the substrate core, even when the height of the individual components is less than the height of the substrate core. Configuring the memory and power components in this manner can provide mechanical stability to the power components and substrate core and provide close access to memory and power for a semiconductor die mounted on the circuit board.
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
An apparatus is provided which comprises: a substrate core comprising a first core layer and a second core layer, one or more redistribution layers on a first substrate core surface, one or more conductive contacts on a second substrate core surface opposite the first substrate core surface, one or more vias through the substrate core, a first circuit component embedded entirely within a cavity in the first core layer, the first circuit component coupled with a first redistribution layers surface, wherein the first circuit component and the first core layer have substantially equivalent heights, and a second circuit component embedded entirely within a cavity in the second core layer, wherein the second circuit component and the second core layer have substantially equivalent heights. Other embodiments are also disclosed and claimed.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
73.
INTEGRATED CIRCUIT STRUCTURE WITH ASYMMETRIC EPITAXIAL SOURCE OR DRAIN ARRANGEMENTS
Integrated circuit structures having asymmetric epitaxial source or drain arrangements are described. An integrated circuit structure includes a gate stack over a plurality of horizontally stacked nanowires. A first epitaxial source or drain structure is at a first end of the plurality of horizontally stacked nanowires. A first gate spacer laterally between the gate stack and the first epitaxial source or drain structure. A second epitaxial source or drain structure is at a second end of the plurality of horizontally stacked nanowires. A second gate spacer is laterally between the gate stack and the first epitaxial source or drain structure. The first gate spacer has a width less than the second gate spacer or the tips of the first epitaxial source or drain structure have a greater lateral width than the tips of the second epitaxial source or drain structure by an amount of 10% or greater, or both.
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
74.
TRANSISTORS WITH ASYMMETRIC SOURCE AND DRAIN CONTACTS
Semiconductor devices and systems with asymmetric source and drain contacts, and methods of forming the same, are disclosed herein. In one example, a semiconductor device includes a source, a drain, a source contact, a drain contact, a channel, and a gate. The source contact is coupled to the source and the drain contact is coupled to the drain, and the source contact and the drain contact are asymmetric. The source and the drain are coupled via the channel, and the gate is coupled to the channel.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
Embodiments disclosed herein include components that are embedded within a core of a package substrate. In an embodiment, the component is supported on a pad provided at a bottom of a cavity through the core. In an embodiment, such an apparatus may comprise a substrate with a cavity through a thickness of the substrate. In an embodiment, the cavity comprises sidewalls. In an embodiment, a layer spans an opening of the cavity, and the layer covers at least a portion of the sidewalls of the cavity. In an embodiment, a component is coupled to the layer, and the component is at least partially within the cavity.
H01L 23/13 - Supports, p. ex. substrats isolants non amovibles caractérisés par leur forme
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/14 - Supports, p. ex. substrats isolants non amovibles caractérisés par le matériau ou par ses propriétés électriques
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 23/498 - Connexions électriques sur des substrats isolants
76.
TECHNOLOGIES FOR GENERATIVE AI FOR WAREHOUSE PICKING
Technologies for generative AI for warehouse picking are disclosed. In an illustrative embodiment, a robot can partially or fully autonomously perform object picking in a warehouse. A description of an object to be picked can be sent to a compute device controlling the robot. The compute device can direct the robot to move to where the object is located. The robot can then take a picture that can be analyzed. A text description as well as the image is encoded and provided to a transformer. The transformer generates an output vector indicating, e.g., where an end effector should grab hold of an object. A goal generator can then determine a pose for the end effector based on the output latent vector. A planner can move the end effector to the determined pose. A new picture can be taken, and the cycle can repeat until the item is picked.
An integrated circuit structure includes a device layer including a plurality of devices. The plurality of devices includes (i) a plurality of source and drain regions, (ii) a plurality of gate stacks, and (iii) a plurality of gate spacers, each gate spacer separating a corresponding source or drain region from a corresponding gate stack, the gate spacers comprising a first dielectric material. A first source or drain contact is coupled to a frontside of a first source or drain region of the plurality of source or drain regions. A second dielectric material is coupled to a backside of the first source or drain region. A second source or drain contact is coupled to a backside of a second source or drain region of the plurality of source or drain regions. In an example, the first dielectric material and the second dielectric material comprise the same elemental constituents.
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
An integrated circuit (IC) device may include features that were patterned using overlapping exposure fields and that span the region of overlap between the exposure fields. The features may be developed from negative tone photoresist exposed using one or more clear-field reticles. A clear-field reticle may include a reflective substrate and absorber features in an opaque mask on the substrate. A single reticle may have complementary portions of an overlapping pattern, e.g., for a line feature, on opposite edges. Complementary portions of an overlapping pattern may be on different reticles.
A method comprising accessing, by at least one computing system, a plurality of layout blocks comprising a plurality of design patterns for an interconnect layer and identifications of lithography risk sites of the plurality of design patterns, the lithography risk sites corresponding to violations of constraint based checks for simulated physical patterns corresponding to the plurality of design patterns; and generating, by the at least one computing system, a layout comprising the plurality of layout blocks and at least one routing path that is coupled to a subset of the plurality of design patterns having lithography risk sites.
G06F 30/31 - Saisie informatique, p. ex. éditeurs spécifiquement adaptés à la conception de circuits
G03F 1/36 - Masques à correction d'effets de proximitéLeur préparation, p. ex. procédés de conception à correction d'effets de proximité [OPC optical proximity correction]
80.
ELECTROLESS NICKEL-ELECTROLESS PALLADIUM-IMMERSION GOLD (ENEPIG) AS A SURFACE FINISH FOR EMBEDDED DIE ATTACHMENTS
In embodiments herein, a surface finish (SF) is formed on conductive contacts of a package substrate for connection to an embedded interconnect bridge circuitry die. In some embodiments, the SF may be electroless nickel-electroless palladium-immersion gold (ENEPIG). In other embodiments, the SF may be immersion gold-electroless palladium-immersion gold (IGEPIG). In other embodiments, the SF may include a layer of electrolytic palladium-gold on a layer of indium or on a layer of cobalt-iron.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/13 - Supports, p. ex. substrats isolants non amovibles caractérisés par leur forme
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
81.
ENHANCING DEVICE PERFORMANCE BY MITIGATION OF OXYGEN MIGRATION IN HAFNIUM OXIDE BASED MATERIAL SYSTEMS
Apparatuses, systems, and techniques related to ferroelectric material systems including hafnium oxide-based ferroelectric layers are described. A ferroelectric material system includes an oxide layer on the hafnium oxide-based ferroelectric layer, and an oxygen migration mitigation layer on the oxide layer. The oxygen migration mitigation layer is niobium nitride, tantalum nitride, ruthenium oxide, molybdenum, tungsten, ruthenium or palladium, and a metallic electrode is formed on the oxygen migration mitigation layer.
H10B 53/30 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par la région noyau de mémoire
H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
H01L 29/51 - Matériaux isolants associés à ces électrodes
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H10B 51/30 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par la région noyau de mémoire
Techniques for register renaming caching are described. In an embodiment, an apparatus includes a register renaming cache, front-end circuitry, lookup circuitry, and execution circuitry. The register renaming cache is to store register renaming information associated with an instruction trace. The register renaming information is to be learned from a first execution of the instruction trace and is to be used to perform register renaming in connection with a second execution of the instruction trace. The front-end circuitry is to provide, based on the instruction trace, operations for execution. The lookup circuitry to look in the register renaming cache for entries corresponding to the operations. The execution circuitry is to execute the instruction trace.
G06F 12/0802 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache
Microelectronic integrated circuit package structures include an apparatus having a a glass substrate embedded within a package substrate. The glass substrate comprises one or more trenches extending within a first portion, the one or more trenches comprising a first conductive layer on individual trench sidewalls, a dielectric layer on the first conductive layer and a second conductive layer on the dielectric layer. A second portion of the glass substrate is below the first portion.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
Techniques for partitioning and/or gradual re-keying of randomized caches are described. In certain examples, an apparatus includes an execution circuit to cause a memory access request; a cache to store a plurality of sets, each of the sets to include a plurality of cache lines; and a cache randomizer circuit to generate a randomized index into the plurality of sets of the cache based on an address of the memory access request by encrypting a first subset of bits of the address of the memory access request to generate an encrypted value, and generating the randomized index based on a first subset of bits of the encrypted value. The encrypting is to be based on a first key for a first segment of the cache and a second segment of the cache during a first period, on a second key for the first segment of the cache and the first key for the second segment of the cache during a second period, and on the second key for the first segment of the cache and the second segment of the cache during a third period.
G06F 12/0891 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache utilisant des moyens d’effacement, d’invalidation ou de réinitialisation
85.
MICROELECTRONIC STRUCTURES INCLUDING EMBEDDED INTEGRATED CAPACITOR IN MULTILAYER CORE
Microelectronic integrated circuit package structures include one or more trench capacitors extending through a portion a device structure. The device structure is embedded within a portion of a core layer of a multi core package substrate, wherein one or more conductive interconnect structures are coupled with the one or more trench capacitors. A thickness of the device structure is equal to a thickness of the core layer.
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/498 - Connexions électriques sur des substrats isolants
86.
MECHANICAL ALIGNMENT FEATURES FOR GLASS WAVEGUIDE TO PHOTONIC INTEGRATED CIRCUIT MATING
An apparatus includes an optical interposer including a first surface, a first mating protrusion extending outwardly from the first surface, and two or more alignment protrusions extending outwardly from the first surface. The first mating protrusion is to be partially disposed within a first recess formed in a second surface of a photonic integrated circuit (PIC) die when the first surface of the optical interposer opposes the second surface of the PIC die and respective distal surfaces of the two or more alignment protrusions contact the second surface of the PIC die. A first portion of an outer surface of the first mating protrusion is to contact a first side wall of the first recess and a second portion of the outer surface of the first mating protrusion is to oppose a second side wall of the first recess such that a second space is to be defined therebetween.
In embodiments herein, a surface finish (SF) is formed on conductive contacts of a package substrate for connection to an embedded interconnect bridge circuitry die. In some embodiments, the SF may be electroless nickel-electroless palladium-immersion gold (ENEPIG). In other embodiments, the SF may be immersion gold-electroless palladium-immersion gold (IGEPIG). In other embodiments, the SF may include a layer of electrolytic palladium-gold on a layer of indium or on a layer of cobalt-iron.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/13 - Supports, p. ex. substrats isolants non amovibles caractérisés par leur forme
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
88.
COMPONENT COUPLED WITH CONDUCTIVE VIAS ENCAPSULATED IN AN ELECTRONIC SUBSTRATE
An apparatus includes a substrate, a cavity within the substrate, and a die within the cavity. The substrate has an exterior surface. The cavity includes a first surface and a second surface opposite the first surface. The die includes a discrete component, a first side, a second side opposite the first side, and conductive features at the first side. In an embodiment, a bond film is between the first surface and the first side. A plurality of conductive vias extend from the exterior surface through the substrate and bond film to the conductive features. In an embodiment, the bond film may be omitted. The plurality of conductive vias extend from the exterior surface through the substrate. The conductive features of the die are coupled with the conductive vias by solder features, and the second side of the die is spaced away from the second surface.
H01L 23/482 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes formées de couches conductrices inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
89.
RECONSTITUTED PASSIVE ASSEMBLIES FOR EMBEDDING IN THICK CORES
Embodiments disclosed herein include apparatuses with assemblies comprising passive electrical devices that are embedded in a core of a package substrate. In an embodiment, such an apparatus may comprise a substrate with a first surface, a second surface opposite from the first surface, and a sidewall surface coupling the first surface to the second surface. In an embodiment the substrate comprises a passive electrical device. In an embodiment, a pad is on the first surface of the substrate, and a layer contacts the substrate. In an embodiment, the layer directly contacts the first surface and the sidewall surface of the substrate.
H01L 23/482 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes formées de couches conductrices inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
90.
ELECTROLYTIC INDIUM-PALLADIUM-GOLD AS A SURFACE FINISH FOR EMBEDDED DIE ATTACHMENTS
In embodiments herein, a surface finish (SF) is formed on conductive contacts of a package substrate for connection to an embedded interconnect bridge circuitry die. In some embodiments, the SF may be electroless nickel-electroless palladium-immersion gold (ENEPIG). In other embodiments, the SF may be immersion gold-electroless palladium-immersion gold (IGEPIG). In other embodiments, the SF may include a layer of electrolytic palladium-gold on a layer of indium or on a layer of cobalt-iron.
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 25/10 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs ayant des conteneurs séparés
91.
ELECTROLYTIC COBALT-IRON-PALLADIUM-GOLD AS A SURFACE FINISH FOR EMBEDDED DIE ATTACHMENTS
In embodiments herein, a surface finish (SF) is formed on conductive contacts of a package substrate for connection to an embedded interconnect bridge circuitry die. In some embodiments, the SF may be electroless nickel-electroless palladium-immersion gold (ENEPIG). In other embodiments, the SF may be immersion gold-electroless palladium-immersion gold (IGEPIG). In other embodiments, the SF may include a layer of electrolytic palladium-gold on a layer of indium or on a layer of cobalt-iron.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
92.
APPARATUSES, METHODS, AND SYSTEMS FOR INSTRUCTIONS FOR MATRIX TRANSPOSE
Examples detailed herein at least include transpose circuitry that is external to a matrix operations accelerator. In some examples, the transpose circuitry at least includes a plurality of transpose engines to transpose a source matrix operand of a single instruction to generate a transposed source matrix, and control circuitry to direct the plurality of transpose engines to alternately operate in a parallel loading mode and a serial loading mode to generate the transposed source matrix, wherein the plurality of transposes engines and the control circuitry are at least a portion of transpose circuitry.
Techniques for software defined super core usage are described. In some examples, a first and second processor core are to operate as a single virtual core enabled by the operating system to fetch the first set of instruction segments of the single threaded program and the second set of instruction segments of the single threaded program concurrently using flow control instructions that have been inserted into the single threaded program.
Methods, systems, and storage media for accessing one or more services provided by one or more detected Internet of Things (“IoT”) devices are described. In embodiments, a mobile device may detect a plurality of IoT devices, obtain an identifier for each of the plurality of IoT devices based on the detection, and obtain an indicator for each of the plurality of IoT devices based at least in part on a corresponding one of the obtained identifiers, wherein each indicator may indicate a service type of a corresponding one of the plurality of IoT devices. The mobile device may generate a notification that indicates a plurality of services available to the mobile device based on each of the obtained indicators. The mobile device may access a service of the plurality of services, wherein the access may include utilization of a set of the plurality of IoT devices required to provide the service. Other embodiments may be described and/or claimed.
H04L 67/51 - Découverte ou gestion de ceux-ci, p. ex. protocole de localisation de service [SLP] ou services du Web
H04L 67/125 - Protocoles spécialement adaptés aux environnements propriétaires ou de mise en réseau pour un usage spécial, p. ex. les réseaux médicaux, les réseaux de capteurs, les réseaux dans les véhicules ou les réseaux de mesure à distance en impliquant la commande des applications des terminaux par un réseau
H04W 4/70 - Services pour la communication de machine à machine ou la communication de type machine
H04W 8/00 - Gestion de données relatives au réseau
H04W 48/10 - Distribution d'informations relatives aux restrictions d'accès ou aux accès, p. ex. distribution de données d'exploration utilisant des informations radiodiffusées
H04W 48/16 - ExplorationTraitement d'informations sur les restrictions d'accès ou les accès
95.
ENHANCED RESOURCE PARTITIONING FOR NEW RADIO (NR)-LONG TERM EVOLUTION (LTE) CO-EXISTENCE
Various embodiments herein provide techniques related to a user equipment (UE). The UE may identify, by a long term evolution (LTE) sidelink (SL) module that is to facilitate communication via a first SL channel of a first cellular network, a resource that is to be used for communication in the first SL channel by another UE; provide, by the LTE SL module, information related to use of the resource to a new radio (NR) SL module that is to facilitate communication via a second SL channel of a second cellular network; and exclude, by the NR SL module based on the information related to use of the resource, the resource for communication via the second SL channel. Other embodiments may be described and/or claimed.
H04W 72/25 - Canaux de commande ou signalisation pour la gestion des ressources entre terminaux au moyen d’une liaison sans fil, p. ex. liaison secondaire
An apparatus and system of providing a service registry function (SRF) and service discovery in a 6G system are described. Registration procedures are provided for a service instance on a user equipment (UE) or in the 6G system to register to the SRF with or without a service mesh. The SRF provides a list of service instances based on criteria in service discovery inquiries from the UE or network function (NF) and notifies a subscribed party about a status change of a particular service instance. The service discovery enables the UE to discover a computing service instance in the 6G system by control plane service discovery to find a service orchestration and chaining function (SOCF) and user plane service discovery to find the computing service instance.
Embodiments disclosed herein include photonics packages. In an embodiment, the photonics package comprises a substrate. In an embodiment, a first interposer is over the substrate, and a first die is on the first interposer. In an embodiment, a second interposer is over the substrate, and a second die is on the second interposer. In an embodiment, an optical bridge is between the first interposer and the second interposer.
G02B 6/43 - Dispositions comprenant une série d'éléments opto-électroniques et d'interconnexions optiques associées
G02B 6/293 - Moyens de couplage optique ayant des bus de données, c.-à-d. plusieurs guides d'ondes interconnectés et assurant un système bidirectionnel par nature en mélangeant et divisant les signaux avec des moyens de sélection de la longueur d'onde
G02B 6/34 - Moyens de couplage optique utilisant des prismes ou des réseaux
G02B 6/42 - Couplage de guides de lumière avec des éléments opto-électroniques
98.
Information system and method for controlling an information system
An information system for a vehicle includes a processor configured to: determine system information representing one or more than one message relating to an occupant of the vehicle and/or the vehicle and/or an environment of the vehicle; determine a current driving task of the vehicle; determine, using sensor data representing a state of the driver of the vehicle, driver information representing a physical and/or mental state of the driver; determine, using the current driving task and the driver information, message presentation information indicating, for each of the one or more than one message, whether the message is to be presented to the driver and/or how the message is to be presented to the driver and/or at what time the message is to be presented to the driver; and generate control instructions to control at least one component of the vehicle according to the message presentation information.
G06V 20/59 - Contexte ou environnement de l’image à l’intérieur d’un véhicule, p. ex. concernant l’occupation des sièges, l’état du conducteur ou les conditions de l’éclairage intérieur
B60Q 9/00 - Agencement ou adaptation des dispositifs de signalisation non prévus dans l'un des groupes principaux
G06V 20/40 - ScènesÉléments spécifiques à la scène dans le contenu vidéo
G06V 40/18 - Caractéristiques de l’œil, p. ex. de l’iris
99.
Control device and method for controlling a display unit in a vehicle
A control device and a method for controlling a display unit arranged in a vehicle, such that the control device comprises a processor configured to receive first data representing an environment of a vehicle; determine a driving trajectory of the vehicle using the first data; receive second sensor data representing a head movement of an occupant of the vehicle; determine a time-dependent relative movement between the head movement of the occupant and a vehicle movement according to the driving trajectory using a speed of the vehicle; determine a time-dependent change in a position of display information to be displayed on a display unit disposed in the vehicle such that the change in the position of the display information compensates for all or part of the relative movement; and generate control instructions for controlling the display unit to display the display information in accordance with the time-dependent change in the position.
G06F 3/01 - Dispositions d'entrée ou dispositions d'entrée et de sortie combinées pour l'interaction entre l'utilisateur et le calculateur
G09G 3/00 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques
100.
MID-PROCESSING REMOVAL OF SEMICONDUCTOR FINS DURING FABRICATION OF INTEGRATED CIRCUIT STRUCTURES
Techniques are disclosed for forming integrated circuit structures having a plurality of semiconductor fins, which in turn can be used to form non-planar transistor structures. The techniques include a mid-process removal of one or more partially-formed fins. The resulting integrated circuit structure includes a plurality of semiconductor fins having relatively uniform dimensions (e.g., fin width and trough depth). In an embodiment, the fin forming procedure includes partially forming a plurality of fins, using a selective etch stop built into the semiconductor structure in which the fins are being formed. One or more of the partially-formed fins are removed via sacrificial fin cut mask layer(s). After fin removal, the process continues by further etching trenches between the partially-formed fins (deep etch) to form portion of fins that will ultimately include transistor channel portion. A liner material may be deposited to protect the partially-formed fins during this subsequent deep trench etch.
H01L 21/308 - Traitement chimique ou électrique, p. ex. gravure électrolytique en utilisant des masques
H10D 62/17 - Régions semi-conductrices connectées à des électrodes ne transportant pas de courant à redresser, amplifier ou commuter, p. ex. régions de canal
H10D 62/832 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe IV, p. ex. Si dopé B ou Ge non dopé étant des matériaux du groupe IV comprenant deux éléments ou plus, p. ex. SiGe
H10D 62/85 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe III-V, p. ex. GaAs
H10D 84/03 - Fabrication ou traitement caractérisés par l'utilisation de technologies basées sur les matériaux utilisant une technologie du groupe IV, p. ex. technologie au silicium ou au carbure de silicium [SiC]
H10D 84/85 - Transistors IGFET complémentaires, p. ex. CMOS
