An apparatus (100) may include a first node (104) coupled to a first terminal, the first terminal to receive a first control signal (S_IN); a second node (102) coupled to a second terminal, the second terminal to receive a second control signal (H_IN); a first capacitor (CO) having a first plate coupled to the first node and a second plate coupled to a first output terminal (H); a second capacitor (Cl) having a first plate coupled to the second node and a second plate coupled to a second output terminal (S); a first stack of transistors (M223, M24, M25) coupled between a positive supply terminal (POS through M2, X0) and a common mode terminal (CM), the first stack operable to divide voltage: and a second stack of transistors (M5, M4, M3) coupled between a negative supply terminal (NEG through M1, X10) and the common mode terminal (CM), the second stack operable to divide voltage.
An apparatus may include a first node coupled to a first terminal, the first terminal to receive a first control signal; a second node coupled to a second terminal, the second terminal to receive a second control signal; a first capacitor having a first plate coupled to the first node and a second plate coupled to a first output terminal; a second capacitor having a first plate coupled to the second node and a second plate coupled to a second output terminal; a first stack of transistors coupled between a positive supply terminal and a common mode terminal, the first stack operable to divide voltage; and a second stack of transistors coupled between a negative supply terminal and the common mode terminal, the second stack operable to divide voltage.
A job manager may receive a request for a design of a semiconductor device to be verified by a set of computing devices, wherein the request comprises design parameters regarding the design of the semiconductor device. The job manager may provide the design parameters as inputs to a machine learning model trained to predict amounts of computational resources and amounts of compute time for verifying designs of semiconductor devices. The job manager may obtain, as an output from the machine learning model, a predicted amount of computational resources and a predicted amount of compute time for verifying the design of the semiconductor device. The job manager may determine an availability of resources, of the set of computing devices, for verifying the design of the semiconductor device. The job manager may cause the design of the semiconductor device to be verified by one or more computing devices.
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
G06F 30/392 - Conception de plans ou d’agencements, p. ex. partitionnement ou positionnement
4.
APPARATUS FORMED FROM ELECTRONIC COMPONENTS HAVING DIFFERENT RESPECTIVE THICKNESSES AND METHODS OF FORMING AN APPARATUS FROM ELECTRONIC COMPONENTS HAVING DIFFERENT RESPECTIVE THICKNESSES
An apparatus includes a pair of substrates with conductive material formed on portions of inwardly facing surfaces thereof, and a step formed in or on the conductive material on one of the pair of substrates. A lead frame having leads and electronic components having different respective thicknesses are mounted between the conductive materials on the pair of substrates. The step has a step thickness dimensioned to facilitate electrical contact between a thickest one of the electronic components or the leads with the step in the conductive material on one of the pair of substrates and the conductive material on the one other of the pair of substrates. An electrical signal path is formed between the electronic components or the leads disposed in electrical contact with the step and the conductive material on the one other of the pair of substrates.
H01L 23/373 - Refroidissement facilité par l'emploi de matériaux particuliers pour le dispositif
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
5.
APPARATUS FORMED FROM ELECTRONIC COMPONENTS HAVING DIFFERENT RESPECTIVE THICKNESSES AND METHODS OF FORMING AN APPARATUS FROM ELECTRONIC COMPONENTS HAVING DIFFERENT RESPECTIVE THICKNESSES
An apparatus includes a pair of substrates with conductive material formed on portions of inwardly facing surfaces thereof, and a step formed in or on the conductive material on one of the pair of substrates. A lead frame having leads and electronic components having different respective thicknesses are mounted between the conductive materials on the pair of substrates. The step has a step thickness dimensioned to facilitate electrical contact between a thickest one of the electronic components or the leads with the step in the conductive material on one of the pair of substrates and the conductive material on the one other of the pair of substrates. An electrical signal path is formed between the electronic components or the leads disposed in electrical contact with the step and the conductive material on the one other of the pair of substrates.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
A FinFET device that may include a substrate (20). A drain layer (30) on a first side of the substrate. A drift layer (40) on a second side of the substrate. The drift layer having a fin-shaped portion (50) and a recessed portion. A doped-well layer (70) over the recessed portion of the drift layer and along sides of the fin-shaped portion of the drift layer. A body layer (80) and a source layer (90) formed over a portion of the doped-well layer over the recessed portion of the drift layer. An insulating layer (75) over the doped-well layer. A gate electrode (110) over the insulating layer.
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
A FinFET device that may include a substrate. A drain layer on a first side of the substrate. A drift layer on a second side of the substrate. The drift layer having a fin-shaped portion and a recessed portion. A doped-well layer over the recessed portion of the drift layer and along sides of the fin-shaped portion of the drift layer. A body layer and a source layer formed over a portion of the doped-well layer over the recessed portion of the drift layer. An insulating layer over the doped-well layer. A gate electrode over the insulating layer.
A FinFET device that may include a substrate. A drain layer on a first side of the substrate. A drift layer on a second side of the substrate. The drift layer having a fin-shaped portion and a recessed portion. A doped-well layer over the fin-shaped portion of the drift layer. An insulating layer over the doped-well layer and over the recessed portion of the drift layer. A gate electrode over the insulating layer.
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 21/336 - Transistors à effet de champ à grille isolée
9.
SYSTEM AND METHODS FOR PHYSICAL IDENTIFICATION OF MANUFACTURED PRODUCTS
A manufactured product may include a machine-readable physical identifier and the machine-readable physical identifier may be stored in a tracking file. The machine-readable physical identifier may be encoded with manufacturing information related to the manufactured product, including but not limited to manufacturing location, lot number and manufacturing date. The tracking file may be updated based on one or more supply chain operations, including but not limited to a testing operation, a shipping operation or a delivery operation. The tracking file may include information on testing results, shipping origin and destinations and delivery locations. The tracking file may be delivered to a customer along with the manufactured products listed in the tracking file.
A FinFET device that may include a substrate. A drain layer on a first side of the substrate. A drift layer on a second side of the substrate. The drift layer having a fin-shaped portion and a recessed portion. A doped-well layer over the fin-shaped portion of the drift layer. An insulating layer over the doped-well layer and over the recessed portion of the drift layer. A gate electrode over the insulating layer.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
H01L 29/66 - Types de dispositifs semi-conducteurs
11.
SYSTEM AND METHODS FOR PHYSICAL IDENTIFICATION OF MANUFACTURED PRODUCTS
A manufactured product may include a machine-readable physical identifier and the machine-readable physical identifier may be stored in a tracking file. The machine-readable physical identifier may be encoded with manufacturing information related to the manufactured product, including but not limited to manufacturing location, lot number and manufacturing date. The tracking file may be updated based on one or more supply chain operations, including but not limited to a testing operation, a shipping operation or a delivery operation. The tracking file may include information on testing results, shipping origin and destinations and delivery locations. The tracking file may be delivered to a customer along with the manufactured products listed in the tracking file.
G06Q 10/06 - Ressources, gestion de tâches, des ressources humaines ou de projetsPlanification d’entreprise ou d’organisationModélisation d’entreprise ou d’organisation
G06K 19/06 - Supports d'enregistrement pour utilisation avec des machines et avec au moins une partie prévue pour supporter des marques numériques caractérisés par le genre de marque numérique, p. ex. forme, nature, code
G06Q 10/08 - Logistique, p. ex. entreposage, chargement ou distributionGestion d’inventaires ou de stocks
A circuit to suppress ringing in a Controller Area Network (CAN) bus having a CAN high (CANH) wire and a CAN low (CANL) wire is provided. The circuit may include processing circuitry to generate a CAN control signal, and a transconductance amplifier to receive a first input signal corresponding to the CAN control signal and a voltage signal from the CANL wire, and to generate an output current signal based on a difference between the first input signal and the voltage signal from the CANL wire. An output terminal of the transconductance amplifier may be coupled to the CANH wire to source current to or sink current from the CANH wire.
H04L 12/413 - Réseaux à ligne bus avec commande décentralisée avec accès aléatoire, p. ex. accès multiple avec détection de porteuse et détection de collision [CSMA-CD]
H03K 5/1252 - Suppression ou limitation du bruit ou des interférences
A system includes one or more processing units adapted to generate, using a first encryption key, a first set of round keys for rounds of an advanced encryption standard (AES) algorithm; generate, using a second encryption key, a second set of round keys; and determine different addresses, of a plurality of memory devices, for the first and second sets of round keys; and store the first and second sets of round keys in the different addresses, wherein the first round key is stored in a memory device, of the plurality of memory devices, using a first port of the memory device, and wherein the memory device is a dual port memory device that includes the first port and a second port.
H04L 9/06 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p. ex. système DES
14.
High Electron Mobility Transistor and Method for Manufacturing Same
A High-Electron-Mobility-Transistor that may include a substrate with a buffer layer formed on the substrate. A recess formed in the buffer layer. A barrier layer formed on the buffer layer. A gate recess formed in the barrier layer, the gate recess overlaps the recess in the buffer layer. A drain terminal formed at a first side of the barrier layer. A source terminal formed at a second side of the barrier layer. An isolation structure formed within the gate recess proximate the drain terminal. A doped structure formed adjacent to the isolation structure within the gate recess proximate the source terminal. A gate terminal formed on the doped structure.
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
15.
TERMINATION STRUCTURE FOR A SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
A termination structure for a semiconductor device that may include a substrate having a first type dopant. A plurality of doped-wells having a second type dopant formed in the substrate. A plurality of trenches formed into the plurality of doped-wells, respective ones of the formed trenches exposing a bottom surface of the doped-well, and exposing side surfaces of the doped-well, and a material within respective ones of the formed trenches, wherein the material in respective ones of the formed trenches is surrounded by the exposed bottom surface of the doped-well of the respective formed trench and the exposed side surfaces of the doped-well of the respective formed trench.
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée
16.
HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD FOR MANUFACTURING SAME
A High-Electron-Mobility-Transistor includes a substrate (20) with a buffer layer (30) formed on the substrate. A recess (50) is formed in the buffer layer. A barrier layer (40) is formed on the buffer layer. A gate recess (55) is formed in the barrier layer, wherein the gate recess overlaps the recess in the buffer layer. A drain terminal (60) is formed at a first side of the barrier layer. A source terminal (70) is formed at a second side of the barrier layer. An isolation structure (80) is formed within the gate recess proximate the drain terminal. A doped structure (90) is formed adjacent to the isolation structure within the gate recess proximate the source terminal. A gate terminal (100) is formed on the doped structure.
H10D 30/47 - Transistors FET ayant des canaux à gaz de porteurs de charge de dimension nulle [0D], à une dimension [1D] ou à deux dimensions [2D] ayant des canaux à gaz de porteurs de charge à deux dimensions, p. ex. transistors FET à nanoruban ou transistors à haute mobilité électronique [HEMT]
H10D 62/17 - Régions semi-conductrices connectées à des électrodes ne transportant pas de courant à redresser, amplifier ou commuter, p. ex. régions de canal
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 62/85 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe III-V, p. ex. GaAs
17.
DETERMINING PHYSICAL ADDRESSES OF MEMORY DEVICES USING DIVISION BY PRIME NUMBERS
A processing unit, associated with a host device, adapted to receive a request to calculate a first physical address of an external device based on a second physical address of the host device; determine a tree of parallel adders corresponding to the division operation; obtain an output value from the tree of parallel adders based on the input values; and calculate the first physical address using the output value. The first physical address of the external device is to be calculated based on a division operation that divides the second physical address by a divisor. The tree of parallel adders is determined based on input values that include a number of bits of the second physical address and a divisor.
G06F 12/06 - Adressage d'un bloc physique de transfert, p. ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
G06F 12/0846 - Mémoire cache avec matrices multiples d’étiquettes ou de données accessibles simultanément
A Controller Area Network (CAN) bus driver for driving a CAN bus is provided. The bus driver may include a first translinear loop circuit to receive an input voltage and output a first output current signal corresponding to an exponential function, a second translinear loop circuit to receive the input voltage and output a second output current signal corresponding to a hyperbolic function, a divider circuit to output a divided output current signal corresponding to the first output current signal divided by the second output current signal, a CAN Lo driver circuit to output the divided output current signal to a CAN Lo wire of the CAN bus, and a CAN Hi driver circuit to output the divided output current signal to a CAN Hi wire of the CAN bus.
A transistor comprising a drain layer, a drift layer over the drain layer, a channel layer over the drift layer, and a source layer over the channel layer. A trench formed through the source layer, through the channel layer and into at least partially the drift layer. A gate formed within the trench.
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 21/265 - Bombardement par des radiations ondulatoires ou corpusculaires par des radiations d'énergie élevée produisant une implantation d'ions
H01L 21/266 - Bombardement par des radiations ondulatoires ou corpusculaires par des radiations d'énergie élevée produisant une implantation d'ions en utilisant des masques
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
20.
TERMINATION STRUCTURE FOR A SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
A termination structure for a semiconductor device that may include a substrate having a first type dopant. A plurality of doped-wells having a second type dopant formed in the substrate. A plurality of trenches formed into the plurality of doped-wells, respective ones of the formed trenches exposing a bottom surface of the doped-well, and exposing side surfaces of the doped-well, and a material within respective ones of the formed trenches, wherein the material in respective ones of the formed trenches is surrounded by the exposed bottom surface of the doped-well of the respective formed trench and the exposed side surfaces of the doped-well of the respective formed trench.
A processing unit, associated with a host device, adapted to receive a request to calculate a first physical address of an external device based on a second physical address of the host device; determine a tree of parallel adders corresponding to the division operation; obtain an output value from the tree of parallel adders based on the input values; and calculate the first physical address using the output value. The first physical address of the external device is to be calculated based on a division operation that divides the second physical address by a divisor. The tree of parallel adders is determined based on input values that include a number of bits of the second physical address and a divisor.
A transistor comprising a drain layer, a drift layer over the drain layer, a channel layer over the drift layer, and a source layer over the channel layer. A trench formed through the source layer, through the channel layer and into at least partially the drift layer. A gate formed within the trench.
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 21/336 - Transistors à effet de champ à grille isolée
23.
STORING AND PROVIDING ACCESS TO ROUND KEYS OF ADVANCED ENCRYPTION STANDARD USING DUAL PORT MEMORY DEVICES
A system includes one or more processing units adapted to generate, using a first encryption key, a first set of round keys for rounds of an advanced encryption standard (AES) algorithm; generate, using a second encryption key, a second set of round keys; and determine different addresses, of a plurality of memory devices, for the first and second sets of round keys; and store the first and second sets of round keys in the different addresses, wherein the first round key is stored in a memory device, of the plurality of memory devices, using a first port of the memory device, and wherein the memory device is a dual port memory device that includes the first port and a second port.
G06F 21/79 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du stockage de données dans les supports de stockage à semi-conducteurs, p. ex. les mémoires adressables directement
24.
CONTROLLER AREA NETWORK (CAN) BUS DRIVER USING TRANSLINEAR LOOPS
A Controller Area Network (CAN) bus driver for driving a CAN bus is provided. The bus driver may include a first translinear loop circuit to receive an input voltage and output a first output current signal corresponding to an exponential function, a second translinear loop circuit to receive the input voltage and output a second output current signal corresponding to a hyperbolic function, a divider circuit to output a divided output current signal corresponding to the first output current signal divided by the second output current signal, a CAN Lo driver circuit to output the divided output current signal to a CAN Lo wire of the CAN bus, and a CAN Hi driver circuit to output the divided output current signal to a CAN Hi wire of the CAN bus.
H03K 17/60 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors bipolaires
H03K 17/687 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
25.
TRANSMISSION OF SIGNALS FOR RANGING, TIMING, AND DATA TRANSFER
A method is disclosed. In various examples, the method may include receiving an instruction for generating a ranging signal, and transmitting the ranging signal at least partially responsive to the instruction. In various examples the ranging signal may be transmitted via a terrestrial transmitter for transmitting radio waves having encoded messaging information and timing information for one or more of positioning, navigation and timing. In various examples, the ranging signal may exhibit a first ranging pulse and a second ranging pulse of a pulse group and an encoded transmitter identifier, the transmitter identifier encoded by modulating an inter-pulse interval defined between a start of the first ranging pulse and a start of the second ranging pulse.
G01S 1/04 - Radiophares ou systèmes de balisage émettant des signaux ayant une ou des caractéristiques pouvant être détectées par des récepteurs non directionnels et définissant des directions, situations ou lignes de position déterminées par rapport aux émetteurs de radiophareRécepteurs travaillant avec ces systèmes utilisant les ondes radioélectriques Détails
26.
TRENCH POWER SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
A trench power semiconductor device comprising a silicon carbide drain layer, a silicon carbide drift layer over the silicon carbide drain layer and a first silicon layer over the silicon carbide drift layer. A second silicon layer over the first silicon layer with a source silicon carbide layer over the second silicon layer. A trench formed through the source silicon carbide layer, through the second silicon layer and into at least partially the first silicon layer. A gate terminal contact formed on the trench with a drain terminal contact formed on the silicon carbide drain layer.
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/165 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée comprenant plusieurs des éléments prévus en dans différentes régions semi-conductrices
27.
IDENTIFYING WORDLINES SUSCEPTIBLE TO DEEPER ERASE CONDITIONS
In some implementations, a controller may identify a block of a memory device that is scheduled for an erase operation. The controller may determine, using a machine learning model or a data structure, whether a wordline of the block is susceptible to a deeper erase condition before the erase operation. The data structure identifies wordlines that are susceptible to deeper erase conditions. The controller may perform a programming operation, on the wordline, to program a predetermined bit pattern on the wordline based on the wordline being susceptible to the deeper erase condition. The controller may perform the erase operation on the block after performing the programming operation.
G11C 16/16 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement pour effacer des blocs, p. ex. des réseaux, des mots, des groupes
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 16/10 - Circuits de programmation ou d'entrée de données
28.
Apparatus and Method for Clock Frequency Estimation With Subsets of Time Measurements
An apparatus includes a clock signal input, a sampling circuit, and an estimation circuit. The clock signal input receives N time measurements. A time measurement denotes a respective portion of a given cycle of a clock signal. The sampling circuit is to generate a first and second sampled window from the clock signal input. The first sampled window includes a sum of a plurality of a first m of the N time measurements. The second sampled window includes a sum of a plurality of a last m of the N time measurements. The estimation circuit is to estimate the frequency or period of the clock signal based upon the first sampled window and the second sampled window.
A trench power semiconductor device comprising a silicon carbide drain layer, a silicon carbide drift layer over the silicon carbide drain layer and a first silicon layer over the silicon carbide drift layer. A second silicon layer over the first silicon layer with a source silicon carbide layer over the second silicon layer. A trench formed through the source silicon carbide layer, through the second silicon layer and into at least partially the first silicon layer. A gate terminal contact formed on the trench with a drain terminal contact formed on the silicon carbide drain layer.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée
H01L 29/167 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée caractérisés en outre par le matériau de dopage
H01L 29/66 - Types de dispositifs semi-conducteurs
30.
Silicon Carbide Driver Using High Voltage Capacitors for Isolation and Signal Transmission
A gate driver circuit to receive an input drive signal and output an output drive signal is provided. The gate driver circuit may include a first capacitor having first and second terminals, a second capacitor having first and second terminals, a first set of switches to selectively couple the first terminals of the first and second capacitors to the input drive signal and a power supply voltage, a second set of switches to selectively couple the second terminals of the first and second capacitors to a reference voltage and a high impedance node, and a comparator having a first terminal coupled to the reference voltage and a second terminal coupled to the high impedance node. The comparator may output the output drive signal based on a comparison of the reference voltage and a voltage at the high impedance node.
H03K 17/567 - Circuits caractérisés par l'utilisation d'au moins deux types de dispositifs à semi-conducteurs, p. ex. BIMOS, dispositifs composites tels que IGBT
H03K 17/687 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
31.
CONTROLLING AN AIR FLOW RATE PROVIDED TO A BURNER BASED ON A CONCENTRATION OF GAS PROVIDED TO THE BURNER
Systems and methods for controlling an air flow rate provided to a burner based on the concentration of one or more gases provided to the burner are disclosed. A method for controlling a burner including receiving a gas concentration value indicating a concentration of one or more gases in a gas mixture provided to a burner; determining, using the gas concentration value, an air flow rate to input to the burner; and controlling the air flow rate provided to the burner based on the determined air flow rate.
NN time measurements. The sampling circuit is to generate a second sampled window from the clock signal input including an accumulation of a plurality of products. The estimation circuit is to estimate the frequency or period of the clock signal based upon the first sampled window and the second sampled window.
G06F 1/14 - Dispositions pour le contrôle du temps, p. ex. horloge temps réel
G01R 23/02 - Dispositions pour procéder à la mesure de fréquences, p. ex. taux de répétition d'impulsionsDispositions pour procéder à la mesure de la période d'un courant ou d'une tension
33.
TUNING A SLIDING MODE OBSERVER FOR A PERMANENT MAGNET SYNCHRONOUS MOTOR
A method is provided that may include receiving an identifier of a permanent magnet synchronous motor (PMSM), and mapping the identifier to electrical parameters of the PMSM. The method may include determining one or more coefficients of a sliding mode observer (SMO) based on the electrical parameters. The method may include providing the determined coefficients to the SMO to estimate the rotor position and speed of the PMSM.
An apparatus includes a clock signal input, a sampling circuit, and an estimation circuit. The clock signal input receives N time measurements. A time measurement denotes a respective portion of a given cycle of a clock signal. The sampling circuit is to generate a first sampled window from the clock signal input. The first sampled window includes an accumulation of the N time measurements. The sampling circuit is to generate a second sampled window from the clock signal input including an accumulation of a plurality of products. The estimation circuit is to estimate the frequency or period of the clock signal based upon the first sampled window and the second sampled window.
An apparatus includes a clock signal input, a sampling circuit, and an estimation circuit. The clock signal input receives N time measurements. A time measurement denotes a respective portion of a given cycle of a clock signal. The sampling circuit is to generate a first sampled window based upon a first time measurement and a first previous time measurement received m time measurements earlier than the first time measurement. The sampling circuit is to generate a second sampled window based upon a second time measurement and a second previous time measurement received m time measurements earlier than the second time measurement. The estimation circuit is to estimate the frequency or period of the clock signal based upon the first sampled window and the second sampled window.
G01R 23/02 - Dispositions pour procéder à la mesure de fréquences, p. ex. taux de répétition d'impulsionsDispositions pour procéder à la mesure de la période d'un courant ou d'une tension
36.
IDENTIFYING WORDLINES SUSCEPTIBLE TO DEEPER ERASE CONDITIONS
In some implementations, a controller may identify a block of a memory device that is scheduled for an erase operation. The controller may determine, using a machine learning model or a data structure, whether a wordline of the block is susceptible to a deeper erase condition before the erase operation. The data structure identifies wordlines that are susceptible to deeper erase conditions. The controller may perform a programming operation, on the wordline, to program a predetermined bit pattern on the wordline based on the wordline being susceptible to the deeper erase condition. The controller may perform the erase operation on the block after performing the programming operation.
A method comprises generating a wireless power signal in one or more transmit coils of a transmitter which inductively couple with one or more receive coils of a receiver for wireless power transfer; terminating the wireless power transfer at least partially responsive to detecting a power loss of the wireless power transfer to be greater than a power loss threshold when a power factor of the wireless power transfer is greater than a power factor threshold; and refraining from terminating the wireless power transfer at least partially based on the power factor being less than the power factor threshold.
H02J 50/10 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique utilisant un couplage inductif
H02J 50/40 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique utilisant plusieurs dispositifs de transmission ou de réception
H02J 50/60 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique sensibles à la présence d’objets étrangers, p. ex. détection d'êtres vivants
38.
TUNING A SLIDING MODE OBSERVER FOR A PERMANENT MAGNET SYNCHRONOUS MOTOR
A method is provided that may include receiving an identifier of a permanent magnet synchronous motor (PMSM), and mapping the identifier to electrical parameters of the PMSM. The method may include determining one or more coefficients of a sliding mode observer (SMO) based on the electrical parameters. The method may include providing the determined coefficients to the SMO to estimate the rotor position and speed of the PMSM.
N m m m time measurements earlier than the second time measurement. The estimation circuit is to estimate the frequency or period of the clock signal based upon the first sampled window and the second sampled window.
G06F 1/14 - Dispositions pour le contrôle du temps, p. ex. horloge temps réel
G01R 23/02 - Dispositions pour procéder à la mesure de fréquences, p. ex. taux de répétition d'impulsionsDispositions pour procéder à la mesure de la période d'un courant ou d'une tension
40.
APPARATUS AND METHOD FOR CLOCK FREQUENCY ESTIMATION WITH SUBSETS OF TIME MEASUREMENTS
N m m m of the N time measurements. The estimation circuit is to estimate the frequency or period of the clock signal based upon the first sampled window and the second sampled window.
G06F 1/14 - Dispositions pour le contrôle du temps, p. ex. horloge temps réel
G01R 23/02 - Dispositions pour procéder à la mesure de fréquences, p. ex. taux de répétition d'impulsionsDispositions pour procéder à la mesure de la période d'un courant ou d'une tension
41.
DETERMINING HEALTH OF A BLOCK OF A NON-VOLATILE MEMORY DEVICE BASED ON A DISTRIBUTION OF THRESHOLD VOLTAGES
In some implementations, a controller may perform, on one or more wordlines of a block of a non-volatile memory device, read operations using default threshold voltages associated with two overlapped charge states. The controller may determine, using a machine learning model, a distribution of threshold voltages for the two overlapped charge states based on read errors associated with the threshold voltages. The controller may determine, based on the determined distribution of threshold voltages, a health of the block. The controller may perform a block refresh operation for the block based on the health of the block. The block refresh operation may be performed when the health satisfies a health threshold. The block refresh operation may not be performed when the health does not satisfy the health threshold.
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
42.
DISPLACED RECEIVER DETECTION IN A WIRELESS POWER SYSTEM AND RELATED APPARATUSES, METHODS, AND SYSTEMS
A method comprises generating a wireless power signal in one or more transmit coils of a transmitter which inductively couple with one or more receive coils of a receiver for wireless power transfer; terminating the wireless power transfer at least partially responsive to detecting a power loss of the wireless power transfer to be greater than a power loss threshold when a power factor of the wireless power transfer is greater than a power factor threshold; and refraining from terminating the wireless power transfer at least partially based on the power factor being less than the power factor threshold.
H02J 50/12 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique utilisant un couplage inductif du type couplage à résonance
H02J 50/60 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique sensibles à la présence d’objets étrangers, p. ex. détection d'êtres vivants
H02J 50/90 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique mettant en œuvre la détection ou l'optimisation de la position, p. ex. de l'alignement
43.
SILICON CARBIDE DRIVER USING HIGH VOLTAGE CAPACITORS FOR ISOLATION AND SIGNAL TRANSMISSION
A gate driver circuit to receive an input drive signal and output an output drive signal is provided. The gate driver circuit may include a first capacitor having first and second terminals, a second capacitor having first and second terminals, a first set of switches to selectively couple the first terminals of the first and second capacitors to the input drive signal and a power supply voltage, a second set of switches to selectively couple the second terminals of the first and second capacitors to a reference voltage and a high impedance node, and a comparator having a first terminal coupled to the reference voltage and a second terminal coupled to the high impedance node. The comparator may output the output drive signal based on a comparison of the reference voltage and a voltage at the high impedance node.
H03K 17/06 - Modifications pour assurer un état complètement conducteur
H03K 17/689 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ avec une isolation galvanique entre le circuit de commande et le circuit de sortie
H02M 1/08 - Circuits spécialement adaptés à la production d'une tension de commande pour les dispositifs à semi-conducteurs incorporés dans des convertisseurs statiques
44.
DIAGNOSIS OF A SHARED BUS USING INDICATORS APPLIED TO A VECTOR BASED ON THE AMPLITUDE OF AN OBSERVED SIGNAL
Systems and methods for diagnosing a shared bus based on an indicator applied to a vector of amplitudes of signals transmitted over the bus. An aspect provides a method comprising: transmitting a pulse signal over a shared bus; capturing an observed signal, wherein the observed signal is a superimposition of the pulse signal and a reflection signal; comparing an amplitude of the observed signal to a plurality of threshold values; creating a vector indicating a given threshold at which the amplitude of the observed signal first exceeds one of the plurality of threshold values at a plurality of sampling times; applying an indicator to the vector; and diagnosing the shared bus based on the indicator.
A controller may determine, using a machine learning model, reliability characteristic data associated with memory cells of a non-volatile memory device. The machine learning model may be trained using characterization data that identifies different reliability characteristic of one or more non-volatile memory devices. The controller may group, based on the reliability characteristic data, a first portion of the memory cells of the non-volatile memory device in a first management group, and a second portion of the memory cells of the non-volatile memory device in a second management group. The controller may manage, based on the reliability characteristic data, background scanning and logical to physical mapping of the first management group of memory cells, and the second management group of memory cells.
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 29/00 - Vérification du fonctionnement correct des mémoiresTest de mémoires lors d'opération en mode de veille ou hors-ligne
46.
CONTROLLING AN AIR FLOW RATE PROVIDED TO A BURNER BASED ON A CONCENTRATION OF GAS PROVIDED TO THE BURNER
Systems and methods for controlling an air flow rate provided to a burner based on the concentration of one or more gases provided to the burner are disclosed. A method for controlling a burner including receiving a gas concentration value indicating a concentration of one or more gases in a gas mixture provided to a burner; determining, using the gas concentration value, an air flow rate to input to the burner; and controlling the air flow rate provided to the burner based on the determined air flow rate.
F23D 14/02 - Brûleurs à gaz avec prémélangeurs, c.-à-d. dans lesquels le combustible gazeux est mélangé à l'air de combustion en amont de la zone de combustion
F23D 14/22 - Brûleurs à gaz sans prémélangeur, c.-à-d. dans lesquels le combustible gazeux est mélangé à l'air de combustion à l'arrivée dans la zone de combustion avec des conduits d'alimentation en air et en gaz séparés, p. ex. avec des conduits disposés parallèlement ou se croisant
47.
DETERMINING HEALTH OF A BLOCK OF A NON-VOLATILE MEMORY DEVICE BASED ON A DISTRIBUTION OF THRESHOLD VOLTAGES
In some implementations, a controller may perform, on one or more wordlines of a block of a non-volatile memory device, read operations using default threshold voltages associated with two overlapped charge states. The controller may determine, using a machine learning model, a distribution of threshold voltages for the two overlapped charge states based on read errors associated with the threshold voltages. The controller may determine, based on the determined distribution of threshold voltages, a health of the block. The controller may perform a block refresh operation for the block based on the health of the block. The block refresh operation may be performed when the health satisfies a health threshold. The block refresh operation may not be performed when the health does not satisfy the health threshold.
In some implementations, a controller may receive a request for an inference. The controller may determine, based on the received request for the inference, a first inference model of a plurality of inference models, to generate the inference. The controller may obtain, from a memory associated with an inference cache, first attribute data regarding first attributes of the first inference model. A location of the first attribute data, in the memory, may be determined using the inference cache. The attributes may include weights associated with the first inference model, biases associated with the first inference model, and a structure of the first inference model. The controller may utilize the first attribute data to generate the inference based on the request.
Systems and methods for communicating brain waves or control signals via body communication from the brain to body extremities to control or activate body parts or even external devices. An EEG coupler/transceiver couples to a person's scalp, wherein the EEG coupler/transceiver comprises an EEG electrode to receive a brain wave from the person, an EEG body communication coupler and an EEG antenna to transmit a signal via the EEG body communication coupler. An activator coupler/transceiver couples to the person's body to stimulate a muscle of the person's body, wherein the activator coupler/transceiver comprises a muscle activator, an activator body communication coupler, and an activator antenna to receive the signal via the activator body communication coupler.
A61N 1/36 - Application de courants électriques par électrodes de contact courants alternatifs ou intermittents pour stimuler, p. ex. stimulateurs cardiaques
H04B 13/00 - Systèmes de transmission caractérisés par le milieu utilisé pour la transmission, non prévus dans les groupes
50.
DETERMINING DATA RETENTION DEGRADATION OF A NON-VOLATILE MEMORY DEVICE BASED ON A MACHINE LEARNING ALGORITHM
A controller, of a solid state drive (SSD), may perform, on one or more blocks of a non-volatile memory device of the SSD, read operations using pre-determined threshold voltages associated with two overlapped charge states. The read operations may be performed after a power-on condition following a power-off condition on the non-volatile memory device. The controller may determine, using a machine learning model, a change in threshold voltages associated with the two overlapped charge states, after the power-off condition. The machine learning model may determine the change in threshold voltages using bit error rates associated with the read operations. The machine learning model may be trained to determine changes in threshold voltages for the two overlapped charge states, after power-off conditions. The controller may determine adjusted threshold voltages associated with the two overlapped charge states based on the change in threshold voltages.
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 29/02 - Détection ou localisation de circuits auxiliaires défectueux, p. ex. compteurs de rafraîchissement défectueux
G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p. ex. de tension, de courant, de phase, de fréquence
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
51.
DIAGNOSIS OF A SHARED BUS USING INDICATORS APPLIED TO A VECTOR BASED ON THE AMPLITUDE OF AN OBSERVED SIGNAL
Systems and methods for diagnosing a shared bus based on an indicator applied to a vector of amplitudes of signals transmitted over the bus. An aspect provides a method comprising: transmitting a pulse signal over a shared bus; capturing an observed signal, wherein the observed signal is a superimposition of the pulse signal and a reflection signal; comparing an amplitude of the observed signal to a plurality of threshold values; creating a vector indicating a given threshold at which the amplitude of the observed signal first exceeds one of the plurality of threshold values at a plurality of sampling times; applying an indicator to the vector; and diagnosing the shared bus based on the indicator.
G06F 11/22 - Détection ou localisation du matériel d'ordinateur défectueux en effectuant des tests pendant les opérations d'attente ou pendant les temps morts, p. ex. essais de mise en route
G06F 11/277 - Matériel de test, c.-à-d. circuits de traitement de signaux de sortie avec une comparaison entre la réponse effective et la réponse connue en l'absence d'erreur
52.
PREDICTION OF DATA RETENTION DEGRADATION OF A NON-VOLATILE MEMORY DEVICE BASED ON A MACHINE LEARNING ALGORITHM
A controller, of a solid state drive (SSD), may perform, on one or more blocks of a non-volatile memory device of the SSD, read operations using pre-determined threshold voltages associated with two overlapped charge states. The read operations may be performed after a power-on condition following a power-off condition on the non-volatile memory device. The controller may determine, using a machine learning model, a change in threshold voltages associated with the two overlapped charge states, after the power-off condition. The machine learning model may determine the change in threshold voltages using bit error rates associated with the read operations. The machine learning model may be trained to determine changes in threshold voltages for the two overlapped charge states, after power-off conditions. The controller may determine adjusted threshold voltages associated with the two overlapped charge states based on the change in threshold voltages.
A controller may determine, using a machine learning model, reliability characteristic data associated with memory cells of a non-volatile memory device. The machine learning model may be trained using characterization data that identifies different reliability characteristic of one or more non-volatile memory devices. The controller may group, based on the reliability characteristic data, a first portion of the memory cells of the non-volatile memory device in a first management group, and a second portion of the memory cells of the non-volatile memory device in a second management group. The controller may manage, based on the reliability characteristic data, background scanning and logical to physical mapping of the first management group of memory cells, and the second management group of memory cells.
G06F 12/06 - Adressage d'un bloc physique de transfert, p. ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
54.
DEVICE AND METHODS FOR RECONFIGURABLE ANALOG INPUT MONITORING
An ADC system may include an ADC, a comparator, a voltage source, a comparator output polarity control circuit and a comparator output counter. An analog input signal may be input to a first input of the comparator, and an output of the voltage source may be input to a second input of the comparator. The comparator may generate an output to the comparator output polarity control circuit, and the comparator output counter may count clock cycles while the comparator output is asserted and may assert a monitor output based on the comparator output counter value. The monitor output may be an interrupt, an alarm or other system alerts and may control system operation.
In some implementations, a controller may receive a request for an inference. The controller may determine, based on the received request for the inference, a first inference model of a plurality of inference models, to generate the inference. The controller may obtain, from a memory associated with an inference cache, first attribute data regarding first attributes of the first inference model. A location of the first attribute data, in the memory, may be determined using the inference cache. The attributes may include weights associated with the first inference model, biases associated with the first inference model, and a structure of the first inference model. The controller may utilize the first attribute data to generate the inference based on the request.
G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
G06F 12/0864 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache utilisant des moyens pseudo-associatifs, p. ex. associatifs d’ensemble ou de hachage
G06F 12/123 - Commande de remplacement utilisant des algorithmes de remplacement avec listes d’âge, p. ex. file d’attente, liste du type le plus récemment utilisé [MRU] ou liste du type le moins récemment utilisé [LRU]
G06F 12/0875 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache avec mémoire cache dédiée, p. ex. instruction ou pile
56.
MULTI-TURN COIL STRUCTURE INCLUDING CROSSOVER CONNECTIONS FOR INDUCTIVE ANGULAR-POSITION SENSOR
An apparatus includes a support structure and a sense coil comprising conductive traces on, or in, multiple layers of the support structure. The sense coil includes a first coil portion, a second coil portion, and first and second crossover connections. The first coil portion has M turns defining one or more in-phase lobes and the second coil portion has N turns defining one or more out-of-phase lobes. The first crossover connection connects an ending portion of an Mth turn of the first coil portion of an in-phase lobe to a starting portion of a first turn of the second coil portion of an out-of-phase lobe. The second crossover connection connects an ending portion of an Nth turn of the second coil portion of the out-of-phase lobe to a starting portion of a first turn of the first coil portion of the in-phase lobe.
G01D 5/20 - Moyens mécaniques pour le transfert de la grandeur de sortie d'un organe sensibleMoyens pour convertir la grandeur de sortie d'un organe sensible en une autre variable, lorsque la forme ou la nature de l'organe sensible n'imposent pas un moyen de conversion déterminéTransducteurs non spécialement adaptés à une variable particulière utilisant des moyens électriques ou magnétiques influençant la valeur d'un courant ou d'une tension en faisant varier l'inductance, p. ex. une armature mobile
57.
GS) VOLTAGE OF A SILICON CARBIDE (SIC) FIELD-EFFECT TRANSISTOR (FET)
An apparatus may include a Silicon Carbide, SiC, Field-Effect Transistor, FET (110), and a sense buffer circuit (102). The sense buffer circuit may sense a gate-to-source voltage, VGS, of the SiC FET. The sense buffer circuit may include a buffer circuit (104) at an input of the sense buffer circuit. The buffer circuit may have a smaller input voltage range than the sense buffer circuit.
H03K 17/0412 - Modifications pour accélérer la commutation sans réaction du circuit de sortie vers le circuit de commande par des dispositions prises dans le circuit de commande
H03K 17/16 - Modifications pour éliminer les tensions ou courants parasites
H03K 19/003 - Modifications pour accroître la fiabilité
A method may include obtaining samples associated with one or more symbols of a packet; determining at least one down-sampling point in a sequence of samples associated with a header portion of the packet; and utilizing samples associated with the determined down-sampling point to recover the one or more symbol and subsequent symbols.
An apparatus includes a support structure and a sense coil comprising conductive traces on, or in, multiple layers of the support structure. The sense coil includes a first coil portion, a second coil portion, and first and second crossover connections. The first coil portion has M turns defining one or more in-phase lobes and the second coil portion has N turns defining one or more out-of-phase lobes. The first crossover connection connects an ending portion of an Mth turn of the first coil portion of an in-phase lobe to a starting portion of a first turn of the second coil portion of an out-of-phase lobe. The second crossover connection connects an ending portion of an Nth turn of the second coil portion of the out-of-phase lobe to a starting portion of a first turn of the first coil portion of the in-phase lobe.
H01F 27/00 - Détails de transformateurs ou d'inductances, en général
G01B 7/30 - Dispositions pour la mesure caractérisées par l'utilisation de techniques électriques ou magnétiques pour mesurer des angles ou des cônesDispositions pour la mesure caractérisées par l'utilisation de techniques électriques ou magnétiques pour tester l'alignement des axes
H01F 5/04 - Dispositions des connexions électriques aux bobines, p. ex. fils de connexion
H01F 17/02 - Inductances fixes du type pour signaux sans noyau magnétique
60.
DEVICE AND METHODS FOR RECONFIGURABLE ANALOG INPUT MONITORING
An ADC system may include an ADC, a comparator, a voltage source, a comparator output polarity control circuit and a comparator output counter. An analog input signal may be input to a first input of the comparator, and an output of the voltage source may be input to a second input of the comparator. The comparator may generate an output to the comparator output polarity control circuit, and the comparator output counter may count clock cycles while the comparator output is asserted and may assert a monitor output based on the comparator output counter value. The monitor output may be an interrupt, an alarm or other system alerts and may control system operation.
A multi-channel ADC system may include a plurality of input channels coupled to input signals. A multiplexer may couple one or more of the plurality of input channels to one or more multiplexer output channels. A control circuit may be coupled between the multiplexer output channels and an ADC. In operation, a configuration setting may configure the multi-channel ADC system in one of a plurality of configurations, including but not limited to single-ended, differential, pseudo-differential and hybrid configurations. The ADC may convert the plurality of input channels based on the configuration setting.
An apparatus may include a Silicon Carbide (SiC) Field-Effect Transistor (PET) and a sense buffer circuit. The sense buffer circuit may sense a gate-to-source voltage (VGS) of the SiC PET. The sense buffer circuit may include a buffer circuit at an input of the sense buffer circuit. The buffer circuit may have a smaller input voltage range than the sense buffer circuit.
H03K 17/687 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
63.
EMI Reduction in PLCA-Based Networks Through Beacon Temporal Spreading
An apparatus may be communicatively coupled to other nodes in a network. The apparatus may include a control circuit configured to repeatedly issue transmission cycles to the other nodes. A given transmission cycle may include a least one send slot for each of the other nodes to send data. The control circuit may be configured to initiate transmission cycles by issuing beacon signals to the other nodes. The control circuit may be configured to determine when to issue a beacon signal in a given transmission cycle by determining that all of the other nodes have completed all associated send slots in an immediately previous transmission cycle and based upon a determination of the completion of the other nodes' transmission, delaying transmission of the beacon signal for the given transmission cycle.
H04L 12/413 - Réseaux à ligne bus avec commande décentralisée avec accès aléatoire, p. ex. accès multiple avec détection de porteuse et détection de collision [CSMA-CD]
A method may include obtaining samples associated with one or more symbols of a packet; determining at least one down-sampling point in a sequence of samples associated with a header portion of the packet; and utilizing samples associated with the determined down-sampling point to recover the one or more symbol and subsequent symbols
A smart cable for backplane storage management is provided. The cable may include a microcontroller, a power conditioning circuitry to regulate an input voltage from a power supply and provide an output voltage to the microcontroller, a storage device coupled to the microcontroller, a first end to be coupled to one or more storage devices, and a second end to be coupled to a storage controller. The microcontroller may receive sideband signals from the one or more storage drives, and may transmit connection topology information to the storage controller based at least in part on the sideband signals.
A multi-channel ADC system may include a plurality of input channels coupled to input signals. A multiplexer may couple one or more of the plurality of input channels to one or more multiplexer output channels. A control circuit may be coupled between the multiplexer output channels and an ADC. In operation, a configuration setting may configure the multi-channel ADC system in one of a plurality of configurations, including but not limited to single-ended, differential, pseudo-differential and hybrid configurations. The ADC may convert the plurality of input channels based on the configuration setting.
A smart cable for backplane storage management is provided. The cable may include a microcontroller, a power conditioning circuitry to regulate an input voltage from a power supply and provide an output voltage to the microcontroller, a storage device coupled to the microcontroller, a first end to be coupled to one or more storage devices, and a second end to be coupled to a storage controller. The microcontroller may receive sideband signals from the one or more storage drives, and may transmit connection topology information to the storage controller based at least in part on the sideband signals.
In one example, a method of a transceiver comprises receiving a first communication signal including a first message; detecting a signal strength of the first communication signal; generating a preamble having a preamble bit length that is adjusted at least partially based on the detected signal strength of the first communication signal; and transmitting a second communication signal including a second message, the second message including the preamble having the preamble bit length.
H04W 52/24 - Commande de puissance d'émission [TPC Transmission power control] le TPC étant effectué selon des paramètres spécifiques utilisant le rapport signal sur parasite [SIR Signal to Interference Ratio] ou d'autres paramètres de trajet sans fil
An apparatus including a power circuit to receive power from a power supply of a life safety device, and at least one control circuit powered by the power circuit. The control circuit to, in a calibration mode, receive a signal from an ambient light sensor and determine a baseline ambient light level based on the signal from the ambient light sensor. The control circuit to, in a proximity detection mode, receive another signal from the ambient light sensor, compare the other signal from the ambient light sensor to the baseline ambient light level, determine with an analysis that a difference in ambient light from the baseline ambient light level indicates a presence of an object in proximity to the life safety device, and issue an alert indicating the presence of the object in proximity to the life safety device based at least in part on the analysis.
A moisture resistant semiconductor device may include a substrate and a plurality of terminations in the substrate of the semiconductor device, wherein the plurality of terminations are laterally adjacent to an active region of the semiconductor device. A first insulating layer which overlays the plurality of terminations and the substrate. A trench into the substrate located laterally beyond an edge of the plurality of terminations. A contact layer which overlays the first insulating layer. A second insulating layer which overlays the contact layer. The second insulating layer which overlays the trench. A third insulating layer which overlays the second insulating layer.
An apparatus including a power circuit to receive power from a power supply of a life safety device, and at least one control circuit powered by the power circuit. The control circuit to, in a calibration mode, receive a signal from an ambient light sensor and determine a baseline ambient light level based on the signal from the ambient light sensor. The control circuit to, in a proximity detection mode, receive another signal from the ambient light sensor, compare the other signal from the ambient light sensor to the baseline ambient light level, determine with an analysis that a difference in ambient light from the baseline ambient light level indicates a presence of an object in proximity to the life safety device, and issue an alert indicating the presence of the object in proximity to the life safety device based at least in part on the analysis.
In one example, a method of a transceiver comprises receiving a first communication signal including a first message; detecting a signal strength of the first communication signal; generating a preamble having a preamble bit length that is adjusted at least partially based on the detected signal strength of the first communication signal; and transmitting a second communication signal including a second message, the second message including the preamble having the preamble bit length.
H04W 72/542 - Critères d’affectation ou de planification des ressources sans fil sur la base de critères de qualité en utilisant la qualité mesurée ou perçue
A moisture resistant semiconductor device (10) may include a substrate (15) and a plurality of terminations (20) in the substrate of the semiconductor device, wherein the plurality of terminations are laterally adjacent to an active region (18) of the semiconductor device. A first insulating layer (30) which overlays the plurality of terminations and the substrate. A trench (70) into the substrate located laterally beyond an edge of the plurality of terminations. A contact layer (40) which overlays the first insulating layer. A second insulating layer (50) which overlays the contact layer. The second insulating layer which overlays the trench. A third insulating layer (60) which overlays the second insulating layer.
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée
A device may have a reference divider circuit to divide a reference clock, a phase-frequency detector circuit to detect a detected phase difference and a detected frequency difference based on the reference divider output and a feedback clock, a loop filter circuit to filter the detector output, a voltage controlled oscillator (VCO) control output pin coupled to the loop filter output, a VCO clock divider control output pin to select a divisor of an external clock divider circuit, a divided VCO clock input pin for coupling to an output of the external clock divider circuit, a pulse-width modulation (PWM) circuit having a PWM clock input coupled to the divided VCO clock input pin, a period register to store a period value, a duty cycle register to store a duty cycle value and a pulse-width modulated output based on the period value and the duty cycle value.
H03L 7/193 - Synthèse de fréquence indirecte, c.-à-d. production d'une fréquence désirée parmi un certain nombre de fréquences prédéterminées en utilisant une boucle verrouillée en fréquence ou en phase en utilisant un diviseur de fréquence ou un compteur dans la boucle une différence de temps étant utilisée pour verrouiller la boucle, le compteur entre des nombres fixes ou le diviseur de fréquence divisant par un nombre fixe le compteur/diviseur de fréquence comportant un prédiviseur commutable, p. ex. un diviseur à double module
H03L 7/18 - Synthèse de fréquence indirecte, c.-à-d. production d'une fréquence désirée parmi un certain nombre de fréquences prédéterminées en utilisant une boucle verrouillée en fréquence ou en phase en utilisant un diviseur de fréquence ou un compteur dans la boucle
H03L 7/089 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie le détecteur de phase ou de fréquence engendrant des impulsions d'augmentation ou de diminution
H03L 7/091 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie le détecteur de phase ou de fréquence utilisant un dispositif d'échantillonnage
H03L 7/093 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie utilisant des caractéristiques de filtrage ou d'amplification particulières dans la boucle
H03L 7/14 - Détails de la boucle verrouillée en phase pour assurer une fréquence constante quand la tension d'alimentation ou la tension de correction fait défaut
A bias circuit may generate a one or more bias outputs for a crystal oscillator. The bias circuit may include a first current mirror, a second current mirror and a third current mirror. A capacitor may be coupled between the second current mirror and the third current mirror. In operation, a first bias output may be generated by the third current mirror, and a second bias output may be generated by the second current mirror. The first bias output and second bias output may be coupled to a crystal oscillator.
H03B 5/36 - Production d'oscillation au moyen d'un amplificateur comportant un circuit de réaction entre sa sortie et son entrée l'élément déterminant la fréquence étant un résonateur électromécanique un résonateur piézo-électrique l'élément actif de l'amplificateur comportant un dispositif semi-conducteur
A bias circuit may generate a one or more bias outputs for a crystal oscillator. The bias circuit may include a first current mirror, a second current mirror and a third current mirror. A capacitor may be coupled between the second current mirror and the third current mirror. In operation, a first bias output may be generated by the third current mirror, and a second bias output may be generated by the second current mirror. The first bias output and second bias output may be coupled to a crystal oscillator.
H03B 5/32 - Production d'oscillation au moyen d'un amplificateur comportant un circuit de réaction entre sa sortie et son entrée l'élément déterminant la fréquence étant un résonateur électromécanique un résonateur piézo-électrique
77.
PREDICTIVE BEAMFORMING ANTENNA AND METHOD OF CONTROLLING SAME
An apparatus that includes a beamforming antenna is provided. The apparatus may include a predictive calculator processing unit to receive position information of one or more airborne receivers, determine future position information of the one or more airborne receivers as a function of time based on the received position information, and determine beamforming antenna parameters. The apparatus may include an antenna instruction processing unit to receive the beamforming antenna parameters and generate beamforming instructions based on the beamforming antenna parameters, a beamforming antenna to receive the beamforming instructions, and to generate a beam at a specified time based on the beamforming instructions to enable communication with at least one of the one or more airborne receivers, and a receiver processing unit to receive airborne receiver data from the at least one of the one or more airborne receivers, and generate output data based on the airborne receiver data.
H04B 7/08 - Systèmes de diversitéSystèmes à plusieurs antennes, c.-à-d. émission ou réception utilisant plusieurs antennes utilisant plusieurs antennes indépendantes espacées à la station de réception
H04B 7/06 - Systèmes de diversitéSystèmes à plusieurs antennes, c.-à-d. émission ou réception utilisant plusieurs antennes utilisant plusieurs antennes indépendantes espacées à la station d'émission
H04W 64/00 - Localisation d'utilisateurs ou de terminaux pour la gestion du réseau, p. ex. gestion de la mobilité
78.
PULSE WIDTH MODULATION CIRCUIT TO GENERATE A FEEDBACK CLOCK
A device may have a reference divider circuit to divide a reference clock, a phase-frequency detector circuit to detect a detected phase difference and a detected frequency difference based on the reference divider output and a feedback clock, a loop filter circuit to filter the detector output, a voltage controlled oscillator (VCO) control output pin coupled to the loop filter output, a VCO clock divider control output pin to select a divisor of an external clock divider circuit, a divided VCO clock input pin for coupling to an output of the external clock divider circuit, a pulse-width modulation (PWM) circuit having a PWM clock input coupled to the divided VCO clock input pin, a period register to store a period value, a duty cycle register to store a duty cycle value and a pulse-width modulated output based on the period value and the duty cycle value.
H03L 7/099 - Détails de la boucle verrouillée en phase concernant principalement l'oscillateur commandé de la boucle
H03K 5/156 - Dispositions dans lesquelles un train d'impulsions est transformé en un train ayant une caractéristique désirée
H03L 7/093 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie utilisant des caractéristiques de filtrage ou d'amplification particulières dans la boucle
H03L 7/18 - Synthèse de fréquence indirecte, c.-à-d. production d'une fréquence désirée parmi un certain nombre de fréquences prédéterminées en utilisant une boucle verrouillée en fréquence ou en phase en utilisant un diviseur de fréquence ou un compteur dans la boucle
79.
PREDICTIVE BEAMFORMING ANTENNA AND METHOD OF CONTROLLING SAME
An apparatus that includes a beamforming antenna is provided. The apparatus may include a predictive calculator processing unit to receive position information of one or more airborne receivers, determine future position information of the one or more airborne receivers as a function of time based on the received position information, and determine beamforming antenna parameters. The apparatus may include an antenna instruction processing unit to receive the beamforming antenna parameters and generate beamforming instructions based on the beamforming antenna parameters, a beamforming antenna to receive the beamforming instructions, and to generate a beam at a specified time based on the beamforming instructions to enable communication with at least one of the one or more airborne receivers, and a receiver processing unit to receive airborne receiver data from the at least one of the one or more airborne receivers, and generate output data based on the airborne receiver data.
H04W 4/02 - Services utilisant des informations de localisation
H01Q 3/26 - Dispositifs pour changer ou faire varier l'orientation ou la forme du diagramme de directivité des ondes rayonnées par une antenne ou un système d'antenne faisant varier la phase relative ou l’amplitude relative et l’énergie d’excitation entre plusieurs éléments rayonnants actifsDispositifs pour changer ou faire varier l'orientation ou la forme du diagramme de directivité des ondes rayonnées par une antenne ou un système d'antenne faisant varier la distribution de l’énergie à travers une ouverture rayonnante
H04B 7/06 - Systèmes de diversitéSystèmes à plusieurs antennes, c.-à-d. émission ou réception utilisant plusieurs antennes utilisant plusieurs antennes indépendantes espacées à la station d'émission
H04B 7/08 - Systèmes de diversitéSystèmes à plusieurs antennes, c.-à-d. émission ou réception utilisant plusieurs antennes utilisant plusieurs antennes indépendantes espacées à la station de réception
B64G 1/10 - Satellites artificielsSystèmes de tels satellitesVéhicules interplanétaires
80.
INDUCTIVE SENSOR DEVICE WITH INDUCTOR COIL FORMED IN REDISTRIBUTION LAYER (RDL) REGION
An inductive sensor device includes at least one die mounted in or on a substrate, a redistribution layer (RDL) region formed over the at least one die and including multiple RDL metal layers, and at least one inductive coil formed in the RDL region and including at least one conductive coil element formed in at least one RDL metal layer of the multiple RDL metal layers, wherein the at least one die includes sensor circuitry connected to the at least one inductive coil to perform sensor measurements.
G01D 5/20 - Moyens mécaniques pour le transfert de la grandeur de sortie d'un organe sensibleMoyens pour convertir la grandeur de sortie d'un organe sensible en une autre variable, lorsque la forme ou la nature de l'organe sensible n'imposent pas un moyen de conversion déterminéTransducteurs non spécialement adaptés à une variable particulière utilisant des moyens électriques ou magnétiques influençant la valeur d'un courant ou d'une tension en faisant varier l'inductance, p. ex. une armature mobile
G01B 7/30 - Dispositions pour la mesure caractérisées par l'utilisation de techniques électriques ou magnétiques pour mesurer des angles ou des cônesDispositions pour la mesure caractérisées par l'utilisation de techniques électriques ou magnétiques pour tester l'alignement des axes
An input signal may be converted into a first PWM signal and a second PWM signal at a PWM controller circuit. The first PWM signal and second signal output may drive a driver circuit. The driver circuit may receive a high-voltage supply from a boost converter or other power circuit. The driver circuit may include a high-side device and a low-side device. The output of the driver circuit may drive a filter circuit, the filter circuit comprising a filter capacitor, an inductor and a haptic actuator. The haptic actuator may produce a desired haptic response at the haptic actuator.
H03F 3/217 - Amplificateurs de puissance de classe DAmplificateurs à commutation
H10N 30/20 - Dispositifs piézo-électriques ou électrostrictifs à entrée électrique et sortie mécanique, p. ex. fonctionnant comme actionneurs ou comme vibrateurs
82.
INDUCTIVE SENSOR DEVICE WITH INDUCTOR COIL FORMED IN REDISTRIBUTION LAYER (RDL) REGION
An inductive sensor device includes at least one die mounted in or on a substrate, a redistribution layer (RDL) region formed over the at least one die and including multiple RDL metal layers, and at least one inductive coil formed in the RDL region and including at least one conductive coil element formed in at least one RDL metal layer of the multiple RDL metal layers, wherein the at least one die includes sensor circuitry connected to the at least one inductive coil to perform sensor measurements.
G01D 5/20 - Moyens mécaniques pour le transfert de la grandeur de sortie d'un organe sensibleMoyens pour convertir la grandeur de sortie d'un organe sensible en une autre variable, lorsque la forme ou la nature de l'organe sensible n'imposent pas un moyen de conversion déterminéTransducteurs non spécialement adaptés à une variable particulière utilisant des moyens électriques ou magnétiques influençant la valeur d'un courant ou d'une tension en faisant varier l'inductance, p. ex. une armature mobile
An input signal may be converted into a first PWM signal and a second PWM signal at a PWM controller circuit. The first PWM signal and second signal output may drive a driver circuit. The driver circuit may receive a high-voltage supply from a boost converter or other power circuit. The driver circuit may include a high-side device and a low-side device. The output of the driver circuit may drive a filter circuit, the filter circuit comprising a filter capacitor, an inductor and a haptic actuator. The haptic actuator may produce a desired haptic response at the haptic actuator.
A method for using a LIDAR-equipped projectile for three-dimensional mapping including sending a signal to a light source to cause the light source to emit a plurality of light pulses, the light source located on a spinning projectile proceeding along a predetermined path; receiving, at the spinning projectile, a plurality of reflected light pulses responsive to the plurality of light pulses reflecting off an object or a terrain portion; determining a distance of the object or the terrain portion from the light source; and generating a three-dimensional map of the object based on the determined distance of the object or the terrain portion from the light source.
G01S 17/10 - Systèmes déterminant les données relatives à la position d'une cible pour mesurer la distance uniquement utilisant la transmission d'ondes à modulation d'impulsion interrompues
A method includes performing a pressing operation on a volume of silicon carbide (SiC) powder to form a polycrystalline SiC (poly-SiC) ingot, and divide the poly-SiC ingot into a plurality of poly-SiC wafer bases. The method further includes, for a respective poly-SiC wafer base, bonding a silicon (Si) wafer structure to the respective poly-SiC wafer base to define a hybrid Si/poly-SiC stack structure, and performing a dividing process to remove a partial thickness of the Si wafer structure from the hybrid Si/poly-SiC stack structure to provide a hybrid Si/poly-SiC wafer comprising a remaining portion of the Si wafer structure bonded to the respective poly-SiC wafer base.
H01L 21/00 - Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de dispositifs à semi-conducteurs ou de dispositifs à l'état solide, ou bien de leurs parties constitutives
A transistor that may include a substrate, a drain layer formed within the substrate at a first side of the substrate. A first well implant having a first implant depth, a second well implant having a second implant depth and a third well implant having a third implant depth. The first well implant, the second well implant and the third well implant formed within the substrate at the second side of the substrate. The second implant depth is greater than the first implant depth and the third implant depth is greater than the second implant depth. A gate formed at the second side of the substrate. The gate overlaps the first well implant by a first distance, the gate overlaps the second well implant by a second distance and the gate overlaps the third well implant by a third distance.
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 21/04 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives les dispositifs ayant des barrières de potentiel, p. ex. une jonction PN, une région d'appauvrissement ou une région de concentration de porteurs de charges
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/66 - Types de dispositifs semi-conducteurs
87.
LOCATING AN EMS UNIT CLOSEST TO A SOURCE OF A DISTRESS SIGNAL AND NOTIFYING PROXIMATE PERSONAL DEVICES
A method for distress signal monitoring with EMS and public notification in crowded public spaces. The method includes receiving a distress signal from a first personal device in a crowded public space; locating the first personal device closest to an EMS unit indicating that a user of the first personal device is in distress; transmitting a location of the first personal device to the EMS unit; identifying a second personal device proximate to the first personal device; and transmitting a notification signal to the second personal device indicating that a person is in distress.
G08B 25/01 - Systèmes d'alarme dans lesquels l'emplacement du lieu où existe la condition déclenchant l'alarme est signalé à une station centrale, p. ex. systèmes télégraphiques d'incendie ou de police caractérisés par le moyen de transmission
G08B 27/00 - Systèmes d'alarme dans lesquels la condition déclenchant l'alarme est signalée par une station centrale à plusieurs sous-stations
88.
THREE-DIMENSIONAL MAPPING USING A LIDAR-EQUIPPED SPINNING PROJECTILE
A method for using a LIDAR-equipped projectile for three-dimensional mapping including sending a signal to a light source to cause the light source to emit a plurality of light pulses, the light source located on a spinning projectile proceeding along a predetermined path; receiving, at the spinning projectile, a plurality of reflected light pulses responsive to the plurality of light pulses reflecting off an object or a terrain portion; determining a distance of the object or the terrain portion from the light source; and generating a three-dimensional map of the object based on the determined distance of the object or the terrain portion from the light source.
F41G 3/02 - Dispositifs de pointage utilisant une ligne de visée indépendante, p. ex. télépointeur
F42B 12/36 - Projectiles ou mines caractérisés par la charge militaire, l'effet recherché ou le matériau caractérisés par la nature de la charge militaire ou par l'effet recherché pour libérer des matériaux, des corps ou des particulesProjectiles ou mines caractérisés par la charge militaire, l'effet recherché ou le matériau caractérisés par la nature de la charge militaire ou par l'effet recherché pour produire une réaction chimique ou physiqueProjectiles ou mines caractérisés par la charge militaire, l'effet recherché ou le matériau caractérisés par la nature de la charge militaire ou par l'effet recherché pour la signalisation
F42B 12/38 - Projectiles ou mines caractérisés par la charge militaire, l'effet recherché ou le matériau caractérisés par la nature de la charge militaire ou par l'effet recherché pour libérer des matériaux, des corps ou des particulesProjectiles ou mines caractérisés par la charge militaire, l'effet recherché ou le matériau caractérisés par la nature de la charge militaire ou par l'effet recherché pour produire une réaction chimique ou physiqueProjectiles ou mines caractérisés par la charge militaire, l'effet recherché ou le matériau caractérisés par la nature de la charge militaire ou par l'effet recherché pour la signalisation du type traçant
F42B 30/00 - Projectiles non prévus ailleurs, caractérisés par la catégorie ou le type de munitions, p. ex. par le lanceur ou l'arme utilisés
G01S 1/00 - Radiophares ou systèmes de balisage émettant des signaux ayant une ou des caractéristiques pouvant être détectées par des récepteurs non directionnels et définissant des directions, situations ou lignes de position déterminées par rapport aux émetteurs de radiophareRécepteurs travaillant avec ces systèmes
G01S 3/00 - Radiogoniomètres pour déterminer la direction d'où proviennent des ondes infrasonores, sonores, ultrasonores ou électromagnétiques ou des émissions de particules sans caractéristiques de direction
G01S 17/86 - Combinaisons de systèmes lidar avec des systèmes autres que lidar, radar ou sonar, p. ex. avec des goniomètres
G01S 17/89 - Systèmes lidar, spécialement adaptés pour des applications spécifiques pour la cartographie ou l'imagerie
F42B 10/26 - Dispositions pour la stabilisation par rotation
G01S 7/481 - Caractéristiques de structure, p. ex. agencements d'éléments optiques
A transistor that may include a substrate, a drain layer formed within the substrate at a first side of the substrate. A first well implant having a first implant depth, a second well implant having a second implant depth and a third well implant having a third implant depth. The first well implant, the second well implant and the third well implant formed within the substrate at the second side of the substrate. The second implant depth is greater than the first implant depth and the third implant depth is greater than the second implant depth. A gate formed at the second side of the substrate. The gate overlaps the first well implant by a first distance, the gate overlaps the second well implant by a second distance and the gate overlaps the third well implant by a third distance.
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
90.
METHOD AND APPARATUS FOR PRECHARGING DC-LINK CAPACITOR IN HIGH-VOLTAGE DC DISTRIBUTION SYSTEM
A pre-charging circuit for charging a DC-link capacitor is provided. The pre-charging circuit may include a first semiconductor switch to be coupled to a first terminal of a high voltage source, a first inductor to be coupled to the first semiconductor switch and a first terminal of a capacitor, a second semiconductor switch to be coupled to a second terminal of the high voltage source, a second inductor to be coupled to the second semiconductor switch and a second terminal of the capacitor, and a diode coupled to the first semiconductor switch, the second semiconductor switch, the first inductor, and the second inductor, and coupled in parallel with the capacitor.
A method includes performing a pressing operation on a volume of silicon carbide (SiC) powder to form a polycrystalline SiC (poly-SiC) ingot, and divide the poly-SiC ingot into a plurality of poly-SiC wafer bases. The method further includes, for a respective poly-SiC wafer base, bonding a silicon (Si) wafer structure to the respective poly-SiC wafer base to define a hybrid Si/poly-SiC stack structure, and performing a dividing process to remove a partial thickness of the Si wafer structure from the hybrid Si/poly-SiC stack structure to provide a hybrid Si/poly-SiC wafer comprising a remaining portion of the Si wafer structure bonded to the respective poly-SiC wafer base.
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
H01L 29/04 - Corps semi-conducteurs caractérisés par leur structure cristalline, p.ex. polycristalline, cubique ou à orientation particulière des plans cristallins
H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
92.
DEVICE AND METHODS FOR FUNCTIONAL DESCRIPTOR-BASED DMA CONTROLLER
A microcontroller may include a DMA controller, a pattern matching circuit and a memory. The DMA controller may read a first descriptor word in the memory at a location addressed by a first descriptor pointer, and may move an input word from a location in the memory addressed by a source payload pointer to a location in the memory addressed by a destination payload pointer. The pattern matching circuit may perform a pattern matching operation based on the input word and one or more register values. The first descriptor pointer may be modified based on the results of the pattern matching circuit and may generate a second descriptor pointer value.
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p. ex. acces direct à la mémoire, vol de cycle
93.
DEVICE AND METHOD FOR PIPELINED MULTIPLY-ACCUMULATOR
A circuit may include a vector arithmetic logic unit (ALU), the vector ALU comprising a multiplier, a first multiplexer, a second multiplexer and an accumulator. The vector ALU may compute a dot product of two or more vector inputs. A system may include two or more vector ALUs, and may partition a vector input into multiple segments. Each segment may be input to a respective vector ALU via a multiplexer, and a controller may route the partial sums of respective ALUs via one or more feedback paths and the system may compute the complete dot product of the vector inputs.
G06F 7/544 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs n'établissant pas de contact, p. ex. tube, dispositif à l'état solideMéthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul
94.
METHOD AND APPARATUS FOR PRE-CHARGING DC-LINK CAPACITOR IN HIGH VOLTAGE DC DISTRIBUTION SYSTEM
A pre-charging circuit for charging a DC-link capacitor is provided. The pre-charging circuit may include a first semiconductor switch to be coupled to a first terminal of a high voltage source, a first inductor to be coupled to the first semiconductor switch and a first terminal of a capacitor, a second semiconductor switch to be coupled to a second terminal of the high voltage source, a second inductor to be coupled to the second semiconductor switch and a second terminal of the capacitor, and a diode coupled to the first semiconductor switch, the second semiconductor switch, the first inductor, and the second inductor, and coupled in parallel with the capacitor.
H02M 1/36 - Moyens pour mettre en marche ou arrêter les convertisseurs
H02M 3/156 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation
95.
LOCATING AN EMS UNIT CLOSEST TO A SOURCE OF A DISTRESS SIGNAL AND NOTIFYING PROXIMATE PERSONAL DEVICES
A method for distress signal monitoring with EMS and public notification in crowded public spaces. The method includes receiving a distress signal from a first personal device in a crowded public space; locating the first personal device closest to an EMS unit indicating that a user of the first personal device is in distress; transmitting a location of the first personal device to the EMS unit; identifying a second personal device proximate to the first personal device; and transmitting a notification signal to the second personal device indicating that a person is in distress.
G08B 27/00 - Systèmes d'alarme dans lesquels la condition déclenchant l'alarme est signalée par une station centrale à plusieurs sous-stations
G08B 5/36 - Systèmes de signalisation optique, p. ex. systèmes d'appel de personnes, indication à distance de l'occupation de sièges utilisant une transmission électriqueSystèmes de signalisation optique, p. ex. systèmes d'appel de personnes, indication à distance de l'occupation de sièges utilisant une transmission électromécanique utilisant des sources de lumière visible
96.
DEVICE AND METHOD FOR PIPELINED MULTIPLY-ACCUMULATOR
A circuit may include a vector arithmetic logic unit (ALU), the vector ALU comprising a multiplier, a first multiplexer, a second multiplexer and an accumulator. The vector ALU may compute a dot product of two or more vector inputs. A system may include two or more vector ALUs, and may partition a vector input into multiple segments. Each segment may be input to a respective vector ALU via a multiplexer, and a controller may route the partial sums of respective ALUs via one or more feedback paths and the system may compute the complete dot product of the vector inputs.
G06F 7/57 - Unités arithmétiques et logiques [UAL], c.-à-d. dispositions ou dispositifs pour accomplir plusieurs des opérations couvertes par les groupes ou pour accomplir des opérations logiques
G06F 7/544 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs n'établissant pas de contact, p. ex. tube, dispositif à l'état solideMéthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul
97.
TELEMETRY SYSTEM INCLUDING A SENSOR STATION ARRAY AND AN AERIAL DATA COLLECTION SYSTEM
A telemetry system includes an array of sensor stations arranged in a spaced apart arrangement, wherein respective sensor stations include a respective sensor to generate respective sensor data regarding a respective sensed parameter, a respective sensor station memory to store the respective sensor data, a respective sensor station antenna, a respective sensor station wireless transmitter, and a respective sensor station processor to periodically activate the respective sensor station wireless transmitter to transmit the respective sensor data via the respective sensor station antenna. The telemetry system includes an aerial data collection system including an aerial data collection system antenna, and an aerial data collection system receiver to receive the respective sensor data transmitted by the respective sensor station antenna.
G05D 1/00 - Commande de la position, du cap, de l'altitude ou de l'attitude des véhicules terrestres, aquatiques, aériens ou spatiaux, p. ex. utilisant des pilotes automatiques
H04L 67/12 - Protocoles spécialement adaptés aux environnements propriétaires ou de mise en réseau pour un usage spécial, p. ex. les réseaux médicaux, les réseaux de capteurs, les réseaux dans les véhicules ou les réseaux de mesure à distance
H04L 67/141 - Configuration des sessions d'application
H04W 4/02 - Services utilisant des informations de localisation
H04W 4/38 - Services spécialement adaptés à des environnements, à des situations ou à des fins spécifiques pour la collecte d’informations de capteurs
98.
DEVICE AND METHODS FOR FUNCTIONAL DESCRIPTOR-BASED DMA CONTROLLER
A microcontroller may include a DMA controller, a pattern matching circuit and a memory. The DMA controller may read a first descriptor word in the memory at a location addressed by a first descriptor pointer, and may move an input word from a location in the memory addressed by a source payload pointer to a location in the memory addressed by a destination payload pointer. The pattern matching circuit may perform a pattern matching operation based on the input word and one or more register values. The first descriptor pointer may be modified based on the results of the pattern matching circuit and may generate a second descriptor pointer value.
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p. ex. acces direct à la mémoire, vol de cycle
G06F 7/76 - Dispositions pour le réagencement, la permutation ou la sélection de données selon des règles prédéterminées, indépendamment du contenu des données
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
99.
SILICON CARBIDE POWER MOSFET AND METHOD FOR MANUFACTURING SAME
A method of manufacturing a semiconductor device is provided. The method may include implanting a silicon-rich layer on a surface of a silicon carbide substrate, and growing a gate oxide layer on the silicon-rich layer on the surface of the silicon carbide substrate.
H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
100.
HYBRID CHANNEL POWER SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
A semiconductor device is provided. The semiconductor device may include a silicon carbide substrate, a silicon layer formed at a first side of the silicon carbide substrate, a gate oxide layer formed on the silicon layer, a gate terminal formed on the gate oxide layer, a drain terminal formed at a second side of the silicon carbide substrate opposite the first side, and a source terminal formed at the first side of the silicon carbide substrate, and at opposite ends of the silicon layer.
H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/808 - Transistors à effet de champ l'effet de champ étant produit par une jonction PN ou une autre jonction redresseuse à jonction PN
