A method includes performing a pressing operation on a volume of silicon carbide (SiC) powder to form a polycrystalline SiC (poly-SiC) ingot, and divide the poly-SiC ingot into a plurality of poly-SiC wafer bases. The method further includes, for a respective poly-SiC wafer base, bonding a silicon (Si) wafer structure to the respective poly-SiC wafer base to define a hybrid Si/poly-SiC stack structure, and performing a dividing process to remove a partial thickness of the Si wafer structure from the hybrid Si/poly-SiC stack structure to provide a hybrid Si/poly-SiC wafer comprising a remaining portion of the Si wafer structure bonded to the respective poly-SiC wafer base.
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
H01L 29/04 - Corps semi-conducteurs caractérisés par leur structure cristalline, p.ex. polycristalline, cubique ou à orientation particulière des plans cristallins
H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
2.
METHOD AND APPARATUS FOR PRECHARGING DC-LINK CAPACITOR IN HIGH-VOLTAGE DC DISTRIBUTION SYSTEM
A pre-charging circuit for charging a DC-link capacitor is provided. The pre-charging circuit may include a first semiconductor switch to be coupled to a first terminal of a high voltage source, a first inductor to be coupled to the first semiconductor switch and a first terminal of a capacitor, a second semiconductor switch to be coupled to a second terminal of the high voltage source, a second inductor to be coupled to the second semiconductor switch and a second terminal of the capacitor, and a diode coupled to the first semiconductor switch, the second semiconductor switch, the first inductor, and the second inductor, and coupled in parallel with the capacitor.
A pre-charging circuit for charging a DC-link capacitor is provided. The pre-charging circuit may include a first semiconductor switch to be coupled to a first terminal of a high voltage source, a first inductor to be coupled to the first semiconductor switch and a first terminal of a capacitor, a second semiconductor switch to be coupled to a second terminal of the high voltage source, a second inductor to be coupled to the second semiconductor switch and a second terminal of the capacitor, and a diode coupled to the first semiconductor switch, the second semiconductor switch, the first inductor, and the second inductor, and coupled in parallel with the capacitor.
H02M 1/36 - Moyens pour mettre en marche ou arrêter les convertisseurs
H02M 3/156 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation
4.
DEVICE AND METHOD FOR PIPELINED MULTIPLY-ACCUMULATOR
A circuit may include a vector arithmetic logic unit (ALU), the vector ALU comprising a multiplier, a first multiplexer, a second multiplexer and an accumulator. The vector ALU may compute a dot product of two or more vector inputs. A system may include two or more vector ALUs, and may partition a vector input into multiple segments. Each segment may be input to a respective vector ALU via a multiplexer, and a controller may route the partial sums of respective ALUs via one or more feedback paths and the system may compute the complete dot product of the vector inputs.
G06F 7/544 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs n'établissant pas de contact, p. ex. tube, dispositif à l'état solideMéthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul
5.
DEVICE AND METHODS FOR FUNCTIONAL DESCRIPTOR-BASED DMA CONTROLLER
A microcontroller may include a DMA controller, a pattern matching circuit and a memory. The DMA controller may read a first descriptor word in the memory at a location addressed by a first descriptor pointer, and may move an input word from a location in the memory addressed by a source payload pointer to a location in the memory addressed by a destination payload pointer. The pattern matching circuit may perform a pattern matching operation based on the input word and one or more register values. The first descriptor pointer may be modified based on the results of the pattern matching circuit and may generate a second descriptor pointer value.
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p. ex. acces direct à la mémoire, vol de cycle
6.
DEVICE AND METHOD FOR PIPELINED MULTIPLY-ACCUMULATOR
A circuit may include a vector arithmetic logic unit (ALU), the vector ALU comprising a multiplier, a first multiplexer, a second multiplexer and an accumulator. The vector ALU may compute a dot product of two or more vector inputs. A system may include two or more vector ALUs, and may partition a vector input into multiple segments. Each segment may be input to a respective vector ALU via a multiplexer, and a controller may route the partial sums of respective ALUs via one or more feedback paths and the system may compute the complete dot product of the vector inputs.
G06F 7/57 - Unités arithmétiques et logiques [UAL], c.-à-d. dispositions ou dispositifs pour accomplir plusieurs des opérations couvertes par les groupes ou pour accomplir des opérations logiques
G06F 7/544 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs n'établissant pas de contact, p. ex. tube, dispositif à l'état solideMéthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul
7.
LOCATING AN EMS UNIT CLOSEST TO A SOURCE OF A DISTRESS SIGNAL AND NOTIFYING PROXIMATE PERSONAL DEVICES
A method for distress signal monitoring with EMS and public notification in crowded public spaces. The method includes receiving a distress signal from a first personal device in a crowded public space; locating the first personal device closest to an EMS unit indicating that a user of the first personal device is in distress; transmitting a location of the first personal device to the EMS unit; identifying a second personal device proximate to the first personal device; and transmitting a notification signal to the second personal device indicating that a person is in distress.
G08B 27/00 - Systèmes d'alarme dans lesquels la condition déclenchant l'alarme est signalée par une station centrale à plusieurs sous-stations
G08B 5/36 - Systèmes de signalisation optique, p. ex. systèmes d'appel de personnes, indication à distance de l'occupation de sièges utilisant une transmission électriqueSystèmes de signalisation optique, p. ex. systèmes d'appel de personnes, indication à distance de l'occupation de sièges utilisant une transmission électromécanique utilisant des sources de lumière visible
8.
TELEMETRY SYSTEM INCLUDING A SENSOR STATION ARRAY AND AN AERIAL DATA COLLECTION SYSTEM
A telemetry system includes an array of sensor stations arranged in a spaced apart arrangement, wherein respective sensor stations include a respective sensor to generate respective sensor data regarding a respective sensed parameter, a respective sensor station memory to store the respective sensor data, a respective sensor station antenna, a respective sensor station wireless transmitter, and a respective sensor station processor to periodically activate the respective sensor station wireless transmitter to transmit the respective sensor data via the respective sensor station antenna. The telemetry system includes an aerial data collection system including an aerial data collection system antenna, and an aerial data collection system receiver to receive the respective sensor data transmitted by the respective sensor station antenna.
G05D 1/00 - Commande de la position, du cap, de l'altitude ou de l'attitude des véhicules terrestres, aquatiques, aériens ou spatiaux, p. ex. utilisant des pilotes automatiques
H04L 67/12 - Protocoles spécialement adaptés aux environnements propriétaires ou de mise en réseau pour un usage spécial, p. ex. les réseaux médicaux, les réseaux de capteurs, les réseaux dans les véhicules ou les réseaux de mesure à distance
H04L 67/141 - Configuration des sessions d'application
H04W 4/02 - Services utilisant des informations de localisation
H04W 4/38 - Services spécialement adaptés à des environnements, à des situations ou à des fins spécifiques pour la collecte d’informations de capteurs
9.
DETECTION OF A STOP CONDITION ASSERTED BY A TARGET ON A SERIAL DATA BUS
A controller is provided that includes a serial data (SDA) line interface to connect the controller to an SDA line of a two-wire, shared, serial data bus. The controller includes processing circuitry to transfer output data on the SDA line, and monitor the SDA line of the data bus while the output data is transferred on the SDA line of the two-wire, shared, serial data bus. The controller detects a stop condition asserted by a target on the data bus while the output data is transferred on the SDA line of the two-wire, shared, serial data bus. The controller then ends transfer of the output data on the SDA line, in response to the detected stop condition.
A microcontroller may include a DMA controller, a pattern matching circuit and a memory. The DMA controller may read a first descriptor word in the memory at a location addressed by a first descriptor pointer, and may move an input word from a location in the memory addressed by a source payload pointer to a location in the memory addressed by a destination payload pointer. The pattern matching circuit may perform a pattern matching operation based on the input word and one or more register values. The first descriptor pointer may be modified based on the results of the pattern matching circuit and may generate a second descriptor pointer value.
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p. ex. acces direct à la mémoire, vol de cycle
G06F 7/76 - Dispositions pour le réagencement, la permutation ou la sélection de données selon des règles prédéterminées, indépendamment du contenu des données
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
11.
SILICON CARBIDE POWER MOSFET AND METHOD FOR MANUFACTURING SAME
A method of manufacturing a semiconductor device is provided. The method may include implanting a silicon-rich layer on a surface of a silicon carbide substrate, and growing a gate oxide layer on the silicon-rich layer on the surface of the silicon carbide substrate.
H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
12.
HYBRID CHANNEL POWER SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
A semiconductor device is provided. The semiconductor device may include a silicon carbide substrate, a silicon layer formed at a first side of the silicon carbide substrate, a gate oxide layer formed on the silicon layer, a gate terminal formed on the gate oxide layer, a drain terminal formed at a second side of the silicon carbide substrate opposite the first side, and a source terminal formed at the first side of the silicon carbide substrate, and at opposite ends of the silicon layer.
H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/808 - Transistors à effet de champ l'effet de champ étant produit par une jonction PN ou une autre jonction redresseuse à jonction PN
13.
REDUCING STARTUP TIME OF A TRELLIS-BASED MLSE DECODER
A method may include at least partially initializing a trellis of an SE engine at least partially based on predetermined state information about a communication channel associated with an incoming data stream; and processing, via the MLSE engine, the incoming data stream to further initialize the trellis and decode the incoming data stream.
A controller is provided that includes a serial data (SDA) line interface to connect the controller to an SDA line of a two-wire, shared, serial data bus. The controller includes a circuitry to provide output data for transfer on to the SDA line via the output SDA pad buffer. The controller includes a logic circuit that is external to the circuitry, and that monitors data on the SDA line while the output data is transferred on to the SDA line. The logic circuit compares the monitored data on the SDA line and the output data to detect an error condition when the monitored data and the output data differ. The logic circuit disables an output SDA pad buffer of the SDA line interface for a current byte of the output data provided by the circuitry, and then causes a stop condition on the data bus.
A method of manufacturing a lateral diffusion metal oxide semiconductor device. The method may include forming a high voltage deep N-well within a substrate, forming a high voltage N-well within the substrate, wherein the high voltage N-well is electrically coupled to the high voltage deep N-well, forming a drain terminal electrically coupled to the high voltage N-well, forming a source terminal, and forming a gate terminal disposed between the source terminal and the drain terminal. At least one of the high voltage N-well and the high voltage deep N-well may extend less than 2.0 microns beyond the drain terminal in a direction opposite from the source terminal.
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
16.
HYBRID CHANNEL POWER SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
A semiconductor device is provided. The semiconductor device may include a silicon carbide substrate, a silicon layer formed at a first side of the silicon carbide substrate, a gate oxide layer formed on the silicon layer, a gate terminal formed on the gate oxide layer, a drain terminal formed at a second side of the silicon carbide substrate opposite the first side, and a source terminal formed at the first side of the silicon carbide substrate, and at opposite ends of the silicon layer.
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée
H01L 29/165 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée comprenant plusieurs des éléments prévus en dans différentes régions semi-conductrices
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 21/336 - Transistors à effet de champ à grille isolée
17.
TELEMETRY SYSTEM INCLUDING A SENSOR STATION ARRAY AND AN AERIAL DATA COLLECTION SYSTEM
A telemetry system includes an array of sensor stations arranged in a spaced apart arrangement, wherein respective sensor stations include a respective sensor to generate respective sensor data regarding a respective sensed parameter, a respective sensor station memory to store the respective sensor data, a respective sensor station antenna, a respective sensor station wireless transmitter, and a respective sensor station processor to periodically activate the respective sensor station wireless transmitter to transmit the respective sensor data via the respective sensor station antenna. The telemetry system includes an aerial data collection system including an aerial data collection system antenna, and an aerial data collection system receiver to receive the respective sensor data transmitted by the respective sensor station antenna.
sconencapsulansconencapsulanencapsulant defines a thermal stress interface (124) between the silicon region and the encapsulant. The IC device includes a dielectric layer (130) formed over the first die and the encapsulant, and includes a dielectric spacer region (134) extending over and laterally across the thermal stress interface. The IC device includes a redistribution layer (RDL) (140) including an RDL element (142) formed over the dielectric spacer region and electrically connected to the conductive contact through an opening (132) in the dielectric layer, wherein the RDL element is physically spaced apart from the thermal stress interface by the dielectric spacer region.
H01L 21/60 - Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
19.
DETECTION OF AN ERROR CONDITION ON A SERIAL DATA BUS
A controller is provided that includes a serial data (SDA) line interface to connect the controller to an SDA line of a two-wire, shared, serial data bus. The controller includes a circuitry to provide output data for transfer on to the SDA line via the output SDA pad buffer. The controller includes a logic circuit that is external to the circuitry, and that monitors data on the SDA line while the output data is transferred on to the SDA line. The logic circuit compares the monitored data on the SDA line and the output data to detect an error condition when the monitored data and the output data differ. The logic circuit disables an output SDA pad buffer of the SDA line interface for a current byte of the output data provided by the circuitry, and then causes a stop condition on the data bus.
A controller is provided that includes a serial data (SDA) line interface to connect the controller to an SDA line of a two-wire, shared, serial data bus. The controller includes processing circuitry to transfer output data on the SDA line, and monitor the SDA line of the data bus while the output data is transferred on the SDA line of the two-wire, shared, serial data bus. The controller detects a stop condition asserted by a target on the data bus while the output data is transferred on the SDA line of the two-wire, shared, serial data bus. The controller then ends transfer of the output data on the SDA line, in response to the detected stop condition.
A method may include at least partially initializing a trellis of an SE engine at least partially based on predetermined state information about a communication channel associated with an incoming data stream; and processing, via the MLSE engine, the incoming data stream to further initialize the trellis and decode the incoming data stream.
H04L 25/03 - Réseaux de mise en forme pour émetteur ou récepteur, p. ex. réseaux de mise en forme adaptatifs
H04L 25/49 - Circuits d'émissionCircuits de réception à conversion de code au transmetteurCircuits d'émissionCircuits de réception à pré-distorsionCircuits d'émissionCircuits de réception à insertion d'intervalles morts pour obtenir un spectre de fréquence désiréCircuits d'émissionCircuits de réception à au moins trois niveaux d'amplitude
22.
SILICON CARBIDE POWER MOSFET AND METHOD FOR MANUFACTURING SAME
A method of manufacturing a semiconductor device is provided. The method may include implanting a silicon-rich layer on a surface of a silicon carbide substrate, and growing a gate oxide layer on the silicon-rich layer on the surface of the silicon carbide substrate.
H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
H01L 21/265 - Bombardement par des radiations ondulatoires ou corpusculaires par des radiations d'énergie élevée produisant une implantation d'ions
H01L 29/51 - Matériaux isolants associés à ces électrodes
H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée
23.
METHOD AND APPARATUS FOR SENSING CURRENT IN A BACK-TO-BACK CONFIGURATION
An apparatus for sensing current in a back-to-back MOSFET configuration is provided. The apparatus may include a first MOSFET having a gate terminal, a drain terminal, and a source terminal, a second MOSFET having a source terminal coupled to the source terminal of the first MOSFET, a gate terminal, and a drain terminal, a gate driver circuit including at least one gate drive output terminal to output a gate drive signal to the gate terminals of the first and second MOSFETs, and a shunt resistor coupled between the source terminals of the first and second MOSFETs. The gate driver circuit may include a return terminal coupled to the source terminal of the first MOSFET, and a return current from the gate terminal of the second MOSFET flows through the shunt resistor to the return terminal of the gate driver circuit.
G01R 19/00 - Dispositions pour procéder aux mesures de courant ou de tension ou pour en indiquer l'existence ou le signe
G01R 1/20 - Modifications des éléments électriques fondamentaux en vue de leur utilisation dans des appareils de mesures électriquesCombinaisons structurelles de ces éléments avec ces appareils
24.
Method and Apparatus for Controlling Battery Storage Mode
A method of causing a first battery to exit a battery storage mode is provided. The method may include receiving, while the first battery is in the battery storage mode, a wake up signal indicating a power up event, generating an exit signal in response to the wake up signal, to cause the first battery to supply power to a first processing circuitry, waiting a predetermined time period following a predetermined edge of the exit signal, determining, after expiration of the predetermined time period, whether the first battery is supplying power to the first processing circuitry, and generating a second exit signal in response to determining that the first battery is not supplying power to the first processing circuitry. In the battery storage mode, a second battery provides power to the second processing circuitry to perform the method of causing the first battery to exit the battery storage mode.
G06F 1/3287 - Économie d’énergie caractérisée par l'action entreprise par la mise hors tension d’une unité fonctionnelle individuelle dans un ordinateur
G06F 1/26 - Alimentation en énergie électrique, p. ex. régulation à cet effet
25.
METHOD AND APPARATUS FOR CONTROLLING BATTERY STORAGE MODE
A method of causing a first battery to exit a battery storage mode is provided. The method may include receiving, while the first battery is in the battery storage mode, a wake up signal indicating a power up event, generating an exit signal in response to the wake up signal, to cause the first battery to supply power to a first processing circuitry, waiting a predetermined time period following a predetermined edge of the exit signal, determining, after expiration of the predetermined time period, whether the first battery is supplying power to the first processing circuitry, and generating a second exit signal in response to determining that the first battery is not supplying power to the first processing circuitry. In the battery storage mode, a second battery provides power to the second processing circuitry to perform the method of causing the first battery to exit the battery storage mode.
An apparatus for sensing current in a back-to-back MOSFET configuration is provided. The apparatus may include a first MOSFET having a gate terminal, a drain terminal, and a source terminal, a second MOSFET having a source terminal coupled to the source terminal of the first MOSFET, a gate terminal, and a drain terminal, a gate driver circuit including at least one gate drive output terminal to output a gate drive signal to the gate terminals of the first and second MOSFETs, and a shunt resistor coupled between the source terminals of the first and second MOSFETs. The gate driver circuit may include a return terminal coupled to the source terminal of the first MOSFET, and a return current from the gate terminal of the second MOSFET flows through the shunt resistor to the return terminal of the gate driver circuit.
H02H 3/08 - Circuits de protection de sécurité pour déconnexion automatique due directement à un changement indésirable des conditions électriques normales de travail avec ou sans reconnexion sensibles à une surcharge
H02H 3/02 - Circuits de protection de sécurité pour déconnexion automatique due directement à un changement indésirable des conditions électriques normales de travail avec ou sans reconnexion Détails
H03K 17/082 - Modifications pour protéger le circuit de commutation contre la surintensité ou la surtension par réaction du circuit de sortie vers le circuit de commande
G01R 19/00 - Dispositions pour procéder aux mesures de courant ou de tension ou pour en indiquer l'existence ou le signe
G01R 1/20 - Modifications des éléments électriques fondamentaux en vue de leur utilisation dans des appareils de mesures électriquesCombinaisons structurelles de ces éléments avec ces appareils
G01R 19/165 - Indication de ce qu'un courant ou une tension est, soit supérieur ou inférieur à une valeur prédéterminée, soit à l'intérieur ou à l'extérieur d'une plage de valeurs prédéterminée
27.
METHOD AND APPARATUS FOR SENSING CURRENT IN A BACK-TO-BACK CONFIGURATION
An apparatus for sensing current in a back-to-back MOSFET configuration is provided. The apparatus may include a first MOSFET having a gate terminal, a drain terminal, and a source terminal, a second MOSFET having a source terminal coupled to the source terminal of the first MOSFET, a gate terminal, and a drain terminal, a gate driver circuit including at least one gate drive output terminal to output a gate drive signal to the gate terminals of the first and second MOSFETs, and a return terminal coupled to the source terminals of the first and second MOSFETs, a shunt resistor coupled between the source terminals of the first and second MOSFETs, and a first MOSFET return resistor coupled between the source terminal of the first MOSFET and the return terminal of the gate driver circuit. The first MOSFET return resistor resistance may be greater than a resistance of the shunt resistor.
H02H 3/08 - Circuits de protection de sécurité pour déconnexion automatique due directement à un changement indésirable des conditions électriques normales de travail avec ou sans reconnexion sensibles à une surcharge
G01R 1/20 - Modifications des éléments électriques fondamentaux en vue de leur utilisation dans des appareils de mesures électriquesCombinaisons structurelles de ces éléments avec ces appareils
G01R 19/00 - Dispositions pour procéder aux mesures de courant ou de tension ou pour en indiquer l'existence ou le signe
G01R 19/165 - Indication de ce qu'un courant ou une tension est, soit supérieur ou inférieur à une valeur prédéterminée, soit à l'intérieur ou à l'extérieur d'une plage de valeurs prédéterminée
H02H 3/02 - Circuits de protection de sécurité pour déconnexion automatique due directement à un changement indésirable des conditions électriques normales de travail avec ou sans reconnexion Détails
H03K 17/082 - Modifications pour protéger le circuit de commutation contre la surintensité ou la surtension par réaction du circuit de sortie vers le circuit de commande
An integrated circuit (IC) device includes a die including a silicon region having a coefficient of thermal expansion (CTEsilicon), and a conductive contact on a first side of the first die. An encapsulant laterally adjacent the silicon region of the first die has a coefficient of thermal expansion (CTEencapsulant), wherein a mismatch between the CTEsilicon and the CTEencapsulant defines a thermal stress interface between the silicon region and the encapsulant. The IC device includes a dielectric layer formed over the first die and the encapsulant, and includes a dielectric spacer region extending over and laterally across the thermal stress interface. The IC device includes a redistribution layer (RDL) including an RDL element formed over the dielectric spacer region and electrically connected to the conductive contact through an opening in the dielectric layer, wherein the RDL element is physically spaced apart from the thermal stress interface by the dielectric spacer region.
H01L 23/42 - Choix ou disposition de matériaux de remplissage ou de pièces auxiliaires dans le conteneur pour faciliter le chauffage ou le refroidissement
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides
29.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
A method of manufacturing a lateral diffusion metal oxide semiconductor device. The method may include forming a high voltage deep N-well within a substrate, forming a high voltage N-well within the substrate, wherein the high voltage N-well is electrically coupled to the high voltage deep N-well, forming a drain terminal electrically coupled to the high voltage N-well, forming a source terminal, and forming a gate terminal disposed between the source terminal and the drain terminal. At least one of the high voltage N-well and the high voltage deep N-well may extend less than 2.0 microns beyond the drain terminal in a direction opposite from the source terminal.
An apparatus for sensing current in a back-to-back MOSFET configuration is provided. The apparatus may include a first MOSFET having a gate terminal, a drain terminal, and a source terminal, a second MOSFET having a source terminal coupled to the source terminal of the first MOSFET, a gate terminal, and a drain terminal, a gate driver circuit including at least one gate drive output terminal to output a gate drive signal to the gate terminals of the first and second MOSFETs, and a return terminal coupled to the source terminals of the first and second MOSFETs, a shunt resistor coupled between the source terminals of the first and second MOSFETs, and a first MOSFET return resistor coupled between the source terminal of the first MOSFET and the return terminal of the gate driver circuit. The first MOSFET return resistor resistance may be greater than a resistance of the shunt resistor.
H02H 1/00 - Détails de circuits de protection de sécurité
H01C 7/13 - Résistances fixes constituées par une ou plusieurs couches ou revêtementsRésistances fixes constituées de matériaux conducteurs en poudre ou de matériaux semi-conducteurs en poudre avec ou sans matériaux isolants sensibles au courant
H03K 17/0812 - Modifications pour protéger le circuit de commutation contre la surintensité ou la surtension sans réaction du circuit de sortie vers le circuit de commande par des dispositions prises dans le circuit de commande
A diode that may include a substrate with a cathode terminal on a first surface of the substrate. An anode terminal on a second surface of the substrate. An implant portion disposed within the substrate.
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/167 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée caractérisés en outre par le matériau de dopage
H01L 29/66 - Types de dispositifs semi-conducteurs
32.
FOREIGN OBJECT DETECTION BY FREQUENCY BANDWIDTH COMPARISON
A wireless power transmitter and methods to: determine a transmitter frequency bandwidth of the wireless power transmitter when no wireless power receiver is inductively coupled with the wireless power transmitter; determine a transmitter-receiver frequency bandwidth when a wireless power receiver is inductively coupled with the wireless power transmitter; compare the transmitter-receiver frequency bandwidth and the transmitter frequency bandwidth; and detect a foreign object near the transmit coil based on the comparison of the transmitter-receiver frequency bandwidth and the transmitter frequency bandwidth.
H02J 50/12 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique utilisant un couplage inductif du type couplage à résonance
H02J 50/40 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique utilisant plusieurs dispositifs de transmission ou de réception
H02J 50/60 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique sensibles à la présence d’objets étrangers, p. ex. détection d'êtres vivants
A digital-to-analog converter (DAC) system includes a first DAC circuitry and a second DAC circuitry. An input splitter circuitry connected to the DAC system receives a first digital input code, and based on a value of the first digital input code, transfers the first digital input code to the first DAC circuitry for conversion to an analog output signal. The input splitter receives a second digital input code, and based on a value of the second digital input code, divides the second digital input code into a primary component and a secondary component, transfers the primary component to the first DAC circuitry for conversion to an analog output signal primary component, and transfers the secondary component to the second DAC circuitry for conversion to an analog output signal secondary component. An adding circuitry combines the analog output signal primary component and secondary component to provide a combined analog output signal.
A digital-to-analog converter (DAC) system includes a first DAC circuitry and a second DAC circuitry. An input splitter circuitry connected to the DAC system receives a first digital input code, and based on a value of the first digital input code, transfers the first digital input code to the first DAC circuitry for conversion to an analog output signal. The input splitter receives a second digital input code, and based on a value of the second digital input code, divides the second digital input code into a primary component and a secondary component, transfers the primary component to the first DAC circuitry for conversion to an analog output signal primary component, and transfers the secondary component to the second DAC circuitry for conversion to an analog output signal secondary component. An adding circuitry combines the analog output signal primary component and secondary component to provide a combined analog output signal.
A diode that may include a substrate with a cathode terminal on a first surface of the substrate. An anode terminal on a second surface of the substrate. An implant portion disposed within the substrate.
H01L 21/329 - Procédés comportant plusieurs étapes pour la fabrication de dispositifs du type bipolaire, p.ex. diodes, transistors, thyristors les dispositifs comportant une ou deux électrodes, p.ex. diodes
36.
FOREIGN OBJECT DETECTION BY FREQUENCY BANDWIDTH COMPARISON
A wireless power transmitter and methods to: determine a transmitter frequency bandwidth of the wireless power transmitter when no wireless power receiver is inductively coupled with the wireless power transmitter; determine a transmitter-receiver frequency bandwidth when a wireless power receiver is inductively coupled with the wireless power transmitter; compare the transmitter-receiver frequency bandwidth and the transmitter frequency bandwidth; and detect a foreign object near the transmit coil based on the comparison of the transmitter-receiver frequency bandwidth and the transmitter frequency bandwidth.
H02J 50/60 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique sensibles à la présence d’objets étrangers, p. ex. détection d'êtres vivants
H02J 50/12 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique utilisant un couplage inductif du type couplage à résonance
H02J 50/40 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique utilisant plusieurs dispositifs de transmission ou de réception
37.
RESERVATION OF PCIe SLOTS FOR MANAGEMENT BY A RAID DRIVER
A system and method including a PCIe slot, a storage device coupled to the PCIe slot, and a host server including a processor and a non-transitory memory including machine-readable instructions that, when executed by a processor, cause the processor to: load a RAID driver; receive, by the RAID driver, a probe call identifying the PCIe slot; determine, based on a slot reservation table stored in a non-volatile RAM accessible by the RAID driver, whether the storage device coupled to the PCIe slot is managed by the RAID driver; send, when the PCIe slot is identified in the slot reservation table, a response indicating that the RAID driver will control access to the storage device coupled to the PCIe slot; and send, when the PCIe slot is not identified in the slot reservation table, a response indicating that the RAID driver will not control access to the storage device.
A system may include a storage array comprised of one or more array member drives. The storage array may be partitioned into stripes of data across the one or more array member drives. In operation, a DMA controller may move source data from a processor memory and may write the data to an accelerator memory. The accelerator may perform a parity calculation and a DMA controller may write the parity result and the source data to at least one of the array member drives. The parity information may be used to reconstruct data in the one or more array member drives in the case of damage or loss of data.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
G06F 9/50 - Allocation de ressources, p. ex. de l'unité centrale de traitement [UCT]
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
39.
DUAL RESONATOR STRUCTURE FOR TEMPERATURE-COMPENSATED OSCILLATORS, INCLUDING RELATED APPARATUSES
An apparatus comprises a micromechanical system including a semiconductor body. The semiconductor body comprises a first resonator, a second resonator, and a supporting portion. The first resonator is to resonate at a first resonating frequency that is generally frequency-stable over a predetermined temperature range. The second resonator is to resonate at a second resonating frequency that is generally linearly decreasing or increasing as temperature increases over the predetermined temperature range. The supporting portion is to support both the first resonator and the second resonator.
An apparatus comprises a microelectromechanical system (MEMS) including a semiconductor body. The semiconductor body comprises a first resonator, a second resonator, a supporting portion, and one or more heating elements of a heater. The first resonator is to resonate at a first resonating frequency that is generally frequency-stable over a predetermined temperature range. The second resonator is to resonate at a second resonating frequency that is generally linearly decreasing or increasing as temperature increases over the predetermined temperature range. The supporting portion is to support both the first resonator and the second resonator. The one or more heating elements of the heater are on, or in, the supporting portion.
H03B 5/04 - Modifications du générateur pour compenser des variations dans les grandeurs physiques, p. ex. alimentation, charge, température
H03B 5/30 - Production d'oscillation au moyen d'un amplificateur comportant un circuit de réaction entre sa sortie et son entrée l'élément déterminant la fréquence étant un résonateur électromécanique
41.
RESERVATION OF PCIe SLOTS FOR MANAGEMENT BY A RAID DRIVER
A system and method including a PCIe slot, a storage device coupled to the PCIe slot, and a host server including a processor and a non-transitory memory including machine-readable instructions that, when executed by a processor, cause the processor to: load a RAID driver; receive, by the RAID driver, a probe call identifying the PCIe slot; determine, based on a slot reservation table stored in a non-volatile RAM accessible by the RAID driver, whether the storage device coupled to the PCIe slot is managed by the RAID driver; send, when the PCIe slot is identified in the slot reservation table, a response indicating that the RAID driver will control access to the storage device coupled to the PCIe slot; and send, when the PCIe slot is not identified in the slot reservation table, a response indicating that the RAID driver will not control access to the storage device.
An apparatus comprises a micromechanical system including a semiconductor body. The semiconductor body comprises a first resonator, a second resonator, and a supporting portion. The first resonator is to resonate at a first resonating frequency that is generally frequency-stable over a predetermined temperature range. The second resonator is to resonate at a second resonating frequency that is generally linearly decreasing or increasing as temperature increases over the predetermined temperature range. The supporting portion is to support both the first resonator and the second resonator.
H03H 3/007 - Appareils ou procédés spécialement adaptés à la fabrication de réseaux d'impédance, de circuits résonnants, de résonateurs pour la fabrication de résonateurs ou de réseaux électromécaniques
H03H 9/02 - Réseaux comprenant des éléments électromécaniques ou électro-acoustiquesRésonateurs électromécaniques Détails
H03H 9/24 - Détails de réalisation de résonateurs en matériau qui n'est ni piézo-électrique, ni électrostrictif, ni magnétostrictif
43.
SYSTEM AND METHODS FOR PARITY CALCULATION IN STORAGE ARRAYS
A system may include a storage array comprised of one or more array member drives. The storage array may be partitioned into stripes of data across the one or more array member drives. In operation, a DMA controller may move source data from a processor memory and may write the data to an accelerator memory. The accelerator may perform a parity calculation and a DMA controller may write the parity result and the source data to at least one of the array member drives. The parity information may be used to reconstruct data in the one or more array member drives in the case of damage or loss of data.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
44.
METHOD AND APPARATUS FOR BLUETOOTH LOW ENERGY ADVERTISING
A method for advertising a Bluetooth low energy (BLE) peripheral device is provided. The method may include partially booting up a processing circuitry of the BLE peripheral device to enter an advertising mode, transmitting a first advertising packet, receiving a response to the first advertising packet from a BLE central device, wherein the response includes a predetermined time, determining whether a complete boot-up time needed to complete boot-up of the processing circuitry is greater than the predetermined time, and in response to determining that the complete boot-up time is not greater than the predetermined time, completing boot-up of the processing circuitry.
Methods, devices and systems to communicate an instruction to generate parities from a host processor (110) to an accelerator engine (120) via a nonvolatile memory transport protocol, generate parities from source data via the accelerator engine based on the instruction, and store the generated parities. Methods, devices and systems to generate parities via an accelerator engine on source data from a central processing unit using nonvolatile memory transport protocol to communicate a parity generation instruction.
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 11/00 - Détection d'erreursCorrection d'erreursContrôle de fonctionnement
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p. ex. acces direct à la mémoire, vol de cycle
G06F 13/42 - Protocole de transfert pour bus, p. ex. liaisonSynchronisation
46.
METHOD AND APPARATUS FOR BLUETOOTH LOW ENERGY ADVERTISING
A method for advertising a Bluetooth low energy (BLE) peripheral device is provided. The method may include partially booting up a processing circuitry of the BLE peripheral device to enter an advertising mode, transmitting a first advertising packet, receiving a response to the first advertising packet from a BLE central device, wherein the response includes a predetermined time, determining whether a complete boot-up time needed to complete boot-up of the processing circuitry is greater than the predetermined time, and in response to determining that the complete boot-up time is not greater than the predetermined time, completing boot-up of the processing circuitry.
Methods, devices and systems to communicate an instruction to generate parities from a host processor to an accelerator engine via a nonvolatile memory transport protocol, generate parities from source data via the accelerator engine based on the instruction, and store the generated parities. Methods, devices and systems to generate parities via an accelerator engine on source data from a central processing unit using non-volatile memory transport protocol to communicate a parity generation instruction.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
G06F 13/42 - Protocole de transfert pour bus, p. ex. liaisonSynchronisation
48.
POLYHEDRON MODELS AND METHODS USING COMPUTATIONAL OPERATIONS FOR DISTRIBUTING DATA
Methods based on polyhedron models using computational operations for distributing data and parities among different data storage media. Devices, systems, and methods that split data into data strips, wherein the number of data strips equals the number of vertices of a polyhedron and respective ones of the number of the data strips correspond to respective ones of the number of vertices of the polyhedron; construct a number of parities, wherein the number of parities equals the number of faces of the polyhedron and respective ones of the number of parities correspond to respective ones of the number of parities of the polyhedron, wherein respective ones of the number of parities are constructed by computationally operating the data strips corresponding to vertices respectively associated with a face of the polyhedron corresponding to the respective parity; and distribute subsets of data strips and subsets of parities to subsets of storage media.
Methods based on polyhedron models using computational operations for distributing data and parities among different data storage media. Devices, systems, and methods that split data into data strips, wherein the number of data strips equals the number of vertices of a polyhedron and respective ones of the number of the data strips correspond to respective ones of the number of vertices of the polyhedron; construct a number of parities, wherein the number of parities equals the number of faces of the polyhedron and respective ones of the number of parities correspond to respective ones of the number of parities of the polyhedron, wherein respective ones of the number of parities are constmcted by computationally operating the data strips corresponding to vertices respectively associated with a face of the polyhedron corresponding to the respective parity; and distribute subsets of data strips and subsets of parities to subsets of storage media.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
50.
CLASSIFYING COMPARATORS BASED ON COMPARATOR OFFSETS
Various embodiments relate to classifying comparators based on comparator offsets. A method may include applying, via a strobe, a first voltage to each of a first input and a second input of a comparator to generate a number of output signals from the comparator, wherein each output signal has one of a first polarity and a second polarity. The method may further include in response to each of the number of output signals being the first polarity, applying, via a strobe, an external offset voltage having the second polarity to the comparator to generate a second number of output signals. Further, the method may include in response to each of the second number of output signals being the same polarity, identifying the comparator as a reliable comparator.
C09J 151/00 - Adhésifs à base de polymères greffés dans lesquels le composant greffé est obtenu par des réactions faisant intervenir uniquement des liaisons non saturées carbone-carboneAdhésifs à base de dérivés de tels polymères
C08F 2/50 - Polymérisation amorcée par énergie ondulatoire ou par rayonnement corpusculaire par la lumière ultraviolette ou visible avec des agents sensibilisants
C08F 220/06 - Acide acryliqueAcide méthacryliqueLeurs sels métalliques ou leurs sels d'ammonium
C08F 220/18 - Esters des alcools ou des phénols monohydriques des phénols ou des alcools contenant plusieurs atomes de carbone avec l'acide acrylique ou l'acide méthacrylique
C08F 236/20 - Copolymères de composés contenant plusieurs radicaux aliphatiques non saturés et l'un au moins contenant plusieurs liaisons doubles carbone-carbone le radical ne contenant que deux doubles liaisons carbone-carbone non conjuguées
C08F 236/22 - Copolymères de composés contenant plusieurs radicaux aliphatiques non saturés et l'un au moins contenant plusieurs liaisons doubles carbone-carbone le radical contenant au moins trois doubles liaisons carbone-carbone
C09J 133/08 - Homopolymères ou copolymères d'esters de l'acide acrylique
C09J 133/10 - Homopolymères ou copolymères d'esters de l'acide méthacrylique
G01R 23/00 - Dispositions pour procéder aux mesures de fréquencesDispositions pour procéder à l'analyse de spectres de fréquences
G01R 31/00 - Dispositions pour tester les propriétés électriquesDispositions pour la localisation des pannes électriquesDispositions pour tests électriques caractérisées par ce qui est testé, non prévues ailleurs
G01R 31/30 - Tests marginaux, p. ex. en faisant varier la tension d'alimentation
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
51.
METHOD OF ALIGNMENT OF ELECTRICAL COMPONENTS OF AN ELECTRICAL APPARATUS WITH A SUPPORT ASSEMBLY
An apparatus includes first electrical components, wherein a respective first electrical component has first connection areas, and second electrical components, wherein a respective second electrical component has second connection areas. The apparatus also includes support structures, wherein a respective support structure is mounted to a respective first electrical component to limit a lateral range of movement of a respective second electrical component relative to the respective first electrical component. The apparatus further includes masses of connection material to at least partially connect corresponding ones of the first connection areas of the first electrical components and the second connection areas of the second electrical components.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 21/98 - Assemblage de dispositifs consistant en composants à l'état solide formés dans ou sur un substrat communAssemblage de dispositifs à circuit intégré
52.
METHOD OF DYNAMIC ASSIGNMENT OF NODE IDENTIFIERS IN A 10BASE-T1S NETWORK
An apparatus may include a physical layer (PHY), a reconciliation sublayer (RS), a Media Access Control layer (MAC), and a logic circuit. The may interface with a shared transmission medium of a network. TheRS may support Physical Layer Collision Avoidance (PLCA), and the circuit may send a request to register a node with a network, and derive a node identifier for use by the PLCA RS to determine transmit opportunities, wherein the node identifier is at least partially derived from the node's position in a table of registered nodes in the network received in response to the registration request.
H04L 12/403 - Réseaux à ligne bus avec commande centralisée, p. ex. interrogation
H04L 12/413 - Réseaux à ligne bus avec commande décentralisée avec accès aléatoire, p. ex. accès multiple avec détection de porteuse et détection de collision [CSMA-CD]
H04L 12/417 - Réseaux à ligne bus avec commande décentralisée avec accès déterminé, p. ex. passage de jeton
53.
Methods for Gather/Scatter Operations in a Vector Processor
A method for gather/scatter operations in a vector processor includes: (a) checking for a read port start signal and when received setting an increment count to zero; (b) initiating a memory read using a port's address register, and setting the increment count to increment count+1; (c) incrementing the port's address register by a port's stride register; (d) checking to see if the increment count is greater than or equal to a port's length register and when not so proceeding to (b); and (e) checking to see if the increment count is greater than or equal to a port's length register and when so proceeding to (a).
A system includes a wearable device, a plurality of sound sensors installed in the wearable device, an alerting element installed in the wearable device, and a controller coupled to the plurality of sound sensors and the alerting element. The controller receives a signal indicative of a sound detected by at least one of the plurality of sound sensors, determines whether the sound indicates the presence of a potentially dangerous event, determines a direction of the sound based on the received signal indicative of the sound, if the sound indicates the presence of the potentially dangerous event, activate the alerting element; and if the sound does not indicate the presence of the potentially dangerous event, not activate the alerting element.
A semiconductor device that may include a silicon carbide substrate, a silicon layer disposed on the silicon carbide substrate, and a gate oxide layer disposed on the silicon layer. The silicon layer may be implanted within the silicon carbide substrate. The silicon layer may comprise a thickness of 100 angstroms 5000 angstroms. The silicon layer may contain less than one percent carbon, or may contain a certain percentage of carbon that decreases as a distance from the surface of the silicon carbide substrate increases.
H01L 21/04 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives les dispositifs ayant des barrières de potentiel, p. ex. une jonction PN, une région d'appauvrissement ou une région de concentration de porteurs de charges
H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée
H01L 29/51 - Matériaux isolants associés à ces électrodes
56.
WEARABLE SYSTEM FOR SPATIAL AUDIO DETECTION WITH ALERTING ELEMENTS FOR DETECTION OF POTENTIALLY DANGEROUS EVENTS
A system includes a wearable device, a plurality of sound sensors installed in the wearable device, an alerting element installed in the wearable device, and a controller coupled to the plurality of sound sensors and the alerting element. The controller receives a signal indicative of a sound detected by at least one of the plurality of sound sensors, determines whether the sound indicates the presence of a potentially dangerous event, determines a direction of the sound based on the received signal indicative of the sound, if the sound indicates the presence of the potentially dangerous event, activate the alerting element; and if the sound does not indicate the presence of the potentially dangerous event, not activate the alerting element.
A method of forming an integrated circuit (IC) device includes forming a first die block including a first die block substrate, a first die at least partially embedded in the first die block substrate, first die contacts located in a first die footprint, and first die block contacts laterally outside the first die footprint. A second die having a larger footprint than the first die footprint, and including second die inner contacts and second die outer contacts, is arranged face-to-face and spatially aligned relative to the first die. The second die is bonded to the first die block by a bonding process including (a) bonding respective second die inner contacts to respective first die contacts to define inner electrical connections between the first and second dies and (b) bonding respective second die outer contacts to respective first die block contacts to define outer electrical connections outside the first die footprint.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/498 - Connexions électriques sur des substrats isolants
58.
METHOD OF ALIGNMENT OF ELECTRICAL COMPONENTS OF AN ELECTRICAL APPARATUS WITH A SUPPORT ASSEMBLY
An apparatus includes first electrical components, wherein a respective first electrical component has first connection areas, and second electrical components, wherein a respective second electrical component has second connection areas. The apparatus also includes support structures, wherein a respective support structure is mounted to a respective first electrical component to limit a lateral range of movement of a respective second electrical component relative to the respective first electrical component. The apparatus further includes masses of connection material to at least partially connect corresponding ones of the first connection areas of the first electrical components and the second connection areas of the second electrical components.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
A method may include: initializing four states of a trellis, the four states corresponding to the four possible symbol levels in PAM4, where a respective initial state starts with an initial score and an empty survivor path; for respective possible transitions between the four initial states and four possible current states of the trellis, determining expected PAM4 symbols; determining error associated with respective transitions based on differences between a received PAM4 symbol and the expected PAM4 symbols; discarding transitions where the error indicates a difference greater than a single signal level, and keep the other transitions; and for respective current state groups of a two state trellis, determining one of the incoming transitions that was not discarded having the highest likelihood of being associated with a transmitted symbol.
H04L 25/49 - Circuits d'émissionCircuits de réception à conversion de code au transmetteurCircuits d'émissionCircuits de réception à pré-distorsionCircuits d'émissionCircuits de réception à insertion d'intervalles morts pour obtenir un spectre de fréquence désiréCircuits d'émissionCircuits de réception à au moins trois niveaux d'amplitude
H04L 25/03 - Réseaux de mise en forme pour émetteur ou récepteur, p. ex. réseaux de mise en forme adaptatifs
60.
INTEGRATED CIRCUIT DEVICE INCLUDING DIES ARRANGED FACE-TO-FACE
A method of forming an integrated circuit (IC) device includes forming a first die block including a first die block substrate, a first die at least partially embedded in the first die block substrate, first die contacts located in a first die footprint, and first die block contacts laterally outside the first die footprint. A second die having a larger footprint than the first die footprint, and including second die inner contacts and second die outer contacts, is arranged face-to-face and spatially aligned relative to the first die. The second die is bonded to the first die block by a bonding process including (a) bonding respective second die inner contacts to respective first die contacts to define inner electrical connections between the first and second dies and (b) bonding respective second die outer contacts to respective first die block contacts to define outer electrical connections outside the first die footprint.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
61.
SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
A semiconductor device that may include a silicon carbide substrate, a silicon layer disposed on the silicon carbide substrate, and a gate oxide layer disposed on the silicon layer. The silicon layer may be implanted within the silicon carbide substrate. The silicon layer may comprise a thickness of 100 angstroms 5000 angstroms. The silicon layer may contain less than one percent carbon, or may contain a certain percentage of carbon that decreases as a distance from the surface of the silicon carbide substrate increases.
H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
H01L 29/51 - Matériaux isolants associés à ces électrodes
H01L 21/20 - Dépôt de matériaux semi-conducteurs sur un substrat, p. ex. croissance épitaxiale
H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée
H01L 21/265 - Bombardement par des radiations ondulatoires ou corpusculaires par des radiations d'énergie élevée produisant une implantation d'ions
H01L 21/306 - Traitement chimique ou électrique, p. ex. gravure électrolytique
A method may include: initializing four states of a trellis, the four states corresponding to the four possible symbol levels in PAM4, where a respective initial state starts with an initial score and an empty survivor path; for respective possible transitions between the four initial states and four possible current states of the trellis, determining expected PAM4 symbols; determining error associated with respective transitions based on differences between a received PAM4 symbol and the expected PAM4 symbols; discarding transitions where the error indicates a difference greater than a single signal level, and keep the other transitions; and for respective current state groups of a two state trellis, determining one of the incoming transitions that was not discarded having the highest likelihood of being associated with a transmitted symbol.
H04L 25/03 - Réseaux de mise en forme pour émetteur ou récepteur, p. ex. réseaux de mise en forme adaptatifs
H04L 25/49 - Circuits d'émissionCircuits de réception à conversion de code au transmetteurCircuits d'émissionCircuits de réception à pré-distorsionCircuits d'émissionCircuits de réception à insertion d'intervalles morts pour obtenir un spectre de fréquence désiréCircuits d'émissionCircuits de réception à au moins trois niveaux d'amplitude
Systems for authenticating a file are disclosed. A system may include one or more physical devices. The one or more physical devices may select, based on an identifier, a subset of data segments of a computer file for generating a first digest with a cryptographic function. The one or more physical devices may also execute the cryptographic function on the selected subset of data segments of the computer file to generate the first digest. Further, the one or more physical devices may generate an authenticator based on the first digest and a private key. The one or more physical devices may further send the computer file, the identifier, and the authenticator to a secure node. Associated methods and non-transitory machine-readable medium are also disclosed.
G06F 21/62 - Protection de l’accès à des données via une plate-forme, p. ex. par clés ou règles de contrôle de l’accès
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p. ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
H04L 9/06 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p. ex. système DES
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
64.
SYSTEM AND METHODS FOR COMPUTING PARITY INFORMATION IN A RAID ARRAY
A redundant disk array may include redundant information to facilitate rebuilding the array in the event of a disk failure. A host processor may allocate buffers in an accelerator memory. Data may be moved from one or more storage devices to the buffers. An accelerator engine may perform parity calculations required to rebuild the array based on data in the buffers without requiring a host CPU to perform the parity calculation.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
65.
SYSTEM AND METHODS FOR COMPUTING PARITY INFORMATION IN A RAID ARRAY
A redundant disk array may include redundant information to facilitate rebuilding the array in the event of a disk failure. A host processor may allocate buffers in an accelerator memory. Data may be moved from one or more storage devices to the buffers. An accelerator engine may perform parity calculations required to rebuild the array based on data in the buffers without requiring a host CPU to perform the parity calculation.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
66.
HIGH VOLTAGE WAKE SIGNALING INPUT/OUTPUT FOR 10BASE-T1S SYSTEM-BASIS-CHIP
A method may include receiving signaling at a system basis chip implementing a transceiver of a 10SPE PHY; changing, at the system basis chip, the signaling from first voltage levels incompatible with a voltage domain of a microcontroller (MCU) implementing a controller of the 10SPE PHY to second voltage levels compatible with the voltage domain of the MCU;and communicating the changed signaling to the MCU.
A circuit may enable communication between a primary device and one or more secondary devices. The communication may utilize a Universal Asynchronous Receiver Transmitter (UART) protocol. In operation, the primary device may require information on the baud rate of the secondary device. The UART may operate in an inverted polarity mode, and this inverted polarity may be interpreted by the secondary device as a request to enter an auto-baud detection mode. Using the inverted polarity mode to enter the auto-baud detection mode may prevent excessive delays in the UART communication and may prevent the need for additional pins to implement the auto-baud detection mode.
G06F 13/10 - Commande par programme pour dispositifs périphériques
H03K 17/687 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
68.
HIGH VOLTAGE WAKE SIGNALING INPUT/OUTPUT FOR 10BASE-T1S SYSTEM BASIS CHIP
A high voltage wake signaling input/output for 10BASE-T1S system basis chip. An apparatus includes a pad associated with wake signaling at a 10BASET 1S PHY, the wake signaling represented by voltage changes between first voltage levels; a system basis chip, comprising: a circuit to change a voltage received from the pad from first voltage levels to second, corresponding voltage levels, the second voltage levels lower than the first voltage levels; and a logic circuit to detect a valid voltage change at the pad responsive to the changed voltage.
Examples include managing address space in a register bank of a system basis chip. An apparatus includes a bus slave and a system basis chip including. The system basis chip includes a register bank, an access controller to confine reach of the bus slave to a select set of addresses of the register bank, and an address space manager to set the select set of addresses of the register bank.
G06F 12/06 - Adressage d'un bloc physique de transfert, p. ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
70.
MANAGING ADDRESS SPACE IN REGISTER BANK OF SYSTEM BASIS CHIP
Examples include managing address space in a register bank of a system basis chip. An apparatus includes a bus slave and a system basis chip including. The system basis chip includes a register bank, an access controller to confine reach of the bus slave to a select set of addresses of the register bank, and an address space manager to set the select set of addresses of the register bank.
G06F 12/06 - Adressage d'un bloc physique de transfert, p. ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
A circuit may enable communication between a primary device and one or more secondary devices. The communication may utilize a Universal Asynchronous Receiver Transmitter (UART) protocol. In operation, the primary device may require information on the baud rate of the secondary device. The UART may operate in an inverted polarity mode, and this inverted polarity may be interpreted by the secondary device as a request to enter an auto-baud detection mode. Using the inverted polarity mode to enter the auto-baud detection mode may prevent excessive delays in the UART communication and may prevent the need for additional pins to implement the auto-baud detection mode.
A powered device (PD) interface controller is provided that includes a switch and control circuitry. The switch controls current to a PD from a power sourcing equipment (PSE). The PD accepts power from a network cable over which data is carried, and the PSE provides the power to the network cable. The PD also accepts power from an auxiliary power source. The control circuitry detects a change-over from the auxiliary power source to the PSE as a source of power. The control circuitry turns on the switch to control the current to a short circuit current limit level, greater than a startup inrush current limit of the PD, for a period of time less than a short circuit time limit, to charge a bulk capacitor of the PD. The control circuitry turns on the switch fully to allow the current to flow towards the PD.
H02J 9/06 - Circuits pour alimentation de puissance de secours ou de réserve, p. ex. pour éclairage de secours dans lesquels le système de distribution est déconnecté de la source normale et connecté à une source de réserve avec commutation automatique
H02M 3/04 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques
A powered device (PD) interface controller is provided that includes a switch and control circuitry. The switch controls current to a PD from a power sourcing equipment (PSE). The PD accepts power from a network cable over which data is carried, and the PSE provides the power to the network cable. The PD also accepts power from an auxiliary power source. The control circuitry detects a change-over from the auxiliary power source to the PSE as a source of power. The control circuitry turns on the switch to control the current to a short circuit current limit level, greater than a startup inrush current limit of the PD, for a period of time less than a short circuit time limit, to charge a bulk capacitor of the PD. The control circuitry turns on the switch fully to allow the current to flow towards the PD.
A method includes providing a system basis chip that supports at least two power states: a sleep state and an awake state; monitoring for power state information via a hardware interface and via a communication interface, wherein the hardware interface allows communication between a physical layer (PHY) transceiver implemented at the system basis chip and a PHY controller implemented at a microcontroller, and wherein the communication interface allows communication between the system basis chip and the microcontroller; and coordinating a change in power state of the system basis chip at least partially based on reception of power state information via the hardware interface and the communication interface.
A method may include executing, by a processor of a microcontroller system, instructions fetched from a first memory of the microcontroller system; setting the processor of the microcontroller to execute instructions from a second memory of the microcontroller at least partially responsive to a state of an internal signal of the microcontroller; and executing, by the processor of the microcontroller system, instructions fetched from the second memory of the microcontroller system.
A method includes providing a system basis chip that supports at least two power states: a sleep state and an awake state; monitoring for power state information via a hardware interface and via a communication interface, wherein the hardware interface allows communication between a physical layer (PHY) transceiver implemented at the system basis chip and a PHY controller implemented at a microcontroller, and wherein the communication interface allows communication between the system basis chip and the microcontroller; and coordinating a change in power state of the system basis chip at least partially based on reception of power state information via the hardware interface and the communication interface.
G06F 1/3209 - Surveillance d’une activité à distance, p. ex. au travers de lignes téléphoniques ou de connexions réseau
G06F 1/3234 - Économie d’énergie caractérisée par l'action entreprise
G06F 1/3287 - Économie d’énergie caractérisée par l'action entreprise par la mise hors tension d’une unité fonctionnelle individuelle dans un ordinateur
77.
CONTROLLING WHICH MEMORY SOURCE IS UTILIZED FOR FETCHING INSTRUCTIONS BY A PROCESSOR OF A MICROCONTROLLER
A method may include executing, by a processor of a microcontroller system, instructions fetched from a first memory of the microcontroller system; setting the processor of the microcontroller to execute instructions from a second memory of the microcontroller at least partially responsive to a state of an internal signal of the microcontroller, and executing, by the processor of the microcontroller system, instructions fetched from the second memory of the microcontroller system.
G01F 23/263 - Indication ou mesure du niveau des liquides ou des matériaux solides fluents, p. ex. indication en fonction du volume ou indication au moyen d'un signal d'alarme en mesurant des variables physiques autres que les dimensions linéaires, la pression ou le poids, selon le niveau à mesurer, p. ex. par la différence de transfert de chaleur de vapeur ou d'eau en mesurant les variations de capacité ou l'inductance de condensateurs ou de bobines produites par la présence d'un liquide ou d'un matériau solide fluent dans des champs électriques ou électromagnétiques en mesurant les variations de capacité de condensateurs
G01F 23/80 - Dispositions pour le traitement des signaux
G01F 25/20 - Test ou étalonnage des appareils pour la mesure du volume, du débit volumétrique ou du niveau des liquides, ou des appareils pour compter par volume des appareils pour mesurer le niveau des liquides
79.
ADAPTING TO SUPPLY VOLTAGE STRESS AT A SYSTEM BASIS CHIP
An apparatus may include a voltage source, a voltage protection circuit, and a chip powered at least in part via the voltage protection circuit. The chip may include at least one regulated voltage source; and a logic circuit. The logic circuit may determine a state of a supply voltage produced by the voltage protection circuit; determine a state of an input voltage produced by the voltage source; and determine and indicate a predicted state of the supply voltage produced by the voltage protection circuit or a predicted state of the at least one regulated voltage source, in either case at least partially based on the determined state of the supply voltage produced by the voltage protection circuit and the determined state of the input voltage produced by the voltage source.
An apparatus comprises an electrostatic discharge (ESD) protection circuitry including a first diode having a cathode coupled to a first signal input and an anode coupled to a signal ground input, a second diode having a cathode coupled to a second signal input and an anode coupled to the signal ground input, and a third diode having a cathode coupled to the signal ground input and an anode coupled to a substrate ground. In one or more examples, the apparatus comprises an analog front-end including a first analog front-end circuitry coupled to the first signal input and the signal ground input, and a second analog front-end circuitry coupled to the second signal input and the signal ground input.
An apparatus comprises an electrostatic discharge (ESD) protection circuitry including a first diode having a cathode coupled to a first signal input and an anode coupled to a signal ground input, a second diode having a cathode coupled to a second signal input and an anode coupled to the signal ground input, and a third diode having a cathode coupled to the signal ground input and an anode coupled to a substrate ground. In one or more examples, the apparatus comprises an analog front-end including a first analog front-end circuitry coupled to the first signal input and the signal ground input, and a second analog front-end circuitry coupled to the second signal input and the signal ground input.
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
G01D 5/20 - Moyens mécaniques pour le transfert de la grandeur de sortie d'un organe sensibleMoyens pour convertir la grandeur de sortie d'un organe sensible en une autre variable, lorsque la forme ou la nature de l'organe sensible n'imposent pas un moyen de conversion déterminéTransducteurs non spécialement adaptés à une variable particulière utilisant des moyens électriques ou magnétiques influençant la valeur d'un courant ou d'une tension en faisant varier l'inductance, p. ex. une armature mobile
H02H 9/04 - Circuits de protection de sécurité pour limiter l'excès de courant ou de tension sans déconnexion sensibles à un excès de tension
82.
DETECTION OF A STUCK DATA LINE OF A SERIAL DATA BUS
A controller is provided that includes a serial data (SDA) line interface to connect the controller to an SDA line of a two-wire, shared, serial data bus. The controller includes processing circuitry to sample the SDA line to obtain samples of a voltage level on the SDA line, and monitor the samples. The processing circuitry detects a predetermined number of consecutive ones of the monitored samples at a low voltage level, without a low-to-high transition in the voltage level. The processing circuitry indicates a stuck SDA condition based on the detected, predetermined number of consecutive ones of the monitored samples.
Electronic packages comprising: a die with a bond pad, a mold compound encapsulating at least exposed surfaces of the die surrounding the bond pad, and a unitary redistribution layer plate on at least a portion of the mold compound and extending through the mold compound in electrical communication with the bond pad. A method comprising: depositing a plug on a die bond pad, encapsulating a proximal end of the plug and at least a portion of the die proximate the proximal end of the plug with a mold compound, removing the plug from the bond pad to form an opening in the mold compound, and depositing a redistribution layer plate on the mold compound and in the opening in the mold compound on the bond pad.
A method comprising: molding a structural support coating over the gate pad and source pad at the front side of a wafer; back-side processing the wafer to remove a portion of a silicon layer so that the silicon layer has a post-process thickness, wherein the post-process thickness is less than the pre-process thickness; and removing the structural support coating at the front side of the wafer sufficiently to expose the gate pad and source pad. An electronic device comprising: a silicon layer less than 50 µm thick and defining a back side of the electronic device, a metal layer on the silicon layer, wherein the metal layer defines a front side of the electronic device, wherein the metal layer has a source pad and a gate pad; and a structural support coating between the source pad and the gate pad.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 21/78 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels
85.
ELECTRONIC PACKAGE WITH REDISTRIBUTION LAYER PLATE FORMED VIA TEMPORARY PLUG
Electronic packages comprising: a die with a bond pad, a mold compound encapsulating at least exposed surfaces of the die surrounding the bond pad, and a unitary redistribution layer plate on at least a portion of the mold compound and extending through the mold compound in electrical communication with the bond pad. A method comprising: depositing a plug on a die bond pad, encapsulating a proximal end of the plug and at least a portion of the die proximate the proximal end of the plug with a mold compound, removing the plug from the bond pad to form an opening in the mold compound, and depositing a redistribution layer plate on the mold compound and in the opening in the mold compound on the bond pad.
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
86.
DETECTION OF A STUCK DATA LINE OF A SERIAL DATA BUS
A controller is provided that includes a serial data (SDA) line interface to connect the controller to an SDA line of a two-wire, shared, serial data bus. The controller includes processing circuitry to sample the SDA line to obtain samples of a voltage level on the SDA line, and monitor the samples. The processing circuitry detects a predetermined number of consecutive ones of the monitored samples at a low voltage level, without a low-to-high transition in the voltage level. The processing circuitry indicates a stuck SDA condition based on the detected, predetermined number of consecutive ones of the monitored samples.
A target is provided that includes a serial data (SDA) line interface to connect the target to a SDA line of a two-wire, shared, serial data bus. The target includes processing circuitry to transfer output data on to the SDA line, and monitor data on the SDA line. The processing circuitry compares the data on the SDA line and the output data to detect an error condition when the data on the SDA line and the output data differ. And the processing circuitry performs at least one operation to recover from the detected error condition, including at least one of disabling an output SDA pad buffer of the target that transfers the output data on to the SDA line, or asserting a stop condition on the data bus.
A target is provided that includes a serial data (SDA) line interface to connect the target to a SDA line of a two-wire, shared, serial data bus. The target includes processing circuitry to transfer output data on to the SDA line, and monitor data on the SDA line. The processing circuitry compares the data on the SDA line and the output data to detect an error condition when the data on the SDA line and the output data differ. And the processing circuitry performs at least one operation to recover from the detected error condition, including at least one of disabling an output SDA pad buffer of the target that transfers the output data on to the SDA line, or asserting a stop condition on the data bus.
A method comprising: molding a structural support coating over the gate pad and source pad at the front side of a wafer; back-side processing the wafer to remove a portion of a silicon layer so that the silicon layer has a post-process thickness, wherein the post-process thickness is less than the pre-process thickness; and removing the structural support coating at the front side of the wafer sufficiently to expose the gate pad and source pad. An electronic device comprising: a silicon layer less than 50 μm thick and defining a back side of the electronic device, a metal layer on the silicon layer, wherein the metal layer defines a front side of the electronic device, wherein the metal layer has a source pad and a gate pad; and a structural support coating between the source pad and the gate pad.
A method of manufacturing a vapor cell includes forming a body of the vapor cell having walls defining a cavity thereinbetween, the cavity having an amount of a subject material contained therein. The method also includes forming a pore structure having a substrate material with pores of a substantially uniform dimension formed therein, the pore structure disposed along a portion of one or more of the walls of the vapor cell. The method further includes forming a liner material of a uniform thickness over one or more internal surfaces of the pores, wherein the subject material exhibits a reduced wetting angle on the liner material which is less than a wetting angle of the subject material on the substrate material.
H03L 7/26 - Commande automatique de fréquence ou de phaseSynchronisation utilisant comme référence de fréquence les niveaux d'énergie de molécules, d'atomes ou de particules subatomiques
A device includes a switched power converter with an inductor, the power converter to produce a voltage output based on a pulse-width modulated (PWM) signal, and produce a peak current feedback signal, the peak current feedback signal representative of a peak current through the inductor. The device includes a comparator to generate a PWM control input (PCI) signal based on whether the peak current feedback signal has reached a reference current. The device includes a PWM generation circuit to generate the PWM signal to control switching of the switched power converter based on the PCI signal. The device includes a synchronization circuit to delay a change in the PCI signal.
H02M 3/158 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation comprenant plusieurs dispositifs à semi-conducteurs comme dispositifs de commande finale pour une charge unique
92.
SYSTEM AND METHODS FOR FEEDBACK CONTROL IN SWITCHED CONVERTERS
A device includes a switched power converter with an inductor, the power converter to produce a voltage output based on a pulse-width modulated (PWM) signal, and produce a peak current feedback signal, the peak current feedback signal representative of a peak current through the inductor. The device includes a comparator to generate a PWM control input (PCI) signal based on whether the peak current feedback signal has reached a reference current. The device includes a PWM generation circuit to generate the PWM signal to control switching of the switched power converter based on the PCI signal. The device includes a synchronization circuit to delay a change in the PCI signal.
H02M 3/156 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation
93.
TECHNIQUES FOR CONTROLLING VAPOR PRESSURE OF SUBJECT MATERIALS IN VAPOR CELLS AND RELATED METHODS
A method of manufacturing a vapor cell includes forming a body of the vapor cell having walls defining a cavity thereinbetween, the cavity having an amount of a subject material contained therein. The method also includes forming a pore structure having a substrate material with pores of a substantially uniform dimension formed therein, the pore structure disposed along a portion of one or more of the walls of the vapor cell. The method further includes forming a liner material of a uniform thickness over one or more internal surfaces of the pores, wherein the subject material exhibits a reduced wetting angle on the liner material which is less than a wetting angle of the subject material on the substrate material.
G01R 33/26 - Dispositions ou appareils pour la mesure des grandeurs magnétiques faisant intervenir la résonance magnétique pour la mesure de la direction ou de l'intensité de champs magnétiques ou de flux magnétiques utilisant le pompage optique
H03L 7/26 - Commande automatique de fréquence ou de phaseSynchronisation utilisant comme référence de fréquence les niveaux d'énergie de molécules, d'atomes ou de particules subatomiques
94.
WIRELESS POWER TRANSMITTER HAVING MULTI-FREQUENCY OPERATION FOR REDUCED ELECTROMAGNETIC INTERFERENCE, AND RELATED METHODS AND APPARATUSES
A method comprises generating a wireless power transmission signal in one or more transmit coils of a wireless power transmitter and, in a multi-frequency operation of the wireless power transmitter, controlling an operating frequency of the wireless power transmission signal to repeatedly switch between a fundamental frequency and one of a lower frequency and an upper frequency in an alternating manner. The lower frequency is offset from the fundamental frequency by a first offset. The upper frequency is offset from the fundamental frequency by a second offset. The second offset is different from the first offset. The first offset associated with the lower frequency and the second offset associated with the upper frequency are to ensure a transmit power in the multi-frequency operation is substantially the same as a transmit power at the fundamental frequency.
H02J 50/70 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique mettant en œuvre la réduction des champs de fuite électriques, magnétiques ou électromagnétiques
H02J 50/00 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique
H02J 50/12 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique utilisant un couplage inductif du type couplage à résonance
95.
SWITCHED CAPACITORS TO GALVANICALLY ISOLATE AND AMPLIFY ANALOG SIGNALS VIA TRANSFERRED DIFFERENTIAL VOLTAGE SIGNAL
Integrated circuits and methods to provide an operative coupling comprising an input stage and an output stage between an analog input and an analog output; synchronously operate a plurality of high voltage domain switches of the input stage and a plurality of low voltage domain switches of the output stage at a frequency to galvanically isolate the input stage from the output stage across a plurality of capacitors having a plurality of input plates respectively connected to the switches of the input and output stages; supply an analog input signal to the input stage; transfer a differential voltage signal component within a range of a common mode voltage supply from the high voltage domain of the input stage to the low voltage domain of the output stage; differentially amplify the low voltage domain differential voltage signal component; and output an analog output signal.
Integrated circuits and methods to provide an operative coupling comprising an input stage and an output stage between an analog input and an analog output; synchronously operate a plurality of high voltage domain switches of the input stage and a plurality of low voltage domain switches of the output stage at a frequency to galvanically isolate the input stage from the output stage across a plurality of capacitors having a plurality of input plates respectively connected to the switches of the input and output stages; supply an analog input signal to the input stage; transfer a differential voltage signal component within a range of a common mode voltage supply from the high voltage domain of the input stage to the low voltage domain of the output stage; differentially amplify the low voltage domain differential voltage signal component; and output an analog output signal.
A method comprises generating a wireless power transmission signal in one or more transmit coils of a wireless power transmitter and, in a multi-frequency operation of the wireless power transmitter, controlling an operating frequency of the wireless power transmission signal to repeatedly switch between a fundamental frequency and one of a lower frequency and an upper frequency in an alternating manner. The lower frequency is offset from the fundamental frequency by a first offset. The upper frequency is offset from the fundamental frequency by a second offset. The second offset is different from the first offset. The first offset associated with the lower frequency and the second offset associated with the upper frequency are to ensure a transmit power in the multi-frequency operation is substantially the same as a transmit power at the fundamental frequency.
H02J 50/00 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique
H02J 50/12 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique utilisant un couplage inductif du type couplage à résonance
H02J 50/40 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique utilisant plusieurs dispositifs de transmission ou de réception
H02J 50/90 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique mettant en œuvre la détection ou l'optimisation de la position, p. ex. de l'alignement
09 - Appareils et instruments scientifiques et électriques
Produits et services
Computer hardware; semiconductors; microcontrollers;
microcontroller units comprised of semiconductor chips,
integrated circuits, computer memories, electronic memories,
data processing apparatus, and electronic and electrical
control apparatus.
In one implementation a processor has an instruction fetch circuit fetching instructions, the instruction fetch circuit having an input and an output and a decode circuit to decode the fetched instructions, the decode circuit having a first and second input, and an output, wherein the decode circuit first input is coupled to the instruction fetch circuit output receiving the fetched instructions, and an execution circuit executing the decoded fetched instructions, the execution circuit having an input coupled to the decode circuit output to receive the decoded fetched instructions, and a switch instruction circuit (SIC) to detect and execute switch instructions of the fetched instructions, the SIC having an input and an output, wherein the SIC input is coupled to the instruction fetch circuit output to receive the fetched instructions, wherein the SIC output is coupled to the decode circuit second input and the instruction fetch circuit input.
In one implementation a processor has an instruction fetch circuit fetching instructions, the instruction fetch circuit having an input and an output and a decode circuit to decode the fetched instructions, the decode circuit having a first and second input, and an output, wherein the decode circuit first input is coupled to the instruction fetch circuit output receiving the fetched instructions, and an execution circuit executing the decoded fetched instructions, the execution circuit having an input coupled to the decode circuit output to receive the decoded fetched instructions, and a switch instruction circuit (SIC) to detect and execute switch instructions of the fetched instructions, the SIC having an input and an output, wherein the SIC input is coupled to the instruction fetch circuit output to receive the fetched instructions, wherein the SIC output is coupled to the decode circuit second input and the instruction fetch circuit input.
