Systems and methods for periodically determining a stack error using a direct memory access (DMA) call are provided. The method may include periodically determining whether a stack pointer is beyond a limit in a stack through a direct memory access (DMA) call. The method may additionally include identifying a stack error based on a determination that the stack pointer is beyond the limit in the stack. In the method, a periodicity of the determination of whether the stack pointer is beyond the limit in the stack through the DMA call may be based on a size of space between the stack pointer and the limit in the stack.
Synchronization of data transmitted by controllers in an Ethernet multidrop network is controlled through a physical layer (PHY). A head unit of a network sends packets of data including masked fields to the PHY. A match on a data pattern of the masked field triggers the sampling of information at the same time from one or more banks of sensors and actuators. The sampled information is stored and synchronized for transmission back to the head unit via a time slot unique to each PHY based on a timeout delay of the pattern match trigger.
Vapor cells may include a body defining a cavity within the body. The body may include a first substrate bonded to a second substrate at an interface, a first window located on a side of the first substrate opposite the second substrate, and a second window located on a side of the second substrate opposite the first substrate. The first substrate may include a first porous volume extending around a circumference of the cavity and located proximate to the first window. The second substrate may include a second porous volume extending around the circumference of the cavity, the second porous volume located proximate to the first substrate, the second porous volume located distal from the second window.
H03L 7/26 - Commande automatique de fréquence ou de phaseSynchronisation utilisant comme référence de fréquence les niveaux d'énergie de molécules, d'atomes ou de particules subatomiques
4.
DETERMINING AN OPERATIONAL LIMIT FOR A CIRCUIT COMPONENT
A non-transitory computer-readable medium comprising instructions executable by a processor to receive a set of input parameters related to a circuit component and perform an age-dependent analysis of the circuit component based on the set of input parameters. The age-dependent analysis of the circuit component includes performing a series of automated simulations of a non-aged model of the circuit component using each of multiple values of a first operational parameter, performing a series of automated simulations of an aged model of the circuit component using each of the multiple values of the first operational parameter, and comparing respective results of the automated simulations of the non-aged and aged models of the circuit component. The instructions are further executable to determine an operational limit for the circuit component based at least on the age-dependent analysis of the circuit component.
Synchronization of data transmitted by controllers in an Ethernet multidrop network is controlled through a physical layer (PHY). A head unit of a network sends packets of data including masked fields to the PHY. A match on a data pattern of the masked field triggers the sampling of information at the same time from one or more banks of sensors and actuators. The sampled information is stored and synchronized for transmission back to the head unit via a time slot unique to each PHY based on a timeout delay of the pattern match trigger.
An apparatus includes a phase-locked loop (PLL) circuit and a logic circuit. The logic circuit may manage, via one or more programmable operating parameters of the PLL circuit, PLL bandwidth variation exhibited by the PLL circuit due to variations in its manufacturing process (P), supply voltage (V) or temperature (T), i.e., PVT variations exhibited by the PLL circuit.
H03L 1/00 - Stabilisation du signal de sortie du générateur contre les variations de valeurs physiques, p. ex. de l'alimentation en énergie
H03L 7/089 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie le détecteur de phase ou de fréquence engendrant des impulsions d'augmentation ou de diminution
H03L 7/093 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie utilisant des caractéristiques de filtrage ou d'amplification particulières dans la boucle
H03L 7/099 - Détails de la boucle verrouillée en phase concernant principalement l'oscillateur commandé de la boucle
7.
DETERMINING INDICATIONS OF SIGNAL QUALITY BASED ON DIGITAL EYE WIDTH
A method includes generating a digital eye mask representative of a digital eye diagram of bits of a received signal, the bits encoded utilizing zero-crossings; and generating an indication of quality for the received signal, the indication of quality proportional to a determined eye width of the digital eye diagram, the determined eye width obtained from the generated digital eye mask.
A High-Electron-Mobility-Transistor that may include a substrate with a first barrier layer formed over a first buffer layer formed on the substrate. A doped structure formed over a first portion of the first barrier layer. A first insulating layer formed over a second portion of the first barrier layer. A second barrier layer formed over the first insulating layer. A second buffer layer formed over the second barrier layer. A second insulating layer formed over the second buffer layer. A gate electrode formed within a spacer through the second insulating layer, through the second buffer layer, and through the second barrier layer. A drain terminal formed at a first side of the gate electrode and a source terminal formed at a second side of the gate electrode.
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
9.
DETERMINING INDICATIONS OF SIGNAL QUALITY BASED ON DIGITAL EYE WIDTH
A method includes generating a digital eye mask representative of a digital eye diagram of bits of a received signal, the bits encoded utilizing zero-crossings; and generating an indication of quality for the received signal, the indication of quality proportional to a determined eye width of the digital eye diagram, the determined eye width obtained from the generated digital eye mask.
An apparatus includes a phase-locked loop (PLL) circuit and a logic circuit. The logic circuit may manage, via one or more programmable operating parameters of the PLL circuit, PLL bandwidth variation exhibited by the PLL circuit due to variations in its manufacturing process (P), supply voltage (V) or temperature (T), i.e., PVT variations exhibited by the PLL circuit.
H03K 19/003 - Modifications pour accroître la fiabilité
H03L 7/18 - Synthèse de fréquence indirecte, c.-à-d. production d'une fréquence désirée parmi un certain nombre de fréquences prédéterminées en utilisant une boucle verrouillée en fréquence ou en phase en utilisant un diviseur de fréquence ou un compteur dans la boucle
11.
SIGNAL QUALITY ANALYSIS BASED ON DIGITAL CORRELATION
A method may include correlating a digital received signal with a selected data pattern, the selected data pattern comprising one of: a predetermined data pattern or a recovered data pattern; and providing an indication of quality that is proportional to a determined correlation between the digital received signal and the selected data pattern.
H04L 7/02 - Commande de vitesse ou de phase au moyen des signaux de code reçus, les signaux ne contenant aucune information de synchronisation particulière
12.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
A semiconductor device that may include a module. A transistor mounted to the module. A diode mounted to the module, wherein the module is integrated to the transistor.
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
13.
SIMO CONVERTER INCLUDING TRANSIENT ENHANCEMENT LOOP
A single inductor multiple output (SIMO) converter includes an inductor, a plurality of output switches, and a transient enhancement loop (TEL). The inductor includes an input terminal and an output terminal. A plurality of output switches may include respective input terminals and output terminals. The input terminals may be electrically connected to the inductor output terminal. The output terminals may be electrically connected to respective loads. The TEL includes a code generator and a plurality of current sources. The code generator may detect a load transient event and activate at least one of the current sources. The current sources include respective source transistors and sink transistor electrically connected to respective output terminals of the output switches. The source transistors may be electrically connected to a source voltage. The sink transistors may be electrically connected to a ground terminal.
H02M 3/156 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation
14.
METHOD INCLUDING UNDER-ETCHING AN ION-INDUCED DAMAGE LAYER TO FACILITATE SEPARATION OF A SUBSTRATE FILM LAYER FROM AN UNDERLYING SUBSTRATE BULK REGION
A method includes performing an ion beam implant in a semiconductor substrate to form an ion-induced damage layer having a damaged structure, wherein a portion of the substrate above the ion-induced damage layer defines a substrate film region, and a portion below the ion-induced damage layer defines a bulk substrate region. Semiconductor device components are formed on the substrate film region, wherein the substrate film region and semiconductor device components formed thereon define a substrate film-based semiconductor device structure. Vertical openings are formed through the substrate film-based semiconductor device structure and extending down to the ion-induced damage layer. An under-etch is performed through the openings to partially remove the ion-induced damage layer. The substrate film-based semiconductor device structure is separated from the bulk substrate region at the partially removed ion-induced damage layer, and the separated substrate film-based semiconductor device structure is mounted on a carrier.
H01L 21/78 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels
15.
APPARATUS AND METHOD FOR FAULT DETECTION IN A DUAL CORE LOCKSTEP MICROCONTROLLER
A method for fault detection in a dual core lockstep microcontroller is provided. The method may include executing a set of instructions by a first central processing circuitry, executing the set of instructions by one or more second central processing circuitries operating in parallel with the first central processing circuitry, comparing an output from the first central processing circuitry with an output from one or more second central processing circuitries using a first comparator, comparing the output from the first central processing circuitry with the output from the one or more second central processing circuitries using one or more second comparators, and triggering, by at least one logic gate, a fault signal in response to output signals received from the first comparator and the one or more second comparators.
A semiconductor device that may include a module. A transistor mounted to the module. A diode mounted to the module, wherein the module is integrated to the transistor.
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
17.
METHOD INCLUDING AN ION BEAM IMPLANT AND STRESSED FILM FOR SEPARATING A SUBSTRATE FILM REGION FROM A BULK SUBSTRATE REGION
A method comprises performing an ion beam implant in a semiconductor substrate to form an ion-induced damage layer at an implant depth in the semiconductor substrate, wherein a portion of the substrate above the ion-induced damage layer defines a substrate film region, a portion of the substrate below the ion-induced damage layer defines a bulk substrate region. Semiconductor device components are formed on the substrate film region, defining a substrate film-based semiconductor device structure. A stressed film is formed on the semiconductor device components, which introduces internal forces in the substrate film-based semiconductor device structure. The substrate film-based semiconductor device structure is separated from the bulk substrate region at the ion-induced damage layer, wherein the separation is facilitated by (a) the ion-induced damage layer and (b) the internal forces introduced by the stressed film. The separated substrate film-based semiconductor device structure may be mounted on a carrier.
H01L 21/78 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels
H01L 21/683 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension
An automotive Ethernet system-on-chip (SoC) implements a power management state that is a lower power standby for an embedded controller of a physical layer (PHY). The SoC combines an always-on power domain (AON) and a switched power domain (SWP). A power manager activates the lower power standby state through a standby signal sent to a power controller in the AON. The standby state enables the power manager of the SoC to switch a system clock from a high-frequency clock to a low frequency clock generated in the AON and turns off a clock dedicated to the PHY.
G06F 1/3209 - Surveillance d’une activité à distance, p. ex. au travers de lignes téléphoniques ou de connexions réseau
G06F 1/3237 - Économie d’énergie caractérisée par l'action entreprise par désactivation de la génération ou de la distribution du signal d’horloge
G06F 1/3234 - Économie d’énergie caractérisée par l'action entreprise
G06F 1/3246 - Économie d’énergie caractérisée par l'action entreprise par mise hors tension initiée par logiciel
G06F 1/3287 - Économie d’énergie caractérisée par l'action entreprise par la mise hors tension d’une unité fonctionnelle individuelle dans un ordinateur
G06F 1/324 - Économie d’énergie caractérisée par l'action entreprise par réduction de la fréquence d’horloge
19.
HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD FOR MANUFACTURING SAME
A High-Electron-Mobility-Transistor that may include a substrate with a first barrier layer formed over a first buffer layer formed on the substrate. A doped structure formed over a first portion of the first barrier layer. A first insulating layer formed over a second portion of the first barrier layer. A second barrier layer formed over the first insulating layer. A second buffer layer formed over the second barrier layer. A second insulating layer formed over the second buffer layer. A gate electrode formed within a spacer through the second insulating layer, through the second buffer layer, and through the second barrier layer. A drain terminal formed at a first side of the gate electrode and a source terminal formed at a second side of the gate electrode.
H10D 30/47 - Transistors FET ayant des canaux à gaz de porteurs de charge de dimension nulle [0D], à une dimension [1D] ou à deux dimensions [2D] ayant des canaux à gaz de porteurs de charge à deux dimensions, p. ex. transistors FET à nanoruban ou transistors à haute mobilité électronique [HEMT]
H10D 62/17 - Régions semi-conductrices connectées à des électrodes ne transportant pas de courant à redresser, amplifier ou commuter, p. ex. régions de canal
H10D 64/27 - Électrodes ne transportant pas le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. grilles
H10D 62/85 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe III-V, p. ex. GaAs
09 - Appareils et instruments scientifiques et électriques
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Ethernet transceivers; ethernet switches; semiconductors; integrated circuits; microcontrollers; recorded and downloadable computer software and firmware for ethernet configuration; recorded and downloadable computer software and firmware for automotive networking and data Communication Consulting and advising in the fields of computer network configuration and ethernet configuration
A transistor having a drain layer formed within a substrate. A drift layer formed over the drain layer, the drift layer having a recessed portion and a protruding portion with a tee-shaped portion. A well layer formed over the recessed portion of the drift layer. A body layer formed over a first portion of the well layer. A source layer formed over a second portion of the well layer. A JFET layer formed within the tee-shaped portion of the drift layer. An insulating layer formed over a portion of the source layer, over a fourth portion of the well layer along the sides of the protruding portion of the drift layer, and over the tee-shaped portion of the drift layer. A gate electrode formed over the insulating layer.
H10D 30/66 - Transistors FET DMOS verticaux [VDMOS]
H10D 62/13 - Régions semi-conductrices connectées à des électrodes transportant le courant à redresser, amplifier ou commuter, p. ex. régions de source ou de drain
H10D 62/17 - Régions semi-conductrices connectées à des électrodes ne transportant pas de courant à redresser, amplifier ou commuter, p. ex. régions de canal
22.
HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD FOR MANUFACTURING SAME
A High-Electron-Mobility-Transistor having a first barrier layer formed on a first buffer layer formed on a substrate. A second barrier layer having a recessed portion and an upper portion formed over the first barrier layer. A doped structure formed on the first barrier layer and surround by the second barrier layer. A second buffer layer formed over the recessed portion and the upper portion of the second barrier layer. A spacer formed on a portion of the doped structure. An insulating layer formed over the second buffer layer. A gate electrode formed within the spacer through the insulating layer, through the second buffer layer and partially into the upper portion of the second barrier layer. A drain terminal formed at a first side of the gate electrode. A source terminal formed at a second side of the gate electrode.
H10D 30/47 - Transistors FET ayant des canaux à gaz de porteurs de charge de dimension nulle [0D], à une dimension [1D] ou à deux dimensions [2D] ayant des canaux à gaz de porteurs de charge à deux dimensions, p. ex. transistors FET à nanoruban ou transistors à haute mobilité électronique [HEMT]
H10D 62/17 - Régions semi-conductrices connectées à des électrodes ne transportant pas de courant à redresser, amplifier ou commuter, p. ex. régions de canal
H10D 64/27 - Électrodes ne transportant pas le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. grilles
H10D 62/85 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe III-V, p. ex. GaAs
23.
SYSTEM AND METHOD TO INTERFACE BETWEEN TIME-SYNCHRONOUS DATA STREAMING AND PACKETISED DATA STREAMING
An apparatus is provided comprising a buffer in direct memory access communication with a network interface to receive data packets comprising data payload portions containing data in a stream of time-synchronous media, a buffer to temporarily store a plurality of time-synchronous media records extracted from the data payload portions, wherein respective ones of the plurality of time-synchronous media records is associated with a respective media channel, a data router circuit to read one of the plurality of time-synchronous media records from the buffer route that time-synchronous media record to a media interface, and a buffer monitor circuit to monitor a ratio of stored records and read records and to trigger a processor interrupt in the event of a buffer underflow or buffer overflow.
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p. ex. acces direct à la mémoire, vol de cycle
An apparatus for performing self-diagnostics in a microcontroller is provided. The apparatus may include one or more registers to store one or more diagnostic settings, a context switching circuitry to select a diagnostic setting from the one or more diagnostic settings based on a trigger signal, and a peripheral device autonomously switched to the selected diagnostic setting by the context switching circuitry.
A method includes powering up a privileged core while leaving an unprivileged core unpowered, the privileged core and the unprivileged core respectively of a microcontroller; configuring a hardware-based mechanism of access control for the unprivileged core, the configuring at least partially based on control parameters that define access to resources by the unprivileged core; and powering up the unprivileged core, operation of the unprivileged core subject to the hardware-based mechanism of access control.
G06F 21/74 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information opérant en mode dual ou compartimenté, c.-à-d. avec au moins un mode sécurisé
G06F 21/81 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur en agissant sur l’alimentation, p. ex. en branchant ou en débranchant l’alimentation, les fonctions de mise en veille ou de reprise
09 - Appareils et instruments scientifiques et électriques
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
downloadable and recorded computer software for monitoring, correcting, updating, generating, and synchronizing times across networked devices; downloadable and recorded computer software for operation of global positioning system (GPS) and global navigation satellite systems (GNSS) systems; downloadable and recorded computer software for use in collecting, organizing, processing, transmitting and viewing data derived from global positioning system (GPS) and global position global navigation satellite systems (GNSS) receivers and sensors for use in establishing and synchronizing time across networked devices providing online, non-downloadable computer software for monitoring, correcting, updating, generating, and synchronizing times across networked devices; software as a service (SaaS) services featuring software for monitoring, correcting, updating, and synchronizing times across networked devices; providing online, non-downloadable computer software for use in collecting, organizing, processing, transmitting and viewing data derived from global positioning system (GPS) and global navigation satellite systems (GNSS) receivers and sensors for use in establishing and synchronizing time across networked devices
27.
METHOD INCLUDING AN ION BEAM IMPLANT AND STRESSED FILM FOR SEPARATING A SUBSTRATE FILM REGION FROM A BULK SUBSTRATE REGION
A method comprises performing an ion beam implant in a semiconductor substrate to form an ion-induced damage layer at an implant depth in the semiconductor substrate, wherein a portion of the substrate above the ion-induced damage layer defines a substrate film region, a portion of the substrate below the ion-induced damage layer defines a bulk substrate region. Semiconductor device components are formed on the substrate film region, defining a substrate film-based semiconductor device structure. A stressed film is formed on the semiconductor device components, which introduces internal forces in the substrate film-based semiconductor device structure. The substrate film-based semiconductor device structure is separated from the bulk substrate region at the ion-induced damage layer, wherein the separation is facilitated by (a) the ion-induced damage layer and (b) the internal forces introduced by the stressed film. The separated substrate film-based semiconductor device structure may be mounted on a carrier.
H01L 21/265 - Bombardement par des radiations ondulatoires ou corpusculaires par des radiations d'énergie élevée produisant une implantation d'ions
H01L 21/324 - Traitement thermique pour modifier les propriétés des corps semi-conducteurs, p. ex. recuit, frittage
H01L 21/70 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun, ou de parties constitutives spécifiques de ceux-ciFabrication de dispositifs à circuit intégré ou de parties constitutives spécifiques de ceux-ci
A method includes performing an ion beam implant in a semiconductor substrate to form an ion-induced damage layer having a damaged structure, wherein a portion of the substrate above the ion-induced damage layer defines a substrate film region, and a portion below the ion-induced damage layer defines a bulk substrate region. Semiconductor device components are formed on the substrate film region, wherein the substrate film region and semiconductor device components formed thereon define a substrate film-based semiconductor device structure. Vertical openings are formed through the substrate film-based semiconductor device structure and extending down to the ion-induced damage layer. An under-etch is performed through the openings to partially remove the ion-induced damage layer. The substrate film-based semiconductor device structure is separated from the bulk substrate region at the partially removed ion-induced damage layer, and the separated substrate film-based semiconductor device structure is mounted on a carrier.
H01L 21/677 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le transport, p. ex. entre différents postes de travail
H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium
H01L 21/8252 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie III-V
H01L 21/8254 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie II-VI
29.
SIMO CONVERTER INCLUDING TRANSIENT ENHANCEMENT LOOP
A single inductor multiple output (SIMO) converter includes an inductor, a plurality of output switches, and a transient enhancement loop (TEL). The inductor includes an input terminal and an output terminal. A plurality of output switches may include respective input terminals and output terminals. The input terminals may be electrically connected to the inductor output terminal. The output terminals may be electrically connected to respective loads. The TEL includes a code generator and a plurality of current sources. The code generator may detect a load transient event and activate at least one of the current sources. The current sources include respective source transistors and sink transistor electrically connected to respective output terminals of the output switches. The source transistors may be electrically connected to a source voltage. The sink transistors may be electrically connected to a ground terminal.
H02M 3/158 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation comprenant plusieurs dispositifs à semi-conducteurs comme dispositifs de commande finale pour une charge unique
H02M 1/32 - Moyens pour protéger les convertisseurs autrement que par mise hors circuit automatique
30.
ENHANCED LOW-POWER STATE OF EMBEDDED DIGITAL PHY CONTROLLER UTILIZING STANDBY OF SYSTEM-ON-CHIP
An automotive Ethernet system-on-chip (SoC) implements a power management state that is a lower power standby for an embedded controller of a physical layer (PHY). The SoC combines an always-on power domain (AON) and a switched power domain (SWP). A power manager activates the lower power standby state through a standby signal sent to a power controller in the AON. The standby state enables the power manager of the SoC to switch a system clock from a high-frequency clock to a low frequency clock generated in the AON and turns off a clock dedicated to the PHY.
A method includes powering up a privileged core while leaving an unprivileged core unpowered, the privileged core and the unprivileged core respectively of a microcontroller, configuring a hardware-based mechanism of access control for the unprivileged core, the configuring at least partially based on control parameters that define access to resources by the unprivileged core; and powering up the unprivileged core, operation of the unprivileged core subject to the hardware-based mechanism of access control.
A method for fault detection in a dual core lockstep microcontroller is provided. The method may include executing a set of instructions by a first central processing circuitry, executing the set of instructions by one or more second central processing circuitries operating in parallel with the first central processing circuitry, comparing an output from the first central processing circuitry with an output from one or more second central processing circuitries using a first comparator, comparing the output from the first central processing circuitry with the output from the one or more second central processing circuitries using one or more second comparators, and triggering, by at least one logic gate, a fault signal in response to output signals received from the first comparator and the one or more second comparators.
An apparatus comprises a data width converter and a forward error correction (FEC) decoder. The data width converter includes an input to receive an input data stream having an input bit width, a first output to produce a first output data stream having a first output bit width, and a second output to produce a second output data stream having at least a second output bit width. The FEC decoder includes an input to receive the second output data stream having the at least second output bit width. The FEC decoder includes an error correction output to produce one or more error correction values at least partially based on one or more FEC code words in the second output data stream. The one or more error correction values are for correction of one or more symbols, one or more partial symbols, or both, in the first output data stream.
H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.-à-d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.-à-d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité
H03M 13/00 - Codage, décodage ou conversion de code pour détecter ou corriger des erreursHypothèses de base sur la théorie du codageLimites de codageMéthodes d'évaluation de la probabilité d'erreurModèles de canauxSimulation ou test des codes
34.
SEMICONDUCTOR CHIP AND METHOD FOR MANUFACTURING SAME
A semiconductor chip that may include a termination ring. An active region formed within the termination ring. A transistor formed within the active region. A diode formed within the active region.
H01L 23/58 - Dispositions électriques structurelles non prévues ailleurs pour dispositifs semi-conducteurs
H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
H10D 84/60 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors BJT
H10D 12/00 - Dispositifs bipolaires contrôlés par effet de champ, p. ex. transistors bipolaires à grille isolée [IGBT]
H10D 30/66 - Transistors FET DMOS verticaux [VDMOS]
35.
10BASE-T1S TRANSCEIVER REGISTER ACCESS USING CONTROLLER REMAPPING
An apparatus having a controller of a physical layer (PHY) and a transceiver of the PHY controller. The controller includes memory with an address space local to the controller and address space assigned to the transceiver that mirrors register locations in the memory of the transceiver. The controller remaps a frame in a first format, based at least in part on an indication that an access operation is directed to the transceiver register space, to a frame in a second format to access the transceiver registers of the second memory space.
An apparatus is provided comprising a buffer in direct memory access communication with a network interface to receive data packets comprising data payload portions containing data in a stream of time-synchronous media, a buffer to temporarily store a plurality of time-synchronous media records extracted from the data payload portions, wherein respective ones of the plurality of time-synchronous media records is associated with a respective media channel, a data router circuit to read one of the plurality of time-synchronous media records from the buffer route that time-synchronous media record to a media interface, and a buffer monitor circuit to monitor a ratio of stored records and read records and to trigger a processor interrupt in the event of a buffer underflow or buffer overflow.
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p. ex. acces direct à la mémoire, vol de cycle
A device with one-time-programmable (OTP) memory, boot code, volatile memory, and non-volatile memory. Boot code may use information in OTP to authenticate code of an implicit owner of the electronic device; receive a first create owner container request; create a first owner container comprising a first signed data image; store the first owner container; and use the first signed data image to authenticate first executable code associated with the first owner. Boot code may transfer ownership from the first owner to a second owner, including authenticating a signed transfer of ownership command using a key stored in the first owner container and creating a second owner container comprising a second signed data image associated with the second owner; storing the second owner container; revoking the first owner container; and using the second signed data image to authenticate second executable code associated with the second owner of the electronic device.
An apparatus comprises a microelectromechanical system (MEMS) including a semiconductor body. The semiconductor body comprises a first resonator, a second resonator, a supporting portion, and one or more heating elements of a heater. The first resonator is to resonate at a first resonating frequency that is generally frequency-stable over a predetermined temperature range. The second resonator is to resonate at a second resonating frequency that is generally linearly decreasing or increasing as temperature increases over the predetermined temperature range. The supporting portion is to support both the first resonator and the second resonator. The one or more heating elements of the heater are on, or in, the supporting portion.
39.
USB HUB WITH CIRCUITRY TO IDENTIFY AND STORE DEVICE RESPONSE DATA
An apparatus comprises an upstream hub port, a plurality of downstream hub ports, a hub controller, a device response memory accessible to the hub controller, and a routing system connecting (a) the upstream hub port to the plurality of downstream hub ports and (b) respective downstream hub ports to the hub controller. The routing system to communicate device responses from respective downstream hub ports to the hub controller. The hub controller includes hub controller circuitry to identify specified device data in a respective device response received from a respective downstream hub port, and store the specified device data in the device response memory.
A system for processing signals from multiple analog-to-digital converters (ADCs) is provided. The system may include a first ADC to receive a first input signal and convert the first input signal to a first digital signal, a second ADC to obtain a second input signal and convert the second input signal to a second digital signal, a control logic circuitry to receive one or more configuration settings of the first ADC and apply the one or more configuration settings to the second ADC, and a computation logic circuitry to generate one or more computational results in response to comparing the first digital signal and the second digital signal.
A transistor having a drain layer formed within a substrate. A drift layer formed over the drain layer, the drift layer having a recessed portion and a protruding portion with a tee-shaped portion. A well layer formed over the recessed portion of the drift layer. A body layer formed over a first portion of the well layer. A source layer formed over a second portion of the well layer. A JFET layer formed within the tee-shaped portion of the drift layer. An insulating layer formed over a portion of the source layer, over a fourth portion of the well layer along the sides of the protruding portion of the drift layer, and over the tee-shaped portion of the drift layer. A gate electrode formed over the insulating layer.
A High-Electron-Mobility-Transistor having a first barrier layer formed on a first buffer layer formed on a substrate. A second barrier layer having a recessed portion and an upper portion formed over the first barrier layer. A doped structure formed on the first barrier layer and surround by the second barrier layer. A second buffer layer formed over the recessed portion and the upper portion of the second barrier layer. A spacer formed on a portion of the doped structure. An insulating layer formed over the second buffer layer. A gate electrode formed within the spacer through the insulating layer, through the second buffer layer and partially into the upper portion of the second barrier layer. A drain terminal formed at a first side of the gate electrode. A source terminal formed at a second side of the gate electrode.
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
43.
SEMICONDUCTOR CHIP AND METHOD FOR MANUFACTURING SAME
A semiconductor chip that may include a termination ring. An active region formed within the termination ring. A transistor formed within the active region. A diode formed within the active region.
H01L 21/76 - Réalisation de régions isolantes entre les composants
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
44.
10BASE-T1S TRANSCEIVER REGISTER ACCESS USING CONTROLLER REMAPPING
An apparatus having a controller of a physical layer (PHY) and a transceiver of the PHY controller. The controller includes memory with an address space local to the controller and address space assigned to the transceiver that mirrors register locations in the memory of the transceiver. The controller remaps a frame in a first format, based at least in part on an indication that an access operation is directed to the transceiver register space, to a frame in a second format to access the transceiver registers of the second memory space.
A system for processing signals from multiple analog-to-digital converters (ADCs) is provided. The system may include a first ADC to receive a first input signal and convert the first input signal to a first digital signal, a second ADC to obtain a second input signal and convert the second input signal to a second digital signal, a control logic circuitry to receive one or more configuration settings of the first ADC and apply the one or more configuration settings to the second ADC, and a computation logic circuitry to generate one or more computational results in response to comparing the first digital signal and the second digital signal.
An apparatus comprises an upstream hub port, a plurality of downstream hub ports, a hub controller, a device response memory accessible to the hub controller, and a routing system connecting (a) the upstream hub port to the plurality of downstream hub ports and (b) respective downstream hub ports to the hub controller. The routing system to communicate device responses from respective downstream hub ports to the hub controller. The hub controller includes hub controller circuitry to identify specified device data in a respective device response received from a respective downstream hub port, and store the specified device data in the device response memory.
A method for training a serial peripheral interface (SPI) controller is provided. The method may include receiving a first data set at a first clock frequency based on a plurality of delayed clock signals corresponding to a plurality of TAP values, obtaining a second data set at a second clock frequency based on the plurality of delayed clock signals corresponding to the plurality of TAP values, determining a plurality of pass/fail statuses for the respective plurality of TAP values by comparing the second data set obtained at the second clock frequency with the first data set received at the first clock frequency, setting the plurality of pass/fail statuses based on the comparison, and selecting, based on the plurality of pass/fail statuses, a selected TAP value from the plurality of TAP values corresponding to one of the plurality of delayed clock signals.
A method for training a serial peripheral interface (SPI) controller is provided. The method may include receiving a first data set at a first clock frequency based on a plurality of delayed clock signals corresponding to a plurality of TAP values, obtaining a second data set at a second clock frequency based on the plurality of delayed clock signals corresponding to the plurality of TAP values, determining a plurality of pass/fail statuses for the respective plurality of TAP values by comparing the second data set obtained at the second clock frequency with the first data set received at the first clock frequency, setting the plurality of pass/fail statuses based on the comparison, and selecting, based on the plurality of pass/fail statuses, a selected TAP value from the plurality of TAP values corresponding to one of the plurality of delayed clock signals.
An apparatus includes interfaces to direct-current-to-direct-current (DC/DC) power converters, the converters to convert power from Ethernet ports to provide power over Ethernet (POE) through POE front-end (FE) circuits to a powered device (PD) consumer device. The apparatus includes a control circuit to cause redundant power to be selectively provided to the PD consumer device from one of the Ethernet ports. The control circuit may determine power characteristics of the POE FE circuits and, based on a power source being inactive and the power characteristics, determine portions from the DC/DC power converters to provide to the PD consumer device.
H02J 1/08 - Systèmes à trois filsSystèmes ayant plus de trois fils
H02J 1/10 - Fonctionnement de sources à courant continu en parallèle
H02M 1/00 - Détails d'appareils pour transformation
H02M 3/335 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu avec transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrodes de commande pour produire le courant alternatif intermédiaire utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
An apparatus includes: a physical layer device (PHY); a PHY management interface; and a multiport Ethernet device coupled with the PHY via the PHY management interface. The multiport Ethernet device may include: a processor; a set of registers accessible to the processor via an internal bus of the multiport Ethernet device; a management interface controller to construct management frames at the PHY management interface; and a logic circuit to initiate copy of data from a register of the PHY via the management interface controller and store copied PHY register data at the register of the multiport Ethernet device.
H04L 69/323 - Protocoles de communication intra-couche entre entités paires ou définitions d'unité de données de protocole [PDU] dans la couche physique [couche OSI 1]
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
An apparatus includes interfaces to direct-current-to-direct-current (DC/DC) power converters, the converters to convert power from Ethernet ports to provide power over Ethernet (POE) through POE front-end (FE) circuits to a powered device (PD) consumer device. The apparatus includes a control circuit to cause redundant power to be selectively provided to the PD consumer device from one of the Ethernet ports. The control circuit may determine power characteristics of the POE FE circuits and, based on a power source being inactive and the power characteristics, determine portions from the DC/DC power converters to provide to the PD consumer device.
An apparatus includes: a physical layer device (PHY); a PHY management interface; and a multiport Ethernet device coupled with the PHY via the PHY management interface. The multiport Ethernet device may include: a processor; a set of registers accessible to the processor via an internal bus of the multiport Ethernet device; a management interface controller to construct management frames at the PHY management interface; and a logic circuit to initiate copy of data from a register of the PHY via the management interface controller and store copied PHY register data at the register of the multiport Ethernet device.
H04L 49/351 - Interrupteurs spécialement adaptés à des applications spécifiques pour des réseaux locaux [LAN], p. ex. des commutateurs Éthernet
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p. ex. acces direct à la mémoire, vol de cycle
G06F 13/32 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant la combinaison d'interruption et de transfert par rafale
09 - Appareils et instruments scientifiques et électriques
Produits et services
Computer hardware; Computer network interface devices; computer hardware, peripherals, and interface devices for programming and debugging microcontrollers, microprocessors, and integrated circuits; downloadable and recorded computer software for programming and debugging microcontrollers, microprocessors, and integrated circuits
In some implementations, a storage device may receive, from a host device, a write command. The storage device may perform a first write operation to write data on a first word line of a block of a virtual block associated with multiple blocks. The storage device may identify a program error associated with the write operation on the first word line. The storage device may perform a second write operation to write additional data on a second word line of the block. In some aspects, the storage device may perform the second write operation after checking and confirming on the reliability of the block through dummy data write operation on subsequent word lines.
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 16/10 - Circuits de programmation ou d'entrée de données
G11C 29/52 - Protection du contenu des mémoiresDétection d'erreurs dans le contenu des mémoires
A controller and a method is provided for controlling a capacitance of an LC circuit having a circuit frequency including, a variable capacitor to couple with an external inductor as part of an LC circuit, a target value, a spread spectrum function to generate an adjustment value, and a circuit to poll the target value, call the spread spectrum function, and set a capacitance of the variable capacitor based on the sum of the target value and the adjustment value.
In some implementations, a first network node may identify a periodic start time of pseudo-ethernet packets based on an available clock. The first network node may receive a client data stream having a constant data rate. The first network node may generate generic mapping procedure (GMP) overhead information based at least in part on the data rate. The first network node may transmit, to a second network node and using the periodic start time, the client data stream within pseudo-ethernet packets that include the GMP overhead information that indicates an amount of information that arrived at the first network node within a period associated with the periodic start time.
H04J 3/16 - Systèmes multiplex à division de temps dans lesquels le temps attribué à chacun des canaux au cours d'un cycle de transmission est variable, p. ex. pour tenir compte de la complexité variable des signaux, pour adapter le nombre de canaux transmis
57.
METHOD AND APPARATUS FOR DETECTING SERIAL COMMUNICATION COLLISION
A serial communication apparatus is provided. The serial communication apparatus may include a transmitter to transmit data by outputting an output signal, and a collision detection circuitry operatively coupled to the transmitter to receive the output signal. The collision detection circuitry is to receive an input signal from an input buffer, compare the input signal and output signal, and provide a collision indication signal in response to a difference between the output signal and the input signal.
G06F 13/376 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus ou au système à bus communs avec commande d'accès décentralisée utilisant une méthode de résolution des conflits d'utilisation, p. ex. détection de collision, évitement de collision
58.
SYSTEM AND METHOD FOR ENCODING AND DECODING IN COMMUNICATION PROTOCOL
A system for encoding and decoding in a communication protocol is provided, and may include a transmitter having a transmit data buffer to store a data, an encoding circuitry operatively coupled to the transmit data buffer to receive the data from the transmit data buffer and encode the data based on a selected encoding method, and a transmit shift register operatively coupled to the encoding circuitry to receive the encoded data and transmit the encoded data in the bitwise manner. The system may include a receiver having a receive shift register to receive the encoded data, a decoding circuitry operatively coupled to the receive shift register to receive the encoded data from the receive shift register in a parallel manner, and decode the encoded data based on a selected decoding method, and a receive data buffer operatively coupled to the decoding circuitry to receive the decoded data.
A serial communication apparatus is provided. The serial communication apparatus may include a transmitter to transmit data by outputting an output signal, and a collision detection circuitry operatively coupled to the transmitter to receive the output signal. The collision detection circuitry is to receive an input signal from an input buffer, compare the input signal and output signal, and provide a collision indication signal in response to a difference between the output signal and the input signal.
H04L 12/413 - Réseaux à ligne bus avec commande décentralisée avec accès aléatoire, p. ex. accès multiple avec détection de porteuse et détection de collision [CSMA-CD]
A system for encoding and decoding in a communication protocol is provided, and may include a transmitter having a transmit data buffer to store a data, an encoding circuitry operatively coupled to the transmit data buffer to receive the data from the transmit data buffer and encode the data based on a selected encoding method, and a transmit shift register operatively coupled to the encoding circuitry to receive the encoded data and transmit the encoded data in the bitwise manner. The system may include a receiver having a receive shift register to receive the encoded data, a decoding circuitry operatively coupled to the receive shift register to receive the encoded data from the receive shift register in a parallel manner, and decode the encoded data based on a selected decoding method, and a receive data buffer operatively coupled to the decoding circuitry to receive the decoded data.
In some implementations, a storage device may receive, from a host device, a write command. The storage device may perform a first write operation to write data on a first word line of a block of a virtual block associated with multiple blocks. The storage device may identify a program error associated with the write operation on the first word line. The storage device may perform a second write operation to write additional data on a second word line of the block. In some aspects, the storage device may perform the second write operation after checking and confirming on the reliability of the block through dummy data write operation on subsequent word lines.
An apparatus includes a body having walls defining a cavity therebetween, the cavity containing an amount of a subject material therein. A channel structure including a channel substrate with channels having a substantially uniform width formed therein is disposed along a portion of the walls of the body, and a liner material is disposed over portions of internal surfaces of the channels.
A transistor that may include a substrate (20). A drift layer (40) on the substrate. The drift layer having a recessed portion and a protruding portion (50). A well layer (70) within the recessed portion of the drift layer and sides of the protruding portion of the drift layer. A source layer (110) within a portion of the recessed portion of the drift layer and the protruding portion of the drift layer. A JFET layer (75) within the protruding portion of the drift layer. An insulating layer (80) over a portion of the source layer and over a portion of the well layer on the sides of the protruding portion of the drift layer. A gate electrode (85) over a portion of the insulating layer.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
64.
HIGH DEFECT SiC WAFER WITH DEVICE LAYER AND METHODS OF MANUFACTURE
Aspects provide forming hLDD SiC substrate wafers having a number of defects per square centimeter in excess of a predetermined threshold, and using the hLDD SiC substrate wafers to make vertical diffused metal oxide semiconductor (DMOS) field effect transistors (FET). In particular, methods comprise: growing by deposition a SiC ingot; slicing the SiC ingot to produce a plurality of base drift wafers; identifying base drift wafers having a number of defects per square centimeter in excess of a predetermined threshold; and forming a respective device layer on the identified base drift wafers. An aspect provides a DMOS FET having a base drift layer on the device layer and comprising SiC and having a number of defects per square centimeter in excess of a predetermined threshold.
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
H01L 21/18 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives les dispositifs ayant des barrières de potentiel, p. ex. une jonction PN, une région d'appauvrissement ou une région de concentration de porteurs de charges les dispositifs ayant des corps semi-conducteurs comprenant des éléments du groupe IV du tableau périodique, ou des composés AIIIBV, avec ou sans impuretés, p. ex. des matériaux de dopage
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée
65.
HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD FOR MANUFACTURING SAME
A High-Electron-Mobility-Transistor that may include a substrate. A first buffer layer formed on the substrate. A barrier layer formed on the first buffer layer. A doped structure surrounded by the barrier layer. A second buffer layer formed on the barrier layer. A spacer formed on a portion of the doped structure. An insulating layer formed over the second buffer layer. A gate electrode formed within the spacer through the insulating layer, through the second buffer layer and partially into the barrier layer, the gate electrode connected to the doped structure. A drain terminal formed at a first side of the gate electrode. A source terminal formed at a second side of the gate electrode.
H10D 30/47 - Transistors FET ayant des canaux à gaz de porteurs de charge de dimension nulle [0D], à une dimension [1D] ou à deux dimensions [2D] ayant des canaux à gaz de porteurs de charge à deux dimensions, p. ex. transistors FET à nanoruban ou transistors à haute mobilité électronique [HEMT]
H10D 62/17 - Régions semi-conductrices connectées à des électrodes ne transportant pas de courant à redresser, amplifier ou commuter, p. ex. régions de canal
H10D 64/27 - Électrodes ne transportant pas le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. grilles
66.
APPARATUS FOR CONTROLLING VAPOR PRESSURE OF A SUBJECT MATERIAL CONTAINED THEREIN, AND RELATED METHODS AND SYSTEMS
An apparatus includes a body having walls defining a cavity therebetween, the cavity containing an amount of a subject material therein. A channel structure including a channel substrate with channels having a substantially uniform width formed therein is disposed along a portion of the walls of the body, and a liner material is disposed over portions of internal surfaces of the channels.
G04F 5/14 - Appareils pour la production d'intervalles de temps prédéterminés, utilisés comme étalons utilisant des horloges atomiques
B82B 1/00 - Nanostructures formées par manipulation d’atomes ou de molécules, ou d’ensembles limités d’atomes ou de molécules un à un comme des unités individuelles
B82Y 20/00 - Nano-optique, p. ex. optique quantique ou cristaux photoniques
G01C 19/62 - Gyromètres à résonance magnétique nucléaire ou électronique avec pompage optique
G01R 33/26 - Dispositions ou appareils pour la mesure des grandeurs magnétiques faisant intervenir la résonance magnétique pour la mesure de la direction ou de l'intensité de champs magnétiques ou de flux magnétiques utilisant le pompage optique
H01J 65/04 - Lampes à atmosphère gazeuse portée à la luminescence par un champ électromagnétique extérieur ou par une radiation corpusculaire extérieure, p. ex. lampe indicatrice
H03L 7/26 - Commande automatique de fréquence ou de phaseSynchronisation utilisant comme référence de fréquence les niveaux d'énergie de molécules, d'atomes ou de particules subatomiques
A device having a crystal driver to operate according to a voltage transfer curve and a current reference to provide a current bias to the crystal driver to produce a voltage from the crystal driver within a linear region of the voltage transfer curve of the crystal driver, and to determining a gain margin of the crystal driver based on the measured first voltage on the driver output. A method to force a current bias from a current reference on a driver input, to measure the voltage on the driver output within a linear region of the voltage transfer curve of the crystal driver, and determine a gain margin of the crystal driver based on the measured voltage on the driver output.
One or more examples relate, generally to supply voltage based or temperature based fine control of a tunable oscillator of a PLL. An associated method includes: receiving one or more values indicative of temperature or supply voltage of a phase-locked loop (PLL); setting a digital fine-tuning control code to an initialization code, the initialization code at least partially based on the received one or more values indicative of temperature or supply voltage of the PLL, wherein the digital fine-tuning control code for setting a number of tuning-elements within a fine bank of a tunable oscillator; and starting, with the set digital fine-tuning control code, a process to set an initial frequency of the oscillator at or close to a target frequency. The process may be a calibration process performed before initially acquiring lock or re-acquiring lock.
H03L 7/099 - Détails de la boucle verrouillée en phase concernant principalement l'oscillateur commandé de la boucle
H03L 1/00 - Stabilisation du signal de sortie du générateur contre les variations de valeurs physiques, p. ex. de l'alimentation en énergie
H03L 1/02 - Stabilisation du signal de sortie du générateur contre les variations de valeurs physiques, p. ex. de l'alimentation en énergie contre les variations de température uniquement
A device having a crystal driver to operate according to a voltage transfer curve and a current reference to provide a current bias to the crystal driver to produce a voltage from the crystal driver within a linear region of the voltage transfer curve of the crystal driver, and to determining a gain margin of the crystal driver based on the measured first voltage on the driver output. A method to force a current bias from a current reference on a driver input, to measure the voltage on the driver output within a linear region of the voltage transfer curve of the crystal driver, and determine a gain margin of the crystal driver based on the measured voltage on the driver output.
G01R 31/26 - Test de dispositifs individuels à semi-conducteurs
H03B 5/36 - Production d'oscillation au moyen d'un amplificateur comportant un circuit de réaction entre sa sortie et son entrée l'élément déterminant la fréquence étant un résonateur électromécanique un résonateur piézo-électrique l'élément actif de l'amplificateur comportant un dispositif semi-conducteur
09 - Appareils et instruments scientifiques et électriques
Produits et services
Electronic circuits; Semiconductor chips; Semiconductor devices; Computer chips; Integrated circuits; Electronic solid state drives controllers; solid state drives module; non-volatile memory express (NVMe) controllers; integrated circuit for memory controllers, namely, for optimizing storage capacity, interfacing between host computer and storage devices, storing information in non-volatile memory, retrieving information from non-volatile memory, and refreshing and recycling storage capacity
71.
HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD FOR MANUFACTURING SAME
A High-Electron-Mobility-Transistor that may include a substrate. A first buffer layer formed on the substrate. A barrier layer formed on the first buffer layer. A doped structure surrounded by the barrier layer. A second buffer layer formed on the barrier layer. A spacer formed on a portion of the doped structure. An insulating layer formed over the second buffer layer. A gate electrode formed within the spacer through the insulating layer, through the second buffer layer and partially into the barrier layer, the gate electrode connected to the doped structure. A drain terminal formed at a first side of the gate electrode. A source terminal formed at a second side of the gate electrode.
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
H01L 29/66 - Types de dispositifs semi-conducteurs
A transistor that may include a substrate. A drift layer within the substrate. A first JFET layer within a portion of the drift layer. A body layer within a portion of the drift layer. A source layer within an upper portion of the body layer. A second JFET layer within a portion of the drift layer. An insulating layer over a portion of the source layer. A gate electrode over the insulating layer.
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 21/225 - Diffusion des impuretés, p. ex. des matériaux de dopage, des matériaux pour électrodes, à l'intérieur ou hors du corps semi-conducteur, ou entre les régions semi-conductricesRedistribution des impuretés, p. ex. sans introduction ou sans élimination de matériau dopant supplémentaire en utilisant la diffusion dans ou hors d'un solide, à partir d'une ou en phase solide, p. ex. une couche d'oxyde dopée
H01L 21/265 - Bombardement par des radiations ondulatoires ou corpusculaires par des radiations d'énergie élevée produisant une implantation d'ions
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
73.
SYSTEM AND METHOD FOR TRAINING SPI MONITOR FOR HIGH-FREQUENCY OPERATION
Systems and methods for training a serial peripheral interface (SPI) monitor for high-frequency operation include storing a training address in memory, comparing an address accessed by an application processor (AP) with the training address, and providing a reset or interrupt signal to the AP in response to an address match. An iterative training operation is performed to train the SPI monitor for respective SPI clock delay values for an SPI clock delay that includes adjusting, for a respective SPI clock delay value, the SPI clock delay of the SPI monitor, reading data from an external SPI flash memory, comparing the read data with a reference value, and storing a pass/fail status of the read data. A selected SPI clock delay value is determined and the SPI clock delay of the SPI monitor is set to the selected SPI clock delay value.
Systems, methods, and apparatuses include a first counter to count a number of clock pulses received by the communication interface within a predetermined time window, a second counter pre-loaded with a predetermined count value indicating a threshold number of clock pulses expected to be received within the predetermined time window, and a comparator to compare a count value of the second counter to the threshold number of clock pulses. Control circuitry may enable the first counter when a chip select signal is asserted, disable the first counter when the chip select signal is de-asserted, start the second counter when a clock pulse is received, stop the second counter when a predetermined number of clock pulses have been received, and trigger a tamper signal if the count value of the second counter is greater than the threshold number of clock pulses.
A controller may map different ranges of logical block addresses, of a flash translation layer of a storage device, to different segments; and map the different segments to different channels of the storage device. The controller may receive a command to perform a write operation on the storage device. The command may identify a range of logical block addresses. The controller may identify a segment, of the different segments, mapped to the range of logical block addresses; and perform the write operation using one or more channels, of the different channels, mapped to the identified segment.
A transistor that may include a substrate. A drift layer within the substrate. A first JFET layer within a portion of the drift layer. A body layer within a portion of the drift layer. A source layer within an upper portion of the body layer. A second JFET layer within a portion of the drift layer. An insulating layer over a portion of the source layer. A gate electrode over the insulating layer.
An apparatus may include a capacitive touch controller, a ball grid array package, firmware, and a driven shield driver circuitry. The ball grid array package may comprise a plurality of balls arranged in multiple concentric rings. The firmware may dynamically select a driven shield pattern based on a received aspect ratio input corresponding to a capacitive sensor array. The driven shield driver circuitry may activate the driven shield balls according to the dynamically selected driven shield pattern to electrically isolate drive balls from sense balls.
A controller may map different ranges of logical block addresses, of a flash translation layer of a storage device, to different segments; and map the different segments to different channels of the storage device. The controller may receive a command to perform a write operation on the storage device. The command may identify a range of logical block addresses. The controller may identify a segment, of the different segments, mapped to the range of logical block addresses; and perform the write operation using one or more channels, of the different channels, mapped to the identified segment.
Aspects provide forming hLDD SiC substrate wafers having a number of defects per square centimeter in excess of a predetermined threshold, and using the hLDD SiC substrate wafers to make vertical diffused metal oxide semiconductor (DMOS) field effect transistors (FET). In particular, methods comprise: growing by deposition a SiC ingot; slicing the SiC ingot to produce a plurality of base drift wafers; identifying base drift wafers having a number of defects per square centimeter in excess of a predetermined threshold; and forming a respective device layer on the identified base drift wafers. An aspect provides a DMOS FET having a base drift layer on the device layer and comprising SiC and having a number of defects per square centimeter in excess of a predetermined threshold.
B28D 5/04 - Travail mécanique des pierres fines, pierres précieuses, cristaux, p. ex. des matériaux pour semi-conducteursAppareillages ou dispositifs à cet effet par outils autres que ceux du type rotatif, p. ex. par des outils animés d'un mouvement alternatif
C30B 25/18 - Croissance d'une couche épitaxiale caractérisée par le substrat
H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
A transistor that may include a substrate. A drift layer on the substrate. The drift layer having a recessed portion and a protruding portion. A well layer within the recessed portion of the drift layer and sides of the protruding portion of the drift layer. A source layer within a portion of the recessed portion of the drift layer and the protruding portion of the drift layer. A JFET layer within the protruding portion of the drift layer. An insulating layer over a portion of the source layer and over a portion of the well layer on the sides of the protruding portion of the drift layer. A gate electrode over a portion of the insulating layer.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/51 - Matériaux isolants associés à ces électrodes
H01L 29/66 - Types de dispositifs semi-conducteurs
81.
APPARATUS AND METHOD FOR PROCESSING TRANSMIT DATA IN A TRANSMIT DATA PATH INCLUDING PARALLEL FEC ENCODING
An apparatus comprises a data width converter and a forward error correction (FEC) encoder. The data width converter includes an input to receive an input data stream at an input bit width, a first output to produce a first output data stream at a first output bit width, and a second output to produce a second output data stream at a second output bit width. The FEC encoder includes an input to receive the second output data stream at the second output bit width. The FEC encoder includes an output to produce parity bits at least partially based on multiple received symbols of the second output data stream having the second output bit width. The parity bits for insertion in the first output data stream having the first output bit width. In one or more examples, the data width converter is in a transmit data path, and the FEC encoder is in parallel with the transmit data path.
H03M 13/29 - Codage, décodage ou conversion de code pour détecter ou corriger des erreursHypothèses de base sur la théorie du codageLimites de codageMéthodes d'évaluation de la probabilité d'erreurModèles de canauxSimulation ou test des codes combinant plusieurs codes ou structures de codes, p. ex. codes de produits, codes de produits généralisés, codes concaténés, codes interne et externe
H03M 13/00 - Codage, décodage ou conversion de code pour détecter ou corriger des erreursHypothèses de base sur la théorie du codageLimites de codageMéthodes d'évaluation de la probabilité d'erreurModèles de canauxSimulation ou test des codes
82.
SYSTEM AND METHOD FOR RECONSTRUCTING DATA FROM A DEGRADED RAID VOLUME USING AN ACCELERATOR ENGINE
A system and method for reconstructing data from a degraded RAID storage device using an accelerator engine is disclosed. An article of manufacture may include a non-transitory memory having machine-readable instructions that, when executed by a processor, cause the processor to send a first command to a first storage device and a second storage device to trigger the first and second storage devices to write strip data to a memory in an accelerator engine. The instructions may also cause the processor to send a second command to the accelerator engine to perform an operation on the written strip data, the operation to reconstruct data stored on a third failed storage device. The first, second, and third storage devices may be part of a RAID volume. Further, the instructions may cause the processor to receive an output of the operation from the accelerator engine.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
83.
SYSTEM AND METHOD FOR TRAINING SPI MONITOR FOR HIGH-FREQUENCY OPERATION
Systems and methods for training a serial peripheral interface (SPI) monitor for high- frequency operation include storing a training address in memory, comparing an address accessed by an application processor (AP) with the training address, and providing a reset or interrupt signal to the AP in response to an address match. An iterative training operation is performed to train the SPI monitor for respective SPI clock delay values for an SPI clock delay that includes adjusting, for a respective SPI clock delay value, the SPI clock delay of the SPI monitor, reading data from an external SPI flash memory, comparing the read data with a reference value, and storing a pass/fail status of the read data. A selected SPI clock delay value is determined and the SPI clock delay of the SPI monitor is set to the selected SPI clock delay value.
Systems, methods, and apparatuses include a first counter to count a number of clock pulses received by the communication interface within a predetermined time window, a second counter pre-loaded with a predetermined count value indicating a threshold number of clock pulses expected to be received within the predetermined time window, and a comparator to compare a count value of the second counter to the threshold number of clock pulses. Control circuitry may enable the first counter when a chip select signal is asserted, disable the first counter when the chip select signal is de-asserted, start the second counter when a clock pulse is received, stop the second counter when a predetermined number of clock pulses have been received, and trigger a tamper signal if the count value of the second counter is greater than the threshold number of clock pulses.
In some implementations, a storage device may receive, from a host device, a first read command that indicates a first logical address for data stored on the storage device. The storage device may translate the first logical address to a local address of the storage device. The storage device may store an indication of a link between the first logical address and the local address on a random access memory (RAM) of the storage device. The storage device may receive a second read command that indicates a second logical address for stored data on the storage device. The storage device may identify a match between the first logical address and the second local address. The storage device may provide the data to the host device based at least in part on the match and the link between the first logical address and the local address.
A system and method for reconstructing data from a degraded RAID storage device using an accelerator engine is disclosed. An article of manufacture may include a non-transitory memory having machine-readable instructions that, when executed by a processor, cause the processor to send a first command to a first storage device and a second storage device to trigger the first and second storage devices to write strip data to a memory in an accelerator engine. The instructions may also cause the processor to send a second command to the accelerator engine to perform an operation on the written strip data, the operation to reconstruct data stored on a third failed storage device. The first, second, and third storage devices may be part of a RAID volume. Further, the instructions may cause the processor to receive an output of the operation from the accelerator engine.
G06F 11/14 - Détection ou correction d'erreur dans les données par redondance dans les opérations, p. ex. en utilisant différentes séquences d'opérations aboutissant au même résultat
87.
SHIELDING PARTICLES COATED WITH ELECTRICAL INSULATION
Methods to coat shielding particles (114) with an electrically insulating coating, disperse the coated shielding particles in a base material (116) to form a mold structure; and position the mold structure proximate a die (102) of an integrated circuit package to shield the die from radiation. Devices comprising: a die; and a mold structure (112) proximate the die, the mold structure comprising: a base material; and shielding particles (114) comprising an electrically insulating coating, wherein the shielding particles are dispersed in the base material (116).
An apparatus comprises a microcontroller including a digital potentiometer provided in a microcontroller packaging. The digital potentiometer includes a resistor ladder including a plurality of resistors arranged in series and a plurality of selectively controllable potentiometer switches, a first resistor terminal connected to the resistor ladder, and a wiper terminal connected to the resistor ladder. The microcontroller includes a processor to transmit a wiper select signal to the digital potentiometer to selectively control the potentiometer switches to selectively connect at least a subset of the resistors between the first resistor terminal and wiper terminal, to thereby control the resistance between the first resistor terminal and wiper terminal. The microcontroller includes a first pin connected to the first resistor terminal and a second pin connected to the wiper terminal, the first and second pins being exposed through the microcontroller packaging to allow connection of the digital potentiometer to an external device.
A method may include receiving eight bits of information; determining a state transition of a convolutional trellis at least partially based on a two-bit portion of the eight bits of information; determining a group of PAM-modulated symbols at least partially based on the determined state transition of the convolutional trellis, the eight bits of information, and a set of predetermined groups of PAM-modulated symbols pre-associated with the determined state transition of the convolutional trellis; and encoding the eight bits of information into the determined group of PAM-modulated symbols.
H04L 25/49 - Circuits d'émissionCircuits de réception à conversion de code au transmetteurCircuits d'émissionCircuits de réception à pré-distorsionCircuits d'émissionCircuits de réception à insertion d'intervalles morts pour obtenir un spectre de fréquence désiréCircuits d'émissionCircuits de réception à au moins trois niveaux d'amplitude
In some implementations, a storage device may receive, from a host device, a first read command that indicates a first logical address for data stored on the storage device. The storage device may translate the first logical address to a local address of the storage device. The storage device may store an indication of a link between the first logical address and the local address on a random access memory (RAM) of the storage device. The storage device may receive a second read command that indicates a second logical address for stored data on the storage device. The storage device may identify a match between the first logical address and the second local address. The storage device may provide the data to the host device based at least in part on the match and the link between the first logical address and the local address.
An electronic device includes a touch detection system and a noise detection system. The touch detection system includes a first capacitive sensing channel, and a touch detection circuitry to perform a series of touch detections based on a capacitance on the first capacitive sensing channel. The noise detection system includes a second capacitive sensing channel, and a noise detection circuitry to perform at least one noise detection measurement, wherein a respective noise detection measurement comprises determining a respective noise-related capacitance measure associated with a capacitance on the second capacitive channel. The noise detection system to determine a presence of a noise condition based on the at least one noise detection measurement, and in response to determining the noise condition, generate a touch detection inhibit signal to inhibit at least one touch detection in the series of touch detections.
An apparatus comprises a microcontroller including a digital potentiometer provided in a microcontroller packaging. The digital potentiometer includes a resistor ladder including a plurality of resistors arranged in series and a plurality of selectively controllable potentiometer switches, a first resistor terminal connected to the resistor ladder, and a wiper terminal connected to the resistor ladder. The microcontroller includes a processor to transmit a wiper select signal to the digital potentiometer to selectively control the potentiometer switches to selectively connect at least a subset of the resistors between the first resistor terminal and wiper terminal, to thereby control the resistance between the first resistor terminal and wiper terminal. The microcontroller includes a first pin connected to the first resistor terminal and a second pin connected to the wiper terminal, the first and second pins being exposed through the microcontroller packaging to allow connection of the digital potentiometer to an external device.
Methods to coat shielding particles with an electrically insulating coating, disperse the coated shielding particles in an base material to form a mold structure; and position the mold structure proximate a die of an integrated circuit package to shield the die from radiation. Devices comprising: a die; and a mold structure proximate the die, the mold structure comprising: an base material; and shielding particles comprising an electrically insulating coating, wherein the shielding particles are dispersed in the base material.
An electronic device includes a touch detection system and a noise detection system. The touch detection system includes a first capacitive sensing channel, and a touch detection circuitry to perform a series of touch detections based on a capacitance on the first capacitive sensing channel. The noise detection system includes a second capacitive sensing channel, and a noise detection circuitry to perform at least one noise detection measurement, wherein a respective noise detection measurement comprises determining a respective noise-related capacitance measure associated with a capacitance on the second capacitive channel. The noise detection system to determine a presence of a noise condition based on the at least one noise detection measurement, and in response to determining the noise condition, generate a touch detection inhibit signal to inhibit at least one touch detection in the series of touch detections.
A foreign object may be detected by measuring inductance and resistance of a transmitter coil using a meter circuit when a plurality of currents are applied to the transmitter coil when the transmitter coil is in standalone conditions and when a receiver coil is mated to the transmitter coil without a foreign object present. A simulation model is generated based on the measured inductance and resistance of the transmitter coil and receiver coil and comprising a characteristic curve as a function of the plurality of currents applied to the transmitter coil. With the receiver coil mated to the transmitter coil, a foreign object may be detected by measuring a power loss from the transmitter coil to the receiver coil based on the simulation model.
H02J 50/60 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique sensibles à la présence d’objets étrangers, p. ex. détection d'êtres vivants
H02J 50/10 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique utilisant un couplage inductif
A method may include receiving eight bits of information; determining a state transition of a convolutional trellis at least partially based on a two-bit portion of the eight bits of information; determining a group of PAM-modulated symbols at least partially based on the determined state transition of the convolutional trellis, the eight bits of information, and a set of predetermined groups of PAM-modulated symbols pre-associated with the determined state transition of the convolutional trellis; and encoding the eight bits of information into the determined group of PAM-modulated symbols.
H04L 25/49 - Circuits d'émissionCircuits de réception à conversion de code au transmetteurCircuits d'émissionCircuits de réception à pré-distorsionCircuits d'émissionCircuits de réception à insertion d'intervalles morts pour obtenir un spectre de fréquence désiréCircuits d'émissionCircuits de réception à au moins trois niveaux d'amplitude
H04L 25/03 - Réseaux de mise en forme pour émetteur ou récepteur, p. ex. réseaux de mise en forme adaptatifs
97.
REDUCING DUTY CYCLE MISMATCH OF CLOCKS FOR CLOCK TRACKING CIRCUITS
One or more examples relate to a method. The method may include: setting, at least partially based on an indication of mismatch between duty cycles of a first clock and a second clock generated to track the first clock, a duty cycle of a third clock; and providing the third clock having set duty cycle to an error detector of the clock tracking circuit in place of one of the first clock or the second clock.
H03L 7/081 - Détails de la boucle verrouillée en phase avec un déphaseur commandé additionnel
H03K 5/135 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés par l'utilisation de signaux de référence de temps, p. ex. des signaux d'horloge
H03K 5/156 - Dispositions dans lesquelles un train d'impulsions est transformé en un train ayant une caractéristique désirée
A system for monitoring analog-front-end (AFE) circuitry of an inductive position sensor is provided. The system may include a sine signal AFE channel coupled to the inductive position sensor, a sine AFE channel buffer, a cosine signal AFE channel coupled to the inductive position sensor, a cosine AFE channel buffer, an automatic gain control (AGC) circuit coupled to the sine signal AFE channel, a memory to store a plurality of parameters, and a processor. The processor may obtain a first voltage difference between a sine AFE output voltage and an estimated sine AFE output voltage, obtain a second voltage difference between a cosine AFE output voltage and an estimated cosine AFE output voltage, determine if the first or second voltage difference is greater than a predetermined threshold value, and signal a fault condition if the first or second voltage difference is greater than the predetermined threshold value.
G01D 3/08 - Dispositions pour la mesure prévues pour les objets particuliers indiqués dans les sous-groupes du présent groupe avec dispositions pour protéger l'appareil, p. ex. contre les fonctionnements anormaux, contre les pannes
G01D 5/20 - Moyens mécaniques pour le transfert de la grandeur de sortie d'un organe sensibleMoyens pour convertir la grandeur de sortie d'un organe sensible en une autre variable, lorsque la forme ou la nature de l'organe sensible n'imposent pas un moyen de conversion déterminéTransducteurs non spécialement adaptés à une variable particulière utilisant des moyens électriques ou magnétiques influençant la valeur d'un courant ou d'une tension en faisant varier l'inductance, p. ex. une armature mobile
An apparatus and method for an adaptive diode emulation mode offset circuit is disclosed. The apparatus includes a polarity detection circuit to identify the polarity of a phase node of a DC-DC converter; and an adaptive diode emulation mode (DEM) offset circuit to: detect a first early termination or a first late termination of an on time of a low-side gate drive of the DC-DC converter based on the identified polarity of the phase node; and output an offset voltage to selectively terminate on time of the low-side gate drive to mitigate a second early termination or a second late termination of the low-side gate drive, a value of the offset voltage based on a polarity of the phase node of the DC-DC converter; wherein the second early termination occurs after the first early termination and the second late termination occurs after the first late termination.
H02M 1/00 - Détails d'appareils pour transformation
H02M 3/158 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation comprenant plusieurs dispositifs à semi-conducteurs comme dispositifs de commande finale pour une charge unique
100.
ASSIGNING TRANSMIT SIGNALS FOR SUPERIMPOSED QUADRATURE RECEIVE SIGNAL
Systems and methods to simultaneously transmit a plurality of transmit signals, assign control logic to assign transmit signals to transmitters, receive a superimposed receive signal comprising a plurality of receive signal components originating from the transmit signals, wherein two receive signal components of the superimposed receive signal are in quadrature. Capacitive touch systems and methods comprising: transmitters of transmit signals; transmit electrodes and a receive electrode positioned to have mutual capacitances between the transmit electrodes and the receive electrode at mutual capacitance nodes, wherein a mutual capacitance at a mutual capacitance node deviates when an interfering object is proximate, wherein the transmit electrodes are physically adjacent, wherein the transmit electrodes are driven by the transmit signals, and a receiver of a superimposed receive signal comprising receive signal components that are in quadrature.
H04B 1/00 - Détails des systèmes de transmission, non couverts par l'un des groupes Détails des systèmes de transmission non caractérisés par le milieu utilisé pour la transmission
