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2025
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P/S
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Recorded computer software and hardware for use in semiconductor design and manufacturing; downlo... |
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Invention
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Computing parasitic values for semiconductor designs.
Some embodiments provide a method for calc... |
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Invention
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Methods for modeling of a design in reticle enhancement technology.
A method for manufacturing a... |
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P/S
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Computer software and hardware for use in semiconductor
design and manufacturing. Technical cons... |
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Invention
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Method for computational metrology and inspection for patterns to be manufactured on a substrate.... |
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Invention
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Method for reticle enhancement technology of a design pattern to be manufactured on a substrate. ... |
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Invention
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Geometric loading effect correction for lithography. Methods and systems involve a plurality of p... |
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Invention
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Method and system for reticle enhancement technology.
Methods and systems incorporate variable s... |
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Invention
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Computation of parasitic values for interconnect segments.
Some embodiments provide a method for... |
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Invention
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Parasitics extraction for interconnect segments in 3d regions.
Some embodiments provide a method... |
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Invention
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Tiling of layout for parasitics extraction.
Some embodiments provide a method for calculating pa... |
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Invention
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Iterative parasitics extraction for interconnect segments in different tiles.
Some embodiments p... |
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Invention
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Dynamic computation of tile size for parasitics extraction.
Some embodiments provide a method ca... |
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2024
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Invention
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Correcting rule violations in a layout.
Some embodiments provide a method for performing pixel-b... |
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Invention
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Pixel-based rule check for layouts.
Some embodiments provide a method for performing pixel-based... |
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Invention
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Mask optimization preferentially accounting for overlap regions.
Some embodiments provide a meth... |
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Invention
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Mask optimization for first layer that accounts for other layers.
Some embodiments provide a met... |
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Invention
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Iterative mask optimization biased towards critical regions of layout.
Some embodiments provide ... |
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Invention
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Concurrent mask optimization for multiple layers.
Some embodiments provide a method for modifyin... |
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Invention
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Variation in taper angles of predicted manufactured shapes for parasitics extraction.
Some embod... |
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Invention
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High accuracy parasitics extraction.
Some embodiments provide a method for performing parasitic ... |
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Invention
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Mask optimization for layer accounting for overlap with other layers.
Some embodiments provide a... |
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Invention
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Mask optimization for layer based on comparison of components in layer to components in other lay... |
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Invention
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Mask optimization accounting for more critical and less critical overlap regions.
Some embodimen... |
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Invention
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Parasitics extraction based on multiple manufacturing process variations.
Some embodiments provi... |
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Invention
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Generation of 3-d shapes for eda operations.
Some embodiments provide q method for performing an... |
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Invention
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Generation of 3-d shapes for eda operations.
Some embodiments provide a method for performing an... |
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P/S
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Computer software for use in semiconductor design and
manufacturing. |
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P/S
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Computer software and hardware for use in semiconductor
design and manufacturing. |
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Invention
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Methods and systems for reticle enhancement technology of a design pattern to be manufactured on ... |
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Invention
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Methods for modeling of a design in reticle enhancement technology. Methods for reticle enhanceme... |
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Invention
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Method and system for reticle enhancement technology. Methods incorporate variable side wall angl... |
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2023
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Invention
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Modeling of a design in reticle enhancement technology.
Methods and systems for reticle enhancem... |
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P/S
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Recorded computer software and hardware for use in
semiconductor design and manufacturing; downl... |
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Invention
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Method and system for determining a charged particle beam exposure for a local pattern density. M... |
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Invention
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Using a machine trained network during routing to account for opc cost.
Some embodiments use a m... |
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Invention
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Using machine trained network during routing to perform parasitic extraction for an ic design.
S... |
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Invention
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Using machine trained network during routing to modify locations of vias in an ic design.
Some e... |
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Invention
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Using topological and geometric routers to produce curvilinear routes.
Some embodiments of the i... |
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Invention
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Integrated circuit with non-preferred direction curvilinear wiring.
Some embodiments of the inve... |
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Invention
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Routing non-preferred direction wiring layers of an integrated circuit by minimizing vias between... |
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Invention
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Generating routes for an integrated circuit design with non-preferred direction curvilinear wirin... |
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Invention
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Using pixel-based definition of an integrated circuit design to perform machine-trained routing. ... |
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Invention
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Training machine-trained network to perform drc check.
A method for performing pixel-based desig... |
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2018
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P/S
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Computer software and hardware for use in semiconductor
design and manufacturing, including comp... |
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P/S
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Computer software and hardware for use in semiconductor design and manufacturing, including compu... |
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2012
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P/S
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Computer software for use in semiconductor design and manufacturing |
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2011
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P/S
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Computer software and hardware for use in semiconductor design and manufacturing |
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2008
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P/S
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Computer software and hardware for use in semiconductor manufacturing, including computer softwar... |
