Applied Materials, Inc.

United States of America

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        Patent 18,018
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[Owner] Applied Materials, Inc. 18,621
Applied Materials Israel, Ltd. 53
Date
New (last 4 weeks) 185
2025 July (MTD) 179
2025 June 167
2025 May 168
2025 April 226
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IPC Class
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components 3,472
H01J 37/32 - Gas-filled discharge tubes 2,827
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof 2,630
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber 1,604
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping 1,303
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NICE Class
07 - Machines and machine tools 320
09 - Scientific and electric apparatus and instruments 298
37 - Construction and mining; installation and repair services 61
42 - Scientific, technological and industrial services, research and design 29
17 - Rubber and plastic; packing and insulating materials 25
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Status
Pending 2,536
Registered / In Force 16,085
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1.

MAGNETIC LEVITATION SYSTEM FOR SUBSTRATE SUPPORT DEVICE

      
Application Number 18422304
Status Pending
Filing Date 2024-01-25
First Publication Date 2025-07-31
Owner Applied Materials, Inc. (USA)
Inventor Aust, Henning

Abstract

A substrate support device is provided. The substrate support device includes a base secured to a processing chamber. The base includes a stator configured to generate a first magnetic field, a second magnetic field, and a third magnetic field. The substrate support device further includes a substrate support above the base for supporting a substrate. The substrate support includes a rotor with a first reactive region that interacts with the first magnetic field to control a vertical position of the substrate support, and interacts with the second magnetic field to center the substrate support to the base. The substrate support includes a second reactive region that interacts with the third magnetic field to rotate the substrate support. The first magnetic field and the first reactive region selectively levitate the substrate support to any distance within a range from 0 mm to 6 mm above a resting position.

IPC Classes  ?

  • H02N 15/00 - Holding or levitation devices using magnetic attraction or repulsion, not otherwise provided for

2.

ALLOY MICROSTRUCTURE FORMATION FOR CHAMBER COMPONENTS

      
Application Number 18422570
Status Pending
Filing Date 2024-01-25
First Publication Date 2025-07-31
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Liao, Chien-Min
  • Liu, Chao C.
  • Cho, Tom
  • Kim, Hyeon Geu
  • Ponnekanti, Hari
  • Merkel, Jay
  • Alger, Bruce
  • Janjam, Sathish Babu
  • Chou, Cheng-Hsuan

Abstract

Described herein is a chamber component having a body comprising a plurality of aluminum alloy compositions. A first portion of the body includes a first aluminum alloy composition having a first grain size, and a second portion of the body includes a second aluminum alloy composition having a second grain size, wherein the first grain size of the first aluminum alloy composition is greater than the second grain size of the second aluminum alloy composition. A method for preparing the chamber component is also provided.

IPC Classes  ?

  • B22F 1/16 - Metallic particles coated with a non-metal
  • B33Y 10/00 - Processes of additive manufacturing
  • B33Y 80/00 - Products made by additive manufacturing
  • C23C 16/40 - Oxides
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber

3.

GROWTH SUPPRESSION DEPOSITION FOR CVD TUNGSTEN GAP FILL WITH THERMAL TREATMENT

      
Application Number 18425408
Status Pending
Filing Date 2024-01-29
First Publication Date 2025-07-31
Owner Applied Materials, Inc. (USA)
Inventor
  • Li, Yang
  • Wang, Peiqi
  • Wu, Kai
  • Iu, Dongming
  • Yu, Xiaozhou
  • Ha, Insu
  • Zhu, Meng

Abstract

Embodiments of the disclosure provided herein include systems and methods for forming low resistivity tungsten features in a semiconductor device manufacturing scheme using growth suppression techniques. The system includes a processing chamber, a gas delivery system, and a system controller configured to expose at least one opening formed in a multi-tier structure of a substrate to a tungsten-containing precursor and a nucleation reducing agent. The tungsten-containing precursor and the nucleation reducing agent are alternated cyclically to form a nucleation layer within the at least one opening of the substrate. The system controller is further configured to expose the at least one opening of the substrate to a nitrogen-containing gas, a tungsten-containing gas, and a gapfill reducing agent gas to produce a non-uniform tungsten nitride passivation layer in the at least one opening.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • C23C 16/04 - Coating on selected surface areas, e.g. using masks
  • C23C 16/14 - Deposition of only one other metal element
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/56 - After-treatment

4.

MULTI-PURPOSE CONFOCAL SENSOR SYSTEMS

      
Application Number 18425460
Status Pending
Filing Date 2024-01-29
First Publication Date 2025-07-31
Owner Applied Materials, Inc. (USA)
Inventor
  • Zhu, Zhaozhao
  • Meyer, Jon
  • Chakarian, Varoujan

Abstract

A method includes causing, by at least one processing device, a confocal sensor system to make a plurality of signal measurements of a target material, each signal measurement of the plurality of signal measurements corresponding to a respective distance of a plurality of distances between a confocal sensor of the confocal sensor system and the target material, generating, by the at least one processing device, target scan data for the target material based on the plurality of signal measurements, and measuring, by the at least one processing device, at least one property of the target material based on the target scan data.

IPC Classes  ?

  • G01B 11/06 - Measuring arrangements characterised by the use of optical techniques for measuring length, width, or thickness for measuring thickness

5.

PLASMA SHOWERHEAD TREATMENT METHODS

      
Application Number 18425675
Status Pending
Filing Date 2024-01-29
First Publication Date 2025-07-31
Owner Applied Materials, Inc. (USA)
Inventor
  • Chen, Hanhong
  • Zhang, Zhejun
  • Lin, Chi-Chou

Abstract

Methods of treating a plasma showerhead comprise placing a showerhead comprising a faceplate and a plurality of gas openings PECVD substrate processing chamber having a process volume between the substrate support and the faceplate, and then exposing the showerhead to a silicon-containing precursor and a reactant gas so that the process volume and the gas openings are filled with the silicon-containing precursor and the reactant gas. The method includes introducing a first plasma in the PECVD substrate processing chamber to form a silicon oxide thin film or a silicon nitride thin film on the lower surface of the faceplate and lining the gas openings. A precursor-removing purge gas is flowed and a second plasma is struck to densify the thin film.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

6.

PROTECTION LAYER FOR OLED SUB-PIXELS

      
Application Number 18989192
Status Pending
Filing Date 2024-12-20
First Publication Date 2025-07-31
Owner Applied Materials, Inc. (USA)
Inventor
  • Lee, Jungmin
  • Haas, Dieter
  • Mcdaniel, Gregory Max
  • Lin, Yu-Hsin

Abstract

Embodiments described herein relate to a sub-pixel. In one or more embodiments, a sub-pixel includes a substrate and overhang structures. The overhang structures include an extension disposed past a sidewall of the overhang structures. The sub-pixel further includes an anode disposed over the substrate, an inorganic layer disposed under each extension of the overhang structures, and organic light-emitting diode (OLED) material disposed over the anode. The OLED material is disposed between the inorganic layer under each extension of the overhang structures; The sub-pixel further includes a cathode disposed over the OLED material.

IPC Classes  ?

  • H10K 59/80 - Constructional details
  • H10K 59/12 - Active-matrix OLED [AMOLED] displays
  • H10K 59/122 - Pixel-defining structures or layers, e.g. banks
  • H10K 102/00 - Constructional details relating to the organic devices covered by this subclass

7.

VENTING HOLE ON PASSIVATION LAYER ON TOP OF GAP-FILL

      
Application Number 18750987
Status Pending
Filing Date 2024-06-21
First Publication Date 2025-07-31
Owner Applied Materials, Inc. (USA)
Inventor Lee, Jungmin

Abstract

Embodiments of the present disclosure relate to sub-pixel devices and methods related to relate to sub-pixel circuits and methods of forming sub-pixel circuits that may be utilized in a display such as an organic light-emitting diode (OLED) display. The sub-pixel includes a substrate, overhang pixel isolation structures (PIS), overhang structures, where the overhang structures include an extension disposed past a sidewall of the overhang structures, separation PIS, a metal structure disposed over the substrate, an inorganic layer disposed over each overhang PIS and over each separation PIS, where the inorganic layer includes a plurality of openings, organic light-emitting diode (OLED) material disposed over the metal structure, where the OLED material is disposed between the inorganic layer under each extension of the overhang structures, and a cathode disposed over the OLED material.

IPC Classes  ?

8.

CONTROL OF SUBSTRATE DEFORMATION DURING MANUFACTURING PROCESSES

      
Application Number 19034428
Status Pending
Filing Date 2025-01-22
First Publication Date 2025-07-31
Owner Applied Materials, Inc. (USA)
Inventor
  • Subrahmanyan, Pradeep Kumar
  • Lee, Wonjae

Abstract

Disclosed techniques include obtaining a wafer with a front side supporting deposited features and identifying first characteristics of one or more protective films and second characteristics of one or more stress-compensation layers (SCLs). The techniques further include forming the protective film(s) on the front side of the wafer and depositing the SCLs on the back side of the wafer. The techniques further include subjecting at least one SCL to a stress-modulation beam causing a saddle deformation of the wafer to be reduced and removing the protective film(s) from the one or more deposited features.

IPC Classes  ?

  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 21/3105 - After-treatment
  • H01L 21/66 - Testing or measuring during manufacture or treatment

9.

OVERHANG PATTERN FOR ADVANCED OLED PATTERNING

      
Application Number 18643809
Status Pending
Filing Date 2024-04-23
First Publication Date 2025-07-31
Owner Applied Materials, Inc. (USA)
Inventor Lee, Jungmin

Abstract

Embodiments described herein relate to a device. The device includes a substrate, a plurality of overhang structures disposed over the substrate, and a plurality of sub-pixels. Each overhang structure includes a first structure, a second structure disposed over the first structure, and adjacent overhangs. The first structure includes an upper section and a lower section. The upper section includes a sidewall parallel to a surface normal of the substrate. The lower section includes a top surface with a first width equal to a second width of a lower surface of the upper section and a lower surface of the first structure having a third width greater than the second width of the lower surface of the upper section. The adjacent overhangs are defined by an overhang extension of the second structure extending laterally past the upper surface of the first structure.

IPC Classes  ?

  • H10K 59/173 - Passive-matrix OLED displays comprising banks or shadow masks
  • H10K 59/12 - Active-matrix OLED [AMOLED] displays
  • H10K 59/122 - Pixel-defining structures or layers, e.g. banks

10.

PROTECTION LAYER FOR OLED SUB-PIXELS

      
Application Number 19060243
Status Pending
Filing Date 2025-02-21
First Publication Date 2025-07-31
Owner Applied Materials, Inc. (USA)
Inventor
  • Lee, Jungmin
  • Haas, Dieter
  • Mcdaniel, Gregory Max
  • Lin, Yu-Hsin

Abstract

Embodiments described herein relate to a sub-pixel. In one or more embodiments, a sub-pixel includes a substrate and overhang structures. The overhang structures include an extension disposed past a sidewall of the overhang structures. The sub-pixel further includes an anode disposed over the substrate, an inorganic layer disposed under each extension of the overhang structures, and organic light-emitting diode (OLED) material disposed over the anode. The OLED material is disposed between the inorganic layer under each extension of the overhang structures; The sub-pixel further includes a cathode disposed over the OLED material.

IPC Classes  ?

  • H10K 59/80 - Constructional details
  • H10K 59/12 - Active-matrix OLED [AMOLED] displays
  • H10K 59/122 - Pixel-defining structures or layers, e.g. banks
  • H10K 102/00 - Constructional details relating to the organic devices covered by this subclass

11.

EXTREME EDGE SHEATH TUNABILITY WITH NON-MOVABLE EDGE RING

      
Application Number 18427509
Status Pending
Filing Date 2024-01-30
First Publication Date 2025-07-31
Owner Applied Materials, Inc. (USA)
Inventor
  • Dash, Shreeram Jyoti
  • Muraoka, Peter
  • Nichols, Michael T.

Abstract

Embodiments described herein generally related to a substrate processing apparatus. In one embodiment, a process kit for a substrate processing chamber disclosed herein. The process kit includes an edge ring configured to circumscribe a substrate in the semiconductor processing chamber, at least one conductive pin electrically coupled to the edge ring, a sliding ring positioned beneath the edge ring and comprising at least one insert hole for receiving the at least one conductive, and an actuator operable to displace the sliding ring relative to the at least one conductive pin along a direction that changes an amount of capacitive coupling between the at least one conductive pin and the sliding ring.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping

12.

SYSTEMS AND METHODS FOR HIGH-THROUGHPUT ANGLED ION PROCESSING

      
Application Number 18424470
Status Pending
Filing Date 2024-01-26
First Publication Date 2025-07-31
Owner Applied Materials, Inc. (USA)
Inventor
  • Likhanskii, Alexandre
  • Biloiu, Costel
  • Teo, Russell Chin Yee
  • Campbell, Christopher

Abstract

Disclosed herein are systems and methods for high throughput angled ion processing. In one approach, a processing apparatus may include a chamber operable to contain a plasma, the chamber defined by a plurality of sidewalls, a first end wall, and a second end wall opposite the first end wall, an extraction assembly coupled to the second end wall, the extraction assembly comprising a plurality of apertures, wherein ions are extracted through the plurality of apertures are delivered to a substrate at a non-zero angle relative to a perpendicular extending from the substrate, and wherein the substrate is positioned external to the chamber. The processing apparatus may further include an actuator operable to shift the substrate relative to the moveable plates as the ions are extracted through the plurality of apertures.

IPC Classes  ?

13.

MAGNETOCALORIC REFRIGERATION FOR SEMICONDUCTOR APPLICATIONS

      
Application Number 19036169
Status Pending
Filing Date 2025-01-24
First Publication Date 2025-07-31
Owner Applied Materials, Inc. (USA)
Inventor
  • Arun, Kadali
  • Ponnekanti, Hari K.
  • Mathew, Rony David
  • Chenna, Varun Kumar
  • Kapadia, Somil

Abstract

A processing system having a substrate support assembly is described herein. The substrate support includes an electrostatic chuck, a cooling base coupled to the electrostatic chuck, a facility plate coupled to the substrate support assembly, and one or more electrical connectors positioned in the substrate support assembly in electrical communication with the electrostatic chuck. The electrostatic chuck further includes one or more cooling channels fluidly coupled to a magnetocaloric chiller utilizing magnetocaloric refrigeration.

IPC Classes  ?

  • F25B 21/00 - Machines, plants or systems, using electric or magnetic effects
  • B23Q 3/15 - Devices for holding work using magnetic or electric force acting directly on the work
  • H02N 13/00 - Clutches or holding devices using electrostatic attraction, e.g. using Johnson-Rahbek effect

14.

CHOKE PLATES FOR SEMICONDUCTOR MANUFACTURING PROCESSING CHAMBERS

      
Application Number 18422727
Status Pending
Filing Date 2024-01-25
First Publication Date 2025-07-31
Owner Applied Materials, Inc. (USA)
Inventor
  • Chang, Youngki
  • Kashyap, Dhritiman Subha
  • Ulavi, Tejas Umesh
  • Kurbet, Sanket S.
  • Moradian, Ala

Abstract

Choke plates and semiconductor manufacturing processing chamber incorporating the choke plates are described. The choke plates include an opening extending through the body with a plurality of angled apertures extending from a gas plenum within the body to the inner face of the opening. The plurality of angled apertures are angled from the gas plenum toward the top surface of the body.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01J 37/32 - Gas-filled discharge tubes

15.

ALLOY MICROSTRUCTURE FORMATION FOR CHAMBER COMPONENTS

      
Application Number US2025012465
Publication Number 2025/160091
Status In Force
Filing Date 2025-01-21
Publication Date 2025-07-31
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Liao, Chien-Min
  • Liu, Chao, C.
  • Cho, Tom
  • Kim, Hyeon, Geu
  • Ponnekanti, Hari
  • Merkel, Jay
  • Alger, Bruce
  • Janjam, Sathish, Babu
  • Chou, Cheng-Hsuan

Abstract

Described herein is a chamber component having a body comprising a plurality of aluminum alloy compositions. A first portion of the body includes a first aluminum alloy composition having a first grain size, and a second portion of the body includes a second aluminum alloy composition having a second grain size, wherein the first grain size of the first aluminum alloy composition is greater than the second grain size of the second aluminum alloy composition. A method for preparing the chamber component is also provided.

IPC Classes  ?

16.

METHOD OF DETERMINING A CHANGE OF A PRESENCE STATE OF A SUBSTRATE, AND PRESENCE SENSOR SYSTEM

      
Application Number EP2024051637
Publication Number 2025/157401
Status In Force
Filing Date 2024-01-24
Publication Date 2025-07-31
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Rathmann, Torben
  • Shi, Huiyuan
  • Ehmann, Christian Wolfgang

Abstract

A method of determining a change of a presence state of a substrate in a processing chamber is provided. The method comprises measuring a first signal of a first infrared sensor over time, a field of view of the first infrared sensor facing towards a substrate transport path in the processing chamber; and analyzing a temporal evolution of the first signal for determining if the presence state of the substrate has changed.

IPC Classes  ?

  • C23C 14/54 - Controlling or regulating the coating process
  • C23C 14/56 - Apparatus specially adapted for continuous coatingArrangements for maintaining the vacuum, e.g. vacuum locks
  • C23C 16/46 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for heating the substrate
  • C23C 16/52 - Controlling or regulating the coating process
  • C23C 16/54 - Apparatus specially adapted for continuous coating
  • G01J 5/00 - Radiation pyrometry, e.g. infrared or optical thermometry
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

17.

CONTROL OF SUBSTRATE DEFORMATION DURING MANUFACTURING PROCESSES

      
Application Number US2025013086
Publication Number 2025/160505
Status In Force
Filing Date 2025-01-25
Publication Date 2025-07-31
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Subrahmanyan, Pradeep Kumar
  • Lee, Wonjae

Abstract

Disclosed techniques include obtaining a wafer with a front side supporting deposited features and identifying first characteristics of one or more protective films and second characteristics of one or more stress-compensation layers (SCLs). The techniques further include forming the protective film(s) on the front side of the wafer and depositing the SCLs on the back side of the wafer. The techniques further include subjecting at least one SCL to a stress-modulation beam causing a saddle deformation of the wafer to be reduced and removing the protective film(s) from the one or more deposited features.

IPC Classes  ?

  • H01L 21/302 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
  • H01L 21/3105 - After-treatment

18.

MAGNETOCALORIC REFRIGERATION FOR SEMICONDUCTOR APPLICATIONS

      
Application Number US2025012805
Publication Number 2025/160303
Status In Force
Filing Date 2025-01-23
Publication Date 2025-07-31
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Arun, Kadali
  • Ponnekanti, Hari K.
  • Mathew, Rony David
  • Chenna, Varun Kumar
  • Kapadia, Somil

Abstract

A processing system having a substrate support assembly is described herein. The substrate support includes an electrostatic chuck, a cooling base coupled to the electrostatic chuck, a facility plate coupled to the substrate support assembly, and one or more electrical connectors positioned in the substrate support assembly in electrical communication with the electrostatic chuck. The electrostatic chuck further includes one or more cooling channels fluidly coupled to a magnetocaloric chiller utilizing magnetocaloric refrigeration.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • F25B 21/00 - Machines, plants or systems, using electric or magnetic effects
  • F25B 41/00 - Fluid-circulation arrangements

19.

SUSCEPTOR WITH A TEXTURED SURFACE

      
Application Number US2025010660
Publication Number 2025/159898
Status In Force
Filing Date 2025-01-08
Publication Date 2025-07-31
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Lei, Wei-Sheng
  • Gronet, Christian
  • Subramani, Anantha K.

Abstract

Disclosed herewith are a susceptor, a processing chamber having the susceptor, and a method for making the susceptor. The susceptor includes a body, an upper surface area supported by the body, and a lower surface area support by the body. The upper surface area and the lower surface area comprise an array of blind holes, the blind holes having a diameter of at least 5 um, a depth of at least 5 um, and an aspect ratio of at least 1:1. The method includes forming the array of the blind holes in the upper surface area and the lower surface area of the susceptor and forming surface textures on the surfaces of the susceptor.

IPC Classes  ?

  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

20.

PLASMA ENHANCED PROCESSING, AND RELATED PROCESSING CHAMBERS, METHODS, AND SYSTEMS FOR SEMICONDUCTOR MANUFACTURING

      
Application Number US2024058096
Publication Number 2025/159831
Status In Force
Filing Date 2024-12-02
Publication Date 2025-07-31
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Yang, Yi
  • Kang, Sean
  • Hayes, Alan
  • Kim, Hyojin
  • Watson, Jacob
  • Gau, Justin
  • Nemani, Srinivas D.
  • Kim, Jong Mun

Abstract

The present disclosure relates to plasma enhanced processing, and related processing chambers, methods, and systems for semiconductor manufacturing. In one or more embodiments, a method of substrate processing includes igniting a plasma, flowing a deposition precursor to interact with the plasma, and flowing the deposition precursor over a substrate positioned in a process volume to form a layer on the substrate. The method includes maintaining the process volume at a pressure less than 100 mTorr, and heating the substrate to a target temperature of 500 degrees Celsius or less.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • C30B 25/14 - Feed and outlet means for the gasesModifying the flow of the reactive gases
  • C30B 25/18 - Epitaxial-layer growth characterised by the substrate
  • C23C 16/02 - Pretreatment of the material to be coated
  • C23C 16/507 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using radio frequency discharges using external electrodes, e.g. in tunnel type reactors
  • C30B 25/10 - Heating of the reaction chamber or the substrate
  • C23C 16/48 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating by irradiation, e.g. photolysis, radiolysis, particle radiation

21.

WATER-BASED, HIGH-EFFICIENCY CHEMICAL REAGENT FOR SUBSTRATE SURFACE PARTICLE REMOVAL

      
Application Number US2024061723
Publication Number 2025/159877
Status In Force
Filing Date 2024-12-23
Publication Date 2025-07-31
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Yan, Hong
  • Hung, Raymond Hoiman
  • Wang, Ying
  • Dai, Xundong

Abstract

Embodiments of the disclosure provided herein include systems and methods for cleaning semiconductor substrates The method includes rotating a substrate disposed on a substrate support, spraying a front side of the substrate using a cleaning agent including one or more chelating agents through a front side nozzle assembly disposed above the substrate support, and spraying a back side of the substrate using the cleaning agent through a back side dispenser assembly disposed below the substrate support.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • C11D 3/00 - Other compounding ingredients of detergent compositions covered in group
  • C11D 3/30 - AminesSubstituted amines
  • C11D 3/43 - Solvents

22.

EVAPORATION SOURCE, METHOD OF COATING AT LEAST TWO LAYERS ON A SUBSTRATE AND OLED DEVICE

      
Application Number IB2024050584
Publication Number 2025/158169
Status In Force
Filing Date 2024-01-22
Publication Date 2025-07-31
Owner APPLIED MATERIALS, INC. (USA)
Inventor Lin, Yu-Hsin

Abstract

An evaporation source for depositing at least two layers on a substrate is described, including a first vapor distribution pipe with a row of first nozzles for depositing a first material onto the substrate, a second vapor distribution pipe with a row of second nozzles for depositing a second material onto the substrate, and a third vapor distribution pipe with a plurality of third nozzles for depositing a third material onto the substrate, wherein the row of first nozzles is configured to direct the first material onto a first region in the substrate plane, the row of second nozzles is configured to direct the second material onto a second region in the substrate plane not substantially overlapping with the first region, and the plurality of third nozzles is configured to direct the third material onto a third region in the substrate plane substantially covering both the first region and the second region.

IPC Classes  ?

  • H10K 71/16 - Deposition of organic active material using physical vapour deposition [PVD], e.g. vacuum deposition or sputtering
  • H10K 59/80 - Constructional details
  • H10K 50/13 - OLEDs or polymer light-emitting diodes [PLED] characterised by the electroluminescent [EL] layers specially adapted for multicolour light emission, e.g. for emitting white light comprising stacked EL layers within one EL unit
  • H10K 50/12 - OLEDs or polymer light-emitting diodes [PLED] characterised by the electroluminescent [EL] layers comprising dopants
  • H10K 85/60 - Organic compounds having low molecular weight
  • C23C 14/12 - Organic material
  • C23C 14/24 - Vacuum evaporation
  • C23C 14/22 - Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating

23.

METHOD FOR MAXIMIZING THIN-FILMS STRESS THROUGH SEASON IMPROVEMENT

      
Application Number 19039723
Status Pending
Filing Date 2025-01-28
First Publication Date 2025-07-31
Owner Applied Materials, Inc. (USA)
Inventor
  • Aydin, Aykut
  • Cheng, Rui
  • Han, Xinhai
  • Janakiraman, Karthik

Abstract

Embodiments of the disclosure provided herein include systems and methods for increasing tensile stress in tungsten layers in a semiconductor device manufacturing scheme. The system includes a processing chamber defining a processing volume, a gas delivery system fluidly coupled to the processing chamber, and a controller having instructions stored thereon for performing a method of processing a plurality of substrates when executed by one or more processors. The method includes cleaning the processing chamber, seasoning the processing chamber with a non-oxygen containing gas, receiving a substrate into the processing volume of the processing chamber fluidly coupled to the gas delivery system, performing a pre-treatment process on the substrate within the processing chamber, and depositing a tungsten-containing layer onto the substrate.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • B08B 7/00 - Cleaning by methods not provided for in a single other subclass or a single group in this subclass
  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layersAfter-treatment of these layers

24.

METHODS AND SYSTEMS FOR TEMPERATURE CONTROL FOR A SUBSTRATE

      
Application Number 19185087
Status Pending
Filing Date 2025-04-21
First Publication Date 2025-07-31
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Wirth, Paul Zachary
  • Shang, Kiyki-Shiy
  • Taraboukhine, Mikhail

Abstract

A first power is supplied to one or more heating elements embedded into a substrate support assembly of a processing chamber to control a temperature of a substrate placed on the substrate support assembly to a target substrate temperature during performance of a process according to a first process setting. A detection is made that a second process setting is to be applied in the processing chamber during the process. A temperature change of the substrate from the target substrate temperature upon application of the second process setting is determined. A second power to deliver to the heating element(s) to maintain the target substrate temperature is determined. The second power counteracts the temperature change of the substrate upon application of the second process setting. The second power is supplied to the heating element(s) to maintain the temperature of the substrate at the target substrate temperature.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

25.

SUBSTRATE HOLDER

      
Application Number 19032966
Status Pending
Filing Date 2025-01-21
First Publication Date 2025-07-31
Owner Applied Materials, Inc. (USA)
Inventor
  • Delmas, Jean
  • Stonas, Bernhard Wolfgang
  • Verhaverbeke, Steven
  • Leschkies, Kurtis Siegfried
  • Acharya, Sumedh
  • Patel, Dakshalkumar Kantilal

Abstract

A substrate holder includes a chuck base forming a chucking vacuum line and a particle vacuum line. The particle vacuum line is to extract particles produced from substrate processing. The substrate holder further includes one or more chuck posts extending from an upper surface of the chuck base. The chucking vacuum line is routed through the one or more chuck posts to chuck a substrate. The substrate holder further includes one or more die collect components disposed on the upper surface of the chuck base. A device is to be supported by at least one of the one or more die collect components responsive to being cut from the substrate.

IPC Classes  ?

  • B23K 26/382 - Removing material by boring or cutting by boring
  • B23K 26/142 - Working by laser beam, e.g. welding, cutting or boring using a fluid stream, e.g. a jet of gas, in conjunction with the laser beamNozzles therefor for the removal of by-products
  • B23K 37/04 - Auxiliary devices or processes, not specially adapted for a procedure covered by only one of the other main groups of this subclass for holding or positioning work

26.

ADHESION PROMOTION LAYER TO PREVENT OH ROOF/BODY DELAMINATION FROM ANODE SURFACE

      
Application Number 18959303
Status Pending
Filing Date 2024-11-25
First Publication Date 2025-07-31
Owner Applied Materials, Inc. (USA)
Inventor Lee, Jungmin

Abstract

Embodiments described herein generally relate to a display. More specifically, embodiments described herein relate to sub-pixel circuits and methods of forming sub-pixel circuits that may be utilized in a display such as an organic light-emitting diode (OLED) display. In an embodiment, a sub-pixel circuit is provided. The sub-pixel circuit includes a substrate, a plurality of sub-pixels, and a cathode ring disposed around a perimeter of the sub-pixel circuit. Each sub-pixel of the plurality of sub-pixels includes a plurality of overhang structures disposed over the substrate, the overhang structures including a first structure, a second structure and an extension disposed past a sidewall of the first structure, a metal structure disposed over the substrate, an adhesion layer disposed under first structure of the plurality of overhang structures, an overhang gap fill structure, an organic OLED material disposed over the metal structure, and a cathode disposed over the OLED material.

IPC Classes  ?

  • H10K 59/80 - Constructional details
  • H10K 59/12 - Active-matrix OLED [AMOLED] displays
  • H10K 71/60 - Forming conductive regions or layers, e.g. electrodes

27.

SUSCEPTOR WITH A TEXTURED SURFACE

      
Application Number 18424156
Status Pending
Filing Date 2024-01-26
First Publication Date 2025-07-31
Owner Applied Materials, Inc. (USA)
Inventor
  • Lei, Wei-Sheng
  • Gronet, Christian
  • Subramani, Anantha K.

Abstract

Disclosed herewith are a susceptor, a processing chamber having the susceptor, and a method for making the susceptor. The susceptor includes a body, an upper surface area supported by the body, and a lower surface area support by the body. The upper surface area and the lower surface area comprise an array of blind holes, the blind holes having a diameter of at least 5 um, a depth of at least 5 um, and an aspect ratio of at least 1:1. The method includes forming the array of the blind holes in the upper surface area and the lower surface area of the susceptor and forming surface textures on the surfaces of the susceptor.

IPC Classes  ?

  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • B23K 26/0622 - Shaping the laser beam, e.g. by masks or multi-focusing by direct control of the laser beam by shaping pulses
  • B23K 26/386 - Removing material by boring or cutting by boring of blind holes
  • B23K 26/402 - Removing material taking account of the properties of the material involved involving non-metallic material, e.g. isolators
  • C23C 16/46 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for heating the substrate
  • C30B 25/10 - Heating of the reaction chamber or the substrate
  • C30B 25/12 - Substrate holders or susceptors

28.

OLED COLOR PATTERNING BASED ON PHOTOLITHOGRAPHY AND CHEMICAL MECHANICAL POLISHING

      
Application Number 18805004
Status Pending
Filing Date 2024-08-14
First Publication Date 2025-07-31
Owner Applied Materials, Inc. (USA)
Inventor
  • Choung, Ji Young
  • Lin, Yu-Hsin
  • Chen, Chung-Chia
  • Park, Minhyung
  • Wang, Sheng-Wen
  • Kim, Si Kyoung
  • Lahiri, Indrajit

Abstract

In one or more embodiments, a sub-pixel includes adjacent overhang structures disposed over a substrate. Each overhang structure has an upper portion having a top surface and a bottom surface. The bottom surface wider than a top surface of a lower portion. Adjacent overhang structures define an opening of the sub-pixel. An anode is disposed over the substrate between the adjacent overhang structures. An organic light-emitting diode (OLED) material disposed over the anode. A cathode is disposed over the OLED material. An encapsulation layer is disposed over the cathode. The encapsulation layer extends under at least a portion of the overhang structures along a sidewall of the lower portion and contacts the bottom surface of the upper portion of the overhang structures.

IPC Classes  ?

29.

CRYOGENIC ETCHING OF SILICON-CONTAINING MATERIALS

      
Application Number 18671417
Status Pending
Filing Date 2024-05-22
First Publication Date 2025-07-31
Owner Applied Materials, Inc. (USA)
Inventor
  • Liao, Lei
  • Fu, Qian
  • Agarwal, Sumit
  • Kwak, Yeonju
  • Shimizu, Daisuke

Abstract

Exemplary semiconductor processing methods may include providing an etchant precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region. The substrate may include a layer of a silicon-containing material. The silicon-containing material may be a silicon-and-carbon-containing material, a silicon-carbon-and-nitrogen-containing material, a silicon-and-nitrogen-containing material, a silicon-and-oxygen-containing material, or silicon material. The methods may include forming plasma effluents of the etchant precursor. The methods may include contacting the substrate with the plasma effluents of the etchant precursor. The contacting may etch a portion of the layer of the silicon-containing material. The processing region may be maintained at a cryogenic temperature while contacting the substrate with the plasma effluents of the etchant precursor.

IPC Classes  ?

  • H01L 21/311 - Etching the insulating layers
  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer

30.

MULTI-ZONE LAMP HEATING AND TEMPERATURE MONITORING IN EPITAXY PROCESS CHAMBER

      
Application Number 19182498
Status Pending
Filing Date 2025-04-17
First Publication Date 2025-07-31
Owner Applied Materials, Inc. (USA)
Inventor
  • Ishikawa, Tetsuya
  • Srinivasan, Swaminathan T.
  • Bauer, Matthias
  • Moradian, Ala
  • Subbanna, Manjunath
  • Shah, Kartik Bhupendra
  • Achkasov, Kostiantyn
  • Sanchez, Errol Antonio C.
  • Rice, Michael R.
  • Shull, Marc
  • Hu, Ji-Dih

Abstract

The present disclosure generally relates to an epitaxial chamber for processing of semiconductor substrates. In one example, the epitaxial chamber has a chamber body assembly. The chamber body assembly includes a lower window and an upper window, wherein chamber body assembly, the lower window and the upper window enclose an internal volume. A susceptor assembly is disposed in the internal volume. The epitaxial chamber also has a plurality of temperature control elements. The plurality of temperature control elements include one or more of an upper lamp module, a lower lamp module, an upper heater, a lower heater, or a heated gas passage.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
  • H10D 48/044 - Conversion of the selenium or tellurium to the conductive state

31.

OUT-GASSING HOLE INSIDE ACTIVE AREA TO IMPROVE AP RELIABILITY

      
Application Number 18887704
Status Pending
Filing Date 2024-09-17
First Publication Date 2025-07-31
Owner Applied Materials, Inc. (USA)
Inventor Chen, Chung-Chia

Abstract

The present disclosure provides devices, sub-pixels, and methods thereof. The sub-pixel includes a plurality of pixel structures separating a plurality of anodes. The plurality of pixel structures are disposed over a substrate. Each pixel structure of the plurality of pixel structures includes an outgassing hole. A plurality of overhang structures are disposed over the plurality of pixel structures. Each overhang structure of the plurality of overhang structures includes an upper portion disposed over a lower potion. A bottom surface of the upper portion extends laterally past an upper surface of the lower portion. The lower portion fills the outgassing hole. An organic light emitting diode (OLED) material is disposed over an upper surface of the plurality of anodes and an upper surface of the plurality of pixel structures. A cathode is disposed over the OLED material and the upper surface of the plurality of pixel structures.

IPC Classes  ?

  • H10K 59/122 - Pixel-defining structures or layers, e.g. banks
  • H10K 59/12 - Active-matrix OLED [AMOLED] displays
  • H10K 59/35 - Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels

32.

FLUORINE RESISTANT COMPOSITIONS

      
Application Number 18670144
Status Pending
Filing Date 2024-05-21
First Publication Date 2025-07-31
Owner Applied Materials, Inc. (USA)
Inventor
  • Woo, Katherine
  • Sun, Jennifer Y.

Abstract

The present disclosure generally provides a fluorine resistant ceramic composition. The fluorine resistant ceramic composition includes about 80 mol % to about 99.9 mol % of a first metal composition including an aluminum based composition selected from the group consisting of a nitride, oxynitride, oxide, and oxy-fluoride. The fluorine resistant ceramic composition includes about 0.1 mol % to about 20 mol % of a second metal composition including an alkaline-earth metal based composition selected from the group consisting of a nitride, oxynitride, oxide, oxy-fluoride, and fluoride.

IPC Classes  ?

  • C04B 35/10 - Shaped ceramic products characterised by their compositionCeramic compositionsProcessing powders of inorganic compounds preparatory to the manufacturing of ceramic products based on oxides based on aluminium oxide

33.

PHOTONIC INTEGRATED CIRCUITS TO GLASS SUBSTRATE BONDING

      
Application Number 18732211
Status Pending
Filing Date 2024-06-03
First Publication Date 2025-07-31
Owner Applied Materials, Inc. (USA)
Inventor
  • Yang, Zijiao
  • Fu, Jinxin
  • Schmidtke, Hans-Juergen
  • Blum, Robert

Abstract

Embodiments described herein also relate to co-packaged optical and electrical device. The co-packaged optical and electrical device include a package substrate, an electrical or opto-electrical chip disposed on the package substrate, a photonic integrated interconnect unit disposed on the package substrate, a plurality of interconnects, and a plurality of optical structures. The photonic integrated interconnect unit includes a photonic integrated circuit (PIC) including a PIC waveguide. The plurality of interconnects connect the electrical or opto-electrical chip to the photonic integrated interconnect unit. The interconnects are formed on or in the package substrate. The plurality of optical structures are configured to connect the photonic integrated interconnect unit to a fiber optic cable. The plurality of optical structures include a substrate waveguide formed on or in the package substrate. The substrate waveguide is coupled to the PIC waveguide via evanescent coupling.

IPC Classes  ?

  • G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind

34.

GROWTH OF THIN OXIDE LAYER IN VERTICAL CHANNEL STRUCTURE

      
Application Number 18982464
Status Pending
Filing Date 2024-12-16
First Publication Date 2025-07-31
Owner Applied Materials, Inc. (USA)
Inventor
  • Chen, Zhijun
  • Chung, Hoi-Sung
  • Fishburn, Fredrick
  • Makala, Raghuveer Satya
  • Pranatharthiharan, Balasubramanian

Abstract

A method for forming an oxide layer in a vertical channel structure includes performing a pre-clean process to remove contaminants on exposed surfaces of channel pillars extending in a first direction, performing a silicon layer formation process to form a silicon layer on the exposed surfaces of the channel pillars, and performing a thermal oxidation process to convert the silicon layer to an oxide layer.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H10D 62/00 - Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D 62/17 - Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions

35.

LOW TEMPERATURE CHEMICAL VAPOR DEPOSITION OF NANOCRYSTALLINE DIAMOND FILM

      
Application Number 18423129
Status Pending
Filing Date 2024-01-25
First Publication Date 2025-07-31
Owner Applied Materials, Inc. (USA)
Inventor
  • Tan, Sze Chieh Yvonne
  • Sahmuganathan, Vicknesh
  • Sudijono, John
  • Chua, Thai Cheng

Abstract

Embodiments include a modular high-frequency emission source for growth of a low roughness nanocrystalline diamond film. In an embodiment, a method of fabricating a nanocrystalline diamond (NCD) film includes loading a substrate such as nanodiamond-seeded silicon wafer or a bare silicon wafer that has been surface-treated and incubated into a microwave plasma-enhanced chemical vapor deposition (MWPECVD) chamber, and processing the nanodiamond-seeded silicon wafer or the bare silicon wafer that has been surface-treated and incubated with a plasma of CxHy (y≥x), CO2 and H2, at a temperature less than 300 degrees Celsius, to form a layer of nanocrystalline diamond thereon.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • C23C 16/27 - Diamond only
  • C23C 16/511 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using microwave discharges
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

36.

SEMICONDUCTOR SUBSTRATE CHUCKING SENSOR

      
Application Number 18429103
Status Pending
Filing Date 2024-01-31
First Publication Date 2025-07-31
Owner Applied Materials, Inc. (USA)
Inventor
  • Hammond, Edward P.
  • Tanaka, Tsutomu
  • Garachtchenko, Alexander V.
  • Dzilno, Dmitry A.

Abstract

A pedestal may be configured to support a substrate during a semiconductor process. An electrostatic chuck (ESC) may include electrodes embedded in the pedestal that are configured to deliver a chucking volage to the pedestal during the semiconductor process. A power source coupled to an electrode may be configured to provide a signal having a frequency range to the electrode during the semiconductor process. A controller may be configured to receive a measurement of an impedance when the frequency range is applied to the electrode. The impedance measurements my then be used to determine a chucking state of the substrate, such as whether an airgap is present between the substrate and the pedestal during the semiconductor process.

IPC Classes  ?

  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

37.

AUTOMATIC ROBOT CALIBRATION FOR MULTI-JOINT ROBOTS

      
Application Number US2025012610
Publication Number 2025/160188
Status In Force
Filing Date 2025-01-22
Publication Date 2025-07-31
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Yu, Ho
  • Wirth, Paul Z.
  • Cox, Damon K.
  • Waqar, Mohsin
  • Hudgens, Jeffrey C.

Abstract

A system includes a chamber, a robot within the chamber, the robot including a plurality of links. The system further includes a vertically oriented sensor within the chamber, the vertically oriented sensor to detect a presence of one or more of the plurality of links. The system further includes a controller, to perform for each link to cause the robot to move the link through a field of view of the vertically oriented sensor. The controller further determines a zero horizontal position for the link based on the position of the link at which the link was detected by the vertically oriented sensor. The controller further automatically calibrates the robot within the chamber based on the zero horizontal position determined for each of the plurality of links.

IPC Classes  ?

  • H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
  • H01L 21/68 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for positioning, orientation or alignment
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • B25J 9/04 - Programme-controlled manipulators characterised by movement of the arms, e.g. cartesian co-ordinate type by rotating at least one arm, excluding the head movement itself, e.g. cylindrical co-ordinate type or polar co-ordinate type
  • B25J 9/16 - Programme controls
  • B25J 13/08 - Controls for manipulators by means of sensing devices, e.g. viewing or touching devices
  • B25J 19/02 - Sensing devices

38.

PROCESS STAGE TRANSITION DETECTION FOR PLASMA SYSTEMS

      
Application Number US2025011660
Publication Number 2025/159952
Status In Force
Filing Date 2025-01-15
Publication Date 2025-07-31
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Neelamraju, Bharati
  • Kulshreshtha, Prashant Kumar
  • Kageyama, Yuta
  • Kitagaki, Takashi

Abstract

A goal of a gapfill deposition process may be to form a relatively flat overgrowth layer of gapfill material above a top of the pillars. The relatively flat overgrowth layer can be formed by automatically stopping the gapfill deposition process after detecting an end of a stage (e.g., a sidewall growth stage) of the gapfill process. A characteristic of the plasma, such as an impedance of the plasma may be monitored during the plasma process. Changes in the characteristic may be correlated with different stages in the process, such as different stages in the gapfill process. When the characteristic indicates, a stage in the gapfill process may be identified, and an action may be taken, such as stopping the gapfill process. This provides live monitoring of the gapfill based on plasma characteristics rather than on measurements taken after the gap fill process is complete.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

39.

SILICON CARBIDE AND QUARTZ COMPOSITIONS FOR PROCESSING CHAMBERS, AND RELATED COMPONENTS AND METHODS

      
Application Number US2024061015
Publication Number 2025/159866
Status In Force
Filing Date 2024-12-19
Publication Date 2025-07-31
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Vellore, Kim Ramkumar
  • Cong, Zhepeng

Abstract

Embodiments of the present disclosure generally relate to compositions for use in a substrate processing chamber, and related methods. In one or more embodiments, a component includes a body having a composition. The composition comprising a mixture of silicon carbide (SiC) particles suspended in quartz.

IPC Classes  ?

  • C30B 25/08 - Reaction chambersSelection of materials therefor
  • C30B 25/12 - Substrate holders or susceptors

40.

MAGNETIC LEVITATION SYSTEM FOR SUBSTRATE SUPPORT DEVICE

      
Application Number US2025012794
Publication Number 2025/160296
Status In Force
Filing Date 2025-01-23
Publication Date 2025-07-31
Owner APPLIED MATERIALS, INC. (USA)
Inventor Aust, Henning

Abstract

A substrate support device is provided. The substrate support device includes a base secured to a processing chamber. The base includes a stator configured to generate a first magnetic field, a second magnetic field, and a third magnetic field. The substrate support device further includes a substrate support above the base for supporting a substrate. The substrate support includes a rotor with a first reactive region that interacts with the first magnetic field to control a vertical position of the substrate support, and interacts with the second magnetic field to center the substrate support to the base. The substrate support includes a second reactive region that interacts with the third magnetic field to rotate the substrate support. The first magnetic field and the first reactive region selectively levitate the substrate support to any distance within a range from 0 mm to 6 mm above a resting position.

IPC Classes  ?

  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

41.

LOW TEMPERATURE CHEMICAL VAPOR DEPOSITION OF NANOCRYSTALLINE DIAMOND FILM

      
Application Number US2025010972
Publication Number 2025/159912
Status In Force
Filing Date 2025-01-09
Publication Date 2025-07-31
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Tan, Sze Chieh Yvonne
  • Sahmuganathan, Vicknesh
  • Sudijono, John
  • Chua, Thai Cheng

Abstract

xy222, at a temperature less than 300 degrees Celsius, to form a layer of nanocrystalline diamond thereon.

IPC Classes  ?

  • C23C 14/06 - Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
  • C23C 14/35 - Sputtering by application of a magnetic field, e.g. magnetron sputtering
  • C23C 14/54 - Controlling or regulating the coating process

42.

FLUORINE RESISTANT COMPOSITIONS

      
Application Number US2025011880
Publication Number 2025/159969
Status In Force
Filing Date 2025-01-16
Publication Date 2025-07-31
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Woo, Katherine
  • Sun, Jennifer Y.

Abstract

The present disclosure generally provides a fluorine resistant ceramic composition. The fluorine resistant ceramic composition includes about 80 mol% to about 99.9 mol% of a first metal composition including an aluminum based composition selected from the group consisting of a nitride, oxynitride, oxide, and oxy-fluoride. The fluorine resistant ceramic composition includes about 0.1 mol% to about 20 mol% of a second metal composition including an alkaline-earth metal based composition selected from the group consisting of a nitride, oxynitride, oxide, oxy-fluoride, and fluoride.

IPC Classes  ?

  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • C04B 35/10 - Shaped ceramic products characterised by their compositionCeramic compositionsProcessing powders of inorganic compounds preparatory to the manufacturing of ceramic products based on oxides based on aluminium oxide
  • C04B 35/03 - Shaped ceramic products characterised by their compositionCeramic compositionsProcessing powders of inorganic compounds preparatory to the manufacturing of ceramic products based on oxides based on magnesium oxide, calcium oxide or oxide mixtures derived from dolomite
  • C04B 35/50 - Shaped ceramic products characterised by their compositionCeramic compositionsProcessing powders of inorganic compounds preparatory to the manufacturing of ceramic products based on rare earth compounds
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01J 37/32 - Gas-filled discharge tubes

43.

XTERA

      
Application Number 1865633
Status Registered
Filing Date 2025-06-13
Registration Date 2025-06-13
Owner Applied Materials, Inc. (USA)
NICE Classes  ? 07 - Machines and machine tools

Goods & Services

Semiconductor manufacturing equipment used to densify materials on wafers.

44.

HELION

      
Application Number 1865666
Status Registered
Filing Date 2025-06-13
Registration Date 2025-06-13
Owner Applied Materials, Inc. (USA)
NICE Classes  ? 07 - Machines and machine tools

Goods & Services

Semiconductor wafer processing equipment used for implanting different materials into wafers.

45.

FULLSCAN

      
Application Number 1865758
Status Registered
Filing Date 2025-06-13
Registration Date 2025-06-13
Owner Applied Materials, Inc. (USA)
NICE Classes  ? 07 - Machines and machine tools

Goods & Services

Semiconductor wafer processing equipment and components, namely, chemical mechanical polishers and monitoring equipment, all for the processing and production of semiconductor substrates, thin films, silicon discs and wafers and metrology-related goods.

46.

POLISHING HEAD WITH RETAINING RING WEAR SENSING

      
Application Number 18417124
Status Pending
Filing Date 2024-01-19
First Publication Date 2025-07-24
Owner Applied Materials, Inc. (USA)
Inventor
  • Oh, Jeonghoon
  • Nagengast, Andrew J.
  • Fujikawa, Takashi
  • Chen, Kuen-Hsiang
  • Zuniga, Steven M.

Abstract

A carrier head for chemical mechanical polishing includes a housing for attachment to a drive shaft. The housing includes an upper carrier body to be attached to a vertically stationary drive shaft and a lower carrier body that is vertically movable relative to the upper carrier body is configured to be secured to and suspend a retaining ring. A first flexible seal forms a loading chamber between the upper carrier body and the lower carrier body. A membrane assembly is arranged beneath the lower carrier body and includes a membrane support and a flexible membrane secured to the membrane support to form one or more lower pressurizable chambers. A second flexible seal forms an upper pressurizable chamber between the lower carrier body and the membrane support, and a sensor is secured to the housing and configured to measure a distance between the upper carrier body and the lower carrier body.

IPC Classes  ?

  • B24B 37/005 - Control means for lapping machines or devices
  • B24B 37/32 - Retaining rings
  • B24B 49/10 - Measuring or gauging equipment for controlling the feed movement of the grinding tool or workArrangements of indicating or measuring equipment, e.g. for indicating the start of the grinding operation involving electrical means
  • B24B 49/12 - Measuring or gauging equipment for controlling the feed movement of the grinding tool or workArrangements of indicating or measuring equipment, e.g. for indicating the start of the grinding operation involving optical means

47.

CHOKE FILMS FOR OLED STRUCTURES

      
Application Number 18830714
Status Pending
Filing Date 2024-09-11
First Publication Date 2025-07-24
Owner Applied Materials, Inc. (USA)
Inventor Lee, Jungmin

Abstract

Embodiments described herein generally relate to a display. More specifically, embodiments described herein relate to sub-pixel circuits and methods of forming sub-pixel circuits that may be utilized in a display such as an organic light-emitting diode (OLED) display. In one or more embodiments, a sub-pixel includes adjacent overhang structures disposed over a substrate. Each overhang structure has an overhang extension extending laterally past a sidewall of each overhang structure. The sub-pixel further includes a pixel isolation structure (PIS) disposed over the substrate between the adjacent overhang structures. The PIS includes an upper surface and at least two sidewalls opposing each other. An anode is disposed on the PIS. An OLED material is disposed over the anode and extends over the upper surface and the sidewalls of the PIS. The OLED material further extends under the overhang extension. A cathode is disposed over the OLED material.

IPC Classes  ?

48.

DIRECT NITRATION FOR BACKSIDE POWER DELIVER NETWORK ISOLATION MODULE

      
Application Number 18947267
Status Pending
Filing Date 2024-11-14
First Publication Date 2025-07-24
Owner Applied Materials, Inc. (USA)
Inventor
  • Bhosale, Prasad
  • Basker, Veeraraghavan S.
  • Colombeau, Benjamin
  • Swenberg, Johanes F.
  • Guarini, Theresa Kramer

Abstract

A method of backside processing of a transistor structure includes performing a substrate trench etch process to form a trench within a substrate and leave a portion of the substrate below a bottom of the trench un-etched, wherein the trench is aligned with a gate of the transistor structure, performing a nitridation process to nitride an inner surface of the trench to form a nitride layer at the inner surface, and after forming the nitride layer, performing a dielectric fill process to form a dielectric layer within the trench.

IPC Classes  ?

  • H01L 21/283 - Deposition of conductive or insulating materials for electrodes
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/3065 - Plasma etchingReactive-ion etching
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
  • H01L 29/24 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only inorganic semiconductor materials not provided for in groups , ,  or
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
  • H01L 29/786 - Thin-film transistors

49.

SELECTIVE SILICON NITRIDE WITH TREATMENT FOR BACKSIDE POWER DELIVERY NETWORK

      
Application Number 18978098
Status Pending
Filing Date 2024-12-12
First Publication Date 2025-07-24
Owner Applied Materials, Inc. (USA)
Inventor
  • Kim, Kyoung Ha
  • Lee, Byeong Chan
  • Basker, Veeraraghavan S.
  • Yoshida, Naomi

Abstract

Methods of manufacturing logic or memory devices are provided. The method includes selectively depositing a silicon-containing dielectric layer in a source/drain recess on a substrate and through an opening in an oxide liner within the source drain recess. The silicon-containing dielectric layer is then densified.

IPC Classes  ?

50.

DEFORMATION CONTROL FOR DIE-TO-WAFER AND DIE-TO-DIE BONDING IN DEVICE MANUFACTURING

      
Application Number 19019449
Status Pending
Filing Date 2025-01-13
First Publication Date 2025-07-24
Owner Applied Materials, Inc. (USA)
Inventor
  • Lin, San-Kuei
  • Lee, Wonjae
  • Subrahmanyan, Pradeep Kumar

Abstract

Disclosed systems and techniques are directed to optimization of semiconductor manufacturing by forming features on a front side of a first substrate and covering the plurality of first features with a stress-compensation layer (SCL). The techniques further include causing the first substrate to adhere to a second substrate and removing a back side portion of the first substrate to expose at least a subplurality of the features and forming a plurality of devices, each device including a portion of the features, a portion of the first substrate, and a portion of the second substrate. The SCL is configured to reduce deformation of the plurality of devices.

IPC Classes  ?

  • H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
  • H01L 21/66 - Testing or measuring during manufacture or treatment

51.

METHOD AND APPARATUS FOR SELECTIVE DEPOSITION OF DIELECTRIC FILMS

      
Application Number 19176611
Status Pending
Filing Date 2025-04-11
First Publication Date 2025-07-24
Owner Applied Materials, Inc. (USA)
Inventor
  • Li, Ning
  • Balseanu, Mihaela A.
  • Xia, Li-Qun
  • Yang, Dongqing
  • Zhu, Lala
  • Bevan, Malcolm J.
  • Guarini, Theresa Kramer
  • Yan, Wenbo

Abstract

Processing platforms having a central transfer station with a robot and an environment having greater than or equal to about 0.1% by weight water vapor, a pre-clean chamber connected to a side of the transfer station and a batch processing chamber connected to a side of the transfer station. The processing platform configured to pre-clean a substrate to remove native oxides from a first surface, form a blocking layer using a alkylsilane and selectively deposit a film. Methods of using the processing platforms and processing a plurality of wafers are also described.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • C23C 16/02 - Pretreatment of the material to be coated
  • C23C 16/04 - Coating on selected surface areas, e.g. using masks
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C23C 16/56 - After-treatment
  • H01L 21/3105 - After-treatment
  • H01L 21/32 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to form insulating layers thereon, e.g. for masking or by using photolithographic techniquesAfter-treatment of these layersSelection of materials for these layers using masks
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

52.

BITLINE SURFACE TREATMENT AND ENCAPSULATION IN DYNAMIC RANDOM-ACCESS MEMORY (DRAM) DEVICES

      
Application Number US2024060520
Publication Number 2025/155403
Status In Force
Filing Date 2024-12-17
Publication Date 2025-07-24
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Seo, Jongbeom
  • Chen, Zhijun
  • Fishburn, Fredrick
  • Makala, Raghuveer Satya

Abstract

A memory cell array includes a bitline encapsulated in a blocking layer within a spacer layer, the bitline extending in a first direction, and a plurality of memory cells aligned in the first direction, each of the plurality of memory cells including a cell transistor having a source electrically connected to the bitline, a drain, a word line, and a channel electrically connected to the source and the drain, and a cell capacitor having a top electrode that is electrically connected to the drain.

IPC Classes  ?

  • H10B 12/00 - Dynamic random access memory [DRAM] devices
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

53.

CHOKE FILMS FOR OLED STRUCTURES

      
Application Number US2024060529
Publication Number 2025/155404
Status In Force
Filing Date 2024-12-17
Publication Date 2025-07-24
Owner APPLIED MATERIALS, INC. (USA)
Inventor Lee, Jungmin

Abstract

Embodiments described herein generally relate to a display. More specifically, embodiments described herein relate to sub-pixel circuits and methods of forming sub-pixel circuits that may be utilized in a display such as an organic light-emitting diode (OLED) display. In one or more embodiments, a sub-pixel includes adjacent overhang structures disposed over a substrate. Each overhang structure has an overhang extension extending laterally past a sidewall of each overhang structure. The sub-pixel further includes a pixel isolation structure (PIS) disposed over the substrate between the adjacent overhang structures. The PIS includes an upper surface and at least two sidewalls opposing each other. An anode is disposed on the PIS. An OLED material is disposed over the anode and extends over the upper surface and the sidewalls of the PIS. The OLED material further extends under the overhang extension. A cathode is disposed over the OLED material.

IPC Classes  ?

  • H10K 59/122 - Pixel-defining structures or layers, e.g. banks
  • H10K 50/17 - Carrier injection layers
  • H10K 50/15 - Hole transporting layers
  • H10K 50/11 - OLEDs or polymer light-emitting diodes [PLED] characterised by the electroluminescent [EL] layers
  • H10K 50/19 - Tandem OLEDs
  • H10K 59/80 - Constructional details

54.

ION EXTRACTION OPTICS FOR ION PROCESSING SYSTEM

      
Application Number US2024061647
Publication Number 2025/155421
Status In Force
Filing Date 2024-12-23
Publication Date 2025-07-24
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Biloiu, Costel
  • Morrell, David
  • Daniels, Kevin M.
  • Campbell, Christopher

Abstract

An ion extraction optics including an extraction plate defining first, second, and third extraction apertures, the second extraction aperture being located between the first and third extraction apertures, first, second, and third beam blockers located adjacent the first, second, and third extraction apertures, respectively, wherein the first beam blocker and the first extraction aperture define first and second extraction slits, the second beam blocker and the second extraction aperture define third and fourth extraction slits, and the third beam blocker and the third extraction aperture define fifth and sixth extraction slits, wherein a height of the first extraction slit is greater than a height of at least one of the third extraction slit and the fourth extraction slit, and wherein a height of the sixth extraction slit is greater than the height of at least one of the third extraction slit and the fourth extraction slit.

IPC Classes  ?

  • H01J 27/02 - Ion sourcesIon guns
  • H01J 37/08 - Ion sourcesIon guns
  • H01J 37/317 - Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. ion implantation

55.

SWITCHING CIRCUIT FOR MULTILEVEL PLASMA IMPEDANCE MATCHING

      
Application Number US2024061677
Publication Number 2025/155424
Status In Force
Filing Date 2024-12-23
Publication Date 2025-07-24
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Azad, Anm Wasekul
  • Guo, Yue
  • Yang, Yang
  • Ramaswamy, Kartik
  • Bright, Nicolas J.

Abstract

Embodiments provided herein generally include apparatus, plasma processing systems and methods for tuning in a radio frequency (RF) plasma processing system for improving substrate processing metrics. Some embodiments are directed to an apparatus for processing a substrate in a plasma processing system. The apparatus generally includes: an impedance for a match circuit configured to perform impedance matching for a plasma load; a diode-based switch coupled to the impedance for the match circuit; at least one signal generator coupled to the diode-based switch and configured to bias the diode-based switch to a first position based on a first impedance generated in the plasma load; and a second position based on a second impedance generated in the plasma load and an RF signal generator configured to provide an RF signal to the plasma load.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • H03K 17/74 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of diodes

56.

SHIELD FOR AN ION IMPLANTER

      
Application Number US2025010447
Publication Number 2025/155447
Status In Force
Filing Date 2025-01-06
Publication Date 2025-07-24
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Hsieh, Tseh-Jen
  • Stratoti, Gregory Edward
  • Dhulapati, Santosh
  • Koo, Bon-Woong

Abstract

A shield for use with a rotatable platen is disclosed. The shield includes an exposed portion and a frame to attach the shield to the platen. The exposed portion of the shield has an arc shaped back surface that faces the platen and an opposite exposed surface that faces toward the ion beam. The exposed surface is designed such that the ion beam strikes the exposed surface at angles that are roughly 90°, as sputtering may be reduced at these angles. The exposed surface may have various shapes, including flat, rounded or sloped. Additionally, the exposed surface may include a plurality of exposed segments, separated by connecting segments that are not exposed to the ion beam. The shield may be graphite, silicon or silicon carbide.

IPC Classes  ?

  • H01J 37/09 - DiaphragmsShields associated with electron- or ion-optical arrangementsCompensation of disturbing fields
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • H01J 37/317 - Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. ion implantation

57.

SELECTIVE SILICON NITRIDE WITH TREATMENT FOR BACKSIDE POWER DELIVERY NETWORK

      
Application Number US2025011495
Publication Number 2025/155517
Status In Force
Filing Date 2025-01-14
Publication Date 2025-07-24
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Kim, Kyoung Ha
  • Lee, Byeong Chan
  • Basker, Veeraraghavan S.
  • Yoshida, Naomi

Abstract

Methods of manufacturing logic or memory devices are provided. The method includes selectively depositing a silicon-containing dielectric layer in a source/drain recess on a substrate and through an opening in an oxide liner within the source drain recess. The silicon-containing dielectric layer is then densified.

IPC Classes  ?

  • H10D 62/00 - Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D 62/13 - Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
  • H10D 84/85 - Complementary IGFETs, e.g. CMOS
  • H10D 30/67 - Thin-film transistors [TFT]

58.

HEAD LOAD/UNLOAD STATION WITH CHARGE DISCHARGE PATH

      
Application Number US2025011661
Publication Number 2025/155595
Status In Force
Filing Date 2025-01-15
Publication Date 2025-07-24
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Wong, Justin H.
  • Chang, Shou-Sung
  • Wu, Haosheng
  • Pollard, Chad
  • Tang, Jianshe
  • Deshpande, Sameer A.
  • Zhong, Elton
  • Drauss, Emily
  • Oh, Jeonghoon

Abstract

Embodiments herein generally relate to chemical mechanical polishing (CMP) systems, and in particular, to head clean load/unload (HCLLI) stations used with CMP systems and methods related thereto. The apparatus includes a substrate loading station that includes a cup assembly, and a support assembly concentrically disposed within the cup assembly, including a substrate support including an annular lip configured to engage with a surface of a substrate, at least one contact sensor disposed on the annular lip, the at least one contact sensor configured to contact a substrate, and a grounded resistive path coupled to the at least one contact sensor. In another embodiment, the cup assembly includes a load cup, at least one contact probe disposed on the load cup configured to contact a substrate, and a grounded resistive path coupled to the at least one contact probe.

IPC Classes  ?

  • B24B 37/30 - Work carriers for single side lapping of plane surfaces
  • B24B 37/005 - Control means for lapping machines or devices
  • B24B 49/10 - Measuring or gauging equipment for controlling the feed movement of the grinding tool or workArrangements of indicating or measuring equipment, e.g. for indicating the start of the grinding operation involving electrical means

59.

NF3 ULTRA LOW FLOW

      
Application Number US2025011992
Publication Number 2025/155797
Status In Force
Filing Date 2025-01-17
Publication Date 2025-07-24
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Ingle, Nitin K.
  • Pakulski, Ryan

Abstract

A system of semiconductor manufacturing may include a gas canister may including a gas mix with NF3 in a range of about.5% to about 5%, inclusive. The system may include a semiconductor processing chamber. The system may include a mass flow controller, configured to provide the gas mix to the semiconductor processing chamber. The system may include a substrate support disposed within the semiconductor processing chamber.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/3065 - Plasma etchingReactive-ion etching
  • H01J 37/32 - Gas-filled discharge tubes

60.

MULTI-MATERIAL GRATINGS WITH INCREASED TRANSMISSION AND REDUCED REFLECTION

      
Application Number US2025012157
Publication Number 2025/155893
Status In Force
Filing Date 2025-01-17
Publication Date 2025-07-24
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Wang, Evan
  • Bhargava, Samarth
  • Lorenzo, Simon
  • Messer, Kevin
  • Sell, David Alexander

Abstract

Embodiments of the disclosure provided herein generally relate to augmented reality displays. More specifically, the disclosure relates to gratings of waveguide combiners for augmented reality displays. The waveguide combiner includes a substrate having a substrate refractive index, and a grating having a plurality of grating structures. Each grating structure of the plurality of grating structures includes a multi-material layer stack. The multi-material layer stack has a first layer disposed over a surface of the substrate, where the first layer has a first refractive index. A second layer is disposed on the first layer having a second refractive index less than the first refractive index. A third layer is disposed on the second layer having a third refractive index less than the second refractive index.

IPC Classes  ?

  • G02B 6/00 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings
  • G02B 5/18 - Diffracting gratings
  • G02B 27/01 - Head-up displays

61.

SILICON CARBIDE AND QUARTZ COMPOSITIONS FOR PROCESSING CHAMBERS, AND RELATED COMPONENTS AND METHODS

      
Application Number 18581127
Status Pending
Filing Date 2024-02-19
First Publication Date 2025-07-24
Owner Applied Materials, Inc. (USA)
Inventor
  • Vellore, Kim Ramkumar
  • Cong, Zhepeng

Abstract

Embodiments of the present disclosure generally relate to compositions for use in a substrate processing chamber, and related methods. In one or more embodiments, a component includes a body having a composition. The composition comprising a mixture of silicon carbide (SiC) particles suspended in quartz.

IPC Classes  ?

  • C30B 25/10 - Heating of the reaction chamber or the substrate
  • C03C 14/00 - Glass compositions containing a non-glass component, e.g. compositions containing fibres, filaments, whiskers, platelets, or the like, dispersed in a glass matrix
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C23C 16/46 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for heating the substrate
  • C30B 25/12 - Substrate holders or susceptors

62.

IMPEDANCE TUNING UTILITY OF VECTOR SPACE DEFINED BY TRANSMISSION LINE QUANTITIES

      
Application Number 19173702
Status Pending
Filing Date 2025-04-08
First Publication Date 2025-07-24
Owner Applied Materials, Inc. (USA)
Inventor
  • Coumou, David
  • Peterson, David

Abstract

Embodiments disclosed herein include a method of impedance tuning in a semiconductor processing tool. In an embodiment, the method comprises measuring a voltage and a current of a transmission line, converting an analog voltage signal and an analog current signal into a digital voltage signal and a digital current signal, calculating a u-vector from the digital voltage signal and the digital current signal, calculating a C1 position of a first capacitor with real components of the u-vector, and calculating a C2 position of a second capacitor with imaginary components of the u-vector.

IPC Classes  ?

  • H03H 7/40 - Automatic matching of load impedance to source impedance
  • H03F 1/56 - Modifications of input or output impedances, not otherwise provided for

63.

METHODS OF OPERATING A SPATIAL DEPOSITION TOOL

      
Application Number 19175364
Status Pending
Filing Date 2025-04-10
First Publication Date 2025-07-24
Owner Applied Materials, Inc. (USA)
Inventor
  • Aubuchon, Joseph
  • Baluja, Sanjeev
  • Rice, Michael
  • Dan, Arkaprava
  • Chen, Hanhong

Abstract

Apparatus and methods to process one or more wafers are described. A spatial deposition tool comprises a plurality of substrate support surfaces on a substrate support assembly and a plurality of spatially separated and isolated processing stations. The spatially separated isolated processing stations have independently controlled temperature, processing gas types, and gas flows. In some embodiments, the processing gases on one or multiple processing stations are activated using plasma sources. The operation of the spatial tool comprises rotating the substrate assembly in a first direction, and rotating the substrate assembly in a second direction, and repeating the rotations in the first direction and the second direction until a predetermined thickness is deposited on the substrate surface(s).

IPC Classes  ?

  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation

64.

Dielectric Deposition Ring with Fins for Physical Vapor Deposition

      
Application Number 18417160
Status Pending
Filing Date 2024-01-19
First Publication Date 2025-07-24
Owner Applied Materials, Inc. (USA)
Inventor
  • Li, Ming-Jui
  • Xiao, Wen
  • Penmethsa, Harish Varma
  • Raju, Brijesh
  • Palanisamy, Puviyarasu
  • Chintala, Vasu Reddy
  • Lizarraga Maldonado, Alejandro
  • Tjakradinata, Michelle
  • Yedla, Srinivasa Rao

Abstract

Methods and apparatus for processing a substrate are provided herein. In some embodiments, a process kit for a substrate support includes: a dielectric plate having a lower surface configured to cover a support surface of the substrate support and an upper surface configured to support a substrate; and a dielectric deposition ring surrounding the dielectric plate and configured to cover a portion of the substrate support disposed radially outward of the support surface.

IPC Classes  ?

65.

SUBSTRATE CARRIER

      
Application Number 18417510
Status Pending
Filing Date 2024-01-19
First Publication Date 2025-07-24
Owner Applied Materials, Inc. (USA)
Inventor
  • Prasad, Bhaskar
  • Brezoczky, Thomas
  • Savandaiah, Kirankumar Neelasandra
  • Kumar, Aditya
  • Patil, Vijet

Abstract

Embodiments of the present disclosure relate to substrate transfer systems, including the use of a carrier configured to transfer objects through a substrate processing system. The carrier generally includes a base, a first magnetic levitation element and a second magnetic levitation element coupled to the base. The first magnetic levitation element and the second magnetic levitation element may be aligned in a first direction, the first magnetic levitation element may include a first array of features, and the second magnetic levitation element may include a second array of features. The carrier may also include a first support member coupled to the base and a second support member coupled to the base. The first support member and the second support member are disposed below the first magnetic levitation element and the second magnetic levitation element, and the first support member and the second support member are configured to support an object.

IPC Classes  ?

  • B65G 54/02 - Non-mechanical conveyors not otherwise provided for electrostatic, electric, or magnetic

66.

SWITCHING CIRCUIT FOR MULTILEVEL PLASMA IMPEDANCE MATCHING

      
Application Number 18418206
Status Pending
Filing Date 2024-01-19
First Publication Date 2025-07-24
Owner Applied Materials, Inc. (USA)
Inventor
  • Azad, Anm Wasekul
  • Guo, Yue
  • Yang, Yang
  • Ramaswamy, Kartik
  • Bright, Nicolas J.

Abstract

Embodiments provided herein generally include apparatus, plasma processing systems and methods for tuning in a radio frequency (RF) plasma processing system for improving substrate processing metrics. Some embodiments are directed to an apparatus for processing a substrate in a plasma processing system. The apparatus generally includes: an impedance for a match circuit configured to perform impedance matching for a plasma load; a diode-based switch coupled to the impedance for the match circuit; at least one signal generator coupled to the diode-based switch and configured to bias the diode-based switch to a first position based on a first impedance generated in the plasma load; and a second position based on a second impedance generated in the plasma load and an RF signal generator configured to provide an RF signal to the plasma load.

IPC Classes  ?

67.

PROCESS STAGE TRANSITION DETECTION FOR PLASMA SYSTEMS

      
Application Number 18420376
Status Pending
Filing Date 2024-01-23
First Publication Date 2025-07-24
Owner Applied Materials, Inc. (USA)
Inventor
  • Neelamraju, Bharati
  • Kulshreshtha, Prashant Kumar
  • Kageyama, Yuta
  • Kitagaki, Takashi

Abstract

A goal of a gapfill deposition process may be to form a relatively flat overgrowth layer of gapfill material above a top of the pillars. The relatively flat overgrowth layer can be formed by automatically stopping the gapfill deposition process after detecting an end of a stage (e.g., a sidewall growth stage) of the gapfill process. A characteristic of the plasma, such as an impedance of the plasma may be monitored during the plasma process. Changes in the characteristic may be correlated with different stages in the process, such as different stages in the gapfill process. When the characteristic indicates, a stage in the gapfill process may be identified, and an action may be taken, such as stopping the gapfill process. This provides live monitoring of the gapfill based on plasma characteristics rather than on measurements taken after the gap fill process is complete.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • C23C 16/06 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
  • C23C 16/24 - Deposition of silicon only
  • C23C 16/26 - Deposition of carbon only

68.

WATER-BASED, HIGH-EFFICIENCY CHEMICAL REAGENT FOR SUBSTRATE SURFACE PARTICLE REMOVAL

      
Application Number 18420408
Status Pending
Filing Date 2024-01-23
First Publication Date 2025-07-24
Owner Applied Materials, Inc. (USA)
Inventor
  • Yan, Hong
  • Hung, Raymond Hoiman
  • Wang, Ying
  • Dai, Xundong

Abstract

Embodiments of the disclosure provided herein include systems and methods for cleaning semiconductor substrates The method includes rotating a substrate disposed on a substrate support, spraying a front side of the substrate using a cleaning agent including one or more chelating agents through a front side nozzle assembly disposed above the substrate support, and spraying a back side of the substrate using the cleaning agent through a back side dispenser assembly disposed below the substrate support.

IPC Classes  ?

  • B08B 3/08 - Cleaning involving contact with liquid the liquid having chemical or dissolving effect
  • B08B 3/04 - Cleaning involving contact with liquid
  • B08B 3/12 - Cleaning involving contact with liquid with additional treatment of the liquid or of the object being cleaned, e.g. by heat, by electricity or by vibration by sonic or ultrasonic vibrations
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

69.

AUTOMATIC ROBOT CALIBRATION FOR MULTI-JOINT ROBOTS

      
Application Number 18421937
Status Pending
Filing Date 2024-01-24
First Publication Date 2025-07-24
Owner Applied Materials, Inc. (USA)
Inventor
  • Yu, Ho
  • Wirth, Paul Z.
  • Cox, Damon K.
  • Waqar, Mohsin
  • Hudgens, Jeffrey C.

Abstract

A system includes a chamber, a robot within the chamber, the robot including a plurality of links. The system further includes a vertically oriented sensor within the chamber, the vertically oriented sensor to detect a presence of one or more of the plurality of links. The system further includes a controller, to perform for each link to cause the robot to move the link through a field of view of the vertically oriented sensor. The controller further determines a zero horizontal position for the link based on the position of the link at which the link was detected by the vertically oriented sensor. The controller further automatically calibrates the robot within the chamber based on the zero horizontal position determined for each of the plurality of links.

IPC Classes  ?

  • B25J 9/16 - Programme controls
  • B25J 11/00 - Manipulators not otherwise provided for
  • B25J 13/08 - Controls for manipulators by means of sensing devices, e.g. viewing or touching devices
  • B25J 21/00 - Chambers provided with manipulation devices

70.

LIQUID DISPERSION OF QUANTUM DOT PARTICLES

      
Application Number US2024012181
Publication Number 2025/155296
Status In Force
Filing Date 2024-01-19
Publication Date 2025-07-24
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Sivanandan, Kulandaivelu
  • Ganapathiappan, Sivapackia
  • Patibandla, Nag Bhushanam

Abstract

Liquid dispersions of quantum dot particles include an acrylic medium having a boiling point in a range of from greater than or equal to 100 °C to less than or equal to 500 °C, quantum dot particles dispersed in the acrylic medium, a photo-initiator, and a surface additive. The liquid dispersions of quantum dot particles are useful as stable liquid formulations that resist gelling for spin-coating and ink-jet printing of color conversion layers in the manufacture of LED and micro-LED panels for advanced displays. Methods of manufacturing light-emitting devices using the liquid dispersions of quantum dot particles are also disclosed.

IPC Classes  ?

  • C09K 11/02 - Use of particular materials as binders, particle coatings or suspension media therefor
  • C09K 11/08 - Luminescent, e.g. electroluminescent, chemiluminescent, materials containing inorganic luminescent materials
  • C09D 11/03 - Printing inks characterised by features other than the chemical nature of the binder
  • H01L 33/50 - Wavelength conversion elements

71.

DIRECT NITRATION FOR BACKSIDE POWER DELIVER NETWORK ISOLATION MODULE

      
Application Number US2024060508
Publication Number 2025/155402
Status In Force
Filing Date 2024-12-17
Publication Date 2025-07-24
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Bhosale, Prasad
  • Basker, Veeraraghavan S.
  • Colombeau, Benjamin
  • Swenberg, Johanes F.
  • Guarini, Theresa Kramer

Abstract

A method of backside processing of a transistor structure includes performing a substrate trench etch process to form a trench within a substrate and leave a portion of the substrate below a bottom of the trench un-etched, wherein the trench is aligned with a gate of the transistor structure, performing a nitridation process to nitride an inner surface of the trench to form a nitride layer at the inner surface, and after forming the nitride layer, performing a dielectric fill process to form a dielectric layer within the trench.

IPC Classes  ?

  • H10D 30/01 - Manufacture or treatment
  • H10D 30/67 - Thin-film transistors [TFT]
  • H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
  • H10D 62/13 - Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
  • H10D 62/00 - Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D 64/01 - Manufacture or treatment
  • H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates

72.

OVERHANG PATTERN FOR ADVANCED OLED PATTERNING

      
Application Number US2024060534
Publication Number 2025/155405
Status In Force
Filing Date 2024-12-17
Publication Date 2025-07-24
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Lee, Jungmin
  • Haas, Dieter
  • Mcdaniel, Gregory Max
  • Lin, Yu-Hsin

Abstract

Embodiments described herein relate to a sub-pixel circuit and methods of forming a sub-pixel circuit. The sub-pixel circuit include adjacent overhang structures, an anode, an organic light emitting diode (OLED) material disposed over the anode, and a cathode disposed over the OLED material. The OLED material extends under the adjacent overhang structures. The cathode extends under the adjacent overhang structures. The overhang structures are defined by an overhang extension of a second structure extending laterally past a first structure. The first structure is disposed over a substrate. The first structure includes a lower section having a first lateral etching rate and an upper section deposited over the lower section having a second lateral etching rate. The second lateral etching rate is different from the first lateral etching rate.

IPC Classes  ?

  • H10K 59/122 - Pixel-defining structures or layers, e.g. banks
  • H10K 59/12 - Active-matrix OLED [AMOLED] displays
  • H10K 71/00 - Manufacture or treatment specially adapted for the organic devices covered by this subclass

73.

RF FILTER TOPOLOGY FOR A SUBSTRATE SUPPORT ASSEMBLY

      
Application Number US2025010197
Publication Number 2025/155441
Status In Force
Filing Date 2025-01-03
Publication Date 2025-07-24
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Guo, Yue
  • Ramaswamy, Kartik
  • Wong, Carlaton
  • Schatz, Kenneth
  • Kirkov, Kiril

Abstract

Described herewith are an RF filter assembly for processing a coupled RF power originated from a substrate support assembly of a processing chamber, a chucking circuit for the substrate support assembly, and a method for processing the coupled RF power. The RF filter assembly includes a compensation circuit connected to an electrode of the substrate support assembly and configured to receive the coupled RF power and reduce a reflection of the coupled RF power back to the substrate support assembly; and an RF filter block configured to receive signals processed by the compensation circuit and comprising a plurality of RF filters configured to filter out predetermined frequencies of the coupled RF power. The chucking circuit includes the RF filter assembly. The method includes process and operations of the RF filter assembly.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • H03H 7/01 - Frequency selective two-port networks
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping

74.

MODEL BASED DEVELOPMENT OF ZONE BASED FLOW OR THERMAL DISTRIBUTION SYSTEMS

      
Application Number US2025010443
Publication Number 2025/155446
Status In Force
Filing Date 2025-01-06
Publication Date 2025-07-24
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Veerappan, Devi, Raghavee
  • Balakrishna, Ajit

Abstract

Embodiments disclosed herein include a method for optimizing zones in a fluid flow system. In an embodiment, the method comprises running a baseline simulation for the fluid flow system, and running a plurality of sensitivity simulations, where each sensitivity simulation perturbs a flowrate through one of a plurality of pitch circles in the fluid flow system by an offset percentage. Tn an embodiment, the method further comprises generating a sensitivity matrix from the plurality of sensitivity simulations, and optimizing an objective function to enable grouping of the plurality of pitch circles into a plurality of zones.

IPC Classes  ?

  • G05B 17/02 - Systems involving the use of models or simulators of said systems electric
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01J 37/32 - Gas-filled discharge tubes

75.

POLISHING HEAD WITH RETAINING RING WEAR SENSING

      
Application Number US2025010462
Publication Number 2025/155448
Status In Force
Filing Date 2025-01-06
Publication Date 2025-07-24
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Oh, Jeonghoon
  • Nagengast, Andrew J.
  • Fujikawa, Takashi
  • Chen, Kuen-Hsiang
  • Zuniga, Steven M.

Abstract

A carrier head for chemical mechanical polishing includes a housing for attachment to a drive shaft. The housing includes an upper carrier body to be attached to a vertically stationary drive shaft and a lower carrier body that is vertically movable relative to the upper carrier body is configured to be secured to and suspend a retaining ring. A first flexible seal forms a loading chamber between the upper carrier body and the lower carrier body. A membrane assembly is arranged beneath the lower carrier body and includes a membrane support and a flexible membrane secured to the membrane support to form one or more lower pressurizable chambers. A second flexible seal forms an upper pressurizable chamber between the lower carrier body and the membrane support, and a sensor is secured to the housing and configured to measure a distance between the upper carrier body and the lower carrier body.

IPC Classes  ?

  • B24B 37/005 - Control means for lapping machines or devices
  • B24B 49/12 - Measuring or gauging equipment for controlling the feed movement of the grinding tool or workArrangements of indicating or measuring equipment, e.g. for indicating the start of the grinding operation involving optical means
  • B24B 37/32 - Retaining rings

76.

SUBSTRATE CARRIER

      
Application Number US2025011153
Publication Number 2025/155484
Status In Force
Filing Date 2025-01-10
Publication Date 2025-07-24
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Prasad, Bhaskar
  • Brezoczky, Thomas
  • Savandaiah, Kirankumar Neelasandra
  • Kumar, Aditya
  • Patil, Vijet

Abstract

Embodiments of the present disclosure relate to substrate transfer systems, including the use of a carrier configured to transfer objects through a substrate processing system. The carrier generally includes a base, a first magnetic levitation element and a second magnetic levitation element coupled to the base. The first magnetic levitation element and the second magnetic levitation element may be aligned in a first direction, the first magnetic levitation element may include a first array of features, and the second magnetic levitation element may include a second array of features. The carrier may also include a first support member coupled to the base and a second support member coupled to the base. The first support member and the second support member are disposed below the first magnetic levitation element and the second magnetic levitation element, and the first support member and the second support member are configured to support an object.

IPC Classes  ?

  • H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches

77.

METHODS OF MANUFACTURING INTERCONNECT STRUCTURES

      
Application Number US2025011519
Publication Number 2025/155527
Status In Force
Filing Date 2025-01-14
Publication Date 2025-07-24
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Bhuyan, Bhaskar Jyoti
  • Enman, Lisa J.
  • Liu, Feng Q.
  • Anthis, Jeffrey W.
  • Saly, Mark
  • Kalutarage, Lakmal C.
  • Dangerfield, Aaron
  • Mendoza-Gutierrez, Jesus Candelario
  • Tan, Sze Chieh

Abstract

Methods of manufacturing interconnect structures as part of a microelectronic device fabrication process are described. The methods include forming a dielectric layer including at least one feature defining a gap having sidewalls and a bottom on a substrate. The methods further include forming a blocking layer on the bottom by exposing the substrate to a blocking compound; selectively depositing a barrier layer on the sidewalls; selectively depositing a metal liner on the barrier layer on the sidewalls; removing the blocking layer; and performing a gap fill process to fill the gap with a gapfill material.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

78.

DEFORMATION CONTROL FOR DIE-TO-WAFER AND DIE-TO-DIE BONDING IN DEVICE MANUFACTURING

      
Application Number US2025011588
Publication Number 2025/155563
Status In Force
Filing Date 2025-01-14
Publication Date 2025-07-24
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Lin, San-Kuei
  • Lee, Wonjae
  • Subrahmanyan, Pradeep Kumar

Abstract

Disclosed systems and techniques are directed to optimization of semiconductor manufacturing by forming features on a front side of a first substrate and covering the plurality of first features with a stress-compensation layer (SCL). The techniques further include causing the first substrate to adhere to a second substrate and removing a back side portion of the first substrate to expose at least a subplurality of the features and forming a plurality of devices, each device including a portion of the features, a portion of the first substrate, and a portion of the second substrate. The SCL is configured to reduce deformation of the plurality of devices.

IPC Classes  ?

  • H01L 21/302 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
  • H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

79.

DIELECTRIC DEPOSITION RING WITH FINS FOR PHYSICAL VAPOR DEPOSITION

      
Application Number US2025011773
Publication Number 2025/155655
Status In Force
Filing Date 2025-01-16
Publication Date 2025-07-24
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Li, Ming-Jui
  • Xiao, Wen
  • Penmethsa, Harish Varma
  • Raju, Brijesh
  • Palanisamy, Puviyarasu
  • Chintala, Vasu Reddy
  • Lizarraga Maldonado, Alejandro
  • Tjakradinata, Michelle
  • Yedla, Srinivasa Rao

Abstract

Methods and apparatus for processing a substrate are provided herein. In some embodiments, a process kit for a substrate support includes: a dielectric plate having a lower surface configured to cover a support surface of the substrate support and an upper surface configured to support a substrate; and a dielectric deposition ring surrounding the dielectric plate and configured to cover a portion of the substrate support disposed radially outward of the support surface.

IPC Classes  ?

80.

ENCAPSULATED ANTI-REFLECTION GRATINGS FOR AUGMENTED REALITY WAVEGUIDE COMBINERS

      
Application Number US2025012211
Publication Number 2025/155927
Status In Force
Filing Date 2025-01-17
Publication Date 2025-07-24
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Shastri, Kunal
  • Wang, Evan
  • Lorenzo, Simon
  • Bhargava, Samarth

Abstract

Embodiments of the disclosure provided herein include an apparatus and method for waveguide combiners with gratings and a coating disposed thereover. The apparatus includes a waveguide with one or more gratings, the one or more gratings including a plurality of structures disposed over a waveguide substrate. The plurality of structures include a waveguide material and exterior structures at outer edges of the one or more gratings. A film is disposed over the waveguide substrate between the exterior structures, the film including the waveguide material. A coating is disposed over the one or more gratings having an outer boundary at an edge of the film. A refractive index of the coating is less than a refractive index of the one or more gratings.

IPC Classes  ?

81.

Gas distribution plate

      
Application Number 29846777
Grant Number D1085029
Status In Force
Filing Date 2022-07-19
First Publication Date 2025-07-22
Grant Date 2025-07-22
Owner Applied Materials, Inc. (USA)
Inventor
  • Iyengar, Prahallad
  • Wang, Chaowei
  • Shah, Kartik
  • Golcha, Janisht
  • Baluja, Sanjeev

82.

Universal Optical Waveguide Trays

      
Application Number 18411294
Status Pending
Filing Date 2024-01-12
First Publication Date 2025-07-17
Owner Applied Materials, Inc. (USA)
Inventor
  • Ahamed, Yaseer Arafath
  • Gowda, Sudhakar Koppa Hanumanthe
  • Carlson, Charles T.
  • Wang, Kangkang
  • Ricks, Neal
  • Shanmugavel, Anandhakannan

Abstract

A tray for carrying workpieces, such as optical waveguides, is disclosed. The tray includes a plurality of openings, each opening having a plurality of fingers extending toward the center of the opening. The top surface of each finger is sloped downward and comprises an elastomer. In this way, the workpieces contact the fingers along their edges and any nanostructures disposed on the workpiece are not contacted. Further, in some embodiments, the tray is stackable and includes a retention mechanism located on the bottom side of the tray. The retention mechanism on a first tray serves to secure the workpiece disposed on a second tray positioned directly below the first tray. The tray may optionally be used for shipping and other purposes.

IPC Classes  ?

  • G02B 6/44 - Mechanical structures for providing tensile strength and external protection for fibres, e.g. optical transmission cables

83.

ION EXTRACTION OPTICS FOR ION PROCESSING SYSTEM

      
Application Number 18415326
Status Pending
Filing Date 2024-01-17
First Publication Date 2025-07-17
Owner Applied Materials, Inc. (USA)
Inventor
  • Biloiu, Costel
  • Morrell, David
  • Daniels, Kevin M.
  • Campbell, Christopher

Abstract

An ion extraction optics including an extraction plate defining first, second, and third extraction apertures, the second extraction aperture being located between the first and third extraction apertures, first, second, and third beam blockers located adjacent the first, second, and third extraction apertures, respectively, wherein the first beam blocker and the first extraction aperture define first and second extraction slits, the second beam blocker and the second extraction aperture define third and fourth extraction slits, and the third beam blocker and the third extraction aperture define fifth and sixth extraction slits, wherein a height of the first extraction slit is greater than a height of at least one of the third extraction slit and the fourth extraction slit, and wherein a height of the sixth extraction slit is greater than the height of at least one of the third extraction slit and the fourth extraction slit.

IPC Classes  ?

  • H01J 37/09 - DiaphragmsShields associated with electron- or ion-optical arrangementsCompensation of disturbing fields
  • H01J 37/04 - Arrangements of electrodes and associated parts for generating or controlling the discharge, e.g. electron-optical arrangement, ion-optical arrangement
  • H01J 37/08 - Ion sourcesIon guns

84.

RF FILTER TOPOLOGY FOR SUBSTRATE SUPPORT ASSEMBLY

      
Application Number 18415506
Status Pending
Filing Date 2024-01-17
First Publication Date 2025-07-17
Owner Applied Materials, Inc. (USA)
Inventor
  • Guo, Yue
  • Ramaswamy, Kartik
  • Wong, Carlaton
  • Schatz, Kenneth
  • Kirkov, Kiril

Abstract

Described herewith are an RF filter assembly for processing a coupled RF power originated from a substrate support assembly of a processing chamber, a chucking circuit for the substrate support assembly, and a method for processing the coupled RF power. The RF filter assembly includes a compensation circuit connected to an electrode of the substrate support assembly and configured to receive the coupled RF power and reduce a reflection of the coupled RF power back to the substrate support assembly; and an RF filter block configured to receive signals processed by the compensation circuit and comprising a plurality of RF filters configured to filter out predetermined frequencies of the coupled RF power. The chucking circuit includes the RF filter assembly. The method includes process and operations of the RF filter assembly.

IPC Classes  ?

85.

Shield for an Ion Implanter

      
Application Number 18946776
Status Pending
Filing Date 2024-11-13
First Publication Date 2025-07-17
Owner Applied Materials, Inc. (USA)
Inventor
  • Hsieh, Tseh-Jen
  • Stratoti, Gregory Edward
  • Dhulapati, Santosh
  • Koo, Bon-Woong

Abstract

A shield for use with a rotatable platen is disclosed. The shield includes an exposed portion and a frame to attach the shield to the platen. The exposed portion of the shield has an arc shaped back surface that faces the platen and an opposite exposed surface that faces toward the ion beam. The exposed surface is designed such that the ion beam strikes the exposed surface at angles that are roughly 90°, as sputtering may be reduced at these angles. The exposed surface may have various shapes, including flat, rounded or sloped. Additionally, the exposed surface may include a plurality of exposed segments, separated by connecting segments that are not exposed to the ion beam. The shield may be graphite, silicon or silicon carbide.

IPC Classes  ?

  • H01J 37/30 - Electron-beam or ion-beam tubes for localised treatment of objects
  • H01J 37/20 - Means for supporting or positioning the object or the materialMeans for adjusting diaphragms or lenses associated with the support
  • H01J 37/317 - Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. ion implantation

86.

IN-SITU ANALYSIS OF METAL SPECIES FOR PROCESSING CHAMBERS

      
Application Number 19015451
Status Pending
Filing Date 2025-01-09
First Publication Date 2025-07-17
Owner Applied Materials, Inc. (USA)
Inventor Wang, Jiansheng

Abstract

Systems and methods are provided for analysis of metal contaminants within a processing chamber. Such systems and methods can include a vacuum system and valve attached to a processing chamber. The vacuum system and valve can effect a reduction in a pressure within a sampling chamber, an opening, while a process is in effect within a processing chamber connected to the sampling chamber, of a first fluid connection from the sampling chamber to the processing chamber such that a fluid ingresses from the processing chamber into the sampling chamber, a closing of the first fluid connection, an opening a second fluid connection from the sampling chamber to an inductively coupled plasma mass spectrometer (ICP-MS) such that the fluid egresses from the sampling chamber into the ICP-MS, an identification, via the ICP-MS, of a presence of trace elements within the fluid, and responsive to the identified presence of trace elements, performance of a corrective action associated with the processing chamber.

IPC Classes  ?

  • G01N 27/68 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating the ionisation of gases, e.g. aerosolsInvestigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating electric discharges, e.g. emission of cathode using electric discharge to ionise a gas
  • G01N 33/00 - Investigating or analysing materials by specific methods not covered by groups
  • G01N 33/2028 - Metallic constituents

87.

Gapfill Process Using Pulsed High-Frequency Radio-Frequency (HFRF) Plasma

      
Application Number 19057197
Status Pending
Filing Date 2025-02-19
First Publication Date 2025-07-17
Owner Applied Materials, Inc. (USA)
Inventor
  • Cheng, Rui
  • Li, Guoqing
  • Zhao, Qinghua

Abstract

Methods for forming a metal carbide liner in features formed in a substrate surface are described. Each of the features extends a distance into the substrate from the substrate surface and have a bottom and at least one sidewall. The methods include depositing a metal carbide liner in the feature of the substrate surface with a plurality of high-frequency ratio-frequency (HFRF) pulses. Semiconductor devices with the metal carbide liner and methods for filling gaps using the metal carbide liner are also described.

IPC Classes  ?

  • C23C 16/04 - Coating on selected surface areas, e.g. using masks
  • C23C 16/32 - Carbides
  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

88.

VERTICALLY ADJUSTABLE PLASMA SOURCE

      
Application Number 19095529
Status Pending
Filing Date 2025-03-31
First Publication Date 2025-07-17
Owner Applied Materials, Inc. (USA)
Inventor
  • Tanaka, Tsutomu
  • Lee, Jared Ahmad
  • Ramadas, Rakesh
  • Dzilno, Dmitry A.
  • Wilson, Gregory J.
  • Srinivasan, Sriharish

Abstract

The disclosure describes a plasma source assemblies comprising a differential screw assembly, an RF hot electrode, a top cover, an upper housing and a lower housing. The differential screw assembly is configured to provide force to align the plasma source assembly vertically matching planarity of a susceptor. More particularly, the differential screw assembly increases a distance between the top cover and the upper housing to align the gap with the susceptor. The disclosure also provides a better thermal management by cooling fins. A temperature capacity of the plasma source assemblies is extended by using titanium electrode. The disclosure provides a cladding material covering a portion of a first surface of RF hot electrode, a second surface of RF hot electrode, a bottom surface of RF hot electrode, a portion of a surface of the showerhead and a portion of lower housing surface.

IPC Classes  ?

89.

METHODS OF FABRICATING OLED PANEL WITH INORGANIC PIXEL ENCAPSULATING BARRIER

      
Application Number 19098503
Status Pending
Filing Date 2025-04-02
First Publication Date 2025-07-17
Owner Applied Materials, Inc. (USA)
Inventor
  • Choung, Ji-Young
  • Haas, Dieter
  • Lin, Yu Hsin
  • Lee, Jungmin
  • Yoo, Seong Ho
  • Kim, Si Kyoung

Abstract

Embodiments described herein relate to sub-pixel circuits and methods of forming sub-pixel circuits that may be utilized in a display such as an organic light-emitting diode (OLED) display. The device includes a plurality of sub-pixels, each sub-pixel of the plurality of sub-pixels defined by adjacent pixel-defining layer (PDL) structures with inorganic overhang structures disposed on the PDL structures, each sub-pixel having an anode, organic light-emitting diode (OLED) material disposed on the anode, and a cathode disposed on the OLED material. The device is made by a process including the steps of: depositing the OLED material and the cathode by evaporation deposition, and depositing an encapsulation layer disposed over the cathode.

IPC Classes  ?

  • H10K 59/173 - Passive-matrix OLED displays comprising banks or shadow masks
  • H10K 50/84 - PassivationContainersEncapsulations
  • H10K 50/844 - Encapsulations
  • H10K 59/12 - Active-matrix OLED [AMOLED] displays
  • H10K 59/122 - Pixel-defining structures or layers, e.g. banks
  • H10K 59/131 - Interconnections, e.g. wiring lines or terminals
  • H10K 59/80 - Constructional details
  • H10K 71/00 - Manufacture or treatment specially adapted for the organic devices covered by this subclass

90.

METHODS OF SELECTIVE ATOMIC LAYER DEPOSITION

      
Application Number 19172056
Status Pending
Filing Date 2025-04-07
First Publication Date 2025-07-17
Owner Applied Materials, Inc. (USA)
Inventor
  • Bhuyan, Bhaskar Jyoti
  • Saly, Mark
  • Thompson, David
  • Kaufman-Osborn, Tobin
  • Fredrickson, Kurt
  • Knisley, Thomas Joseph
  • Wu, Liqi

Abstract

Methods of depositing a film selectively onto a first substrate surface relative to a second substrate surface are described. The methods include exposing the substrate surfaces to a blocking compound to selectively form a blocking layer on at least a portion of the first surface over the second surface. The substrate is sequentially exposed to a metal precursor with a kinetic diameter in excess of 21 angstroms and a reactant to selectively form a metal-containing layer on the second surface over the blocking layer or the first surface. The relatively larger metal precursors of some embodiments allow for the use of blocking layers with gaps or voids without the loss of selectivity.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

91.

SYSTEMS AND METHODS FOR VISUAL INSPECTION OF PHARMACEUTICAL CONTAINERS

      
Application Number US2025010200
Publication Number 2025/151336
Status In Force
Filing Date 2025-01-03
Publication Date 2025-07-17
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Schlezinger, Asaf
  • Qin, Lang

Abstract

Systems and methods for fluid inspection are disclosed. The system includes a transportation system to transport a plurality of containers of fluid through an inspection zone, one or more cameras operable to view the plurality of containers from a first direction, and a back illuminator positioned to direct light in a second direction while the plurality of containers are in the inspection zone. The second direction is oriented greater than 90 degrees and less than 180 degrees from the first direction. The system further includes a controller electrically coupled to the back illuminator and the one or more cameras. The controller is operable to cause the back illuminator to emit light in the second direction while the plurality of containers are in the inspection zone and capture a plurality of images of the fluid in the plurality of containers while being illuminated by the back illuminator.

IPC Classes  ?

  • G01N 21/90 - Investigating the presence of flaws, defects or contamination in a container or its contents
  • G01N 21/88 - Investigating the presence of flaws, defects or contamination

92.

COMPLEMENTARY FIELD-EFFECT TRANSISTORS

      
Application Number US2025010567
Publication Number 2025/151417
Status In Force
Filing Date 2025-01-07
Publication Date 2025-07-17
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Lin, San-Kuei
  • Subrahmanyan, Pradeep, K.

Abstract

Methods of manufacturing electronic devices are described. Embodiments of the present disclosure advantageously provide methods of manufacturing electronic devices, e.g., complementary field-effect transistors (CFETs) that have improved negative bias temperature (NBTI) and boosted performance of the PMOS transistor due to the presence of a silicon germanium (SiGe) channel in the PMOS transistor. Specifically, a plurality of nanosheet release layers are removed from the N-channel metal-oxide-semiconductor (NMOS) transistor to form a plurality of openings adjacent the corresponding plurality of nanosheet channel layers, and a plurality of oxide layers are deposited in each of the plurality of openings.

IPC Classes  ?

  • H10D 84/85 - Complementary IGFETs, e.g. CMOS
  • H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
  • H10D 84/01 - Manufacture or treatment
  • H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
  • H10D 30/00 - Field-effect transistors [FET]
  • H10D 30/01 - Manufacture or treatment
  • H10D 30/67 - Thin-film transistors [TFT]

93.

CAUSALITY-BASED FLEET MATCHING

      
Application Number US2025010812
Publication Number 2025/151556
Status In Force
Filing Date 2025-01-08
Publication Date 2025-07-17
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Bhatia, Sidharth
  • Balaji, Bala Shyamala
  • Sridhar, Murali
  • Kamalanathan, Geethanzali
  • Wylie, Mark Mctaggart
  • Babayan, Steven Eduard

Abstract

A method includes generating a causal graph based on a plurality of values, each value corresponding to a causal relationship between two or more sensors of a plurality of sensors in one or more manufacturing systems. The method further includes determining a causal strength index matrix. The method further includes responsive to identifying an anomalous behavior in at least one of the plurality of sensors, determining a root cause of the anomalous behavior using at least one of the causal strength index matrix or the causal graph. The method further includes causing a recommended corrective action to be issued based on the root cause of the anomalous behavior.

IPC Classes  ?

  • G05B 23/02 - Electric testing or monitoring
  • G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM]
  • G06N 20/00 - Machine learning

94.

ASYMMETRIC GRATINGS FOR PARASITIC ORDER MITIGATION

      
Application Number US2025011208
Publication Number 2025/151798
Status In Force
Filing Date 2025-01-10
Publication Date 2025-07-17
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Lorenzo, Simon
  • Bhargava, Samarth
  • Sell, David Alexander
  • Liu, Yingnan
  • Wang, Evan

Abstract

An optical device includes a substrate, an input coupler disposed on a first surface of the substrate and configured to receive input light, a first output coupler disposed on the first surface of the substrate, a second output coupler disposed on a second surface of the substrate, wherein the first output coupler and the second output coupler comprise asymmetric grating structures the first surface of the substrate opposes the second surface of the substrate.

IPC Classes  ?

  • G02B 6/34 - Optical coupling means utilising prism or grating
  • G02B 6/00 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings
  • G02B 27/01 - Head-up displays
  • G02B 5/18 - Diffracting gratings

95.

DIETHYL ZINC AND METAL HALIDE PRECURSORS FOR DEPOSITION OF METAL FILMS ON SEMICONDUCTOR SUBSTRATES

      
Application Number 18591976
Status Pending
Filing Date 2024-02-29
First Publication Date 2025-07-17
Owner Applied Materials, Inc. (USA)
Inventor
  • Gandikota, Srinivas
  • Yang, Yixiong
  • Ailihumaer, Tuerxun
  • Bajaj, Geetika
  • Ganguli, Seshadri
  • Tripathi, Vijay
  • Sen, Jayeeta
  • Chandran, Gopi

Abstract

Methods for depositing metal films using a metal halide precursor and diethyl zinc are described. The substrate is exposed to a first metal precursor and diethyl zinc to form the metal film. The exposures can be sequential or simultaneous. The metal films are pure with a low carbon content. The first metal precursor may be a metal halide selected from the group consisting of tantalum chloride, aluminum chloride, niobium chloride, titanium chloride, zirconium chloride, hafnium chloride, tungsten chloride, molybdenum chloride, tantalum bromide, aluminum bromide, niobium bromide titanium bromide, zirconium bromide, hafnium bromide, tungsten bromide, molybdenum bromide, tantalum fluoride, aluminum fluoride, niobium fluoride, titanium fluoride, zirconium fluoride, hafnium fluoride, tungsten fluoride, molybdenum fluoride, tantalum iodide, aluminum iodide, niobium iodide, titanium iodide, zirconium iodide, hafnium iodide, tungsten iodide, and molybdenum iodide.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/08 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metal halides
  • C23C 16/18 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metallo-organic compounds
  • H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation

96.

SOURCE/DRAIN (S/D) EPITAXIAL GROWTH IN GATE-ALL-AROUND (GAA) NANOSHEET DEVICE

      
Application Number 18979201
Status Pending
Filing Date 2024-12-12
First Publication Date 2025-07-17
Owner Applied Materials, Inc. (USA)
Inventor
  • Lin, San-Kuei
  • Subrahmanyan, Pradeep K.

Abstract

A method of forming a portion of a gate-all-around field-effect transistor (GAA FET) nanosheet structure includes performing a trim back recess process to form recesses in inner spacers of a fin-shaped column in a first direction from a sidewall of the fin-shaped column, wherein the fin-shaped column includes a stack of nanosheet channels and sacrificial layers having the inner spacers on both sides thereof in the first direction, performing an interface epitaxial growth process to grow interface source/drain (S/D) epi layers from exposed surfaces of the nanosheet channels of the fin-shaped column on the sidewalls of the fin-shaped column, performing an etch back process to etch back the interface S/D epi layer and form a continuous surface of the interface S/D epi layer, and performing a full epitaxial growth process to fully grow an S/D epi layer from the continuous surface of the interface S/D epi layer.

IPC Classes  ?

97.

BITLINE SURFACE TREATMENT AND ENCAPSULATION IN DYNAMIC RANDOM-ACCESS MEMORY (DRAM) DEVICES

      
Application Number 18984928
Status Pending
Filing Date 2024-12-17
First Publication Date 2025-07-17
Owner Applied Materials, Inc. (USA)
Inventor
  • Seo, Jongbeom
  • Chen, Zhijun
  • Fishburn, Fredrick
  • Makala, Raghuveer Satya

Abstract

A memory cell array includes a bitline encapsulated in a blocking layer within a spacer layer, the bitline extending in a first direction, and a plurality of memory cells aligned in the first direction, each of the plurality of memory cells including a cell transistor having a source electrically connected to the bitline, a drain, a word line, and a channel electrically connected to the source and the drain, and a cell capacitor having a top electrode that is electrically connected to the drain.

IPC Classes  ?

  • H10B 12/00 - Dynamic random access memory [DRAM] devices

98.

OVERHANG PATTERN FOR ADVANCED OLED PATTERNING

      
Application Number 19006989
Status Pending
Filing Date 2024-12-31
First Publication Date 2025-07-17
Owner Applied Materials, Inc. (USA)
Inventor
  • Lee, Jungmin
  • Haas, Dieter
  • Mcdaniel, Grgory Max
  • Lin, Yu-Hsin

Abstract

Embodiments described herein relate to a sub-pixel circuit and methods of forming a sub-pixel circuit. The sub-pixel circuit include adjacent overhang structures, an anode, an organic light emitting diode (OLED) material disposed over the anode, and a cathode disposed over the OLED material. The OLED material extends under the adjacent overhang structures. The cathode extends under the adjacent overhang structures. The overhang structures are defined by an overhang extension of a second structure extending laterally past a first structure. The first structure is disposed over a substrate. The first structure includes a lower section having a first lateral etching rate and an upper section deposited over the lower section having a second lateral etching rate. The second lateral etching rate is different from the first lateral etching rate.

IPC Classes  ?

  • H10K 59/122 - Pixel-defining structures or layers, e.g. banks
  • H10K 59/12 - Active-matrix OLED [AMOLED] displays
  • H10K 59/80 - Constructional details
  • H10K 102/00 - Constructional details relating to the organic devices covered by this subclass

99.

TEMPERATURE PROFILE MEASUREMENT AND SYNCHRONIZED CONTROL ON SUBSTRATE AND SUSCEPTOR IN AN EPITAXY CHAMBER

      
Application Number 19018999
Status Pending
Filing Date 2025-01-13
First Publication Date 2025-07-17
Owner Applied Materials, Inc. (USA)
Inventor
  • Zhu, Zuoming
  • Lau, Shu-Kwan
  • Choo, Enle
  • Moradian, Ala
  • Chang, Flora Fong-Song
  • Shaposhnikov, Maxim D.
  • Marath Sankarathodi, Bindusagar
  • Cong, Zhepeng
  • Ye, Zhiyuan
  • Nestorov, Vilen K.
  • Srivastava, Surendra Singh
  • Chopra, Saurabh
  • Liu, Patricia M.
  • Sanchez, Errol Antonio C.
  • Lin, Jenny
  • Chu, Schubert

Abstract

An apparatus for controlling temperature profile of a substrate within an epitaxial chamber includes a bottom center pyrometer and a bottom outer pyrometer to respectively measure temperatures at a center location and an outer location of a first surface of a susceptor of an epitaxy chamber, a top center pyrometer and a top outer pyrometer to respectively measure temperatures at a center location and an outer location of a substrate disposed on a second surface of the susceptor opposite the first surface, a first controller to receive signals, from the bottom center pyrometer and the bottom outer pyrometer, and output a feedback signal to a first heating lamp module that heats the first surface based on the measured temperatures of the first surface, and a second controller to receive signals, from the top center pyrometer, the top outer pyrometer, the bottom center pyrometer, and the bottom outer pyrometer, and output a feedback signal to a second heating lamp module that heats the substrate based on the measured temperatures of a substrate and the measured temperatures of the first surface.

IPC Classes  ?

  • G01J 5/00 - Radiation pyrometry, e.g. infrared or optical thermometry
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

100.

METHODS OF MANUFACTURING INTERCONNECT STRUCTURES

      
Application Number 19019830
Status Pending
Filing Date 2025-01-14
First Publication Date 2025-07-17
Owner Applied Materials, Inc. (USA)
Inventor
  • Bhuyan, Bhaskar Jyoti
  • Enman, Lisa J.
  • Liu, Feng Q.
  • Anthis, Jeffrey W.
  • Saly, Mark
  • Kalutarage, Lakmal C.
  • Dangerfield, Aaron
  • Mendoza-Gutierrez, Jesus Candelario
  • Tan, Sze Chieh

Abstract

Methods of manufacturing interconnect structures as part of a microelectronic device fabrication process are described. The methods include forming a dielectric layer including at least one feature defining a gap having sidewalls and a bottom on a substrate. The methods further include forming a blocking layer on the bottom by exposing the substrate to a blocking compound; selectively depositing a barrier layer on the sidewalls; selectively depositing a metal liner on the barrier layer on the sidewalls; removing the blocking layer; and performing a gap fill process to fill the gap with a gapfill material.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
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